1b886d83cSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 26ac0ba5aSNaveen N. Rao /* 36ac0ba5aSNaveen N. Rao * bpf_jit.h: BPF JIT compiler for PPC 40ca87f05SMatt Evans * 50ca87f05SMatt Evans * Copyright 2011 Matt Evans <matt@ozlabs.org>, IBM Corporation 6156d0e29SNaveen N. Rao * 2016 Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> 70ca87f05SMatt Evans */ 80ca87f05SMatt Evans #ifndef _BPF_JIT_H 90ca87f05SMatt Evans #define _BPF_JIT_H 100ca87f05SMatt Evans 110ca87f05SMatt Evans #ifndef __ASSEMBLY__ 120ca87f05SMatt Evans 13156d0e29SNaveen N. Rao #include <asm/types.h> 1406541865SBalamuruhan S #include <asm/ppc-opcode.h> 15156d0e29SNaveen N. Rao 16156d0e29SNaveen N. Rao #ifdef PPC64_ELF_ABI_v1 170ca87f05SMatt Evans #define FUNCTION_DESCR_SIZE 24 1809ca5ab2SDenis Kirjanov #else 1909ca5ab2SDenis Kirjanov #define FUNCTION_DESCR_SIZE 0 2009ca5ab2SDenis Kirjanov #endif 210ca87f05SMatt Evans 220ca87f05SMatt Evans #define PLANT_INSTR(d, idx, instr) \ 230ca87f05SMatt Evans do { if (d) { (d)[idx] = instr; } idx++; } while (0) 240ca87f05SMatt Evans #define EMIT(instr) PLANT_INSTR(image, ctx->idx, instr) 250ca87f05SMatt Evans 260ca87f05SMatt Evans /* Long jump; (unconditional 'branch') */ 270ca87f05SMatt Evans #define PPC_JMP(dest) EMIT(PPC_INST_BRANCH | \ 280ca87f05SMatt Evans (((dest) - (ctx->idx * 4)) & 0x03fffffc)) 290ca87f05SMatt Evans /* "cond" here covers BO:BI fields. */ 300ca87f05SMatt Evans #define PPC_BCC_SHORT(cond, dest) EMIT(PPC_INST_BRANCH_COND | \ 310ca87f05SMatt Evans (((cond) & 0x3ff) << 16) | \ 320ca87f05SMatt Evans (((dest) - (ctx->idx * 4)) & \ 330ca87f05SMatt Evans 0xfffc)) 34aaf2f7e0SNaveen N. Rao /* Sign-extended 32-bit immediate load */ 35aaf2f7e0SNaveen N. Rao #define PPC_LI32(d, i) do { \ 36aaf2f7e0SNaveen N. Rao if ((int)(uintptr_t)(i) >= -32768 && \ 37aaf2f7e0SNaveen N. Rao (int)(uintptr_t)(i) < 32768) \ 383a181237SBalamuruhan S EMIT(PPC_RAW_LI(d, i)); \ 39aaf2f7e0SNaveen N. Rao else { \ 403a181237SBalamuruhan S EMIT(PPC_RAW_LIS(d, IMM_H(i))); \ 41aaf2f7e0SNaveen N. Rao if (IMM_L(i)) \ 423a181237SBalamuruhan S EMIT(PPC_RAW_ORI(d, d, IMM_L(i))); \ 430ca87f05SMatt Evans } } while(0) 44aaf2f7e0SNaveen N. Rao 450ca87f05SMatt Evans #define PPC_LI64(d, i) do { \ 46b1a05787SNaveen N. Rao if ((long)(i) >= -2147483648 && \ 47b1a05787SNaveen N. Rao (long)(i) < 2147483648) \ 480ca87f05SMatt Evans PPC_LI32(d, i); \ 490ca87f05SMatt Evans else { \ 50b1a05787SNaveen N. Rao if (!((uintptr_t)(i) & 0xffff800000000000ULL)) \ 513a181237SBalamuruhan S EMIT(PPC_RAW_LI(d, ((uintptr_t)(i) >> 32) & \ 523a181237SBalamuruhan S 0xffff)); \ 53b1a05787SNaveen N. Rao else { \ 543a181237SBalamuruhan S EMIT(PPC_RAW_LIS(d, ((uintptr_t)(i) >> 48))); \ 550ca87f05SMatt Evans if ((uintptr_t)(i) & 0x0000ffff00000000ULL) \ 563a181237SBalamuruhan S EMIT(PPC_RAW_ORI(d, d, \ 573a181237SBalamuruhan S ((uintptr_t)(i) >> 32) & 0xffff)); \ 58b1a05787SNaveen N. Rao } \ 593a181237SBalamuruhan S EMIT(PPC_RAW_SLDI(d, d, 32)); \ 600ca87f05SMatt Evans if ((uintptr_t)(i) & 0x00000000ffff0000ULL) \ 613a181237SBalamuruhan S EMIT(PPC_RAW_ORIS(d, d, \ 623a181237SBalamuruhan S ((uintptr_t)(i) >> 16) & 0xffff)); \ 630ca87f05SMatt Evans if ((uintptr_t)(i) & 0x000000000000ffffULL) \ 643a181237SBalamuruhan S EMIT(PPC_RAW_ORI(d, d, (uintptr_t)(i) & \ 653a181237SBalamuruhan S 0xffff)); \ 66b1a05787SNaveen N. Rao } } while (0) 670ca87f05SMatt Evans 6809ca5ab2SDenis Kirjanov #ifdef CONFIG_PPC64 6909ca5ab2SDenis Kirjanov #define PPC_FUNC_ADDR(d,i) do { PPC_LI64(d, i); } while(0) 7009ca5ab2SDenis Kirjanov #else 7109ca5ab2SDenis Kirjanov #define PPC_FUNC_ADDR(d,i) do { PPC_LI32(d, i); } while(0) 7209ca5ab2SDenis Kirjanov #endif 7309ca5ab2SDenis Kirjanov 740ca87f05SMatt Evans static inline bool is_nearbranch(int offset) 750ca87f05SMatt Evans { 760ca87f05SMatt Evans return (offset < 32768) && (offset >= -32768); 770ca87f05SMatt Evans } 780ca87f05SMatt Evans 790ca87f05SMatt Evans /* 800ca87f05SMatt Evans * The fly in the ointment of code size changing from pass to pass is 810ca87f05SMatt Evans * avoided by padding the short branch case with a NOP. If code size differs 820ca87f05SMatt Evans * with different branch reaches we will have the issue of code moving from 830ca87f05SMatt Evans * one pass to the next and will need a few passes to converge on a stable 840ca87f05SMatt Evans * state. 850ca87f05SMatt Evans */ 860ca87f05SMatt Evans #define PPC_BCC(cond, dest) do { \ 870ca87f05SMatt Evans if (is_nearbranch((dest) - (ctx->idx * 4))) { \ 880ca87f05SMatt Evans PPC_BCC_SHORT(cond, dest); \ 893a181237SBalamuruhan S EMIT(PPC_RAW_NOP()); \ 900ca87f05SMatt Evans } else { \ 910ca87f05SMatt Evans /* Flip the 'T or F' bit to invert comparison */ \ 920ca87f05SMatt Evans PPC_BCC_SHORT(cond ^ COND_CMP_TRUE, (ctx->idx+2)*4); \ 930ca87f05SMatt Evans PPC_JMP(dest); \ 940ca87f05SMatt Evans } } while(0) 950ca87f05SMatt Evans 960ca87f05SMatt Evans /* To create a branch condition, select a bit of cr0... */ 970ca87f05SMatt Evans #define CR0_LT 0 980ca87f05SMatt Evans #define CR0_GT 1 990ca87f05SMatt Evans #define CR0_EQ 2 1000ca87f05SMatt Evans /* ...and modify BO[3] */ 1010ca87f05SMatt Evans #define COND_CMP_TRUE 0x100 1020ca87f05SMatt Evans #define COND_CMP_FALSE 0x000 1030ca87f05SMatt Evans /* Together, they make all required comparisons: */ 1040ca87f05SMatt Evans #define COND_GT (CR0_GT | COND_CMP_TRUE) 1050ca87f05SMatt Evans #define COND_GE (CR0_LT | COND_CMP_FALSE) 1060ca87f05SMatt Evans #define COND_EQ (CR0_EQ | COND_CMP_TRUE) 1070ca87f05SMatt Evans #define COND_NE (CR0_EQ | COND_CMP_FALSE) 1080ca87f05SMatt Evans #define COND_LT (CR0_LT | COND_CMP_TRUE) 10920dbf5ccSDaniel Borkmann #define COND_LE (CR0_GT | COND_CMP_FALSE) 1100ca87f05SMatt Evans 1110ca87f05SMatt Evans #endif 1120ca87f05SMatt Evans 1130ca87f05SMatt Evans #endif 114