1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * This file contains common routines for dealing with free of page tables 4 * Along with common page table handling code 5 * 6 * Derived from arch/powerpc/mm/tlb_64.c: 7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 8 * 9 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) 10 * and Cort Dougan (PReP) (cort@cs.nmt.edu) 11 * Copyright (C) 1996 Paul Mackerras 12 * 13 * Derived from "arch/i386/mm/init.c" 14 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds 15 * 16 * Dave Engebretsen <engebret@us.ibm.com> 17 * Rework for PPC64 port. 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/gfp.h> 22 #include <linux/mm.h> 23 #include <linux/percpu.h> 24 #include <linux/hardirq.h> 25 #include <linux/hugetlb.h> 26 #include <asm/tlbflush.h> 27 #include <asm/tlb.h> 28 #include <asm/hugetlb.h> 29 #include <asm/pte-walk.h> 30 31 #ifdef CONFIG_PPC64 32 #define PGD_ALIGN (sizeof(pgd_t) * MAX_PTRS_PER_PGD) 33 #else 34 #define PGD_ALIGN PAGE_SIZE 35 #endif 36 37 pgd_t swapper_pg_dir[MAX_PTRS_PER_PGD] __section(".bss..page_aligned") __aligned(PGD_ALIGN); 38 39 static inline int is_exec_fault(void) 40 { 41 return current->thread.regs && TRAP(current->thread.regs) == 0x400; 42 } 43 44 /* We only try to do i/d cache coherency on stuff that looks like 45 * reasonably "normal" PTEs. We currently require a PTE to be present 46 * and we avoid _PAGE_SPECIAL and cache inhibited pte. We also only do that 47 * on userspace PTEs 48 */ 49 static inline int pte_looks_normal(pte_t pte) 50 { 51 52 if (pte_present(pte) && !pte_special(pte)) { 53 if (pte_ci(pte)) 54 return 0; 55 if (pte_user(pte)) 56 return 1; 57 } 58 return 0; 59 } 60 61 static struct folio *maybe_pte_to_folio(pte_t pte) 62 { 63 unsigned long pfn = pte_pfn(pte); 64 struct page *page; 65 66 if (unlikely(!pfn_valid(pfn))) 67 return NULL; 68 page = pfn_to_page(pfn); 69 if (PageReserved(page)) 70 return NULL; 71 return page_folio(page); 72 } 73 74 #ifdef CONFIG_PPC_BOOK3S 75 76 /* Server-style MMU handles coherency when hashing if HW exec permission 77 * is supposed per page (currently 64-bit only). If not, then, we always 78 * flush the cache for valid PTEs in set_pte. Embedded CPU without HW exec 79 * support falls into the same category. 80 */ 81 82 static pte_t set_pte_filter_hash(pte_t pte) 83 { 84 pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS); 85 if (pte_looks_normal(pte) && !(cpu_has_feature(CPU_FTR_COHERENT_ICACHE) || 86 cpu_has_feature(CPU_FTR_NOEXECUTE))) { 87 struct folio *folio = maybe_pte_to_folio(pte); 88 if (!folio) 89 return pte; 90 if (!test_bit(PG_dcache_clean, &folio->flags)) { 91 flush_dcache_icache_folio(folio); 92 set_bit(PG_dcache_clean, &folio->flags); 93 } 94 } 95 return pte; 96 } 97 98 #else /* CONFIG_PPC_BOOK3S */ 99 100 static pte_t set_pte_filter_hash(pte_t pte) { return pte; } 101 102 #endif /* CONFIG_PPC_BOOK3S */ 103 104 /* Embedded type MMU with HW exec support. This is a bit more complicated 105 * as we don't have two bits to spare for _PAGE_EXEC and _PAGE_HWEXEC so 106 * instead we "filter out" the exec permission for non clean pages. 107 */ 108 static inline pte_t set_pte_filter(pte_t pte) 109 { 110 struct folio *folio; 111 112 if (radix_enabled()) 113 return pte; 114 115 if (mmu_has_feature(MMU_FTR_HPTE_TABLE)) 116 return set_pte_filter_hash(pte); 117 118 /* No exec permission in the first place, move on */ 119 if (!pte_exec(pte) || !pte_looks_normal(pte)) 120 return pte; 121 122 /* If you set _PAGE_EXEC on weird pages you're on your own */ 123 folio = maybe_pte_to_folio(pte); 124 if (unlikely(!folio)) 125 return pte; 126 127 /* If the page clean, we move on */ 128 if (test_bit(PG_dcache_clean, &folio->flags)) 129 return pte; 130 131 /* If it's an exec fault, we flush the cache and make it clean */ 132 if (is_exec_fault()) { 133 flush_dcache_icache_folio(folio); 134 set_bit(PG_dcache_clean, &folio->flags); 135 return pte; 136 } 137 138 /* Else, we filter out _PAGE_EXEC */ 139 return pte_exprotect(pte); 140 } 141 142 static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma, 143 int dirty) 144 { 145 struct folio *folio; 146 147 if (IS_ENABLED(CONFIG_PPC_BOOK3S_64)) 148 return pte; 149 150 if (mmu_has_feature(MMU_FTR_HPTE_TABLE)) 151 return pte; 152 153 /* So here, we only care about exec faults, as we use them 154 * to recover lost _PAGE_EXEC and perform I$/D$ coherency 155 * if necessary. Also if _PAGE_EXEC is already set, same deal, 156 * we just bail out 157 */ 158 if (dirty || pte_exec(pte) || !is_exec_fault()) 159 return pte; 160 161 #ifdef CONFIG_DEBUG_VM 162 /* So this is an exec fault, _PAGE_EXEC is not set. If it was 163 * an error we would have bailed out earlier in do_page_fault() 164 * but let's make sure of it 165 */ 166 if (WARN_ON(!(vma->vm_flags & VM_EXEC))) 167 return pte; 168 #endif /* CONFIG_DEBUG_VM */ 169 170 /* If you set _PAGE_EXEC on weird pages you're on your own */ 171 folio = maybe_pte_to_folio(pte); 172 if (unlikely(!folio)) 173 goto bail; 174 175 /* If the page is already clean, we move on */ 176 if (test_bit(PG_dcache_clean, &folio->flags)) 177 goto bail; 178 179 /* Clean the page and set PG_dcache_clean */ 180 flush_dcache_icache_folio(folio); 181 set_bit(PG_dcache_clean, &folio->flags); 182 183 bail: 184 return pte_mkexec(pte); 185 } 186 187 /* 188 * set_pte stores a linux PTE into the linux page table. 189 */ 190 void set_ptes(struct mm_struct *mm, unsigned long addr, pte_t *ptep, 191 pte_t pte, unsigned int nr) 192 { 193 /* 194 * Make sure hardware valid bit is not set. We don't do 195 * tlb flush for this update. 196 */ 197 VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep)); 198 199 /* Note: mm->context.id might not yet have been assigned as 200 * this context might not have been activated yet when this 201 * is called. 202 */ 203 pte = set_pte_filter(pte); 204 205 /* Perform the setting of the PTE */ 206 arch_enter_lazy_mmu_mode(); 207 for (;;) { 208 __set_pte_at(mm, addr, ptep, pte, 0); 209 if (--nr == 0) 210 break; 211 ptep++; 212 pte = __pte(pte_val(pte) + (1UL << PTE_RPN_SHIFT)); 213 addr += PAGE_SIZE; 214 } 215 arch_leave_lazy_mmu_mode(); 216 } 217 218 void unmap_kernel_page(unsigned long va) 219 { 220 pmd_t *pmdp = pmd_off_k(va); 221 pte_t *ptep = pte_offset_kernel(pmdp, va); 222 223 pte_clear(&init_mm, va, ptep); 224 flush_tlb_kernel_range(va, va + PAGE_SIZE); 225 } 226 227 /* 228 * This is called when relaxing access to a PTE. It's also called in the page 229 * fault path when we don't hit any of the major fault cases, ie, a minor 230 * update of _PAGE_ACCESSED, _PAGE_DIRTY, etc... The generic code will have 231 * handled those two for us, we additionally deal with missing execute 232 * permission here on some processors 233 */ 234 int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address, 235 pte_t *ptep, pte_t entry, int dirty) 236 { 237 int changed; 238 entry = set_access_flags_filter(entry, vma, dirty); 239 changed = !pte_same(*(ptep), entry); 240 if (changed) { 241 assert_pte_locked(vma->vm_mm, address); 242 __ptep_set_access_flags(vma, ptep, entry, 243 address, mmu_virtual_psize); 244 } 245 return changed; 246 } 247 248 #ifdef CONFIG_HUGETLB_PAGE 249 int huge_ptep_set_access_flags(struct vm_area_struct *vma, 250 unsigned long addr, pte_t *ptep, 251 pte_t pte, int dirty) 252 { 253 #ifdef HUGETLB_NEED_PRELOAD 254 /* 255 * The "return 1" forces a call of update_mmu_cache, which will write a 256 * TLB entry. Without this, platforms that don't do a write of the TLB 257 * entry in the TLB miss handler asm will fault ad infinitum. 258 */ 259 ptep_set_access_flags(vma, addr, ptep, pte, dirty); 260 return 1; 261 #else 262 int changed, psize; 263 264 pte = set_access_flags_filter(pte, vma, dirty); 265 changed = !pte_same(*(ptep), pte); 266 if (changed) { 267 268 #ifdef CONFIG_PPC_BOOK3S_64 269 struct hstate *h = hstate_vma(vma); 270 271 psize = hstate_get_psize(h); 272 #ifdef CONFIG_DEBUG_VM 273 assert_spin_locked(huge_pte_lockptr(h, vma->vm_mm, ptep)); 274 #endif 275 276 #else 277 /* 278 * Not used on non book3s64 platforms. 279 * 8xx compares it with mmu_virtual_psize to 280 * know if it is a huge page or not. 281 */ 282 psize = MMU_PAGE_COUNT; 283 #endif 284 __ptep_set_access_flags(vma, ptep, pte, addr, psize); 285 } 286 return changed; 287 #endif 288 } 289 290 #if defined(CONFIG_PPC_8xx) 291 void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte) 292 { 293 pmd_t *pmd = pmd_off(mm, addr); 294 pte_basic_t val; 295 pte_basic_t *entry = (pte_basic_t *)ptep; 296 int num, i; 297 298 /* 299 * Make sure hardware valid bit is not set. We don't do 300 * tlb flush for this update. 301 */ 302 VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep)); 303 304 pte = set_pte_filter(pte); 305 306 val = pte_val(pte); 307 308 num = number_of_cells_per_pte(pmd, val, 1); 309 310 for (i = 0; i < num; i++, entry++, val += SZ_4K) 311 *entry = val; 312 } 313 #endif 314 #endif /* CONFIG_HUGETLB_PAGE */ 315 316 #ifdef CONFIG_DEBUG_VM 317 void assert_pte_locked(struct mm_struct *mm, unsigned long addr) 318 { 319 pgd_t *pgd; 320 p4d_t *p4d; 321 pud_t *pud; 322 pmd_t *pmd; 323 pte_t *pte; 324 spinlock_t *ptl; 325 326 if (mm == &init_mm) 327 return; 328 pgd = mm->pgd + pgd_index(addr); 329 BUG_ON(pgd_none(*pgd)); 330 p4d = p4d_offset(pgd, addr); 331 BUG_ON(p4d_none(*p4d)); 332 pud = pud_offset(p4d, addr); 333 BUG_ON(pud_none(*pud)); 334 pmd = pmd_offset(pud, addr); 335 /* 336 * khugepaged to collapse normal pages to hugepage, first set 337 * pmd to none to force page fault/gup to take mmap_lock. After 338 * pmd is set to none, we do a pte_clear which does this assertion 339 * so if we find pmd none, return. 340 */ 341 if (pmd_none(*pmd)) 342 return; 343 pte = pte_offset_map_nolock(mm, pmd, addr, &ptl); 344 BUG_ON(!pte); 345 assert_spin_locked(ptl); 346 pte_unmap(pte); 347 } 348 #endif /* CONFIG_DEBUG_VM */ 349 350 unsigned long vmalloc_to_phys(void *va) 351 { 352 unsigned long pfn = vmalloc_to_pfn(va); 353 354 BUG_ON(!pfn); 355 return __pa(pfn_to_kaddr(pfn)) + offset_in_page(va); 356 } 357 EXPORT_SYMBOL_GPL(vmalloc_to_phys); 358 359 /* 360 * We have 4 cases for pgds and pmds: 361 * (1) invalid (all zeroes) 362 * (2) pointer to next table, as normal; bottom 6 bits == 0 363 * (3) leaf pte for huge page _PAGE_PTE set 364 * (4) hugepd pointer, _PAGE_PTE = 0 and bits [2..6] indicate size of table 365 * 366 * So long as we atomically load page table pointers we are safe against teardown, 367 * we can follow the address down to the page and take a ref on it. 368 * This function need to be called with interrupts disabled. We use this variant 369 * when we have MSR[EE] = 0 but the paca->irq_soft_mask = IRQS_ENABLED 370 */ 371 pte_t *__find_linux_pte(pgd_t *pgdir, unsigned long ea, 372 bool *is_thp, unsigned *hpage_shift) 373 { 374 pgd_t *pgdp; 375 p4d_t p4d, *p4dp; 376 pud_t pud, *pudp; 377 pmd_t pmd, *pmdp; 378 pte_t *ret_pte; 379 hugepd_t *hpdp = NULL; 380 unsigned pdshift; 381 382 if (hpage_shift) 383 *hpage_shift = 0; 384 385 if (is_thp) 386 *is_thp = false; 387 388 /* 389 * Always operate on the local stack value. This make sure the 390 * value don't get updated by a parallel THP split/collapse, 391 * page fault or a page unmap. The return pte_t * is still not 392 * stable. So should be checked there for above conditions. 393 * Top level is an exception because it is folded into p4d. 394 */ 395 pgdp = pgdir + pgd_index(ea); 396 p4dp = p4d_offset(pgdp, ea); 397 p4d = READ_ONCE(*p4dp); 398 pdshift = P4D_SHIFT; 399 400 if (p4d_none(p4d)) 401 return NULL; 402 403 if (p4d_is_leaf(p4d)) { 404 ret_pte = (pte_t *)p4dp; 405 goto out; 406 } 407 408 if (is_hugepd(__hugepd(p4d_val(p4d)))) { 409 hpdp = (hugepd_t *)&p4d; 410 goto out_huge; 411 } 412 413 /* 414 * Even if we end up with an unmap, the pgtable will not 415 * be freed, because we do an rcu free and here we are 416 * irq disabled 417 */ 418 pdshift = PUD_SHIFT; 419 pudp = pud_offset(&p4d, ea); 420 pud = READ_ONCE(*pudp); 421 422 if (pud_none(pud)) 423 return NULL; 424 425 if (pud_is_leaf(pud)) { 426 ret_pte = (pte_t *)pudp; 427 goto out; 428 } 429 430 if (is_hugepd(__hugepd(pud_val(pud)))) { 431 hpdp = (hugepd_t *)&pud; 432 goto out_huge; 433 } 434 435 pdshift = PMD_SHIFT; 436 pmdp = pmd_offset(&pud, ea); 437 pmd = READ_ONCE(*pmdp); 438 439 /* 440 * A hugepage collapse is captured by this condition, see 441 * pmdp_collapse_flush. 442 */ 443 if (pmd_none(pmd)) 444 return NULL; 445 446 #ifdef CONFIG_PPC_BOOK3S_64 447 /* 448 * A hugepage split is captured by this condition, see 449 * pmdp_invalidate. 450 * 451 * Huge page modification can be caught here too. 452 */ 453 if (pmd_is_serializing(pmd)) 454 return NULL; 455 #endif 456 457 if (pmd_trans_huge(pmd) || pmd_devmap(pmd)) { 458 if (is_thp) 459 *is_thp = true; 460 ret_pte = (pte_t *)pmdp; 461 goto out; 462 } 463 464 if (pmd_is_leaf(pmd)) { 465 ret_pte = (pte_t *)pmdp; 466 goto out; 467 } 468 469 if (is_hugepd(__hugepd(pmd_val(pmd)))) { 470 hpdp = (hugepd_t *)&pmd; 471 goto out_huge; 472 } 473 474 return pte_offset_kernel(&pmd, ea); 475 476 out_huge: 477 if (!hpdp) 478 return NULL; 479 480 ret_pte = hugepte_offset(*hpdp, ea, pdshift); 481 pdshift = hugepd_shift(*hpdp); 482 out: 483 if (hpage_shift) 484 *hpage_shift = pdshift; 485 return ret_pte; 486 } 487 EXPORT_SYMBOL_GPL(__find_linux_pte); 488 489 /* Note due to the way vm flags are laid out, the bits are XWR */ 490 const pgprot_t protection_map[16] = { 491 [VM_NONE] = PAGE_NONE, 492 [VM_READ] = PAGE_READONLY, 493 [VM_WRITE] = PAGE_COPY, 494 [VM_WRITE | VM_READ] = PAGE_COPY, 495 [VM_EXEC] = PAGE_READONLY_X, 496 [VM_EXEC | VM_READ] = PAGE_READONLY_X, 497 [VM_EXEC | VM_WRITE] = PAGE_COPY_X, 498 [VM_EXEC | VM_WRITE | VM_READ] = PAGE_COPY_X, 499 [VM_SHARED] = PAGE_NONE, 500 [VM_SHARED | VM_READ] = PAGE_READONLY, 501 [VM_SHARED | VM_WRITE] = PAGE_SHARED, 502 [VM_SHARED | VM_WRITE | VM_READ] = PAGE_SHARED, 503 [VM_SHARED | VM_EXEC] = PAGE_READONLY_X, 504 [VM_SHARED | VM_EXEC | VM_READ] = PAGE_READONLY_X, 505 [VM_SHARED | VM_EXEC | VM_WRITE] = PAGE_SHARED_X, 506 [VM_SHARED | VM_EXEC | VM_WRITE | VM_READ] = PAGE_SHARED_X 507 }; 508 509 #ifndef CONFIG_PPC_BOOK3S_64 510 DECLARE_VM_GET_PAGE_PROT 511 #endif 512