1 /* 2 * This file contains common routines for dealing with free of page tables 3 * Along with common page table handling code 4 * 5 * Derived from arch/powerpc/mm/tlb_64.c: 6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 7 * 8 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) 9 * and Cort Dougan (PReP) (cort@cs.nmt.edu) 10 * Copyright (C) 1996 Paul Mackerras 11 * 12 * Derived from "arch/i386/mm/init.c" 13 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds 14 * 15 * Dave Engebretsen <engebret@us.ibm.com> 16 * Rework for PPC64 port. 17 * 18 * This program is free software; you can redistribute it and/or 19 * modify it under the terms of the GNU General Public License 20 * as published by the Free Software Foundation; either version 21 * 2 of the License, or (at your option) any later version. 22 */ 23 24 #include <linux/kernel.h> 25 #include <linux/gfp.h> 26 #include <linux/mm.h> 27 #include <linux/init.h> 28 #include <linux/percpu.h> 29 #include <linux/hardirq.h> 30 #include <asm/pgalloc.h> 31 #include <asm/tlbflush.h> 32 #include <asm/tlb.h> 33 34 #include "mmu_decl.h" 35 36 static inline int is_exec_fault(void) 37 { 38 return current->thread.regs && TRAP(current->thread.regs) == 0x400; 39 } 40 41 /* We only try to do i/d cache coherency on stuff that looks like 42 * reasonably "normal" PTEs. We currently require a PTE to be present 43 * and we avoid _PAGE_SPECIAL and _PAGE_NO_CACHE. We also only do that 44 * on userspace PTEs 45 */ 46 static inline int pte_looks_normal(pte_t pte) 47 { 48 return (pte_val(pte) & 49 (_PAGE_PRESENT | _PAGE_SPECIAL | _PAGE_NO_CACHE | _PAGE_USER)) == 50 (_PAGE_PRESENT | _PAGE_USER); 51 } 52 53 struct page * maybe_pte_to_page(pte_t pte) 54 { 55 unsigned long pfn = pte_pfn(pte); 56 struct page *page; 57 58 if (unlikely(!pfn_valid(pfn))) 59 return NULL; 60 page = pfn_to_page(pfn); 61 if (PageReserved(page)) 62 return NULL; 63 return page; 64 } 65 66 #if defined(CONFIG_PPC_STD_MMU) || _PAGE_EXEC == 0 67 68 /* Server-style MMU handles coherency when hashing if HW exec permission 69 * is supposed per page (currently 64-bit only). If not, then, we always 70 * flush the cache for valid PTEs in set_pte. Embedded CPU without HW exec 71 * support falls into the same category. 72 */ 73 74 static pte_t set_pte_filter(pte_t pte, unsigned long addr) 75 { 76 pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS); 77 if (pte_looks_normal(pte) && !(cpu_has_feature(CPU_FTR_COHERENT_ICACHE) || 78 cpu_has_feature(CPU_FTR_NOEXECUTE))) { 79 struct page *pg = maybe_pte_to_page(pte); 80 if (!pg) 81 return pte; 82 if (!test_bit(PG_arch_1, &pg->flags)) { 83 #ifdef CONFIG_8xx 84 /* On 8xx, cache control instructions (particularly 85 * "dcbst" from flush_dcache_icache) fault as write 86 * operation if there is an unpopulated TLB entry 87 * for the address in question. To workaround that, 88 * we invalidate the TLB here, thus avoiding dcbst 89 * misbehaviour. 90 */ 91 /* 8xx doesn't care about PID, size or ind args */ 92 _tlbil_va(addr, 0, 0, 0); 93 #endif /* CONFIG_8xx */ 94 flush_dcache_icache_page(pg); 95 set_bit(PG_arch_1, &pg->flags); 96 } 97 } 98 return pte; 99 } 100 101 static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma, 102 int dirty) 103 { 104 return pte; 105 } 106 107 #else /* defined(CONFIG_PPC_STD_MMU) || _PAGE_EXEC == 0 */ 108 109 /* Embedded type MMU with HW exec support. This is a bit more complicated 110 * as we don't have two bits to spare for _PAGE_EXEC and _PAGE_HWEXEC so 111 * instead we "filter out" the exec permission for non clean pages. 112 */ 113 static pte_t set_pte_filter(pte_t pte, unsigned long addr) 114 { 115 struct page *pg; 116 117 /* No exec permission in the first place, move on */ 118 if (!(pte_val(pte) & _PAGE_EXEC) || !pte_looks_normal(pte)) 119 return pte; 120 121 /* If you set _PAGE_EXEC on weird pages you're on your own */ 122 pg = maybe_pte_to_page(pte); 123 if (unlikely(!pg)) 124 return pte; 125 126 /* If the page clean, we move on */ 127 if (test_bit(PG_arch_1, &pg->flags)) 128 return pte; 129 130 /* If it's an exec fault, we flush the cache and make it clean */ 131 if (is_exec_fault()) { 132 flush_dcache_icache_page(pg); 133 set_bit(PG_arch_1, &pg->flags); 134 return pte; 135 } 136 137 /* Else, we filter out _PAGE_EXEC */ 138 return __pte(pte_val(pte) & ~_PAGE_EXEC); 139 } 140 141 static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma, 142 int dirty) 143 { 144 struct page *pg; 145 146 /* So here, we only care about exec faults, as we use them 147 * to recover lost _PAGE_EXEC and perform I$/D$ coherency 148 * if necessary. Also if _PAGE_EXEC is already set, same deal, 149 * we just bail out 150 */ 151 if (dirty || (pte_val(pte) & _PAGE_EXEC) || !is_exec_fault()) 152 return pte; 153 154 #ifdef CONFIG_DEBUG_VM 155 /* So this is an exec fault, _PAGE_EXEC is not set. If it was 156 * an error we would have bailed out earlier in do_page_fault() 157 * but let's make sure of it 158 */ 159 if (WARN_ON(!(vma->vm_flags & VM_EXEC))) 160 return pte; 161 #endif /* CONFIG_DEBUG_VM */ 162 163 /* If you set _PAGE_EXEC on weird pages you're on your own */ 164 pg = maybe_pte_to_page(pte); 165 if (unlikely(!pg)) 166 goto bail; 167 168 /* If the page is already clean, we move on */ 169 if (test_bit(PG_arch_1, &pg->flags)) 170 goto bail; 171 172 /* Clean the page and set PG_arch_1 */ 173 flush_dcache_icache_page(pg); 174 set_bit(PG_arch_1, &pg->flags); 175 176 bail: 177 return __pte(pte_val(pte) | _PAGE_EXEC); 178 } 179 180 #endif /* !(defined(CONFIG_PPC_STD_MMU) || _PAGE_EXEC == 0) */ 181 182 /* 183 * set_pte stores a linux PTE into the linux page table. 184 */ 185 void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, 186 pte_t pte) 187 { 188 #ifdef CONFIG_DEBUG_VM 189 WARN_ON(pte_present(*ptep)); 190 #endif 191 /* Note: mm->context.id might not yet have been assigned as 192 * this context might not have been activated yet when this 193 * is called. 194 */ 195 pte = set_pte_filter(pte, addr); 196 197 /* Perform the setting of the PTE */ 198 __set_pte_at(mm, addr, ptep, pte, 0); 199 } 200 201 /* 202 * This is called when relaxing access to a PTE. It's also called in the page 203 * fault path when we don't hit any of the major fault cases, ie, a minor 204 * update of _PAGE_ACCESSED, _PAGE_DIRTY, etc... The generic code will have 205 * handled those two for us, we additionally deal with missing execute 206 * permission here on some processors 207 */ 208 int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address, 209 pte_t *ptep, pte_t entry, int dirty) 210 { 211 int changed; 212 entry = set_access_flags_filter(entry, vma, dirty); 213 changed = !pte_same(*(ptep), entry); 214 if (changed) { 215 if (!(vma->vm_flags & VM_HUGETLB)) 216 assert_pte_locked(vma->vm_mm, address); 217 __ptep_set_access_flags(ptep, entry); 218 flush_tlb_page_nohash(vma, address); 219 } 220 return changed; 221 } 222 223 #ifdef CONFIG_DEBUG_VM 224 void assert_pte_locked(struct mm_struct *mm, unsigned long addr) 225 { 226 pgd_t *pgd; 227 pud_t *pud; 228 pmd_t *pmd; 229 230 if (mm == &init_mm) 231 return; 232 pgd = mm->pgd + pgd_index(addr); 233 BUG_ON(pgd_none(*pgd)); 234 pud = pud_offset(pgd, addr); 235 BUG_ON(pud_none(*pud)); 236 pmd = pmd_offset(pud, addr); 237 BUG_ON(!pmd_present(*pmd)); 238 assert_spin_locked(pte_lockptr(mm, pmd)); 239 } 240 #endif /* CONFIG_DEBUG_VM */ 241 242