xref: /openbmc/linux/arch/powerpc/mm/pgtable.c (revision 0bf49ffb)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * This file contains common routines for dealing with free of page tables
4  * Along with common page table handling code
5  *
6  *  Derived from arch/powerpc/mm/tlb_64.c:
7  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8  *
9  *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
10  *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
11  *    Copyright (C) 1996 Paul Mackerras
12  *
13  *  Derived from "arch/i386/mm/init.c"
14  *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
15  *
16  *  Dave Engebretsen <engebret@us.ibm.com>
17  *      Rework for PPC64 port.
18  */
19 
20 #include <linux/kernel.h>
21 #include <linux/gfp.h>
22 #include <linux/mm.h>
23 #include <linux/percpu.h>
24 #include <linux/hardirq.h>
25 #include <linux/hugetlb.h>
26 #include <asm/tlbflush.h>
27 #include <asm/tlb.h>
28 #include <asm/hugetlb.h>
29 #include <asm/pte-walk.h>
30 
31 static inline int is_exec_fault(void)
32 {
33 	return current->thread.regs && TRAP(current->thread.regs) == 0x400;
34 }
35 
36 /* We only try to do i/d cache coherency on stuff that looks like
37  * reasonably "normal" PTEs. We currently require a PTE to be present
38  * and we avoid _PAGE_SPECIAL and cache inhibited pte. We also only do that
39  * on userspace PTEs
40  */
41 static inline int pte_looks_normal(pte_t pte)
42 {
43 
44 	if (pte_present(pte) && !pte_special(pte)) {
45 		if (pte_ci(pte))
46 			return 0;
47 		if (pte_user(pte))
48 			return 1;
49 	}
50 	return 0;
51 }
52 
53 static struct page *maybe_pte_to_page(pte_t pte)
54 {
55 	unsigned long pfn = pte_pfn(pte);
56 	struct page *page;
57 
58 	if (unlikely(!pfn_valid(pfn)))
59 		return NULL;
60 	page = pfn_to_page(pfn);
61 	if (PageReserved(page))
62 		return NULL;
63 	return page;
64 }
65 
66 #ifdef CONFIG_PPC_BOOK3S
67 
68 /* Server-style MMU handles coherency when hashing if HW exec permission
69  * is supposed per page (currently 64-bit only). If not, then, we always
70  * flush the cache for valid PTEs in set_pte. Embedded CPU without HW exec
71  * support falls into the same category.
72  */
73 
74 static pte_t set_pte_filter_hash(pte_t pte)
75 {
76 	if (radix_enabled())
77 		return pte;
78 
79 	pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
80 	if (pte_looks_normal(pte) && !(cpu_has_feature(CPU_FTR_COHERENT_ICACHE) ||
81 				       cpu_has_feature(CPU_FTR_NOEXECUTE))) {
82 		struct page *pg = maybe_pte_to_page(pte);
83 		if (!pg)
84 			return pte;
85 		if (!test_bit(PG_dcache_clean, &pg->flags)) {
86 			flush_dcache_icache_page(pg);
87 			set_bit(PG_dcache_clean, &pg->flags);
88 		}
89 	}
90 	return pte;
91 }
92 
93 #else /* CONFIG_PPC_BOOK3S */
94 
95 static pte_t set_pte_filter_hash(pte_t pte) { return pte; }
96 
97 #endif /* CONFIG_PPC_BOOK3S */
98 
99 /* Embedded type MMU with HW exec support. This is a bit more complicated
100  * as we don't have two bits to spare for _PAGE_EXEC and _PAGE_HWEXEC so
101  * instead we "filter out" the exec permission for non clean pages.
102  */
103 static inline pte_t set_pte_filter(pte_t pte)
104 {
105 	struct page *pg;
106 
107 	if (mmu_has_feature(MMU_FTR_HPTE_TABLE))
108 		return set_pte_filter_hash(pte);
109 
110 	/* No exec permission in the first place, move on */
111 	if (!pte_exec(pte) || !pte_looks_normal(pte))
112 		return pte;
113 
114 	/* If you set _PAGE_EXEC on weird pages you're on your own */
115 	pg = maybe_pte_to_page(pte);
116 	if (unlikely(!pg))
117 		return pte;
118 
119 	/* If the page clean, we move on */
120 	if (test_bit(PG_dcache_clean, &pg->flags))
121 		return pte;
122 
123 	/* If it's an exec fault, we flush the cache and make it clean */
124 	if (is_exec_fault()) {
125 		flush_dcache_icache_page(pg);
126 		set_bit(PG_dcache_clean, &pg->flags);
127 		return pte;
128 	}
129 
130 	/* Else, we filter out _PAGE_EXEC */
131 	return pte_exprotect(pte);
132 }
133 
134 static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma,
135 				     int dirty)
136 {
137 	struct page *pg;
138 
139 	if (mmu_has_feature(MMU_FTR_HPTE_TABLE))
140 		return pte;
141 
142 	/* So here, we only care about exec faults, as we use them
143 	 * to recover lost _PAGE_EXEC and perform I$/D$ coherency
144 	 * if necessary. Also if _PAGE_EXEC is already set, same deal,
145 	 * we just bail out
146 	 */
147 	if (dirty || pte_exec(pte) || !is_exec_fault())
148 		return pte;
149 
150 #ifdef CONFIG_DEBUG_VM
151 	/* So this is an exec fault, _PAGE_EXEC is not set. If it was
152 	 * an error we would have bailed out earlier in do_page_fault()
153 	 * but let's make sure of it
154 	 */
155 	if (WARN_ON(!(vma->vm_flags & VM_EXEC)))
156 		return pte;
157 #endif /* CONFIG_DEBUG_VM */
158 
159 	/* If you set _PAGE_EXEC on weird pages you're on your own */
160 	pg = maybe_pte_to_page(pte);
161 	if (unlikely(!pg))
162 		goto bail;
163 
164 	/* If the page is already clean, we move on */
165 	if (test_bit(PG_dcache_clean, &pg->flags))
166 		goto bail;
167 
168 	/* Clean the page and set PG_dcache_clean */
169 	flush_dcache_icache_page(pg);
170 	set_bit(PG_dcache_clean, &pg->flags);
171 
172  bail:
173 	return pte_mkexec(pte);
174 }
175 
176 /*
177  * set_pte stores a linux PTE into the linux page table.
178  */
179 void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
180 		pte_t pte)
181 {
182 	/*
183 	 * Make sure hardware valid bit is not set. We don't do
184 	 * tlb flush for this update.
185 	 */
186 	VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep));
187 
188 	/* Note: mm->context.id might not yet have been assigned as
189 	 * this context might not have been activated yet when this
190 	 * is called.
191 	 */
192 	pte = set_pte_filter(pte);
193 
194 	/* Perform the setting of the PTE */
195 	__set_pte_at(mm, addr, ptep, pte, 0);
196 }
197 
198 /*
199  * This is called when relaxing access to a PTE. It's also called in the page
200  * fault path when we don't hit any of the major fault cases, ie, a minor
201  * update of _PAGE_ACCESSED, _PAGE_DIRTY, etc... The generic code will have
202  * handled those two for us, we additionally deal with missing execute
203  * permission here on some processors
204  */
205 int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
206 			  pte_t *ptep, pte_t entry, int dirty)
207 {
208 	int changed;
209 	entry = set_access_flags_filter(entry, vma, dirty);
210 	changed = !pte_same(*(ptep), entry);
211 	if (changed) {
212 		assert_pte_locked(vma->vm_mm, address);
213 		__ptep_set_access_flags(vma, ptep, entry,
214 					address, mmu_virtual_psize);
215 	}
216 	return changed;
217 }
218 
219 #ifdef CONFIG_HUGETLB_PAGE
220 int huge_ptep_set_access_flags(struct vm_area_struct *vma,
221 			       unsigned long addr, pte_t *ptep,
222 			       pte_t pte, int dirty)
223 {
224 #ifdef HUGETLB_NEED_PRELOAD
225 	/*
226 	 * The "return 1" forces a call of update_mmu_cache, which will write a
227 	 * TLB entry.  Without this, platforms that don't do a write of the TLB
228 	 * entry in the TLB miss handler asm will fault ad infinitum.
229 	 */
230 	ptep_set_access_flags(vma, addr, ptep, pte, dirty);
231 	return 1;
232 #else
233 	int changed, psize;
234 
235 	pte = set_access_flags_filter(pte, vma, dirty);
236 	changed = !pte_same(*(ptep), pte);
237 	if (changed) {
238 
239 #ifdef CONFIG_PPC_BOOK3S_64
240 		struct hstate *h = hstate_vma(vma);
241 
242 		psize = hstate_get_psize(h);
243 #ifdef CONFIG_DEBUG_VM
244 		assert_spin_locked(huge_pte_lockptr(h, vma->vm_mm, ptep));
245 #endif
246 
247 #else
248 		/*
249 		 * Not used on non book3s64 platforms.
250 		 * 8xx compares it with mmu_virtual_psize to
251 		 * know if it is a huge page or not.
252 		 */
253 		psize = MMU_PAGE_COUNT;
254 #endif
255 		__ptep_set_access_flags(vma, ptep, pte, addr, psize);
256 	}
257 	return changed;
258 #endif
259 }
260 
261 #if defined(CONFIG_PPC_8xx)
262 void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
263 {
264 	pmd_t *pmd = pmd_off(mm, addr);
265 	pte_basic_t val;
266 	pte_basic_t *entry = &ptep->pte;
267 	int num, i;
268 
269 	/*
270 	 * Make sure hardware valid bit is not set. We don't do
271 	 * tlb flush for this update.
272 	 */
273 	VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep));
274 
275 	pte = set_pte_filter(pte);
276 
277 	val = pte_val(pte);
278 
279 	num = number_of_cells_per_pte(pmd, val, 1);
280 
281 	for (i = 0; i < num; i++, entry++, val += SZ_4K)
282 		*entry = val;
283 }
284 #endif
285 #endif /* CONFIG_HUGETLB_PAGE */
286 
287 #ifdef CONFIG_DEBUG_VM
288 void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
289 {
290 	pgd_t *pgd;
291 	p4d_t *p4d;
292 	pud_t *pud;
293 	pmd_t *pmd;
294 
295 	if (mm == &init_mm)
296 		return;
297 	pgd = mm->pgd + pgd_index(addr);
298 	BUG_ON(pgd_none(*pgd));
299 	p4d = p4d_offset(pgd, addr);
300 	BUG_ON(p4d_none(*p4d));
301 	pud = pud_offset(p4d, addr);
302 	BUG_ON(pud_none(*pud));
303 	pmd = pmd_offset(pud, addr);
304 	/*
305 	 * khugepaged to collapse normal pages to hugepage, first set
306 	 * pmd to none to force page fault/gup to take mmap_lock. After
307 	 * pmd is set to none, we do a pte_clear which does this assertion
308 	 * so if we find pmd none, return.
309 	 */
310 	if (pmd_none(*pmd))
311 		return;
312 	BUG_ON(!pmd_present(*pmd));
313 	assert_spin_locked(pte_lockptr(mm, pmd));
314 }
315 #endif /* CONFIG_DEBUG_VM */
316 
317 unsigned long vmalloc_to_phys(void *va)
318 {
319 	unsigned long pfn = vmalloc_to_pfn(va);
320 
321 	BUG_ON(!pfn);
322 	return __pa(pfn_to_kaddr(pfn)) + offset_in_page(va);
323 }
324 EXPORT_SYMBOL_GPL(vmalloc_to_phys);
325 
326 /*
327  * We have 4 cases for pgds and pmds:
328  * (1) invalid (all zeroes)
329  * (2) pointer to next table, as normal; bottom 6 bits == 0
330  * (3) leaf pte for huge page _PAGE_PTE set
331  * (4) hugepd pointer, _PAGE_PTE = 0 and bits [2..6] indicate size of table
332  *
333  * So long as we atomically load page table pointers we are safe against teardown,
334  * we can follow the address down to the the page and take a ref on it.
335  * This function need to be called with interrupts disabled. We use this variant
336  * when we have MSR[EE] = 0 but the paca->irq_soft_mask = IRQS_ENABLED
337  */
338 pte_t *__find_linux_pte(pgd_t *pgdir, unsigned long ea,
339 			bool *is_thp, unsigned *hpage_shift)
340 {
341 	pgd_t *pgdp;
342 	p4d_t p4d, *p4dp;
343 	pud_t pud, *pudp;
344 	pmd_t pmd, *pmdp;
345 	pte_t *ret_pte;
346 	hugepd_t *hpdp = NULL;
347 	unsigned pdshift;
348 
349 	if (hpage_shift)
350 		*hpage_shift = 0;
351 
352 	if (is_thp)
353 		*is_thp = false;
354 
355 	/*
356 	 * Always operate on the local stack value. This make sure the
357 	 * value don't get updated by a parallel THP split/collapse,
358 	 * page fault or a page unmap. The return pte_t * is still not
359 	 * stable. So should be checked there for above conditions.
360 	 * Top level is an exception because it is folded into p4d.
361 	 */
362 	pgdp = pgdir + pgd_index(ea);
363 	p4dp = p4d_offset(pgdp, ea);
364 	p4d  = READ_ONCE(*p4dp);
365 	pdshift = P4D_SHIFT;
366 
367 	if (p4d_none(p4d))
368 		return NULL;
369 
370 	if (p4d_is_leaf(p4d)) {
371 		ret_pte = (pte_t *)p4dp;
372 		goto out;
373 	}
374 
375 	if (is_hugepd(__hugepd(p4d_val(p4d)))) {
376 		hpdp = (hugepd_t *)&p4d;
377 		goto out_huge;
378 	}
379 
380 	/*
381 	 * Even if we end up with an unmap, the pgtable will not
382 	 * be freed, because we do an rcu free and here we are
383 	 * irq disabled
384 	 */
385 	pdshift = PUD_SHIFT;
386 	pudp = pud_offset(&p4d, ea);
387 	pud  = READ_ONCE(*pudp);
388 
389 	if (pud_none(pud))
390 		return NULL;
391 
392 	if (pud_is_leaf(pud)) {
393 		ret_pte = (pte_t *)pudp;
394 		goto out;
395 	}
396 
397 	if (is_hugepd(__hugepd(pud_val(pud)))) {
398 		hpdp = (hugepd_t *)&pud;
399 		goto out_huge;
400 	}
401 
402 	pdshift = PMD_SHIFT;
403 	pmdp = pmd_offset(&pud, ea);
404 	pmd  = READ_ONCE(*pmdp);
405 
406 	/*
407 	 * A hugepage collapse is captured by this condition, see
408 	 * pmdp_collapse_flush.
409 	 */
410 	if (pmd_none(pmd))
411 		return NULL;
412 
413 #ifdef CONFIG_PPC_BOOK3S_64
414 	/*
415 	 * A hugepage split is captured by this condition, see
416 	 * pmdp_invalidate.
417 	 *
418 	 * Huge page modification can be caught here too.
419 	 */
420 	if (pmd_is_serializing(pmd))
421 		return NULL;
422 #endif
423 
424 	if (pmd_trans_huge(pmd) || pmd_devmap(pmd)) {
425 		if (is_thp)
426 			*is_thp = true;
427 		ret_pte = (pte_t *)pmdp;
428 		goto out;
429 	}
430 
431 	if (pmd_is_leaf(pmd)) {
432 		ret_pte = (pte_t *)pmdp;
433 		goto out;
434 	}
435 
436 	if (is_hugepd(__hugepd(pmd_val(pmd)))) {
437 		hpdp = (hugepd_t *)&pmd;
438 		goto out_huge;
439 	}
440 
441 	return pte_offset_kernel(&pmd, ea);
442 
443 out_huge:
444 	if (!hpdp)
445 		return NULL;
446 
447 	ret_pte = hugepte_offset(*hpdp, ea, pdshift);
448 	pdshift = hugepd_shift(*hpdp);
449 out:
450 	if (hpage_shift)
451 		*hpage_shift = pdshift;
452 	return ret_pte;
453 }
454 EXPORT_SYMBOL_GPL(__find_linux_pte);
455