1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * This file contains the routines for TLB flushing. 4 * On machines where the MMU does not use a hash table to store virtual to 5 * physical translations (ie, SW loaded TLBs or Book3E compilant processors, 6 * this does -not- include 603 however which shares the implementation with 7 * hash based processors) 8 * 9 * -- BenH 10 * 11 * Copyright 2008,2009 Ben Herrenschmidt <benh@kernel.crashing.org> 12 * IBM Corp. 13 * 14 * Derived from arch/ppc/mm/init.c: 15 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 16 * 17 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) 18 * and Cort Dougan (PReP) (cort@cs.nmt.edu) 19 * Copyright (C) 1996 Paul Mackerras 20 * 21 * Derived from "arch/i386/mm/init.c" 22 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds 23 */ 24 25 #include <linux/kernel.h> 26 #include <linux/export.h> 27 #include <linux/mm.h> 28 #include <linux/init.h> 29 #include <linux/highmem.h> 30 #include <linux/pagemap.h> 31 #include <linux/preempt.h> 32 #include <linux/spinlock.h> 33 #include <linux/memblock.h> 34 #include <linux/of_fdt.h> 35 #include <linux/hugetlb.h> 36 37 #include <asm/pgalloc.h> 38 #include <asm/tlbflush.h> 39 #include <asm/tlb.h> 40 #include <asm/code-patching.h> 41 #include <asm/cputhreads.h> 42 #include <asm/hugetlb.h> 43 #include <asm/paca.h> 44 45 #include <mm/mmu_decl.h> 46 47 /* 48 * This struct lists the sw-supported page sizes. The hardawre MMU may support 49 * other sizes not listed here. The .ind field is only used on MMUs that have 50 * indirect page table entries. 51 */ 52 #if defined(CONFIG_PPC_BOOK3E_MMU) || defined(CONFIG_PPC_8xx) 53 #ifdef CONFIG_PPC_FSL_BOOK3E 54 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = { 55 [MMU_PAGE_4K] = { 56 .shift = 12, 57 .enc = BOOK3E_PAGESZ_4K, 58 }, 59 [MMU_PAGE_2M] = { 60 .shift = 21, 61 .enc = BOOK3E_PAGESZ_2M, 62 }, 63 [MMU_PAGE_4M] = { 64 .shift = 22, 65 .enc = BOOK3E_PAGESZ_4M, 66 }, 67 [MMU_PAGE_16M] = { 68 .shift = 24, 69 .enc = BOOK3E_PAGESZ_16M, 70 }, 71 [MMU_PAGE_64M] = { 72 .shift = 26, 73 .enc = BOOK3E_PAGESZ_64M, 74 }, 75 [MMU_PAGE_256M] = { 76 .shift = 28, 77 .enc = BOOK3E_PAGESZ_256M, 78 }, 79 [MMU_PAGE_1G] = { 80 .shift = 30, 81 .enc = BOOK3E_PAGESZ_1GB, 82 }, 83 }; 84 #elif defined(CONFIG_PPC_8xx) 85 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = { 86 [MMU_PAGE_4K] = { 87 .shift = 12, 88 }, 89 [MMU_PAGE_16K] = { 90 .shift = 14, 91 }, 92 [MMU_PAGE_512K] = { 93 .shift = 19, 94 }, 95 [MMU_PAGE_8M] = { 96 .shift = 23, 97 }, 98 }; 99 #else 100 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = { 101 [MMU_PAGE_4K] = { 102 .shift = 12, 103 .ind = 20, 104 .enc = BOOK3E_PAGESZ_4K, 105 }, 106 [MMU_PAGE_16K] = { 107 .shift = 14, 108 .enc = BOOK3E_PAGESZ_16K, 109 }, 110 [MMU_PAGE_64K] = { 111 .shift = 16, 112 .ind = 28, 113 .enc = BOOK3E_PAGESZ_64K, 114 }, 115 [MMU_PAGE_1M] = { 116 .shift = 20, 117 .enc = BOOK3E_PAGESZ_1M, 118 }, 119 [MMU_PAGE_16M] = { 120 .shift = 24, 121 .ind = 36, 122 .enc = BOOK3E_PAGESZ_16M, 123 }, 124 [MMU_PAGE_256M] = { 125 .shift = 28, 126 .enc = BOOK3E_PAGESZ_256M, 127 }, 128 [MMU_PAGE_1G] = { 129 .shift = 30, 130 .enc = BOOK3E_PAGESZ_1GB, 131 }, 132 }; 133 #endif /* CONFIG_FSL_BOOKE */ 134 135 static inline int mmu_get_tsize(int psize) 136 { 137 return mmu_psize_defs[psize].enc; 138 } 139 #else 140 static inline int mmu_get_tsize(int psize) 141 { 142 /* This isn't used on !Book3E for now */ 143 return 0; 144 } 145 #endif /* CONFIG_PPC_BOOK3E_MMU */ 146 147 /* The variables below are currently only used on 64-bit Book3E 148 * though this will probably be made common with other nohash 149 * implementations at some point 150 */ 151 #ifdef CONFIG_PPC64 152 153 int mmu_pte_psize; /* Page size used for PTE pages */ 154 int mmu_vmemmap_psize; /* Page size used for the virtual mem map */ 155 int book3e_htw_mode; /* HW tablewalk? Value is PPC_HTW_* */ 156 unsigned long linear_map_top; /* Top of linear mapping */ 157 158 159 /* 160 * Number of bytes to add to SPRN_SPRG_TLB_EXFRAME on crit/mcheck/debug 161 * exceptions. This is used for bolted and e6500 TLB miss handlers which 162 * do not modify this SPRG in the TLB miss code; for other TLB miss handlers, 163 * this is set to zero. 164 */ 165 int extlb_level_exc; 166 167 #endif /* CONFIG_PPC64 */ 168 169 #ifdef CONFIG_PPC_FSL_BOOK3E 170 /* next_tlbcam_idx is used to round-robin tlbcam entry assignment */ 171 DEFINE_PER_CPU(int, next_tlbcam_idx); 172 EXPORT_PER_CPU_SYMBOL(next_tlbcam_idx); 173 #endif 174 175 /* 176 * Base TLB flushing operations: 177 * 178 * - flush_tlb_mm(mm) flushes the specified mm context TLB's 179 * - flush_tlb_page(vma, vmaddr) flushes one page 180 * - flush_tlb_range(vma, start, end) flushes a range of pages 181 * - flush_tlb_kernel_range(start, end) flushes kernel pages 182 * 183 * - local_* variants of page and mm only apply to the current 184 * processor 185 */ 186 187 #ifndef CONFIG_PPC_8xx 188 /* 189 * These are the base non-SMP variants of page and mm flushing 190 */ 191 void local_flush_tlb_mm(struct mm_struct *mm) 192 { 193 unsigned int pid; 194 195 preempt_disable(); 196 pid = mm->context.id; 197 if (pid != MMU_NO_CONTEXT) 198 _tlbil_pid(pid); 199 preempt_enable(); 200 } 201 EXPORT_SYMBOL(local_flush_tlb_mm); 202 203 void __local_flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr, 204 int tsize, int ind) 205 { 206 unsigned int pid; 207 208 preempt_disable(); 209 pid = mm ? mm->context.id : 0; 210 if (pid != MMU_NO_CONTEXT) 211 _tlbil_va(vmaddr, pid, tsize, ind); 212 preempt_enable(); 213 } 214 215 void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr) 216 { 217 __local_flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr, 218 mmu_get_tsize(mmu_virtual_psize), 0); 219 } 220 EXPORT_SYMBOL(local_flush_tlb_page); 221 #endif 222 223 /* 224 * And here are the SMP non-local implementations 225 */ 226 #ifdef CONFIG_SMP 227 228 static DEFINE_RAW_SPINLOCK(tlbivax_lock); 229 230 struct tlb_flush_param { 231 unsigned long addr; 232 unsigned int pid; 233 unsigned int tsize; 234 unsigned int ind; 235 }; 236 237 static void do_flush_tlb_mm_ipi(void *param) 238 { 239 struct tlb_flush_param *p = param; 240 241 _tlbil_pid(p ? p->pid : 0); 242 } 243 244 static void do_flush_tlb_page_ipi(void *param) 245 { 246 struct tlb_flush_param *p = param; 247 248 _tlbil_va(p->addr, p->pid, p->tsize, p->ind); 249 } 250 251 252 /* Note on invalidations and PID: 253 * 254 * We snapshot the PID with preempt disabled. At this point, it can still 255 * change either because: 256 * - our context is being stolen (PID -> NO_CONTEXT) on another CPU 257 * - we are invaliating some target that isn't currently running here 258 * and is concurrently acquiring a new PID on another CPU 259 * - some other CPU is re-acquiring a lost PID for this mm 260 * etc... 261 * 262 * However, this shouldn't be a problem as we only guarantee 263 * invalidation of TLB entries present prior to this call, so we 264 * don't care about the PID changing, and invalidating a stale PID 265 * is generally harmless. 266 */ 267 268 void flush_tlb_mm(struct mm_struct *mm) 269 { 270 unsigned int pid; 271 272 preempt_disable(); 273 pid = mm->context.id; 274 if (unlikely(pid == MMU_NO_CONTEXT)) 275 goto no_context; 276 if (!mm_is_core_local(mm)) { 277 struct tlb_flush_param p = { .pid = pid }; 278 /* Ignores smp_processor_id() even if set. */ 279 smp_call_function_many(mm_cpumask(mm), 280 do_flush_tlb_mm_ipi, &p, 1); 281 } 282 _tlbil_pid(pid); 283 no_context: 284 preempt_enable(); 285 } 286 EXPORT_SYMBOL(flush_tlb_mm); 287 288 void __flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr, 289 int tsize, int ind) 290 { 291 struct cpumask *cpu_mask; 292 unsigned int pid; 293 294 /* 295 * This function as well as __local_flush_tlb_page() must only be called 296 * for user contexts. 297 */ 298 if (WARN_ON(!mm)) 299 return; 300 301 preempt_disable(); 302 pid = mm->context.id; 303 if (unlikely(pid == MMU_NO_CONTEXT)) 304 goto bail; 305 cpu_mask = mm_cpumask(mm); 306 if (!mm_is_core_local(mm)) { 307 /* If broadcast tlbivax is supported, use it */ 308 if (mmu_has_feature(MMU_FTR_USE_TLBIVAX_BCAST)) { 309 int lock = mmu_has_feature(MMU_FTR_LOCK_BCAST_INVAL); 310 if (lock) 311 raw_spin_lock(&tlbivax_lock); 312 _tlbivax_bcast(vmaddr, pid, tsize, ind); 313 if (lock) 314 raw_spin_unlock(&tlbivax_lock); 315 goto bail; 316 } else { 317 struct tlb_flush_param p = { 318 .pid = pid, 319 .addr = vmaddr, 320 .tsize = tsize, 321 .ind = ind, 322 }; 323 /* Ignores smp_processor_id() even if set in cpu_mask */ 324 smp_call_function_many(cpu_mask, 325 do_flush_tlb_page_ipi, &p, 1); 326 } 327 } 328 _tlbil_va(vmaddr, pid, tsize, ind); 329 bail: 330 preempt_enable(); 331 } 332 333 void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr) 334 { 335 #ifdef CONFIG_HUGETLB_PAGE 336 if (vma && is_vm_hugetlb_page(vma)) 337 flush_hugetlb_page(vma, vmaddr); 338 #endif 339 340 __flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr, 341 mmu_get_tsize(mmu_virtual_psize), 0); 342 } 343 EXPORT_SYMBOL(flush_tlb_page); 344 345 #endif /* CONFIG_SMP */ 346 347 #ifdef CONFIG_PPC_47x 348 void __init early_init_mmu_47x(void) 349 { 350 #ifdef CONFIG_SMP 351 unsigned long root = of_get_flat_dt_root(); 352 if (of_get_flat_dt_prop(root, "cooperative-partition", NULL)) 353 mmu_clear_feature(MMU_FTR_USE_TLBIVAX_BCAST); 354 #endif /* CONFIG_SMP */ 355 } 356 #endif /* CONFIG_PPC_47x */ 357 358 /* 359 * Flush kernel TLB entries in the given range 360 */ 361 void flush_tlb_kernel_range(unsigned long start, unsigned long end) 362 { 363 #ifdef CONFIG_SMP 364 preempt_disable(); 365 smp_call_function(do_flush_tlb_mm_ipi, NULL, 1); 366 _tlbil_pid(0); 367 preempt_enable(); 368 #else 369 _tlbil_pid(0); 370 #endif 371 } 372 EXPORT_SYMBOL(flush_tlb_kernel_range); 373 374 /* 375 * Currently, for range flushing, we just do a full mm flush. This should 376 * be optimized based on a threshold on the size of the range, since 377 * some implementation can stack multiple tlbivax before a tlbsync but 378 * for now, we keep it that way 379 */ 380 void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, 381 unsigned long end) 382 383 { 384 if (end - start == PAGE_SIZE && !(start & ~PAGE_MASK)) 385 flush_tlb_page(vma, start); 386 else 387 flush_tlb_mm(vma->vm_mm); 388 } 389 EXPORT_SYMBOL(flush_tlb_range); 390 391 void tlb_flush(struct mmu_gather *tlb) 392 { 393 flush_tlb_mm(tlb->mm); 394 } 395 396 /* 397 * Below are functions specific to the 64-bit variant of Book3E though that 398 * may change in the future 399 */ 400 401 #ifdef CONFIG_PPC64 402 403 /* 404 * Handling of virtual linear page tables or indirect TLB entries 405 * flushing when PTE pages are freed 406 */ 407 void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address) 408 { 409 int tsize = mmu_psize_defs[mmu_pte_psize].enc; 410 411 if (book3e_htw_mode != PPC_HTW_NONE) { 412 unsigned long start = address & PMD_MASK; 413 unsigned long end = address + PMD_SIZE; 414 unsigned long size = 1UL << mmu_psize_defs[mmu_pte_psize].shift; 415 416 /* This isn't the most optimal, ideally we would factor out the 417 * while preempt & CPU mask mucking around, or even the IPI but 418 * it will do for now 419 */ 420 while (start < end) { 421 __flush_tlb_page(tlb->mm, start, tsize, 1); 422 start += size; 423 } 424 } else { 425 unsigned long rmask = 0xf000000000000000ul; 426 unsigned long rid = (address & rmask) | 0x1000000000000000ul; 427 unsigned long vpte = address & ~rmask; 428 429 vpte = (vpte >> (PAGE_SHIFT - 3)) & ~0xffful; 430 vpte |= rid; 431 __flush_tlb_page(tlb->mm, vpte, tsize, 0); 432 } 433 } 434 435 static void __init setup_page_sizes(void) 436 { 437 unsigned int tlb0cfg; 438 unsigned int tlb0ps; 439 unsigned int eptcfg; 440 int i, psize; 441 442 #ifdef CONFIG_PPC_FSL_BOOK3E 443 unsigned int mmucfg = mfspr(SPRN_MMUCFG); 444 int fsl_mmu = mmu_has_feature(MMU_FTR_TYPE_FSL_E); 445 446 if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) { 447 unsigned int tlb1cfg = mfspr(SPRN_TLB1CFG); 448 unsigned int min_pg, max_pg; 449 450 min_pg = (tlb1cfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT; 451 max_pg = (tlb1cfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT; 452 453 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) { 454 struct mmu_psize_def *def; 455 unsigned int shift; 456 457 def = &mmu_psize_defs[psize]; 458 shift = def->shift; 459 460 if (shift == 0 || shift & 1) 461 continue; 462 463 /* adjust to be in terms of 4^shift Kb */ 464 shift = (shift - 10) >> 1; 465 466 if ((shift >= min_pg) && (shift <= max_pg)) 467 def->flags |= MMU_PAGE_SIZE_DIRECT; 468 } 469 470 goto out; 471 } 472 473 if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V2) { 474 u32 tlb1cfg, tlb1ps; 475 476 tlb0cfg = mfspr(SPRN_TLB0CFG); 477 tlb1cfg = mfspr(SPRN_TLB1CFG); 478 tlb1ps = mfspr(SPRN_TLB1PS); 479 eptcfg = mfspr(SPRN_EPTCFG); 480 481 if ((tlb1cfg & TLBnCFG_IND) && (tlb0cfg & TLBnCFG_PT)) 482 book3e_htw_mode = PPC_HTW_E6500; 483 484 /* 485 * We expect 4K subpage size and unrestricted indirect size. 486 * The lack of a restriction on indirect size is a Freescale 487 * extension, indicated by PSn = 0 but SPSn != 0. 488 */ 489 if (eptcfg != 2) 490 book3e_htw_mode = PPC_HTW_NONE; 491 492 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) { 493 struct mmu_psize_def *def = &mmu_psize_defs[psize]; 494 495 if (!def->shift) 496 continue; 497 498 if (tlb1ps & (1U << (def->shift - 10))) { 499 def->flags |= MMU_PAGE_SIZE_DIRECT; 500 501 if (book3e_htw_mode && psize == MMU_PAGE_2M) 502 def->flags |= MMU_PAGE_SIZE_INDIRECT; 503 } 504 } 505 506 goto out; 507 } 508 #endif 509 510 tlb0cfg = mfspr(SPRN_TLB0CFG); 511 tlb0ps = mfspr(SPRN_TLB0PS); 512 eptcfg = mfspr(SPRN_EPTCFG); 513 514 /* Look for supported direct sizes */ 515 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) { 516 struct mmu_psize_def *def = &mmu_psize_defs[psize]; 517 518 if (tlb0ps & (1U << (def->shift - 10))) 519 def->flags |= MMU_PAGE_SIZE_DIRECT; 520 } 521 522 /* Indirect page sizes supported ? */ 523 if ((tlb0cfg & TLBnCFG_IND) == 0 || 524 (tlb0cfg & TLBnCFG_PT) == 0) 525 goto out; 526 527 book3e_htw_mode = PPC_HTW_IBM; 528 529 /* Now, we only deal with one IND page size for each 530 * direct size. Hopefully all implementations today are 531 * unambiguous, but we might want to be careful in the 532 * future. 533 */ 534 for (i = 0; i < 3; i++) { 535 unsigned int ps, sps; 536 537 sps = eptcfg & 0x1f; 538 eptcfg >>= 5; 539 ps = eptcfg & 0x1f; 540 eptcfg >>= 5; 541 if (!ps || !sps) 542 continue; 543 for (psize = 0; psize < MMU_PAGE_COUNT; psize++) { 544 struct mmu_psize_def *def = &mmu_psize_defs[psize]; 545 546 if (ps == (def->shift - 10)) 547 def->flags |= MMU_PAGE_SIZE_INDIRECT; 548 if (sps == (def->shift - 10)) 549 def->ind = ps + 10; 550 } 551 } 552 553 out: 554 /* Cleanup array and print summary */ 555 pr_info("MMU: Supported page sizes\n"); 556 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) { 557 struct mmu_psize_def *def = &mmu_psize_defs[psize]; 558 const char *__page_type_names[] = { 559 "unsupported", 560 "direct", 561 "indirect", 562 "direct & indirect" 563 }; 564 if (def->flags == 0) { 565 def->shift = 0; 566 continue; 567 } 568 pr_info(" %8ld KB as %s\n", 1ul << (def->shift - 10), 569 __page_type_names[def->flags & 0x3]); 570 } 571 } 572 573 static void __init setup_mmu_htw(void) 574 { 575 /* 576 * If we want to use HW tablewalk, enable it by patching the TLB miss 577 * handlers to branch to the one dedicated to it. 578 */ 579 580 switch (book3e_htw_mode) { 581 case PPC_HTW_IBM: 582 patch_exception(0x1c0, exc_data_tlb_miss_htw_book3e); 583 patch_exception(0x1e0, exc_instruction_tlb_miss_htw_book3e); 584 break; 585 #ifdef CONFIG_PPC_FSL_BOOK3E 586 case PPC_HTW_E6500: 587 extlb_level_exc = EX_TLB_SIZE; 588 patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e); 589 patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e); 590 break; 591 #endif 592 } 593 pr_info("MMU: Book3E HW tablewalk %s\n", 594 book3e_htw_mode != PPC_HTW_NONE ? "enabled" : "not supported"); 595 } 596 597 /* 598 * Early initialization of the MMU TLB code 599 */ 600 static void early_init_this_mmu(void) 601 { 602 unsigned int mas4; 603 604 /* Set MAS4 based on page table setting */ 605 606 mas4 = 0x4 << MAS4_WIMGED_SHIFT; 607 switch (book3e_htw_mode) { 608 case PPC_HTW_E6500: 609 mas4 |= MAS4_INDD; 610 mas4 |= BOOK3E_PAGESZ_2M << MAS4_TSIZED_SHIFT; 611 mas4 |= MAS4_TLBSELD(1); 612 mmu_pte_psize = MMU_PAGE_2M; 613 break; 614 615 case PPC_HTW_IBM: 616 mas4 |= MAS4_INDD; 617 mas4 |= BOOK3E_PAGESZ_1M << MAS4_TSIZED_SHIFT; 618 mmu_pte_psize = MMU_PAGE_1M; 619 break; 620 621 case PPC_HTW_NONE: 622 mas4 |= BOOK3E_PAGESZ_4K << MAS4_TSIZED_SHIFT; 623 mmu_pte_psize = mmu_virtual_psize; 624 break; 625 } 626 mtspr(SPRN_MAS4, mas4); 627 628 #ifdef CONFIG_PPC_FSL_BOOK3E 629 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) { 630 unsigned int num_cams; 631 bool map = true; 632 633 /* use a quarter of the TLBCAM for bolted linear map */ 634 num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4; 635 636 /* 637 * Only do the mapping once per core, or else the 638 * transient mapping would cause problems. 639 */ 640 #ifdef CONFIG_SMP 641 if (hweight32(get_tensr()) > 1) 642 map = false; 643 #endif 644 645 if (map) 646 linear_map_top = map_mem_in_cams(linear_map_top, 647 num_cams, false, true); 648 } 649 #endif 650 651 /* A sync won't hurt us after mucking around with 652 * the MMU configuration 653 */ 654 mb(); 655 } 656 657 static void __init early_init_mmu_global(void) 658 { 659 /* XXX This should be decided at runtime based on supported 660 * page sizes in the TLB, but for now let's assume 16M is 661 * always there and a good fit (which it probably is) 662 * 663 * Freescale booke only supports 4K pages in TLB0, so use that. 664 */ 665 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) 666 mmu_vmemmap_psize = MMU_PAGE_4K; 667 else 668 mmu_vmemmap_psize = MMU_PAGE_16M; 669 670 /* XXX This code only checks for TLB 0 capabilities and doesn't 671 * check what page size combos are supported by the HW. It 672 * also doesn't handle the case where a separate array holds 673 * the IND entries from the array loaded by the PT. 674 */ 675 /* Look for supported page sizes */ 676 setup_page_sizes(); 677 678 /* Look for HW tablewalk support */ 679 setup_mmu_htw(); 680 681 #ifdef CONFIG_PPC_FSL_BOOK3E 682 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) { 683 if (book3e_htw_mode == PPC_HTW_NONE) { 684 extlb_level_exc = EX_TLB_SIZE; 685 patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e); 686 patch_exception(0x1e0, 687 exc_instruction_tlb_miss_bolted_book3e); 688 } 689 } 690 #endif 691 692 /* Set the global containing the top of the linear mapping 693 * for use by the TLB miss code 694 */ 695 linear_map_top = memblock_end_of_DRAM(); 696 697 ioremap_bot = IOREMAP_BASE; 698 } 699 700 static void __init early_mmu_set_memory_limit(void) 701 { 702 #ifdef CONFIG_PPC_FSL_BOOK3E 703 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) { 704 /* 705 * Limit memory so we dont have linear faults. 706 * Unlike memblock_set_current_limit, which limits 707 * memory available during early boot, this permanently 708 * reduces the memory available to Linux. We need to 709 * do this because highmem is not supported on 64-bit. 710 */ 711 memblock_enforce_memory_limit(linear_map_top); 712 } 713 #endif 714 715 memblock_set_current_limit(linear_map_top); 716 } 717 718 /* boot cpu only */ 719 void __init early_init_mmu(void) 720 { 721 early_init_mmu_global(); 722 early_init_this_mmu(); 723 early_mmu_set_memory_limit(); 724 } 725 726 void early_init_mmu_secondary(void) 727 { 728 early_init_this_mmu(); 729 } 730 731 void setup_initial_memory_limit(phys_addr_t first_memblock_base, 732 phys_addr_t first_memblock_size) 733 { 734 /* On non-FSL Embedded 64-bit, we adjust the RMA size to match 735 * the bolted TLB entry. We know for now that only 1G 736 * entries are supported though that may eventually 737 * change. 738 * 739 * on FSL Embedded 64-bit, usually all RAM is bolted, but with 740 * unusual memory sizes it's possible for some RAM to not be mapped 741 * (such RAM is not used at all by Linux, since we don't support 742 * highmem on 64-bit). We limit ppc64_rma_size to what would be 743 * mappable if this memblock is the only one. Additional memblocks 744 * can only increase, not decrease, the amount that ends up getting 745 * mapped. We still limit max to 1G even if we'll eventually map 746 * more. This is due to what the early init code is set up to do. 747 * 748 * We crop it to the size of the first MEMBLOCK to 749 * avoid going over total available memory just in case... 750 */ 751 #ifdef CONFIG_PPC_FSL_BOOK3E 752 if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E)) { 753 unsigned long linear_sz; 754 unsigned int num_cams; 755 756 /* use a quarter of the TLBCAM for bolted linear map */ 757 num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4; 758 759 linear_sz = map_mem_in_cams(first_memblock_size, num_cams, 760 true, true); 761 762 ppc64_rma_size = min_t(u64, linear_sz, 0x40000000); 763 } else 764 #endif 765 ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000); 766 767 /* Finally limit subsequent allocations */ 768 memblock_set_current_limit(first_memblock_base + ppc64_rma_size); 769 } 770 #else /* ! CONFIG_PPC64 */ 771 void __init early_init_mmu(void) 772 { 773 #ifdef CONFIG_PPC_47x 774 early_init_mmu_47x(); 775 #endif 776 777 #ifdef CONFIG_PPC_MM_SLICES 778 mm_ctx_set_slb_addr_limit(&init_mm.context, SLB_ADDR_LIMIT_DEFAULT); 779 #endif 780 } 781 #endif /* CONFIG_PPC64 */ 782