1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * This file contains the routines for initializing the MMU 4 * on the 8xx series of chips. 5 * -- christophe 6 * 7 * Derived from arch/powerpc/mm/40x_mmu.c: 8 */ 9 10 #include <linux/memblock.h> 11 #include <linux/mmu_context.h> 12 #include <asm/fixmap.h> 13 #include <asm/code-patching.h> 14 15 #include <mm/mmu_decl.h> 16 17 #define IMMR_SIZE (FIX_IMMR_SIZE << PAGE_SHIFT) 18 19 extern int __map_without_ltlbs; 20 21 static unsigned long block_mapped_ram; 22 23 /* 24 * Return PA for this VA if it is in an area mapped with LTLBs. 25 * Otherwise, returns 0 26 */ 27 phys_addr_t v_block_mapped(unsigned long va) 28 { 29 unsigned long p = PHYS_IMMR_BASE; 30 31 if (__map_without_ltlbs) 32 return 0; 33 if (va >= VIRT_IMMR_BASE && va < VIRT_IMMR_BASE + IMMR_SIZE) 34 return p + va - VIRT_IMMR_BASE; 35 if (va >= PAGE_OFFSET && va < PAGE_OFFSET + block_mapped_ram) 36 return __pa(va); 37 return 0; 38 } 39 40 /* 41 * Return VA for a given PA mapped with LTLBs or 0 if not mapped 42 */ 43 unsigned long p_block_mapped(phys_addr_t pa) 44 { 45 unsigned long p = PHYS_IMMR_BASE; 46 47 if (__map_without_ltlbs) 48 return 0; 49 if (pa >= p && pa < p + IMMR_SIZE) 50 return VIRT_IMMR_BASE + pa - p; 51 if (pa < block_mapped_ram) 52 return (unsigned long)__va(pa); 53 return 0; 54 } 55 56 #define LARGE_PAGE_SIZE_8M (1<<23) 57 58 /* 59 * MMU_init_hw does the chip-specific initialization of the MMU hardware. 60 */ 61 void __init MMU_init_hw(void) 62 { 63 /* PIN up to the 3 first 8Mb after IMMR in DTLB table */ 64 if (IS_ENABLED(CONFIG_PIN_TLB_DATA)) { 65 unsigned long ctr = mfspr(SPRN_MD_CTR) & 0xfe000000; 66 unsigned long flags = 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY; 67 int i = IS_ENABLED(CONFIG_PIN_TLB_IMMR) ? 29 : 28; 68 unsigned long addr = 0; 69 unsigned long mem = total_lowmem; 70 71 for (; i < 32 && mem >= LARGE_PAGE_SIZE_8M; i++) { 72 mtspr(SPRN_MD_CTR, ctr | (i << 8)); 73 mtspr(SPRN_MD_EPN, (unsigned long)__va(addr) | MD_EVALID); 74 mtspr(SPRN_MD_TWC, MD_PS8MEG | MD_SVALID); 75 mtspr(SPRN_MD_RPN, addr | flags | _PAGE_PRESENT); 76 addr += LARGE_PAGE_SIZE_8M; 77 mem -= LARGE_PAGE_SIZE_8M; 78 } 79 } 80 } 81 82 static void __init mmu_mapin_immr(void) 83 { 84 unsigned long p = PHYS_IMMR_BASE; 85 unsigned long v = VIRT_IMMR_BASE; 86 int offset; 87 88 for (offset = 0; offset < IMMR_SIZE; offset += PAGE_SIZE) 89 map_kernel_page(v + offset, p + offset, PAGE_KERNEL_NCG); 90 } 91 92 static void mmu_patch_cmp_limit(s32 *site, unsigned long mapped) 93 { 94 modify_instruction_site(site, 0xffff, (unsigned long)__va(mapped) >> 16); 95 } 96 97 static void mmu_patch_addis(s32 *site, long simm) 98 { 99 unsigned int instr = *(unsigned int *)patch_site_addr(site); 100 101 instr &= 0xffff0000; 102 instr |= ((unsigned long)simm) >> 16; 103 patch_instruction_site(site, instr); 104 } 105 106 static void mmu_mapin_ram_chunk(unsigned long offset, unsigned long top, pgprot_t prot) 107 { 108 unsigned long s = offset; 109 unsigned long v = PAGE_OFFSET + s; 110 phys_addr_t p = memstart_addr + s; 111 112 for (; s < top; s += PAGE_SIZE) { 113 map_kernel_page(v, p, prot); 114 v += PAGE_SIZE; 115 p += PAGE_SIZE; 116 } 117 } 118 119 unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top) 120 { 121 unsigned long mapped; 122 123 if (__map_without_ltlbs) { 124 mapped = 0; 125 mmu_mapin_immr(); 126 if (!IS_ENABLED(CONFIG_PIN_TLB_IMMR)) 127 patch_instruction_site(&patch__dtlbmiss_immr_jmp, PPC_INST_NOP); 128 if (!IS_ENABLED(CONFIG_PIN_TLB_TEXT)) 129 mmu_patch_cmp_limit(&patch__itlbmiss_linmem_top, 0); 130 } else { 131 unsigned long einittext8 = ALIGN(__pa(_einittext), SZ_8M); 132 133 mapped = top & ~(LARGE_PAGE_SIZE_8M - 1); 134 if (!IS_ENABLED(CONFIG_PIN_TLB_TEXT)) 135 mmu_patch_cmp_limit(&patch__itlbmiss_linmem_top, einittext8); 136 137 /* 138 * Populate page tables to: 139 * - have them appear in /sys/kernel/debug/kernel_page_tables 140 * - allow the BDI to find the pages when they are not PINNED 141 */ 142 mmu_mapin_ram_chunk(0, einittext8, PAGE_KERNEL_X); 143 mmu_mapin_ram_chunk(einittext8, mapped, PAGE_KERNEL); 144 mmu_mapin_immr(); 145 } 146 147 mmu_patch_cmp_limit(&patch__dtlbmiss_linmem_top, mapped); 148 mmu_patch_cmp_limit(&patch__fixupdar_linmem_top, mapped); 149 150 /* If the size of RAM is not an exact power of two, we may not 151 * have covered RAM in its entirety with 8 MiB 152 * pages. Consequently, restrict the top end of RAM currently 153 * allocable so that calls to the MEMBLOCK to allocate PTEs for "tail" 154 * coverage with normal-sized pages (or other reasons) do not 155 * attempt to allocate outside the allowed range. 156 */ 157 if (mapped) 158 memblock_set_current_limit(mapped); 159 160 block_mapped_ram = mapped; 161 162 return mapped; 163 } 164 165 void mmu_mark_initmem_nx(void) 166 { 167 if (IS_ENABLED(CONFIG_STRICT_KERNEL_RWX) && CONFIG_ETEXT_SHIFT < 23) 168 mmu_patch_addis(&patch__itlbmiss_linmem_top8, 169 -((long)_etext & ~(LARGE_PAGE_SIZE_8M - 1))); 170 if (!IS_ENABLED(CONFIG_PIN_TLB_TEXT)) { 171 unsigned long einittext8 = ALIGN(__pa(_einittext), SZ_8M); 172 unsigned long etext8 = ALIGN(__pa(_etext), SZ_8M); 173 unsigned long etext = __pa(_etext); 174 175 mmu_patch_cmp_limit(&patch__itlbmiss_linmem_top, __pa(_etext)); 176 177 /* Update page tables for PTDUMP and BDI */ 178 mmu_mapin_ram_chunk(0, einittext8, __pgprot(0)); 179 if (IS_ENABLED(CONFIG_STRICT_KERNEL_RWX)) { 180 mmu_mapin_ram_chunk(0, etext, PAGE_KERNEL_TEXT); 181 mmu_mapin_ram_chunk(etext, einittext8, PAGE_KERNEL); 182 } else { 183 mmu_mapin_ram_chunk(0, etext8, PAGE_KERNEL_TEXT); 184 mmu_mapin_ram_chunk(etext8, einittext8, PAGE_KERNEL); 185 } 186 } 187 } 188 189 #ifdef CONFIG_STRICT_KERNEL_RWX 190 void mmu_mark_rodata_ro(void) 191 { 192 unsigned long sinittext = __pa(_sinittext); 193 unsigned long etext = __pa(_etext); 194 195 if (CONFIG_DATA_SHIFT < 23) 196 mmu_patch_addis(&patch__dtlbmiss_romem_top8, 197 -__pa(((unsigned long)_sinittext) & 198 ~(LARGE_PAGE_SIZE_8M - 1))); 199 mmu_patch_addis(&patch__dtlbmiss_romem_top, -__pa(_sinittext)); 200 201 /* Update page tables for PTDUMP and BDI */ 202 mmu_mapin_ram_chunk(0, sinittext, __pgprot(0)); 203 mmu_mapin_ram_chunk(0, etext, PAGE_KERNEL_ROX); 204 mmu_mapin_ram_chunk(etext, sinittext, PAGE_KERNEL_RO); 205 } 206 #endif 207 208 void __init setup_initial_memory_limit(phys_addr_t first_memblock_base, 209 phys_addr_t first_memblock_size) 210 { 211 /* We don't currently support the first MEMBLOCK not mapping 0 212 * physical on those processors 213 */ 214 BUG_ON(first_memblock_base != 0); 215 216 /* 8xx can only access 32MB at the moment */ 217 memblock_set_current_limit(min_t(u64, first_memblock_size, 0x02000000)); 218 } 219 220 /* 221 * Set up to use a given MMU context. 222 * id is context number, pgd is PGD pointer. 223 * 224 * We place the physical address of the new task page directory loaded 225 * into the MMU base register, and set the ASID compare register with 226 * the new "context." 227 */ 228 void set_context(unsigned long id, pgd_t *pgd) 229 { 230 s16 offset = (s16)(__pa(swapper_pg_dir)); 231 232 /* Context switch the PTE pointer for the Abatron BDI2000. 233 * The PGDIR is passed as second argument. 234 */ 235 if (IS_ENABLED(CONFIG_BDI_SWITCH)) 236 abatron_pteptrs[1] = pgd; 237 238 /* Register M_TWB will contain base address of level 1 table minus the 239 * lower part of the kernel PGDIR base address, so that all accesses to 240 * level 1 table are done relative to lower part of kernel PGDIR base 241 * address. 242 */ 243 mtspr(SPRN_M_TWB, __pa(pgd) - offset); 244 245 /* Update context */ 246 mtspr(SPRN_M_CASID, id - 1); 247 /* sync */ 248 mb(); 249 } 250 251 void flush_instruction_cache(void) 252 { 253 isync(); 254 mtspr(SPRN_IC_CST, IDC_INVALL); 255 isync(); 256 } 257 258 #ifdef CONFIG_PPC_KUEP 259 void __init setup_kuep(bool disabled) 260 { 261 if (disabled) 262 return; 263 264 pr_info("Activating Kernel Userspace Execution Prevention\n"); 265 266 mtspr(SPRN_MI_AP, MI_APG_KUEP); 267 } 268 #endif 269 270 #ifdef CONFIG_PPC_KUAP 271 void __init setup_kuap(bool disabled) 272 { 273 pr_info("Activating Kernel Userspace Access Protection\n"); 274 275 if (disabled) 276 pr_warn("KUAP cannot be disabled yet on 8xx when compiled in\n"); 277 278 mtspr(SPRN_MD_AP, MD_APG_KUAP); 279 } 280 #endif 281