12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
227e23b5fSChristophe Leroy /*
327e23b5fSChristophe Leroy * Modifications by Matt Porter (mporter@mvista.com) to support
427e23b5fSChristophe Leroy * PPC44x Book E processors.
527e23b5fSChristophe Leroy *
627e23b5fSChristophe Leroy * This file contains the routines for initializing the MMU
727e23b5fSChristophe Leroy * on the 4xx series of chips.
827e23b5fSChristophe Leroy * -- paulus
927e23b5fSChristophe Leroy *
1027e23b5fSChristophe Leroy * Derived from arch/ppc/mm/init.c:
1127e23b5fSChristophe Leroy * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
1227e23b5fSChristophe Leroy *
1327e23b5fSChristophe Leroy * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
1427e23b5fSChristophe Leroy * and Cort Dougan (PReP) (cort@cs.nmt.edu)
1527e23b5fSChristophe Leroy * Copyright (C) 1996 Paul Mackerras
1627e23b5fSChristophe Leroy *
1727e23b5fSChristophe Leroy * Derived from "arch/i386/mm/init.c"
1827e23b5fSChristophe Leroy * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
1927e23b5fSChristophe Leroy */
2027e23b5fSChristophe Leroy
2127e23b5fSChristophe Leroy #include <linux/init.h>
2227e23b5fSChristophe Leroy #include <linux/memblock.h>
2327e23b5fSChristophe Leroy
2427e23b5fSChristophe Leroy #include <asm/mmu.h>
2527e23b5fSChristophe Leroy #include <asm/page.h>
2627e23b5fSChristophe Leroy #include <asm/cacheflush.h>
2727e23b5fSChristophe Leroy #include <asm/code-patching.h>
28fc499986SChristophe Leroy #include <asm/smp.h>
2927e23b5fSChristophe Leroy
3027e23b5fSChristophe Leroy #include <mm/mmu_decl.h>
3127e23b5fSChristophe Leroy
3227e23b5fSChristophe Leroy /* Used by the 44x TLB replacement exception handler.
3327e23b5fSChristophe Leroy * Just needed it declared someplace.
3427e23b5fSChristophe Leroy */
3527e23b5fSChristophe Leroy unsigned int tlb_44x_index; /* = 0 */
3627e23b5fSChristophe Leroy unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
3727e23b5fSChristophe Leroy int icache_44x_need_flush;
3827e23b5fSChristophe Leroy
3927e23b5fSChristophe Leroy unsigned long tlb_47x_boltmap[1024/8];
4027e23b5fSChristophe Leroy
ppc44x_update_tlb_hwater(void)41*c13f2b2bSNick Child static void __init ppc44x_update_tlb_hwater(void)
4227e23b5fSChristophe Leroy {
4327e23b5fSChristophe Leroy /* The TLB miss handlers hard codes the watermark in a cmpli
4427e23b5fSChristophe Leroy * instruction to improve performances rather than loading it
4527e23b5fSChristophe Leroy * from the global variable. Thus, we patch the instructions
4627e23b5fSChristophe Leroy * in the 2 TLB miss handlers when updating the value
4727e23b5fSChristophe Leroy */
4827e23b5fSChristophe Leroy modify_instruction_site(&patch__tlb_44x_hwater_D, 0xffff, tlb_44x_hwater);
4927e23b5fSChristophe Leroy modify_instruction_site(&patch__tlb_44x_hwater_I, 0xffff, tlb_44x_hwater);
5027e23b5fSChristophe Leroy }
5127e23b5fSChristophe Leroy
5227e23b5fSChristophe Leroy /*
5327e23b5fSChristophe Leroy * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 44x type MMU
5427e23b5fSChristophe Leroy */
ppc44x_pin_tlb(unsigned int virt,unsigned int phys)5527e23b5fSChristophe Leroy static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
5627e23b5fSChristophe Leroy {
5727e23b5fSChristophe Leroy unsigned int entry = tlb_44x_hwater--;
5827e23b5fSChristophe Leroy
5927e23b5fSChristophe Leroy ppc44x_update_tlb_hwater();
6027e23b5fSChristophe Leroy
6127e23b5fSChristophe Leroy mtspr(SPRN_MMUCR, 0);
6227e23b5fSChristophe Leroy
6327e23b5fSChristophe Leroy __asm__ __volatile__(
6427e23b5fSChristophe Leroy "tlbwe %2,%3,%4\n"
6527e23b5fSChristophe Leroy "tlbwe %1,%3,%5\n"
6627e23b5fSChristophe Leroy "tlbwe %0,%3,%6\n"
6727e23b5fSChristophe Leroy :
6827e23b5fSChristophe Leroy : "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
6927e23b5fSChristophe Leroy "r" (phys),
7027e23b5fSChristophe Leroy "r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M),
7127e23b5fSChristophe Leroy "r" (entry),
7227e23b5fSChristophe Leroy "i" (PPC44x_TLB_PAGEID),
7327e23b5fSChristophe Leroy "i" (PPC44x_TLB_XLAT),
7427e23b5fSChristophe Leroy "i" (PPC44x_TLB_ATTRIB));
7527e23b5fSChristophe Leroy }
7627e23b5fSChristophe Leroy
ppc47x_find_free_bolted(void)7727e23b5fSChristophe Leroy static int __init ppc47x_find_free_bolted(void)
7827e23b5fSChristophe Leroy {
7927e23b5fSChristophe Leroy unsigned int mmube0 = mfspr(SPRN_MMUBE0);
8027e23b5fSChristophe Leroy unsigned int mmube1 = mfspr(SPRN_MMUBE1);
8127e23b5fSChristophe Leroy
8227e23b5fSChristophe Leroy if (!(mmube0 & MMUBE0_VBE0))
8327e23b5fSChristophe Leroy return 0;
8427e23b5fSChristophe Leroy if (!(mmube0 & MMUBE0_VBE1))
8527e23b5fSChristophe Leroy return 1;
8627e23b5fSChristophe Leroy if (!(mmube0 & MMUBE0_VBE2))
8727e23b5fSChristophe Leroy return 2;
8827e23b5fSChristophe Leroy if (!(mmube1 & MMUBE1_VBE3))
8927e23b5fSChristophe Leroy return 3;
9027e23b5fSChristophe Leroy if (!(mmube1 & MMUBE1_VBE4))
9127e23b5fSChristophe Leroy return 4;
9227e23b5fSChristophe Leroy if (!(mmube1 & MMUBE1_VBE5))
9327e23b5fSChristophe Leroy return 5;
9427e23b5fSChristophe Leroy return -1;
9527e23b5fSChristophe Leroy }
9627e23b5fSChristophe Leroy
ppc47x_update_boltmap(void)9727e23b5fSChristophe Leroy static void __init ppc47x_update_boltmap(void)
9827e23b5fSChristophe Leroy {
9927e23b5fSChristophe Leroy unsigned int mmube0 = mfspr(SPRN_MMUBE0);
10027e23b5fSChristophe Leroy unsigned int mmube1 = mfspr(SPRN_MMUBE1);
10127e23b5fSChristophe Leroy
10227e23b5fSChristophe Leroy if (mmube0 & MMUBE0_VBE0)
10327e23b5fSChristophe Leroy __set_bit((mmube0 >> MMUBE0_IBE0_SHIFT) & 0xff,
10427e23b5fSChristophe Leroy tlb_47x_boltmap);
10527e23b5fSChristophe Leroy if (mmube0 & MMUBE0_VBE1)
10627e23b5fSChristophe Leroy __set_bit((mmube0 >> MMUBE0_IBE1_SHIFT) & 0xff,
10727e23b5fSChristophe Leroy tlb_47x_boltmap);
10827e23b5fSChristophe Leroy if (mmube0 & MMUBE0_VBE2)
10927e23b5fSChristophe Leroy __set_bit((mmube0 >> MMUBE0_IBE2_SHIFT) & 0xff,
11027e23b5fSChristophe Leroy tlb_47x_boltmap);
11127e23b5fSChristophe Leroy if (mmube1 & MMUBE1_VBE3)
11227e23b5fSChristophe Leroy __set_bit((mmube1 >> MMUBE1_IBE3_SHIFT) & 0xff,
11327e23b5fSChristophe Leroy tlb_47x_boltmap);
11427e23b5fSChristophe Leroy if (mmube1 & MMUBE1_VBE4)
11527e23b5fSChristophe Leroy __set_bit((mmube1 >> MMUBE1_IBE4_SHIFT) & 0xff,
11627e23b5fSChristophe Leroy tlb_47x_boltmap);
11727e23b5fSChristophe Leroy if (mmube1 & MMUBE1_VBE5)
11827e23b5fSChristophe Leroy __set_bit((mmube1 >> MMUBE1_IBE5_SHIFT) & 0xff,
11927e23b5fSChristophe Leroy tlb_47x_boltmap);
12027e23b5fSChristophe Leroy }
12127e23b5fSChristophe Leroy
12227e23b5fSChristophe Leroy /*
12327e23b5fSChristophe Leroy * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 47x type MMU
12427e23b5fSChristophe Leroy */
ppc47x_pin_tlb(unsigned int virt,unsigned int phys)125*c13f2b2bSNick Child static void __init ppc47x_pin_tlb(unsigned int virt, unsigned int phys)
12627e23b5fSChristophe Leroy {
12727e23b5fSChristophe Leroy unsigned int rA;
12827e23b5fSChristophe Leroy int bolted;
12927e23b5fSChristophe Leroy
13027e23b5fSChristophe Leroy /* Base rA is HW way select, way 0, bolted bit set */
13127e23b5fSChristophe Leroy rA = 0x88000000;
13227e23b5fSChristophe Leroy
13327e23b5fSChristophe Leroy /* Look for a bolted entry slot */
13427e23b5fSChristophe Leroy bolted = ppc47x_find_free_bolted();
13527e23b5fSChristophe Leroy BUG_ON(bolted < 0);
13627e23b5fSChristophe Leroy
13727e23b5fSChristophe Leroy /* Insert bolted slot number */
13827e23b5fSChristophe Leroy rA |= bolted << 24;
13927e23b5fSChristophe Leroy
14027e23b5fSChristophe Leroy pr_debug("256M TLB entry for 0x%08x->0x%08x in bolt slot %d\n",
14127e23b5fSChristophe Leroy virt, phys, bolted);
14227e23b5fSChristophe Leroy
14327e23b5fSChristophe Leroy mtspr(SPRN_MMUCR, 0);
14427e23b5fSChristophe Leroy
14527e23b5fSChristophe Leroy __asm__ __volatile__(
14627e23b5fSChristophe Leroy "tlbwe %2,%3,0\n"
14727e23b5fSChristophe Leroy "tlbwe %1,%3,1\n"
14827e23b5fSChristophe Leroy "tlbwe %0,%3,2\n"
14927e23b5fSChristophe Leroy :
15027e23b5fSChristophe Leroy : "r" (PPC47x_TLB2_SW | PPC47x_TLB2_SR |
15127e23b5fSChristophe Leroy PPC47x_TLB2_SX
15227e23b5fSChristophe Leroy #ifdef CONFIG_SMP
15327e23b5fSChristophe Leroy | PPC47x_TLB2_M
15427e23b5fSChristophe Leroy #endif
15527e23b5fSChristophe Leroy ),
15627e23b5fSChristophe Leroy "r" (phys),
15727e23b5fSChristophe Leroy "r" (virt | PPC47x_TLB0_VALID | PPC47x_TLB0_256M),
15827e23b5fSChristophe Leroy "r" (rA));
15927e23b5fSChristophe Leroy }
16027e23b5fSChristophe Leroy
MMU_init_hw(void)16127e23b5fSChristophe Leroy void __init MMU_init_hw(void)
16227e23b5fSChristophe Leroy {
16327e23b5fSChristophe Leroy /* This is not useful on 47x but won't hurt either */
16427e23b5fSChristophe Leroy ppc44x_update_tlb_hwater();
16527e23b5fSChristophe Leroy
16627e23b5fSChristophe Leroy flush_instruction_cache();
16727e23b5fSChristophe Leroy }
16827e23b5fSChristophe Leroy
mmu_mapin_ram(unsigned long base,unsigned long top)16927e23b5fSChristophe Leroy unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
17027e23b5fSChristophe Leroy {
17127e23b5fSChristophe Leroy unsigned long addr;
17227e23b5fSChristophe Leroy unsigned long memstart = memstart_addr & ~(PPC_PIN_SIZE - 1);
17327e23b5fSChristophe Leroy
17427e23b5fSChristophe Leroy /* Pin in enough TLBs to cover any lowmem not covered by the
17527e23b5fSChristophe Leroy * initial 256M mapping established in head_44x.S */
17627e23b5fSChristophe Leroy for (addr = memstart + PPC_PIN_SIZE; addr < lowmem_end_addr;
17727e23b5fSChristophe Leroy addr += PPC_PIN_SIZE) {
17827e23b5fSChristophe Leroy if (mmu_has_feature(MMU_FTR_TYPE_47x))
17927e23b5fSChristophe Leroy ppc47x_pin_tlb(addr + PAGE_OFFSET, addr);
18027e23b5fSChristophe Leroy else
18127e23b5fSChristophe Leroy ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
18227e23b5fSChristophe Leroy }
18327e23b5fSChristophe Leroy if (mmu_has_feature(MMU_FTR_TYPE_47x)) {
18427e23b5fSChristophe Leroy ppc47x_update_boltmap();
18527e23b5fSChristophe Leroy
18627e23b5fSChristophe Leroy #ifdef DEBUG
18727e23b5fSChristophe Leroy {
18827e23b5fSChristophe Leroy int i;
18927e23b5fSChristophe Leroy
19027e23b5fSChristophe Leroy printk(KERN_DEBUG "bolted entries: ");
19127e23b5fSChristophe Leroy for (i = 0; i < 255; i++) {
19227e23b5fSChristophe Leroy if (test_bit(i, tlb_47x_boltmap))
19327e23b5fSChristophe Leroy printk("%d ", i);
19427e23b5fSChristophe Leroy }
19527e23b5fSChristophe Leroy printk("\n");
19627e23b5fSChristophe Leroy }
19727e23b5fSChristophe Leroy #endif /* DEBUG */
19827e23b5fSChristophe Leroy }
19927e23b5fSChristophe Leroy return total_lowmem;
20027e23b5fSChristophe Leroy }
20127e23b5fSChristophe Leroy
setup_initial_memory_limit(phys_addr_t first_memblock_base,phys_addr_t first_memblock_size)20227e23b5fSChristophe Leroy void setup_initial_memory_limit(phys_addr_t first_memblock_base,
20327e23b5fSChristophe Leroy phys_addr_t first_memblock_size)
20427e23b5fSChristophe Leroy {
20527e23b5fSChristophe Leroy u64 size;
20627e23b5fSChristophe Leroy
20727e23b5fSChristophe Leroy #ifndef CONFIG_NONSTATIC_KERNEL
20827e23b5fSChristophe Leroy /* We don't currently support the first MEMBLOCK not mapping 0
20927e23b5fSChristophe Leroy * physical on those processors
21027e23b5fSChristophe Leroy */
21127e23b5fSChristophe Leroy BUG_ON(first_memblock_base != 0);
21227e23b5fSChristophe Leroy #endif
21327e23b5fSChristophe Leroy
21427e23b5fSChristophe Leroy /* 44x has a 256M TLB entry pinned at boot */
21527e23b5fSChristophe Leroy size = (min_t(u64, first_memblock_size, PPC_PIN_SIZE));
21627e23b5fSChristophe Leroy memblock_set_current_limit(first_memblock_base + size);
21727e23b5fSChristophe Leroy }
21827e23b5fSChristophe Leroy
21927e23b5fSChristophe Leroy #ifdef CONFIG_SMP
mmu_init_secondary(int cpu)22027e23b5fSChristophe Leroy void __init mmu_init_secondary(int cpu)
22127e23b5fSChristophe Leroy {
22227e23b5fSChristophe Leroy unsigned long addr;
22327e23b5fSChristophe Leroy unsigned long memstart = memstart_addr & ~(PPC_PIN_SIZE - 1);
22427e23b5fSChristophe Leroy
22527e23b5fSChristophe Leroy /* Pin in enough TLBs to cover any lowmem not covered by the
22627e23b5fSChristophe Leroy * initial 256M mapping established in head_44x.S
22727e23b5fSChristophe Leroy *
22827e23b5fSChristophe Leroy * WARNING: This is called with only the first 256M of the
22927e23b5fSChristophe Leroy * linear mapping in the TLB and we can't take faults yet
23027e23b5fSChristophe Leroy * so beware of what this code uses. It runs off a temporary
23127e23b5fSChristophe Leroy * stack. current (r2) isn't initialized, smp_processor_id()
23227e23b5fSChristophe Leroy * will not work, current thread info isn't accessible, ...
23327e23b5fSChristophe Leroy */
23427e23b5fSChristophe Leroy for (addr = memstart + PPC_PIN_SIZE; addr < lowmem_end_addr;
23527e23b5fSChristophe Leroy addr += PPC_PIN_SIZE) {
23627e23b5fSChristophe Leroy if (mmu_has_feature(MMU_FTR_TYPE_47x))
23727e23b5fSChristophe Leroy ppc47x_pin_tlb(addr + PAGE_OFFSET, addr);
23827e23b5fSChristophe Leroy else
23927e23b5fSChristophe Leroy ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
24027e23b5fSChristophe Leroy }
24127e23b5fSChristophe Leroy }
24227e23b5fSChristophe Leroy #endif /* CONFIG_SMP */
243