1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * This file contains the routines for initializing the MMU 4 * on the 4xx series of chips. 5 * -- paulus 6 * 7 * Derived from arch/ppc/mm/init.c: 8 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 9 * 10 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) 11 * and Cort Dougan (PReP) (cort@cs.nmt.edu) 12 * Copyright (C) 1996 Paul Mackerras 13 * 14 * Derived from "arch/i386/mm/init.c" 15 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds 16 */ 17 18 #include <linux/signal.h> 19 #include <linux/sched.h> 20 #include <linux/kernel.h> 21 #include <linux/errno.h> 22 #include <linux/string.h> 23 #include <linux/types.h> 24 #include <linux/ptrace.h> 25 #include <linux/mman.h> 26 #include <linux/mm.h> 27 #include <linux/swap.h> 28 #include <linux/stddef.h> 29 #include <linux/vmalloc.h> 30 #include <linux/init.h> 31 #include <linux/delay.h> 32 #include <linux/highmem.h> 33 #include <linux/memblock.h> 34 35 #include <asm/pgalloc.h> 36 #include <asm/prom.h> 37 #include <asm/io.h> 38 #include <asm/mmu_context.h> 39 #include <asm/pgtable.h> 40 #include <asm/mmu.h> 41 #include <linux/uaccess.h> 42 #include <asm/smp.h> 43 #include <asm/bootx.h> 44 #include <asm/machdep.h> 45 #include <asm/setup.h> 46 47 #include <mm/mmu_decl.h> 48 49 extern int __map_without_ltlbs; 50 /* 51 * MMU_init_hw does the chip-specific initialization of the MMU hardware. 52 */ 53 void __init MMU_init_hw(void) 54 { 55 /* 56 * The Zone Protection Register (ZPR) defines how protection will 57 * be applied to every page which is a member of a given zone. At 58 * present, we utilize only two of the 4xx's zones. 59 * The zone index bits (of ZSEL) in the PTE are used for software 60 * indicators, except the LSB. For user access, zone 1 is used, 61 * for kernel access, zone 0 is used. We set all but zone 1 62 * to zero, allowing only kernel access as indicated in the PTE. 63 * For zone 1, we set a 01 binary (a value of 10 will not work) 64 * to allow user access as indicated in the PTE. This also allows 65 * kernel access as indicated in the PTE. 66 */ 67 68 mtspr(SPRN_ZPR, 0x10000000); 69 70 flush_instruction_cache(); 71 72 /* 73 * Set up the real-mode cache parameters for the exception vector 74 * handlers (which are run in real-mode). 75 */ 76 77 mtspr(SPRN_DCWR, 0x00000000); /* All caching is write-back */ 78 79 /* 80 * Cache instruction and data space where the exception 81 * vectors and the kernel live in real-mode. 82 */ 83 84 mtspr(SPRN_DCCR, 0xFFFF0000); /* 2GByte of data space at 0x0. */ 85 mtspr(SPRN_ICCR, 0xFFFF0000); /* 2GByte of instr. space at 0x0. */ 86 } 87 88 #define LARGE_PAGE_SIZE_16M (1<<24) 89 #define LARGE_PAGE_SIZE_4M (1<<22) 90 91 unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top) 92 { 93 unsigned long v, s, mapped; 94 phys_addr_t p; 95 96 v = KERNELBASE; 97 p = 0; 98 s = total_lowmem; 99 100 if (__map_without_ltlbs) 101 return 0; 102 103 while (s >= LARGE_PAGE_SIZE_16M) { 104 pmd_t *pmdp; 105 unsigned long val = p | _PMD_SIZE_16M | _PAGE_EXEC | _PAGE_HWWRITE; 106 107 pmdp = pmd_offset(pud_offset(pgd_offset_k(v), v), v); 108 *pmdp++ = __pmd(val); 109 *pmdp++ = __pmd(val); 110 *pmdp++ = __pmd(val); 111 *pmdp++ = __pmd(val); 112 113 v += LARGE_PAGE_SIZE_16M; 114 p += LARGE_PAGE_SIZE_16M; 115 s -= LARGE_PAGE_SIZE_16M; 116 } 117 118 while (s >= LARGE_PAGE_SIZE_4M) { 119 pmd_t *pmdp; 120 unsigned long val = p | _PMD_SIZE_4M | _PAGE_EXEC | _PAGE_HWWRITE; 121 122 pmdp = pmd_offset(pud_offset(pgd_offset_k(v), v), v); 123 *pmdp = __pmd(val); 124 125 v += LARGE_PAGE_SIZE_4M; 126 p += LARGE_PAGE_SIZE_4M; 127 s -= LARGE_PAGE_SIZE_4M; 128 } 129 130 mapped = total_lowmem - s; 131 132 /* If the size of RAM is not an exact power of two, we may not 133 * have covered RAM in its entirety with 16 and 4 MiB 134 * pages. Consequently, restrict the top end of RAM currently 135 * allocable so that calls to the MEMBLOCK to allocate PTEs for "tail" 136 * coverage with normal-sized pages (or other reasons) do not 137 * attempt to allocate outside the allowed range. 138 */ 139 memblock_set_current_limit(mapped); 140 141 return mapped; 142 } 143 144 void setup_initial_memory_limit(phys_addr_t first_memblock_base, 145 phys_addr_t first_memblock_size) 146 { 147 /* We don't currently support the first MEMBLOCK not mapping 0 148 * physical on those processors 149 */ 150 BUG_ON(first_memblock_base != 0); 151 152 /* 40x can only access 16MB at the moment (see head_40x.S) */ 153 memblock_set_current_limit(min_t(u64, first_memblock_size, 0x00800000)); 154 } 155