1 /* 2 * Common implementation of switch_mm_irqs_off 3 * 4 * Copyright IBM Corp. 2017 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 * 11 */ 12 13 #include <linux/mm.h> 14 #include <linux/cpu.h> 15 16 #include <asm/mmu_context.h> 17 18 #if defined(CONFIG_PPC32) 19 static inline void switch_mm_pgdir(struct task_struct *tsk, 20 struct mm_struct *mm) 21 { 22 /* 32-bit keeps track of the current PGDIR in the thread struct */ 23 tsk->thread.pgdir = mm->pgd; 24 } 25 #elif defined(CONFIG_PPC_BOOK3E_64) 26 static inline void switch_mm_pgdir(struct task_struct *tsk, 27 struct mm_struct *mm) 28 { 29 /* 64-bit Book3E keeps track of current PGD in the PACA */ 30 get_paca()->pgd = mm->pgd; 31 } 32 #else 33 static inline void switch_mm_pgdir(struct task_struct *tsk, 34 struct mm_struct *mm) { } 35 #endif 36 37 void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, 38 struct task_struct *tsk) 39 { 40 bool new_on_cpu = false; 41 42 /* Mark this context has been used on the new CPU */ 43 if (!cpumask_test_cpu(smp_processor_id(), mm_cpumask(next))) { 44 cpumask_set_cpu(smp_processor_id(), mm_cpumask(next)); 45 inc_mm_active_cpus(next); 46 47 /* 48 * This full barrier orders the store to the cpumask above vs 49 * a subsequent operation which allows this CPU to begin loading 50 * translations for next. 51 * 52 * When using the radix MMU that operation is the load of the 53 * MMU context id, which is then moved to SPRN_PID. 54 * 55 * For the hash MMU it is either the first load from slb_cache 56 * in switch_slb(), and/or the store of paca->mm_ctx_id in 57 * copy_mm_to_paca(). 58 * 59 * On the read side the barrier is in pte_xchg(), which orders 60 * the store to the PTE vs the load of mm_cpumask. 61 */ 62 smp_mb(); 63 64 new_on_cpu = true; 65 } 66 67 /* Some subarchs need to track the PGD elsewhere */ 68 switch_mm_pgdir(tsk, next); 69 70 /* Nothing else to do if we aren't actually switching */ 71 if (prev == next) 72 return; 73 74 /* 75 * We must stop all altivec streams before changing the HW 76 * context 77 */ 78 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 79 asm volatile ("dssall"); 80 81 if (new_on_cpu) 82 radix_kvm_prefetch_workaround(next); 83 84 /* 85 * The actual HW switching method differs between the various 86 * sub architectures. Out of line for now 87 */ 88 switch_mmu_context(prev, next, tsk); 89 } 90 91