1 /* 2 * Common implementation of switch_mm_irqs_off 3 * 4 * Copyright IBM Corp. 2017 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 * 11 */ 12 13 #include <linux/mm.h> 14 #include <linux/cpu.h> 15 #include <linux/sched/mm.h> 16 17 #include <asm/mmu_context.h> 18 #include <asm/pgalloc.h> 19 20 #if defined(CONFIG_PPC32) 21 static inline void switch_mm_pgdir(struct task_struct *tsk, 22 struct mm_struct *mm) 23 { 24 /* 32-bit keeps track of the current PGDIR in the thread struct */ 25 tsk->thread.pgdir = mm->pgd; 26 } 27 #elif defined(CONFIG_PPC_BOOK3E_64) 28 static inline void switch_mm_pgdir(struct task_struct *tsk, 29 struct mm_struct *mm) 30 { 31 /* 64-bit Book3E keeps track of current PGD in the PACA */ 32 get_paca()->pgd = mm->pgd; 33 } 34 #else 35 static inline void switch_mm_pgdir(struct task_struct *tsk, 36 struct mm_struct *mm) { } 37 #endif 38 39 void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, 40 struct task_struct *tsk) 41 { 42 bool new_on_cpu = false; 43 44 /* Mark this context has been used on the new CPU */ 45 if (!cpumask_test_cpu(smp_processor_id(), mm_cpumask(next))) { 46 cpumask_set_cpu(smp_processor_id(), mm_cpumask(next)); 47 inc_mm_active_cpus(next); 48 49 /* 50 * This full barrier orders the store to the cpumask above vs 51 * a subsequent operation which allows this CPU to begin loading 52 * translations for next. 53 * 54 * When using the radix MMU that operation is the load of the 55 * MMU context id, which is then moved to SPRN_PID. 56 * 57 * For the hash MMU it is either the first load from slb_cache 58 * in switch_slb(), and/or the store of paca->mm_ctx_id in 59 * copy_mm_to_paca(). 60 * 61 * On the other side, the barrier is in mm/tlb-radix.c for 62 * radix which orders earlier stores to clear the PTEs vs 63 * the load of mm_cpumask. And pte_xchg which does the same 64 * thing for hash. 65 * 66 * This full barrier is needed by membarrier when switching 67 * between processes after store to rq->curr, before user-space 68 * memory accesses. 69 */ 70 smp_mb(); 71 72 new_on_cpu = true; 73 } 74 75 /* Some subarchs need to track the PGD elsewhere */ 76 switch_mm_pgdir(tsk, next); 77 78 /* Nothing else to do if we aren't actually switching */ 79 if (prev == next) 80 return; 81 82 /* 83 * We must stop all altivec streams before changing the HW 84 * context 85 */ 86 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 87 asm volatile ("dssall"); 88 89 if (new_on_cpu) 90 radix_kvm_prefetch_workaround(next); 91 else 92 membarrier_arch_switch_mm(prev, next, tsk); 93 94 /* 95 * The actual HW switching method differs between the various 96 * sub architectures. Out of line for now 97 */ 98 switch_mmu_context(prev, next, tsk); 99 } 100 101 #ifdef CONFIG_PPC32 102 void arch_exit_mmap(struct mm_struct *mm) 103 { 104 void *frag = pte_frag_get(&mm->context); 105 106 if (frag) 107 pte_frag_destroy(frag); 108 } 109 #endif 110