1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Page table handling routines for radix page table. 4 * 5 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation. 6 */ 7 8 #define pr_fmt(fmt) "radix-mmu: " fmt 9 10 #include <linux/io.h> 11 #include <linux/kernel.h> 12 #include <linux/sched/mm.h> 13 #include <linux/memblock.h> 14 #include <linux/of_fdt.h> 15 #include <linux/mm.h> 16 #include <linux/hugetlb.h> 17 #include <linux/string_helpers.h> 18 #include <linux/memory.h> 19 20 #include <asm/pgalloc.h> 21 #include <asm/mmu_context.h> 22 #include <asm/dma.h> 23 #include <asm/machdep.h> 24 #include <asm/mmu.h> 25 #include <asm/firmware.h> 26 #include <asm/powernv.h> 27 #include <asm/sections.h> 28 #include <asm/smp.h> 29 #include <asm/trace.h> 30 #include <asm/uaccess.h> 31 #include <asm/ultravisor.h> 32 33 #include <trace/events/thp.h> 34 35 unsigned int mmu_pid_bits; 36 unsigned int mmu_base_pid; 37 unsigned long radix_mem_block_size __ro_after_init; 38 39 static __ref void *early_alloc_pgtable(unsigned long size, int nid, 40 unsigned long region_start, unsigned long region_end) 41 { 42 phys_addr_t min_addr = MEMBLOCK_LOW_LIMIT; 43 phys_addr_t max_addr = MEMBLOCK_ALLOC_ANYWHERE; 44 void *ptr; 45 46 if (region_start) 47 min_addr = region_start; 48 if (region_end) 49 max_addr = region_end; 50 51 ptr = memblock_alloc_try_nid(size, size, min_addr, max_addr, nid); 52 53 if (!ptr) 54 panic("%s: Failed to allocate %lu bytes align=0x%lx nid=%d from=%pa max_addr=%pa\n", 55 __func__, size, size, nid, &min_addr, &max_addr); 56 57 return ptr; 58 } 59 60 /* 61 * When allocating pud or pmd pointers, we allocate a complete page 62 * of PAGE_SIZE rather than PUD_TABLE_SIZE or PMD_TABLE_SIZE. This 63 * is to ensure that the page obtained from the memblock allocator 64 * can be completely used as page table page and can be freed 65 * correctly when the page table entries are removed. 66 */ 67 static int early_map_kernel_page(unsigned long ea, unsigned long pa, 68 pgprot_t flags, 69 unsigned int map_page_size, 70 int nid, 71 unsigned long region_start, unsigned long region_end) 72 { 73 unsigned long pfn = pa >> PAGE_SHIFT; 74 pgd_t *pgdp; 75 p4d_t *p4dp; 76 pud_t *pudp; 77 pmd_t *pmdp; 78 pte_t *ptep; 79 80 pgdp = pgd_offset_k(ea); 81 p4dp = p4d_offset(pgdp, ea); 82 if (p4d_none(*p4dp)) { 83 pudp = early_alloc_pgtable(PAGE_SIZE, nid, 84 region_start, region_end); 85 p4d_populate(&init_mm, p4dp, pudp); 86 } 87 pudp = pud_offset(p4dp, ea); 88 if (map_page_size == PUD_SIZE) { 89 ptep = (pte_t *)pudp; 90 goto set_the_pte; 91 } 92 if (pud_none(*pudp)) { 93 pmdp = early_alloc_pgtable(PAGE_SIZE, nid, region_start, 94 region_end); 95 pud_populate(&init_mm, pudp, pmdp); 96 } 97 pmdp = pmd_offset(pudp, ea); 98 if (map_page_size == PMD_SIZE) { 99 ptep = pmdp_ptep(pmdp); 100 goto set_the_pte; 101 } 102 if (!pmd_present(*pmdp)) { 103 ptep = early_alloc_pgtable(PAGE_SIZE, nid, 104 region_start, region_end); 105 pmd_populate_kernel(&init_mm, pmdp, ptep); 106 } 107 ptep = pte_offset_kernel(pmdp, ea); 108 109 set_the_pte: 110 set_pte_at(&init_mm, ea, ptep, pfn_pte(pfn, flags)); 111 asm volatile("ptesync": : :"memory"); 112 return 0; 113 } 114 115 /* 116 * nid, region_start, and region_end are hints to try to place the page 117 * table memory in the same node or region. 118 */ 119 static int __map_kernel_page(unsigned long ea, unsigned long pa, 120 pgprot_t flags, 121 unsigned int map_page_size, 122 int nid, 123 unsigned long region_start, unsigned long region_end) 124 { 125 unsigned long pfn = pa >> PAGE_SHIFT; 126 pgd_t *pgdp; 127 p4d_t *p4dp; 128 pud_t *pudp; 129 pmd_t *pmdp; 130 pte_t *ptep; 131 /* 132 * Make sure task size is correct as per the max adddr 133 */ 134 BUILD_BUG_ON(TASK_SIZE_USER64 > RADIX_PGTABLE_RANGE); 135 136 #ifdef CONFIG_PPC_64K_PAGES 137 BUILD_BUG_ON(RADIX_KERN_MAP_SIZE != (1UL << MAX_EA_BITS_PER_CONTEXT)); 138 #endif 139 140 if (unlikely(!slab_is_available())) 141 return early_map_kernel_page(ea, pa, flags, map_page_size, 142 nid, region_start, region_end); 143 144 /* 145 * Should make page table allocation functions be able to take a 146 * node, so we can place kernel page tables on the right nodes after 147 * boot. 148 */ 149 pgdp = pgd_offset_k(ea); 150 p4dp = p4d_offset(pgdp, ea); 151 pudp = pud_alloc(&init_mm, p4dp, ea); 152 if (!pudp) 153 return -ENOMEM; 154 if (map_page_size == PUD_SIZE) { 155 ptep = (pte_t *)pudp; 156 goto set_the_pte; 157 } 158 pmdp = pmd_alloc(&init_mm, pudp, ea); 159 if (!pmdp) 160 return -ENOMEM; 161 if (map_page_size == PMD_SIZE) { 162 ptep = pmdp_ptep(pmdp); 163 goto set_the_pte; 164 } 165 ptep = pte_alloc_kernel(pmdp, ea); 166 if (!ptep) 167 return -ENOMEM; 168 169 set_the_pte: 170 set_pte_at(&init_mm, ea, ptep, pfn_pte(pfn, flags)); 171 asm volatile("ptesync": : :"memory"); 172 return 0; 173 } 174 175 int radix__map_kernel_page(unsigned long ea, unsigned long pa, 176 pgprot_t flags, 177 unsigned int map_page_size) 178 { 179 return __map_kernel_page(ea, pa, flags, map_page_size, -1, 0, 0); 180 } 181 182 #ifdef CONFIG_STRICT_KERNEL_RWX 183 static void radix__change_memory_range(unsigned long start, unsigned long end, 184 unsigned long clear) 185 { 186 unsigned long idx; 187 pgd_t *pgdp; 188 p4d_t *p4dp; 189 pud_t *pudp; 190 pmd_t *pmdp; 191 pte_t *ptep; 192 193 start = ALIGN_DOWN(start, PAGE_SIZE); 194 end = PAGE_ALIGN(end); // aligns up 195 196 pr_debug("Changing flags on range %lx-%lx removing 0x%lx\n", 197 start, end, clear); 198 199 for (idx = start; idx < end; idx += PAGE_SIZE) { 200 pgdp = pgd_offset_k(idx); 201 p4dp = p4d_offset(pgdp, idx); 202 pudp = pud_alloc(&init_mm, p4dp, idx); 203 if (!pudp) 204 continue; 205 if (pud_is_leaf(*pudp)) { 206 ptep = (pte_t *)pudp; 207 goto update_the_pte; 208 } 209 pmdp = pmd_alloc(&init_mm, pudp, idx); 210 if (!pmdp) 211 continue; 212 if (pmd_is_leaf(*pmdp)) { 213 ptep = pmdp_ptep(pmdp); 214 goto update_the_pte; 215 } 216 ptep = pte_alloc_kernel(pmdp, idx); 217 if (!ptep) 218 continue; 219 update_the_pte: 220 radix__pte_update(&init_mm, idx, ptep, clear, 0, 0); 221 } 222 223 radix__flush_tlb_kernel_range(start, end); 224 } 225 226 void radix__mark_rodata_ro(void) 227 { 228 unsigned long start, end; 229 230 start = (unsigned long)_stext; 231 end = (unsigned long)__init_begin; 232 233 radix__change_memory_range(start, end, _PAGE_WRITE); 234 } 235 236 void radix__mark_initmem_nx(void) 237 { 238 unsigned long start = (unsigned long)__init_begin; 239 unsigned long end = (unsigned long)__init_end; 240 241 radix__change_memory_range(start, end, _PAGE_EXEC); 242 } 243 #endif /* CONFIG_STRICT_KERNEL_RWX */ 244 245 static inline void __meminit 246 print_mapping(unsigned long start, unsigned long end, unsigned long size, bool exec) 247 { 248 char buf[10]; 249 250 if (end <= start) 251 return; 252 253 string_get_size(size, 1, STRING_UNITS_2, buf, sizeof(buf)); 254 255 pr_info("Mapped 0x%016lx-0x%016lx with %s pages%s\n", start, end, buf, 256 exec ? " (exec)" : ""); 257 } 258 259 static unsigned long next_boundary(unsigned long addr, unsigned long end) 260 { 261 #ifdef CONFIG_STRICT_KERNEL_RWX 262 if (addr < __pa_symbol(__init_begin)) 263 return __pa_symbol(__init_begin); 264 #endif 265 return end; 266 } 267 268 static int __meminit create_physical_mapping(unsigned long start, 269 unsigned long end, 270 unsigned long max_mapping_size, 271 int nid, pgprot_t _prot) 272 { 273 unsigned long vaddr, addr, mapping_size = 0; 274 bool prev_exec, exec = false; 275 pgprot_t prot; 276 int psize; 277 278 start = ALIGN(start, PAGE_SIZE); 279 end = ALIGN_DOWN(end, PAGE_SIZE); 280 for (addr = start; addr < end; addr += mapping_size) { 281 unsigned long gap, previous_size; 282 int rc; 283 284 gap = next_boundary(addr, end) - addr; 285 if (gap > max_mapping_size) 286 gap = max_mapping_size; 287 previous_size = mapping_size; 288 prev_exec = exec; 289 290 if (IS_ALIGNED(addr, PUD_SIZE) && gap >= PUD_SIZE && 291 mmu_psize_defs[MMU_PAGE_1G].shift) { 292 mapping_size = PUD_SIZE; 293 psize = MMU_PAGE_1G; 294 } else if (IS_ALIGNED(addr, PMD_SIZE) && gap >= PMD_SIZE && 295 mmu_psize_defs[MMU_PAGE_2M].shift) { 296 mapping_size = PMD_SIZE; 297 psize = MMU_PAGE_2M; 298 } else { 299 mapping_size = PAGE_SIZE; 300 psize = mmu_virtual_psize; 301 } 302 303 vaddr = (unsigned long)__va(addr); 304 305 if (overlaps_kernel_text(vaddr, vaddr + mapping_size) || 306 overlaps_interrupt_vector_text(vaddr, vaddr + mapping_size)) { 307 prot = PAGE_KERNEL_X; 308 exec = true; 309 } else { 310 prot = _prot; 311 exec = false; 312 } 313 314 if (mapping_size != previous_size || exec != prev_exec) { 315 print_mapping(start, addr, previous_size, prev_exec); 316 start = addr; 317 } 318 319 rc = __map_kernel_page(vaddr, addr, prot, mapping_size, nid, start, end); 320 if (rc) 321 return rc; 322 323 update_page_count(psize, 1); 324 } 325 326 print_mapping(start, addr, mapping_size, exec); 327 return 0; 328 } 329 330 static void __init radix_init_pgtable(void) 331 { 332 unsigned long rts_field; 333 phys_addr_t start, end; 334 u64 i; 335 336 /* We don't support slb for radix */ 337 mmu_slb_size = 0; 338 339 /* 340 * Create the linear mapping 341 */ 342 for_each_mem_range(i, &start, &end) { 343 /* 344 * The memblock allocator is up at this point, so the 345 * page tables will be allocated within the range. No 346 * need or a node (which we don't have yet). 347 */ 348 349 if (end >= RADIX_VMALLOC_START) { 350 pr_warn("Outside the supported range\n"); 351 continue; 352 } 353 354 WARN_ON(create_physical_mapping(start, end, 355 radix_mem_block_size, 356 -1, PAGE_KERNEL)); 357 } 358 359 /* Find out how many PID bits are supported */ 360 if (!cpu_has_feature(CPU_FTR_HVMODE) && 361 cpu_has_feature(CPU_FTR_P9_RADIX_PREFETCH_BUG)) { 362 /* 363 * Older versions of KVM on these machines perfer if the 364 * guest only uses the low 19 PID bits. 365 */ 366 if (!mmu_pid_bits) 367 mmu_pid_bits = 19; 368 } else { 369 if (!mmu_pid_bits) 370 mmu_pid_bits = 20; 371 } 372 mmu_base_pid = 1; 373 374 /* 375 * Allocate Partition table and process table for the 376 * host. 377 */ 378 BUG_ON(PRTB_SIZE_SHIFT > 36); 379 process_tb = early_alloc_pgtable(1UL << PRTB_SIZE_SHIFT, -1, 0, 0); 380 /* 381 * Fill in the process table. 382 */ 383 rts_field = radix__get_tree_size(); 384 process_tb->prtb0 = cpu_to_be64(rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE); 385 386 /* 387 * The init_mm context is given the first available (non-zero) PID, 388 * which is the "guard PID" and contains no page table. PIDR should 389 * never be set to zero because that duplicates the kernel address 390 * space at the 0x0... offset (quadrant 0)! 391 * 392 * An arbitrary PID that may later be allocated by the PID allocator 393 * for userspace processes must not be used either, because that 394 * would cause stale user mappings for that PID on CPUs outside of 395 * the TLB invalidation scheme (because it won't be in mm_cpumask). 396 * 397 * So permanently carve out one PID for the purpose of a guard PID. 398 */ 399 init_mm.context.id = mmu_base_pid; 400 mmu_base_pid++; 401 } 402 403 static void __init radix_init_partition_table(void) 404 { 405 unsigned long rts_field, dw0, dw1; 406 407 mmu_partition_table_init(); 408 rts_field = radix__get_tree_size(); 409 dw0 = rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE | PATB_HR; 410 dw1 = __pa(process_tb) | (PRTB_SIZE_SHIFT - 12) | PATB_GR; 411 mmu_partition_table_set_entry(0, dw0, dw1, false); 412 413 pr_info("Initializing Radix MMU\n"); 414 } 415 416 static int __init get_idx_from_shift(unsigned int shift) 417 { 418 int idx = -1; 419 420 switch (shift) { 421 case 0xc: 422 idx = MMU_PAGE_4K; 423 break; 424 case 0x10: 425 idx = MMU_PAGE_64K; 426 break; 427 case 0x15: 428 idx = MMU_PAGE_2M; 429 break; 430 case 0x1e: 431 idx = MMU_PAGE_1G; 432 break; 433 } 434 return idx; 435 } 436 437 static int __init radix_dt_scan_page_sizes(unsigned long node, 438 const char *uname, int depth, 439 void *data) 440 { 441 int size = 0; 442 int shift, idx; 443 unsigned int ap; 444 const __be32 *prop; 445 const char *type = of_get_flat_dt_prop(node, "device_type", NULL); 446 447 /* We are scanning "cpu" nodes only */ 448 if (type == NULL || strcmp(type, "cpu") != 0) 449 return 0; 450 451 /* Find MMU PID size */ 452 prop = of_get_flat_dt_prop(node, "ibm,mmu-pid-bits", &size); 453 if (prop && size == 4) 454 mmu_pid_bits = be32_to_cpup(prop); 455 456 /* Grab page size encodings */ 457 prop = of_get_flat_dt_prop(node, "ibm,processor-radix-AP-encodings", &size); 458 if (!prop) 459 return 0; 460 461 pr_info("Page sizes from device-tree:\n"); 462 for (; size >= 4; size -= 4, ++prop) { 463 464 struct mmu_psize_def *def; 465 466 /* top 3 bit is AP encoding */ 467 shift = be32_to_cpu(prop[0]) & ~(0xe << 28); 468 ap = be32_to_cpu(prop[0]) >> 29; 469 pr_info("Page size shift = %d AP=0x%x\n", shift, ap); 470 471 idx = get_idx_from_shift(shift); 472 if (idx < 0) 473 continue; 474 475 def = &mmu_psize_defs[idx]; 476 def->shift = shift; 477 def->ap = ap; 478 } 479 480 /* needed ? */ 481 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B; 482 return 1; 483 } 484 485 #ifdef CONFIG_MEMORY_HOTPLUG 486 static int __init probe_memory_block_size(unsigned long node, const char *uname, int 487 depth, void *data) 488 { 489 unsigned long *mem_block_size = (unsigned long *)data; 490 const __be32 *prop; 491 int len; 492 493 if (depth != 1) 494 return 0; 495 496 if (strcmp(uname, "ibm,dynamic-reconfiguration-memory")) 497 return 0; 498 499 prop = of_get_flat_dt_prop(node, "ibm,lmb-size", &len); 500 501 if (!prop || len < dt_root_size_cells * sizeof(__be32)) 502 /* 503 * Nothing in the device tree 504 */ 505 *mem_block_size = MIN_MEMORY_BLOCK_SIZE; 506 else 507 *mem_block_size = of_read_number(prop, dt_root_size_cells); 508 return 1; 509 } 510 511 static unsigned long radix_memory_block_size(void) 512 { 513 unsigned long mem_block_size = MIN_MEMORY_BLOCK_SIZE; 514 515 /* 516 * OPAL firmware feature is set by now. Hence we are ok 517 * to test OPAL feature. 518 */ 519 if (firmware_has_feature(FW_FEATURE_OPAL)) 520 mem_block_size = 1UL * 1024 * 1024 * 1024; 521 else 522 of_scan_flat_dt(probe_memory_block_size, &mem_block_size); 523 524 return mem_block_size; 525 } 526 527 #else /* CONFIG_MEMORY_HOTPLUG */ 528 529 static unsigned long radix_memory_block_size(void) 530 { 531 return 1UL * 1024 * 1024 * 1024; 532 } 533 534 #endif /* CONFIG_MEMORY_HOTPLUG */ 535 536 537 void __init radix__early_init_devtree(void) 538 { 539 int rc; 540 541 /* 542 * Try to find the available page sizes in the device-tree 543 */ 544 rc = of_scan_flat_dt(radix_dt_scan_page_sizes, NULL); 545 if (!rc) { 546 /* 547 * No page size details found in device tree. 548 * Let's assume we have page 4k and 64k support 549 */ 550 mmu_psize_defs[MMU_PAGE_4K].shift = 12; 551 mmu_psize_defs[MMU_PAGE_4K].ap = 0x0; 552 553 mmu_psize_defs[MMU_PAGE_64K].shift = 16; 554 mmu_psize_defs[MMU_PAGE_64K].ap = 0x5; 555 } 556 557 /* 558 * Max mapping size used when mapping pages. We don't use 559 * ppc_md.memory_block_size() here because this get called 560 * early and we don't have machine probe called yet. Also 561 * the pseries implementation only check for ibm,lmb-size. 562 * All hypervisor supporting radix do expose that device 563 * tree node. 564 */ 565 radix_mem_block_size = radix_memory_block_size(); 566 return; 567 } 568 569 static void radix_init_amor(void) 570 { 571 /* 572 * In HV mode, we init AMOR (Authority Mask Override Register) so that 573 * the hypervisor and guest can setup IAMR (Instruction Authority Mask 574 * Register), enable key 0 and set it to 1. 575 * 576 * AMOR = 0b1100 .... 0000 (Mask for key 0 is 11) 577 */ 578 mtspr(SPRN_AMOR, (3ul << 62)); 579 } 580 581 void __init radix__early_init_mmu(void) 582 { 583 unsigned long lpcr; 584 585 #ifdef CONFIG_PPC_64K_PAGES 586 /* PAGE_SIZE mappings */ 587 mmu_virtual_psize = MMU_PAGE_64K; 588 #else 589 mmu_virtual_psize = MMU_PAGE_4K; 590 #endif 591 592 #ifdef CONFIG_SPARSEMEM_VMEMMAP 593 /* vmemmap mapping */ 594 if (mmu_psize_defs[MMU_PAGE_2M].shift) { 595 /* 596 * map vmemmap using 2M if available 597 */ 598 mmu_vmemmap_psize = MMU_PAGE_2M; 599 } else 600 mmu_vmemmap_psize = mmu_virtual_psize; 601 #endif 602 /* 603 * initialize page table size 604 */ 605 __pte_index_size = RADIX_PTE_INDEX_SIZE; 606 __pmd_index_size = RADIX_PMD_INDEX_SIZE; 607 __pud_index_size = RADIX_PUD_INDEX_SIZE; 608 __pgd_index_size = RADIX_PGD_INDEX_SIZE; 609 __pud_cache_index = RADIX_PUD_INDEX_SIZE; 610 __pte_table_size = RADIX_PTE_TABLE_SIZE; 611 __pmd_table_size = RADIX_PMD_TABLE_SIZE; 612 __pud_table_size = RADIX_PUD_TABLE_SIZE; 613 __pgd_table_size = RADIX_PGD_TABLE_SIZE; 614 615 __pmd_val_bits = RADIX_PMD_VAL_BITS; 616 __pud_val_bits = RADIX_PUD_VAL_BITS; 617 __pgd_val_bits = RADIX_PGD_VAL_BITS; 618 619 __kernel_virt_start = RADIX_KERN_VIRT_START; 620 __vmalloc_start = RADIX_VMALLOC_START; 621 __vmalloc_end = RADIX_VMALLOC_END; 622 __kernel_io_start = RADIX_KERN_IO_START; 623 __kernel_io_end = RADIX_KERN_IO_END; 624 vmemmap = (struct page *)RADIX_VMEMMAP_START; 625 ioremap_bot = IOREMAP_BASE; 626 627 #ifdef CONFIG_PCI 628 pci_io_base = ISA_IO_BASE; 629 #endif 630 __pte_frag_nr = RADIX_PTE_FRAG_NR; 631 __pte_frag_size_shift = RADIX_PTE_FRAG_SIZE_SHIFT; 632 __pmd_frag_nr = RADIX_PMD_FRAG_NR; 633 __pmd_frag_size_shift = RADIX_PMD_FRAG_SIZE_SHIFT; 634 635 radix_init_pgtable(); 636 637 if (!firmware_has_feature(FW_FEATURE_LPAR)) { 638 lpcr = mfspr(SPRN_LPCR); 639 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR); 640 radix_init_partition_table(); 641 radix_init_amor(); 642 } else { 643 radix_init_pseries(); 644 } 645 646 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE); 647 648 /* Switch to the guard PID before turning on MMU */ 649 radix__switch_mmu_context(NULL, &init_mm); 650 tlbiel_all(); 651 } 652 653 void radix__early_init_mmu_secondary(void) 654 { 655 unsigned long lpcr; 656 /* 657 * update partition table control register and UPRT 658 */ 659 if (!firmware_has_feature(FW_FEATURE_LPAR)) { 660 lpcr = mfspr(SPRN_LPCR); 661 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR); 662 663 set_ptcr_when_no_uv(__pa(partition_tb) | 664 (PATB_SIZE_SHIFT - 12)); 665 666 radix_init_amor(); 667 } 668 669 radix__switch_mmu_context(NULL, &init_mm); 670 tlbiel_all(); 671 672 /* Make sure userspace can't change the AMR */ 673 mtspr(SPRN_UAMOR, 0); 674 } 675 676 void radix__mmu_cleanup_all(void) 677 { 678 unsigned long lpcr; 679 680 if (!firmware_has_feature(FW_FEATURE_LPAR)) { 681 lpcr = mfspr(SPRN_LPCR); 682 mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT); 683 set_ptcr_when_no_uv(0); 684 powernv_set_nmmu_ptcr(0); 685 radix__flush_tlb_all(); 686 } 687 } 688 689 #ifdef CONFIG_MEMORY_HOTPLUG 690 static void free_pte_table(pte_t *pte_start, pmd_t *pmd) 691 { 692 pte_t *pte; 693 int i; 694 695 for (i = 0; i < PTRS_PER_PTE; i++) { 696 pte = pte_start + i; 697 if (!pte_none(*pte)) 698 return; 699 } 700 701 pte_free_kernel(&init_mm, pte_start); 702 pmd_clear(pmd); 703 } 704 705 static void free_pmd_table(pmd_t *pmd_start, pud_t *pud) 706 { 707 pmd_t *pmd; 708 int i; 709 710 for (i = 0; i < PTRS_PER_PMD; i++) { 711 pmd = pmd_start + i; 712 if (!pmd_none(*pmd)) 713 return; 714 } 715 716 pmd_free(&init_mm, pmd_start); 717 pud_clear(pud); 718 } 719 720 static void free_pud_table(pud_t *pud_start, p4d_t *p4d) 721 { 722 pud_t *pud; 723 int i; 724 725 for (i = 0; i < PTRS_PER_PUD; i++) { 726 pud = pud_start + i; 727 if (!pud_none(*pud)) 728 return; 729 } 730 731 pud_free(&init_mm, pud_start); 732 p4d_clear(p4d); 733 } 734 735 static void remove_pte_table(pte_t *pte_start, unsigned long addr, 736 unsigned long end) 737 { 738 unsigned long next; 739 pte_t *pte; 740 741 pte = pte_start + pte_index(addr); 742 for (; addr < end; addr = next, pte++) { 743 next = (addr + PAGE_SIZE) & PAGE_MASK; 744 if (next > end) 745 next = end; 746 747 if (!pte_present(*pte)) 748 continue; 749 750 if (!PAGE_ALIGNED(addr) || !PAGE_ALIGNED(next)) { 751 /* 752 * The vmemmap_free() and remove_section_mapping() 753 * codepaths call us with aligned addresses. 754 */ 755 WARN_ONCE(1, "%s: unaligned range\n", __func__); 756 continue; 757 } 758 759 pte_clear(&init_mm, addr, pte); 760 } 761 } 762 763 static void __meminit remove_pmd_table(pmd_t *pmd_start, unsigned long addr, 764 unsigned long end) 765 { 766 unsigned long next; 767 pte_t *pte_base; 768 pmd_t *pmd; 769 770 pmd = pmd_start + pmd_index(addr); 771 for (; addr < end; addr = next, pmd++) { 772 next = pmd_addr_end(addr, end); 773 774 if (!pmd_present(*pmd)) 775 continue; 776 777 if (pmd_is_leaf(*pmd)) { 778 if (!IS_ALIGNED(addr, PMD_SIZE) || 779 !IS_ALIGNED(next, PMD_SIZE)) { 780 WARN_ONCE(1, "%s: unaligned range\n", __func__); 781 continue; 782 } 783 pte_clear(&init_mm, addr, (pte_t *)pmd); 784 continue; 785 } 786 787 pte_base = (pte_t *)pmd_page_vaddr(*pmd); 788 remove_pte_table(pte_base, addr, next); 789 free_pte_table(pte_base, pmd); 790 } 791 } 792 793 static void __meminit remove_pud_table(pud_t *pud_start, unsigned long addr, 794 unsigned long end) 795 { 796 unsigned long next; 797 pmd_t *pmd_base; 798 pud_t *pud; 799 800 pud = pud_start + pud_index(addr); 801 for (; addr < end; addr = next, pud++) { 802 next = pud_addr_end(addr, end); 803 804 if (!pud_present(*pud)) 805 continue; 806 807 if (pud_is_leaf(*pud)) { 808 if (!IS_ALIGNED(addr, PUD_SIZE) || 809 !IS_ALIGNED(next, PUD_SIZE)) { 810 WARN_ONCE(1, "%s: unaligned range\n", __func__); 811 continue; 812 } 813 pte_clear(&init_mm, addr, (pte_t *)pud); 814 continue; 815 } 816 817 pmd_base = (pmd_t *)pud_page_vaddr(*pud); 818 remove_pmd_table(pmd_base, addr, next); 819 free_pmd_table(pmd_base, pud); 820 } 821 } 822 823 static void __meminit remove_pagetable(unsigned long start, unsigned long end) 824 { 825 unsigned long addr, next; 826 pud_t *pud_base; 827 pgd_t *pgd; 828 p4d_t *p4d; 829 830 spin_lock(&init_mm.page_table_lock); 831 832 for (addr = start; addr < end; addr = next) { 833 next = pgd_addr_end(addr, end); 834 835 pgd = pgd_offset_k(addr); 836 p4d = p4d_offset(pgd, addr); 837 if (!p4d_present(*p4d)) 838 continue; 839 840 if (p4d_is_leaf(*p4d)) { 841 if (!IS_ALIGNED(addr, P4D_SIZE) || 842 !IS_ALIGNED(next, P4D_SIZE)) { 843 WARN_ONCE(1, "%s: unaligned range\n", __func__); 844 continue; 845 } 846 847 pte_clear(&init_mm, addr, (pte_t *)pgd); 848 continue; 849 } 850 851 pud_base = (pud_t *)p4d_page_vaddr(*p4d); 852 remove_pud_table(pud_base, addr, next); 853 free_pud_table(pud_base, p4d); 854 } 855 856 spin_unlock(&init_mm.page_table_lock); 857 radix__flush_tlb_kernel_range(start, end); 858 } 859 860 int __meminit radix__create_section_mapping(unsigned long start, 861 unsigned long end, int nid, 862 pgprot_t prot) 863 { 864 if (end >= RADIX_VMALLOC_START) { 865 pr_warn("Outside the supported range\n"); 866 return -1; 867 } 868 869 return create_physical_mapping(__pa(start), __pa(end), 870 radix_mem_block_size, nid, prot); 871 } 872 873 int __meminit radix__remove_section_mapping(unsigned long start, unsigned long end) 874 { 875 remove_pagetable(start, end); 876 return 0; 877 } 878 #endif /* CONFIG_MEMORY_HOTPLUG */ 879 880 #ifdef CONFIG_SPARSEMEM_VMEMMAP 881 static int __map_kernel_page_nid(unsigned long ea, unsigned long pa, 882 pgprot_t flags, unsigned int map_page_size, 883 int nid) 884 { 885 return __map_kernel_page(ea, pa, flags, map_page_size, nid, 0, 0); 886 } 887 888 int __meminit radix__vmemmap_create_mapping(unsigned long start, 889 unsigned long page_size, 890 unsigned long phys) 891 { 892 /* Create a PTE encoding */ 893 unsigned long flags = _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_KERNEL_RW; 894 int nid = early_pfn_to_nid(phys >> PAGE_SHIFT); 895 int ret; 896 897 if ((start + page_size) >= RADIX_VMEMMAP_END) { 898 pr_warn("Outside the supported range\n"); 899 return -1; 900 } 901 902 ret = __map_kernel_page_nid(start, phys, __pgprot(flags), page_size, nid); 903 BUG_ON(ret); 904 905 return 0; 906 } 907 908 #ifdef CONFIG_MEMORY_HOTPLUG 909 void __meminit radix__vmemmap_remove_mapping(unsigned long start, unsigned long page_size) 910 { 911 remove_pagetable(start, start + page_size); 912 } 913 #endif 914 #endif 915 916 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 917 918 unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, 919 pmd_t *pmdp, unsigned long clr, 920 unsigned long set) 921 { 922 unsigned long old; 923 924 #ifdef CONFIG_DEBUG_VM 925 WARN_ON(!radix__pmd_trans_huge(*pmdp) && !pmd_devmap(*pmdp)); 926 assert_spin_locked(pmd_lockptr(mm, pmdp)); 927 #endif 928 929 old = radix__pte_update(mm, addr, (pte_t *)pmdp, clr, set, 1); 930 trace_hugepage_update(addr, old, clr, set); 931 932 return old; 933 } 934 935 pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address, 936 pmd_t *pmdp) 937 938 { 939 pmd_t pmd; 940 941 VM_BUG_ON(address & ~HPAGE_PMD_MASK); 942 VM_BUG_ON(radix__pmd_trans_huge(*pmdp)); 943 VM_BUG_ON(pmd_devmap(*pmdp)); 944 /* 945 * khugepaged calls this for normal pmd 946 */ 947 pmd = *pmdp; 948 pmd_clear(pmdp); 949 950 /* 951 * pmdp collapse_flush need to ensure that there are no parallel gup 952 * walk after this call. This is needed so that we can have stable 953 * page ref count when collapsing a page. We don't allow a collapse page 954 * if we have gup taken on the page. We can ensure that by sending IPI 955 * because gup walk happens with IRQ disabled. 956 */ 957 serialize_against_pte_lookup(vma->vm_mm); 958 959 radix__flush_tlb_collapsed_pmd(vma->vm_mm, address); 960 961 return pmd; 962 } 963 964 /* 965 * For us pgtable_t is pte_t *. Inorder to save the deposisted 966 * page table, we consider the allocated page table as a list 967 * head. On withdraw we need to make sure we zero out the used 968 * list_head memory area. 969 */ 970 void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 971 pgtable_t pgtable) 972 { 973 struct list_head *lh = (struct list_head *) pgtable; 974 975 assert_spin_locked(pmd_lockptr(mm, pmdp)); 976 977 /* FIFO */ 978 if (!pmd_huge_pte(mm, pmdp)) 979 INIT_LIST_HEAD(lh); 980 else 981 list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp)); 982 pmd_huge_pte(mm, pmdp) = pgtable; 983 } 984 985 pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp) 986 { 987 pte_t *ptep; 988 pgtable_t pgtable; 989 struct list_head *lh; 990 991 assert_spin_locked(pmd_lockptr(mm, pmdp)); 992 993 /* FIFO */ 994 pgtable = pmd_huge_pte(mm, pmdp); 995 lh = (struct list_head *) pgtable; 996 if (list_empty(lh)) 997 pmd_huge_pte(mm, pmdp) = NULL; 998 else { 999 pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next; 1000 list_del(lh); 1001 } 1002 ptep = (pte_t *) pgtable; 1003 *ptep = __pte(0); 1004 ptep++; 1005 *ptep = __pte(0); 1006 return pgtable; 1007 } 1008 1009 pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm, 1010 unsigned long addr, pmd_t *pmdp) 1011 { 1012 pmd_t old_pmd; 1013 unsigned long old; 1014 1015 old = radix__pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0); 1016 old_pmd = __pmd(old); 1017 return old_pmd; 1018 } 1019 1020 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1021 1022 void radix__ptep_set_access_flags(struct vm_area_struct *vma, pte_t *ptep, 1023 pte_t entry, unsigned long address, int psize) 1024 { 1025 struct mm_struct *mm = vma->vm_mm; 1026 unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_ACCESSED | 1027 _PAGE_RW | _PAGE_EXEC); 1028 1029 unsigned long change = pte_val(entry) ^ pte_val(*ptep); 1030 /* 1031 * To avoid NMMU hang while relaxing access, we need mark 1032 * the pte invalid in between. 1033 */ 1034 if ((change & _PAGE_RW) && atomic_read(&mm->context.copros) > 0) { 1035 unsigned long old_pte, new_pte; 1036 1037 old_pte = __radix_pte_update(ptep, _PAGE_PRESENT, _PAGE_INVALID); 1038 /* 1039 * new value of pte 1040 */ 1041 new_pte = old_pte | set; 1042 radix__flush_tlb_page_psize(mm, address, psize); 1043 __radix_pte_update(ptep, _PAGE_INVALID, new_pte); 1044 } else { 1045 __radix_pte_update(ptep, 0, set); 1046 /* 1047 * Book3S does not require a TLB flush when relaxing access 1048 * restrictions when the address space is not attached to a 1049 * NMMU, because the core MMU will reload the pte after taking 1050 * an access fault, which is defined by the architecture. 1051 */ 1052 } 1053 /* See ptesync comment in radix__set_pte_at */ 1054 } 1055 1056 void radix__ptep_modify_prot_commit(struct vm_area_struct *vma, 1057 unsigned long addr, pte_t *ptep, 1058 pte_t old_pte, pte_t pte) 1059 { 1060 struct mm_struct *mm = vma->vm_mm; 1061 1062 /* 1063 * To avoid NMMU hang while relaxing access we need to flush the tlb before 1064 * we set the new value. We need to do this only for radix, because hash 1065 * translation does flush when updating the linux pte. 1066 */ 1067 if (is_pte_rw_upgrade(pte_val(old_pte), pte_val(pte)) && 1068 (atomic_read(&mm->context.copros) > 0)) 1069 radix__flush_tlb_page(vma, addr); 1070 1071 set_pte_at(mm, addr, ptep, pte); 1072 } 1073 1074 int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) 1075 { 1076 pte_t *ptep = (pte_t *)pud; 1077 pte_t new_pud = pfn_pte(__phys_to_pfn(addr), prot); 1078 1079 if (!radix_enabled()) 1080 return 0; 1081 1082 set_pte_at(&init_mm, 0 /* radix unused */, ptep, new_pud); 1083 1084 return 1; 1085 } 1086 1087 int pud_clear_huge(pud_t *pud) 1088 { 1089 if (pud_huge(*pud)) { 1090 pud_clear(pud); 1091 return 1; 1092 } 1093 1094 return 0; 1095 } 1096 1097 int pud_free_pmd_page(pud_t *pud, unsigned long addr) 1098 { 1099 pmd_t *pmd; 1100 int i; 1101 1102 pmd = (pmd_t *)pud_page_vaddr(*pud); 1103 pud_clear(pud); 1104 1105 flush_tlb_kernel_range(addr, addr + PUD_SIZE); 1106 1107 for (i = 0; i < PTRS_PER_PMD; i++) { 1108 if (!pmd_none(pmd[i])) { 1109 pte_t *pte; 1110 pte = (pte_t *)pmd_page_vaddr(pmd[i]); 1111 1112 pte_free_kernel(&init_mm, pte); 1113 } 1114 } 1115 1116 pmd_free(&init_mm, pmd); 1117 1118 return 1; 1119 } 1120 1121 int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot) 1122 { 1123 pte_t *ptep = (pte_t *)pmd; 1124 pte_t new_pmd = pfn_pte(__phys_to_pfn(addr), prot); 1125 1126 if (!radix_enabled()) 1127 return 0; 1128 1129 set_pte_at(&init_mm, 0 /* radix unused */, ptep, new_pmd); 1130 1131 return 1; 1132 } 1133 1134 int pmd_clear_huge(pmd_t *pmd) 1135 { 1136 if (pmd_huge(*pmd)) { 1137 pmd_clear(pmd); 1138 return 1; 1139 } 1140 1141 return 0; 1142 } 1143 1144 int pmd_free_pte_page(pmd_t *pmd, unsigned long addr) 1145 { 1146 pte_t *pte; 1147 1148 pte = (pte_t *)pmd_page_vaddr(*pmd); 1149 pmd_clear(pmd); 1150 1151 flush_tlb_kernel_range(addr, addr + PMD_SIZE); 1152 1153 pte_free_kernel(&init_mm, pte); 1154 1155 return 1; 1156 } 1157