1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * PowerPC64 port by Mike Corrigan and Dave Engebretsen 4 * {mikejc|engebret}@us.ibm.com 5 * 6 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com> 7 * 8 * SMP scalability work: 9 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM 10 * 11 * Module name: htab.c 12 * 13 * Description: 14 * PowerPC Hashed Page Table functions 15 */ 16 17 #undef DEBUG 18 #undef DEBUG_LOW 19 20 #define pr_fmt(fmt) "hash-mmu: " fmt 21 #include <linux/spinlock.h> 22 #include <linux/errno.h> 23 #include <linux/sched/mm.h> 24 #include <linux/proc_fs.h> 25 #include <linux/stat.h> 26 #include <linux/sysctl.h> 27 #include <linux/export.h> 28 #include <linux/ctype.h> 29 #include <linux/cache.h> 30 #include <linux/init.h> 31 #include <linux/signal.h> 32 #include <linux/memblock.h> 33 #include <linux/context_tracking.h> 34 #include <linux/libfdt.h> 35 #include <linux/pkeys.h> 36 #include <linux/hugetlb.h> 37 #include <linux/cpu.h> 38 #include <linux/pgtable.h> 39 40 #include <asm/debugfs.h> 41 #include <asm/interrupt.h> 42 #include <asm/processor.h> 43 #include <asm/mmu.h> 44 #include <asm/mmu_context.h> 45 #include <asm/page.h> 46 #include <asm/types.h> 47 #include <linux/uaccess.h> 48 #include <asm/machdep.h> 49 #include <asm/prom.h> 50 #include <asm/io.h> 51 #include <asm/eeh.h> 52 #include <asm/tlb.h> 53 #include <asm/cacheflush.h> 54 #include <asm/cputable.h> 55 #include <asm/sections.h> 56 #include <asm/copro.h> 57 #include <asm/udbg.h> 58 #include <asm/code-patching.h> 59 #include <asm/fadump.h> 60 #include <asm/firmware.h> 61 #include <asm/tm.h> 62 #include <asm/trace.h> 63 #include <asm/ps3.h> 64 #include <asm/pte-walk.h> 65 #include <asm/asm-prototypes.h> 66 #include <asm/ultravisor.h> 67 68 #include <mm/mmu_decl.h> 69 70 #include "internal.h" 71 72 73 #ifdef DEBUG 74 #define DBG(fmt...) udbg_printf(fmt) 75 #else 76 #define DBG(fmt...) 77 #endif 78 79 #ifdef DEBUG_LOW 80 #define DBG_LOW(fmt...) udbg_printf(fmt) 81 #else 82 #define DBG_LOW(fmt...) 83 #endif 84 85 #define KB (1024) 86 #define MB (1024*KB) 87 #define GB (1024L*MB) 88 89 /* 90 * Note: pte --> Linux PTE 91 * HPTE --> PowerPC Hashed Page Table Entry 92 * 93 * Execution context: 94 * htab_initialize is called with the MMU off (of course), but 95 * the kernel has been copied down to zero so it can directly 96 * reference global data. At this point it is very difficult 97 * to print debug info. 98 * 99 */ 100 101 static unsigned long _SDR1; 102 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; 103 EXPORT_SYMBOL_GPL(mmu_psize_defs); 104 105 u8 hpte_page_sizes[1 << LP_BITS]; 106 EXPORT_SYMBOL_GPL(hpte_page_sizes); 107 108 struct hash_pte *htab_address; 109 unsigned long htab_size_bytes; 110 unsigned long htab_hash_mask; 111 EXPORT_SYMBOL_GPL(htab_hash_mask); 112 int mmu_linear_psize = MMU_PAGE_4K; 113 EXPORT_SYMBOL_GPL(mmu_linear_psize); 114 int mmu_virtual_psize = MMU_PAGE_4K; 115 int mmu_vmalloc_psize = MMU_PAGE_4K; 116 EXPORT_SYMBOL_GPL(mmu_vmalloc_psize); 117 #ifdef CONFIG_SPARSEMEM_VMEMMAP 118 int mmu_vmemmap_psize = MMU_PAGE_4K; 119 #endif 120 int mmu_io_psize = MMU_PAGE_4K; 121 int mmu_kernel_ssize = MMU_SEGSIZE_256M; 122 EXPORT_SYMBOL_GPL(mmu_kernel_ssize); 123 int mmu_highuser_ssize = MMU_SEGSIZE_256M; 124 u16 mmu_slb_size = 64; 125 EXPORT_SYMBOL_GPL(mmu_slb_size); 126 #ifdef CONFIG_PPC_64K_PAGES 127 int mmu_ci_restrictions; 128 #endif 129 #ifdef CONFIG_DEBUG_PAGEALLOC 130 static u8 *linear_map_hash_slots; 131 static unsigned long linear_map_hash_count; 132 static DEFINE_SPINLOCK(linear_map_hash_lock); 133 #endif /* CONFIG_DEBUG_PAGEALLOC */ 134 struct mmu_hash_ops mmu_hash_ops; 135 EXPORT_SYMBOL(mmu_hash_ops); 136 137 /* 138 * These are definitions of page sizes arrays to be used when none 139 * is provided by the firmware. 140 */ 141 142 /* 143 * Fallback (4k pages only) 144 */ 145 static struct mmu_psize_def mmu_psize_defaults[] = { 146 [MMU_PAGE_4K] = { 147 .shift = 12, 148 .sllp = 0, 149 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, 150 .avpnm = 0, 151 .tlbiel = 0, 152 }, 153 }; 154 155 /* 156 * POWER4, GPUL, POWER5 157 * 158 * Support for 16Mb large pages 159 */ 160 static struct mmu_psize_def mmu_psize_defaults_gp[] = { 161 [MMU_PAGE_4K] = { 162 .shift = 12, 163 .sllp = 0, 164 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, 165 .avpnm = 0, 166 .tlbiel = 1, 167 }, 168 [MMU_PAGE_16M] = { 169 .shift = 24, 170 .sllp = SLB_VSID_L, 171 .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0, 172 [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 }, 173 .avpnm = 0x1UL, 174 .tlbiel = 0, 175 }, 176 }; 177 178 /* 179 * 'R' and 'C' update notes: 180 * - Under pHyp or KVM, the updatepp path will not set C, thus it *will* 181 * create writeable HPTEs without C set, because the hcall H_PROTECT 182 * that we use in that case will not update C 183 * - The above is however not a problem, because we also don't do that 184 * fancy "no flush" variant of eviction and we use H_REMOVE which will 185 * do the right thing and thus we don't have the race I described earlier 186 * 187 * - Under bare metal, we do have the race, so we need R and C set 188 * - We make sure R is always set and never lost 189 * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping 190 */ 191 unsigned long htab_convert_pte_flags(unsigned long pteflags, unsigned long flags) 192 { 193 unsigned long rflags = 0; 194 195 /* _PAGE_EXEC -> NOEXEC */ 196 if ((pteflags & _PAGE_EXEC) == 0) 197 rflags |= HPTE_R_N; 198 /* 199 * PPP bits: 200 * Linux uses slb key 0 for kernel and 1 for user. 201 * kernel RW areas are mapped with PPP=0b000 202 * User area is mapped with PPP=0b010 for read/write 203 * or PPP=0b011 for read-only (including writeable but clean pages). 204 */ 205 if (pteflags & _PAGE_PRIVILEGED) { 206 /* 207 * Kernel read only mapped with ppp bits 0b110 208 */ 209 if (!(pteflags & _PAGE_WRITE)) { 210 if (mmu_has_feature(MMU_FTR_KERNEL_RO)) 211 rflags |= (HPTE_R_PP0 | 0x2); 212 else 213 rflags |= 0x3; 214 } 215 } else { 216 if (pteflags & _PAGE_RWX) 217 rflags |= 0x2; 218 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY))) 219 rflags |= 0x1; 220 } 221 /* 222 * We can't allow hardware to update hpte bits. Hence always 223 * set 'R' bit and set 'C' if it is a write fault 224 */ 225 rflags |= HPTE_R_R; 226 227 if (pteflags & _PAGE_DIRTY) 228 rflags |= HPTE_R_C; 229 /* 230 * Add in WIG bits 231 */ 232 233 if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) 234 rflags |= HPTE_R_I; 235 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT) 236 rflags |= (HPTE_R_I | HPTE_R_G); 237 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO) 238 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M); 239 else 240 /* 241 * Add memory coherence if cache inhibited is not set 242 */ 243 rflags |= HPTE_R_M; 244 245 rflags |= pte_to_hpte_pkey_bits(pteflags, flags); 246 return rflags; 247 } 248 249 int htab_bolt_mapping(unsigned long vstart, unsigned long vend, 250 unsigned long pstart, unsigned long prot, 251 int psize, int ssize) 252 { 253 unsigned long vaddr, paddr; 254 unsigned int step, shift; 255 int ret = 0; 256 257 shift = mmu_psize_defs[psize].shift; 258 step = 1 << shift; 259 260 prot = htab_convert_pte_flags(prot, HPTE_USE_KERNEL_KEY); 261 262 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n", 263 vstart, vend, pstart, prot, psize, ssize); 264 265 /* Carefully map only the possible range */ 266 vaddr = ALIGN(vstart, step); 267 paddr = ALIGN(pstart, step); 268 vend = ALIGN_DOWN(vend, step); 269 270 for (; vaddr < vend; vaddr += step, paddr += step) { 271 unsigned long hash, hpteg; 272 unsigned long vsid = get_kernel_vsid(vaddr, ssize); 273 unsigned long vpn = hpt_vpn(vaddr, vsid, ssize); 274 unsigned long tprot = prot; 275 bool secondary_hash = false; 276 277 /* 278 * If we hit a bad address return error. 279 */ 280 if (!vsid) 281 return -1; 282 /* Make kernel text executable */ 283 if (overlaps_kernel_text(vaddr, vaddr + step)) 284 tprot &= ~HPTE_R_N; 285 286 /* 287 * If relocatable, check if it overlaps interrupt vectors that 288 * are copied down to real 0. For relocatable kernel 289 * (e.g. kdump case) we copy interrupt vectors down to real 290 * address 0. Mark that region as executable. This is 291 * because on p8 system with relocation on exception feature 292 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence 293 * in order to execute the interrupt handlers in virtual 294 * mode the vector region need to be marked as executable. 295 */ 296 if ((PHYSICAL_START > MEMORY_START) && 297 overlaps_interrupt_vector_text(vaddr, vaddr + step)) 298 tprot &= ~HPTE_R_N; 299 300 hash = hpt_hash(vpn, shift, ssize); 301 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); 302 303 BUG_ON(!mmu_hash_ops.hpte_insert); 304 repeat: 305 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot, 306 HPTE_V_BOLTED, psize, psize, 307 ssize); 308 if (ret == -1) { 309 /* 310 * Try to to keep bolted entries in primary. 311 * Remove non bolted entries and try insert again 312 */ 313 ret = mmu_hash_ops.hpte_remove(hpteg); 314 if (ret != -1) 315 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot, 316 HPTE_V_BOLTED, psize, psize, 317 ssize); 318 if (ret == -1 && !secondary_hash) { 319 secondary_hash = true; 320 hpteg = ((~hash & htab_hash_mask) * HPTES_PER_GROUP); 321 goto repeat; 322 } 323 } 324 325 if (ret < 0) 326 break; 327 328 cond_resched(); 329 #ifdef CONFIG_DEBUG_PAGEALLOC 330 if (debug_pagealloc_enabled() && 331 (paddr >> PAGE_SHIFT) < linear_map_hash_count) 332 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80; 333 #endif /* CONFIG_DEBUG_PAGEALLOC */ 334 } 335 return ret < 0 ? ret : 0; 336 } 337 338 int htab_remove_mapping(unsigned long vstart, unsigned long vend, 339 int psize, int ssize) 340 { 341 unsigned long vaddr; 342 unsigned int step, shift; 343 int rc; 344 int ret = 0; 345 346 shift = mmu_psize_defs[psize].shift; 347 step = 1 << shift; 348 349 if (!mmu_hash_ops.hpte_removebolted) 350 return -ENODEV; 351 352 /* Unmap the full range specificied */ 353 vaddr = ALIGN_DOWN(vstart, step); 354 for (;vaddr < vend; vaddr += step) { 355 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize); 356 if (rc == -ENOENT) { 357 ret = -ENOENT; 358 continue; 359 } 360 if (rc < 0) 361 return rc; 362 } 363 364 return ret; 365 } 366 367 static bool disable_1tb_segments = false; 368 369 static int __init parse_disable_1tb_segments(char *p) 370 { 371 disable_1tb_segments = true; 372 return 0; 373 } 374 early_param("disable_1tb_segments", parse_disable_1tb_segments); 375 376 static int __init htab_dt_scan_seg_sizes(unsigned long node, 377 const char *uname, int depth, 378 void *data) 379 { 380 const char *type = of_get_flat_dt_prop(node, "device_type", NULL); 381 const __be32 *prop; 382 int size = 0; 383 384 /* We are scanning "cpu" nodes only */ 385 if (type == NULL || strcmp(type, "cpu") != 0) 386 return 0; 387 388 prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size); 389 if (prop == NULL) 390 return 0; 391 for (; size >= 4; size -= 4, ++prop) { 392 if (be32_to_cpu(prop[0]) == 40) { 393 DBG("1T segment support detected\n"); 394 395 if (disable_1tb_segments) { 396 DBG("1T segments disabled by command line\n"); 397 break; 398 } 399 400 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT; 401 return 1; 402 } 403 } 404 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B; 405 return 0; 406 } 407 408 static int __init get_idx_from_shift(unsigned int shift) 409 { 410 int idx = -1; 411 412 switch (shift) { 413 case 0xc: 414 idx = MMU_PAGE_4K; 415 break; 416 case 0x10: 417 idx = MMU_PAGE_64K; 418 break; 419 case 0x14: 420 idx = MMU_PAGE_1M; 421 break; 422 case 0x18: 423 idx = MMU_PAGE_16M; 424 break; 425 case 0x22: 426 idx = MMU_PAGE_16G; 427 break; 428 } 429 return idx; 430 } 431 432 static int __init htab_dt_scan_page_sizes(unsigned long node, 433 const char *uname, int depth, 434 void *data) 435 { 436 const char *type = of_get_flat_dt_prop(node, "device_type", NULL); 437 const __be32 *prop; 438 int size = 0; 439 440 /* We are scanning "cpu" nodes only */ 441 if (type == NULL || strcmp(type, "cpu") != 0) 442 return 0; 443 444 prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size); 445 if (!prop) 446 return 0; 447 448 pr_info("Page sizes from device-tree:\n"); 449 size /= 4; 450 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE); 451 while(size > 0) { 452 unsigned int base_shift = be32_to_cpu(prop[0]); 453 unsigned int slbenc = be32_to_cpu(prop[1]); 454 unsigned int lpnum = be32_to_cpu(prop[2]); 455 struct mmu_psize_def *def; 456 int idx, base_idx; 457 458 size -= 3; prop += 3; 459 base_idx = get_idx_from_shift(base_shift); 460 if (base_idx < 0) { 461 /* skip the pte encoding also */ 462 prop += lpnum * 2; size -= lpnum * 2; 463 continue; 464 } 465 def = &mmu_psize_defs[base_idx]; 466 if (base_idx == MMU_PAGE_16M) 467 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE; 468 469 def->shift = base_shift; 470 if (base_shift <= 23) 471 def->avpnm = 0; 472 else 473 def->avpnm = (1 << (base_shift - 23)) - 1; 474 def->sllp = slbenc; 475 /* 476 * We don't know for sure what's up with tlbiel, so 477 * for now we only set it for 4K and 64K pages 478 */ 479 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K) 480 def->tlbiel = 1; 481 else 482 def->tlbiel = 0; 483 484 while (size > 0 && lpnum) { 485 unsigned int shift = be32_to_cpu(prop[0]); 486 int penc = be32_to_cpu(prop[1]); 487 488 prop += 2; size -= 2; 489 lpnum--; 490 491 idx = get_idx_from_shift(shift); 492 if (idx < 0) 493 continue; 494 495 if (penc == -1) 496 pr_err("Invalid penc for base_shift=%d " 497 "shift=%d\n", base_shift, shift); 498 499 def->penc[idx] = penc; 500 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx," 501 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n", 502 base_shift, shift, def->sllp, 503 def->avpnm, def->tlbiel, def->penc[idx]); 504 } 505 } 506 507 return 1; 508 } 509 510 #ifdef CONFIG_HUGETLB_PAGE 511 /* 512 * Scan for 16G memory blocks that have been set aside for huge pages 513 * and reserve those blocks for 16G huge pages. 514 */ 515 static int __init htab_dt_scan_hugepage_blocks(unsigned long node, 516 const char *uname, int depth, 517 void *data) { 518 const char *type = of_get_flat_dt_prop(node, "device_type", NULL); 519 const __be64 *addr_prop; 520 const __be32 *page_count_prop; 521 unsigned int expected_pages; 522 long unsigned int phys_addr; 523 long unsigned int block_size; 524 525 /* We are scanning "memory" nodes only */ 526 if (type == NULL || strcmp(type, "memory") != 0) 527 return 0; 528 529 /* 530 * This property is the log base 2 of the number of virtual pages that 531 * will represent this memory block. 532 */ 533 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL); 534 if (page_count_prop == NULL) 535 return 0; 536 expected_pages = (1 << be32_to_cpu(page_count_prop[0])); 537 addr_prop = of_get_flat_dt_prop(node, "reg", NULL); 538 if (addr_prop == NULL) 539 return 0; 540 phys_addr = be64_to_cpu(addr_prop[0]); 541 block_size = be64_to_cpu(addr_prop[1]); 542 if (block_size != (16 * GB)) 543 return 0; 544 printk(KERN_INFO "Huge page(16GB) memory: " 545 "addr = 0x%lX size = 0x%lX pages = %d\n", 546 phys_addr, block_size, expected_pages); 547 if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) { 548 memblock_reserve(phys_addr, block_size * expected_pages); 549 pseries_add_gpage(phys_addr, block_size, expected_pages); 550 } 551 return 0; 552 } 553 #endif /* CONFIG_HUGETLB_PAGE */ 554 555 static void mmu_psize_set_default_penc(void) 556 { 557 int bpsize, apsize; 558 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++) 559 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++) 560 mmu_psize_defs[bpsize].penc[apsize] = -1; 561 } 562 563 #ifdef CONFIG_PPC_64K_PAGES 564 565 static bool might_have_hea(void) 566 { 567 /* 568 * The HEA ethernet adapter requires awareness of the 569 * GX bus. Without that awareness we can easily assume 570 * we will never see an HEA ethernet device. 571 */ 572 #ifdef CONFIG_IBMEBUS 573 return !cpu_has_feature(CPU_FTR_ARCH_207S) && 574 firmware_has_feature(FW_FEATURE_SPLPAR); 575 #else 576 return false; 577 #endif 578 } 579 580 #endif /* #ifdef CONFIG_PPC_64K_PAGES */ 581 582 static void __init htab_scan_page_sizes(void) 583 { 584 int rc; 585 586 /* se the invalid penc to -1 */ 587 mmu_psize_set_default_penc(); 588 589 /* Default to 4K pages only */ 590 memcpy(mmu_psize_defs, mmu_psize_defaults, 591 sizeof(mmu_psize_defaults)); 592 593 /* 594 * Try to find the available page sizes in the device-tree 595 */ 596 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL); 597 if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) { 598 /* 599 * Nothing in the device-tree, but the CPU supports 16M pages, 600 * so let's fallback on a known size list for 16M capable CPUs. 601 */ 602 memcpy(mmu_psize_defs, mmu_psize_defaults_gp, 603 sizeof(mmu_psize_defaults_gp)); 604 } 605 606 #ifdef CONFIG_HUGETLB_PAGE 607 if (!hugetlb_disabled && !early_radix_enabled() ) { 608 /* Reserve 16G huge page memory sections for huge pages */ 609 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL); 610 } 611 #endif /* CONFIG_HUGETLB_PAGE */ 612 } 613 614 /* 615 * Fill in the hpte_page_sizes[] array. 616 * We go through the mmu_psize_defs[] array looking for all the 617 * supported base/actual page size combinations. Each combination 618 * has a unique pagesize encoding (penc) value in the low bits of 619 * the LP field of the HPTE. For actual page sizes less than 1MB, 620 * some of the upper LP bits are used for RPN bits, meaning that 621 * we need to fill in several entries in hpte_page_sizes[]. 622 * 623 * In diagrammatic form, with r = RPN bits and z = page size bits: 624 * PTE LP actual page size 625 * rrrr rrrz >=8KB 626 * rrrr rrzz >=16KB 627 * rrrr rzzz >=32KB 628 * rrrr zzzz >=64KB 629 * ... 630 * 631 * The zzzz bits are implementation-specific but are chosen so that 632 * no encoding for a larger page size uses the same value in its 633 * low-order N bits as the encoding for the 2^(12+N) byte page size 634 * (if it exists). 635 */ 636 static void init_hpte_page_sizes(void) 637 { 638 long int ap, bp; 639 long int shift, penc; 640 641 for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) { 642 if (!mmu_psize_defs[bp].shift) 643 continue; /* not a supported page size */ 644 for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) { 645 penc = mmu_psize_defs[bp].penc[ap]; 646 if (penc == -1 || !mmu_psize_defs[ap].shift) 647 continue; 648 shift = mmu_psize_defs[ap].shift - LP_SHIFT; 649 if (shift <= 0) 650 continue; /* should never happen */ 651 /* 652 * For page sizes less than 1MB, this loop 653 * replicates the entry for all possible values 654 * of the rrrr bits. 655 */ 656 while (penc < (1 << LP_BITS)) { 657 hpte_page_sizes[penc] = (ap << 4) | bp; 658 penc += 1 << shift; 659 } 660 } 661 } 662 } 663 664 static void __init htab_init_page_sizes(void) 665 { 666 bool aligned = true; 667 init_hpte_page_sizes(); 668 669 if (!debug_pagealloc_enabled()) { 670 /* 671 * Pick a size for the linear mapping. Currently, we only 672 * support 16M, 1M and 4K which is the default 673 */ 674 if (IS_ENABLED(CONFIG_STRICT_KERNEL_RWX) && 675 (unsigned long)_stext % 0x1000000) { 676 if (mmu_psize_defs[MMU_PAGE_16M].shift) 677 pr_warn("Kernel not 16M aligned, disabling 16M linear map alignment\n"); 678 aligned = false; 679 } 680 681 if (mmu_psize_defs[MMU_PAGE_16M].shift && aligned) 682 mmu_linear_psize = MMU_PAGE_16M; 683 else if (mmu_psize_defs[MMU_PAGE_1M].shift) 684 mmu_linear_psize = MMU_PAGE_1M; 685 } 686 687 #ifdef CONFIG_PPC_64K_PAGES 688 /* 689 * Pick a size for the ordinary pages. Default is 4K, we support 690 * 64K for user mappings and vmalloc if supported by the processor. 691 * We only use 64k for ioremap if the processor 692 * (and firmware) support cache-inhibited large pages. 693 * If not, we use 4k and set mmu_ci_restrictions so that 694 * hash_page knows to switch processes that use cache-inhibited 695 * mappings to 4k pages. 696 */ 697 if (mmu_psize_defs[MMU_PAGE_64K].shift) { 698 mmu_virtual_psize = MMU_PAGE_64K; 699 mmu_vmalloc_psize = MMU_PAGE_64K; 700 if (mmu_linear_psize == MMU_PAGE_4K) 701 mmu_linear_psize = MMU_PAGE_64K; 702 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) { 703 /* 704 * When running on pSeries using 64k pages for ioremap 705 * would stop us accessing the HEA ethernet. So if we 706 * have the chance of ever seeing one, stay at 4k. 707 */ 708 if (!might_have_hea()) 709 mmu_io_psize = MMU_PAGE_64K; 710 } else 711 mmu_ci_restrictions = 1; 712 } 713 #endif /* CONFIG_PPC_64K_PAGES */ 714 715 #ifdef CONFIG_SPARSEMEM_VMEMMAP 716 /* 717 * We try to use 16M pages for vmemmap if that is supported 718 * and we have at least 1G of RAM at boot 719 */ 720 if (mmu_psize_defs[MMU_PAGE_16M].shift && 721 memblock_phys_mem_size() >= 0x40000000) 722 mmu_vmemmap_psize = MMU_PAGE_16M; 723 else 724 mmu_vmemmap_psize = mmu_virtual_psize; 725 #endif /* CONFIG_SPARSEMEM_VMEMMAP */ 726 727 printk(KERN_DEBUG "Page orders: linear mapping = %d, " 728 "virtual = %d, io = %d" 729 #ifdef CONFIG_SPARSEMEM_VMEMMAP 730 ", vmemmap = %d" 731 #endif 732 "\n", 733 mmu_psize_defs[mmu_linear_psize].shift, 734 mmu_psize_defs[mmu_virtual_psize].shift, 735 mmu_psize_defs[mmu_io_psize].shift 736 #ifdef CONFIG_SPARSEMEM_VMEMMAP 737 ,mmu_psize_defs[mmu_vmemmap_psize].shift 738 #endif 739 ); 740 } 741 742 static int __init htab_dt_scan_pftsize(unsigned long node, 743 const char *uname, int depth, 744 void *data) 745 { 746 const char *type = of_get_flat_dt_prop(node, "device_type", NULL); 747 const __be32 *prop; 748 749 /* We are scanning "cpu" nodes only */ 750 if (type == NULL || strcmp(type, "cpu") != 0) 751 return 0; 752 753 prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL); 754 if (prop != NULL) { 755 /* pft_size[0] is the NUMA CEC cookie */ 756 ppc64_pft_size = be32_to_cpu(prop[1]); 757 return 1; 758 } 759 return 0; 760 } 761 762 unsigned htab_shift_for_mem_size(unsigned long mem_size) 763 { 764 unsigned memshift = __ilog2(mem_size); 765 unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift; 766 unsigned pteg_shift; 767 768 /* round mem_size up to next power of 2 */ 769 if ((1UL << memshift) < mem_size) 770 memshift += 1; 771 772 /* aim for 2 pages / pteg */ 773 pteg_shift = memshift - (pshift + 1); 774 775 /* 776 * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab 777 * size permitted by the architecture. 778 */ 779 return max(pteg_shift + 7, 18U); 780 } 781 782 static unsigned long __init htab_get_table_size(void) 783 { 784 /* 785 * If hash size isn't already provided by the platform, we try to 786 * retrieve it from the device-tree. If it's not there neither, we 787 * calculate it now based on the total RAM size 788 */ 789 if (ppc64_pft_size == 0) 790 of_scan_flat_dt(htab_dt_scan_pftsize, NULL); 791 if (ppc64_pft_size) 792 return 1UL << ppc64_pft_size; 793 794 return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size()); 795 } 796 797 #ifdef CONFIG_MEMORY_HOTPLUG 798 static int resize_hpt_for_hotplug(unsigned long new_mem_size) 799 { 800 unsigned target_hpt_shift; 801 802 if (!mmu_hash_ops.resize_hpt) 803 return 0; 804 805 target_hpt_shift = htab_shift_for_mem_size(new_mem_size); 806 807 /* 808 * To avoid lots of HPT resizes if memory size is fluctuating 809 * across a boundary, we deliberately have some hysterisis 810 * here: we immediately increase the HPT size if the target 811 * shift exceeds the current shift, but we won't attempt to 812 * reduce unless the target shift is at least 2 below the 813 * current shift 814 */ 815 if (target_hpt_shift > ppc64_pft_size || 816 target_hpt_shift < ppc64_pft_size - 1) 817 return mmu_hash_ops.resize_hpt(target_hpt_shift); 818 819 return 0; 820 } 821 822 int hash__create_section_mapping(unsigned long start, unsigned long end, 823 int nid, pgprot_t prot) 824 { 825 int rc; 826 827 if (end >= H_VMALLOC_START) { 828 pr_warn("Outside the supported range\n"); 829 return -1; 830 } 831 832 resize_hpt_for_hotplug(memblock_phys_mem_size()); 833 834 rc = htab_bolt_mapping(start, end, __pa(start), 835 pgprot_val(prot), mmu_linear_psize, 836 mmu_kernel_ssize); 837 838 if (rc < 0) { 839 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize, 840 mmu_kernel_ssize); 841 BUG_ON(rc2 && (rc2 != -ENOENT)); 842 } 843 return rc; 844 } 845 846 int hash__remove_section_mapping(unsigned long start, unsigned long end) 847 { 848 int rc = htab_remove_mapping(start, end, mmu_linear_psize, 849 mmu_kernel_ssize); 850 851 if (resize_hpt_for_hotplug(memblock_phys_mem_size()) == -ENOSPC) 852 pr_warn("Hash collision while resizing HPT\n"); 853 854 return rc; 855 } 856 #endif /* CONFIG_MEMORY_HOTPLUG */ 857 858 static void __init hash_init_partition_table(phys_addr_t hash_table, 859 unsigned long htab_size) 860 { 861 mmu_partition_table_init(); 862 863 /* 864 * PS field (VRMA page size) is not used for LPID 0, hence set to 0. 865 * For now, UPRT is 0 and we have no segment table. 866 */ 867 htab_size = __ilog2(htab_size) - 18; 868 mmu_partition_table_set_entry(0, hash_table | htab_size, 0, false); 869 pr_info("Partition table %p\n", partition_tb); 870 } 871 872 static void __init htab_initialize(void) 873 { 874 unsigned long table; 875 unsigned long pteg_count; 876 unsigned long prot; 877 phys_addr_t base = 0, size = 0, end; 878 u64 i; 879 880 DBG(" -> htab_initialize()\n"); 881 882 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) { 883 mmu_kernel_ssize = MMU_SEGSIZE_1T; 884 mmu_highuser_ssize = MMU_SEGSIZE_1T; 885 printk(KERN_INFO "Using 1TB segments\n"); 886 } 887 888 if (stress_slb_enabled) 889 static_branch_enable(&stress_slb_key); 890 891 /* 892 * Calculate the required size of the htab. We want the number of 893 * PTEGs to equal one half the number of real pages. 894 */ 895 htab_size_bytes = htab_get_table_size(); 896 pteg_count = htab_size_bytes >> 7; 897 898 htab_hash_mask = pteg_count - 1; 899 900 if (firmware_has_feature(FW_FEATURE_LPAR) || 901 firmware_has_feature(FW_FEATURE_PS3_LV1)) { 902 /* Using a hypervisor which owns the htab */ 903 htab_address = NULL; 904 _SDR1 = 0; 905 #ifdef CONFIG_FA_DUMP 906 /* 907 * If firmware assisted dump is active firmware preserves 908 * the contents of htab along with entire partition memory. 909 * Clear the htab if firmware assisted dump is active so 910 * that we dont end up using old mappings. 911 */ 912 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all) 913 mmu_hash_ops.hpte_clear_all(); 914 #endif 915 } else { 916 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE; 917 918 #ifdef CONFIG_PPC_CELL 919 /* 920 * Cell may require the hash table down low when using the 921 * Axon IOMMU in order to fit the dynamic region over it, see 922 * comments in cell/iommu.c 923 */ 924 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) { 925 limit = 0x80000000; 926 pr_info("Hash table forced below 2G for Axon IOMMU\n"); 927 } 928 #endif /* CONFIG_PPC_CELL */ 929 930 table = memblock_phys_alloc_range(htab_size_bytes, 931 htab_size_bytes, 932 0, limit); 933 if (!table) 934 panic("ERROR: Failed to allocate %pa bytes below %pa\n", 935 &htab_size_bytes, &limit); 936 937 DBG("Hash table allocated at %lx, size: %lx\n", table, 938 htab_size_bytes); 939 940 htab_address = __va(table); 941 942 /* htab absolute addr + encoded htabsize */ 943 _SDR1 = table + __ilog2(htab_size_bytes) - 18; 944 945 /* Initialize the HPT with no entries */ 946 memset((void *)table, 0, htab_size_bytes); 947 948 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 949 /* Set SDR1 */ 950 mtspr(SPRN_SDR1, _SDR1); 951 else 952 hash_init_partition_table(table, htab_size_bytes); 953 } 954 955 prot = pgprot_val(PAGE_KERNEL); 956 957 #ifdef CONFIG_DEBUG_PAGEALLOC 958 if (debug_pagealloc_enabled()) { 959 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT; 960 linear_map_hash_slots = memblock_alloc_try_nid( 961 linear_map_hash_count, 1, MEMBLOCK_LOW_LIMIT, 962 ppc64_rma_size, NUMA_NO_NODE); 963 if (!linear_map_hash_slots) 964 panic("%s: Failed to allocate %lu bytes max_addr=%pa\n", 965 __func__, linear_map_hash_count, &ppc64_rma_size); 966 } 967 #endif /* CONFIG_DEBUG_PAGEALLOC */ 968 969 /* create bolted the linear mapping in the hash table */ 970 for_each_mem_range(i, &base, &end) { 971 size = end - base; 972 base = (unsigned long)__va(base); 973 974 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n", 975 base, size, prot); 976 977 if ((base + size) >= H_VMALLOC_START) { 978 pr_warn("Outside the supported range\n"); 979 continue; 980 } 981 982 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base), 983 prot, mmu_linear_psize, mmu_kernel_ssize)); 984 } 985 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE); 986 987 /* 988 * If we have a memory_limit and we've allocated TCEs then we need to 989 * explicitly map the TCE area at the top of RAM. We also cope with the 990 * case that the TCEs start below memory_limit. 991 * tce_alloc_start/end are 16MB aligned so the mapping should work 992 * for either 4K or 16MB pages. 993 */ 994 if (tce_alloc_start) { 995 tce_alloc_start = (unsigned long)__va(tce_alloc_start); 996 tce_alloc_end = (unsigned long)__va(tce_alloc_end); 997 998 if (base + size >= tce_alloc_start) 999 tce_alloc_start = base + size + 1; 1000 1001 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end, 1002 __pa(tce_alloc_start), prot, 1003 mmu_linear_psize, mmu_kernel_ssize)); 1004 } 1005 1006 1007 DBG(" <- htab_initialize()\n"); 1008 } 1009 #undef KB 1010 #undef MB 1011 1012 void __init hash__early_init_devtree(void) 1013 { 1014 /* Initialize segment sizes */ 1015 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL); 1016 1017 /* Initialize page sizes */ 1018 htab_scan_page_sizes(); 1019 } 1020 1021 static struct hash_mm_context init_hash_mm_context; 1022 void __init hash__early_init_mmu(void) 1023 { 1024 #ifndef CONFIG_PPC_64K_PAGES 1025 /* 1026 * We have code in __hash_page_4K() and elsewhere, which assumes it can 1027 * do the following: 1028 * new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX); 1029 * 1030 * Where the slot number is between 0-15, and values of 8-15 indicate 1031 * the secondary bucket. For that code to work H_PAGE_F_SECOND and 1032 * H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and 1033 * H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here 1034 * with a BUILD_BUG_ON(). 1035 */ 1036 BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3))); 1037 #endif /* CONFIG_PPC_64K_PAGES */ 1038 1039 htab_init_page_sizes(); 1040 1041 /* 1042 * initialize page table size 1043 */ 1044 __pte_frag_nr = H_PTE_FRAG_NR; 1045 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT; 1046 __pmd_frag_nr = H_PMD_FRAG_NR; 1047 __pmd_frag_size_shift = H_PMD_FRAG_SIZE_SHIFT; 1048 1049 __pte_index_size = H_PTE_INDEX_SIZE; 1050 __pmd_index_size = H_PMD_INDEX_SIZE; 1051 __pud_index_size = H_PUD_INDEX_SIZE; 1052 __pgd_index_size = H_PGD_INDEX_SIZE; 1053 __pud_cache_index = H_PUD_CACHE_INDEX; 1054 __pte_table_size = H_PTE_TABLE_SIZE; 1055 __pmd_table_size = H_PMD_TABLE_SIZE; 1056 __pud_table_size = H_PUD_TABLE_SIZE; 1057 __pgd_table_size = H_PGD_TABLE_SIZE; 1058 /* 1059 * 4k use hugepd format, so for hash set then to 1060 * zero 1061 */ 1062 __pmd_val_bits = HASH_PMD_VAL_BITS; 1063 __pud_val_bits = HASH_PUD_VAL_BITS; 1064 __pgd_val_bits = HASH_PGD_VAL_BITS; 1065 1066 __kernel_virt_start = H_KERN_VIRT_START; 1067 __vmalloc_start = H_VMALLOC_START; 1068 __vmalloc_end = H_VMALLOC_END; 1069 __kernel_io_start = H_KERN_IO_START; 1070 __kernel_io_end = H_KERN_IO_END; 1071 vmemmap = (struct page *)H_VMEMMAP_START; 1072 ioremap_bot = IOREMAP_BASE; 1073 1074 #ifdef CONFIG_PCI 1075 pci_io_base = ISA_IO_BASE; 1076 #endif 1077 1078 /* Select appropriate backend */ 1079 if (firmware_has_feature(FW_FEATURE_PS3_LV1)) 1080 ps3_early_mm_init(); 1081 else if (firmware_has_feature(FW_FEATURE_LPAR)) 1082 hpte_init_pseries(); 1083 else if (IS_ENABLED(CONFIG_PPC_NATIVE)) 1084 hpte_init_native(); 1085 1086 if (!mmu_hash_ops.hpte_insert) 1087 panic("hash__early_init_mmu: No MMU hash ops defined!\n"); 1088 1089 /* 1090 * Initialize the MMU Hash table and create the linear mapping 1091 * of memory. Has to be done before SLB initialization as this is 1092 * currently where the page size encoding is obtained. 1093 */ 1094 htab_initialize(); 1095 1096 init_mm.context.hash_context = &init_hash_mm_context; 1097 mm_ctx_set_slb_addr_limit(&init_mm.context, SLB_ADDR_LIMIT_DEFAULT); 1098 1099 pr_info("Initializing hash mmu with SLB\n"); 1100 /* Initialize SLB management */ 1101 slb_initialize(); 1102 1103 if (cpu_has_feature(CPU_FTR_ARCH_206) 1104 && cpu_has_feature(CPU_FTR_HVMODE)) 1105 tlbiel_all(); 1106 } 1107 1108 #ifdef CONFIG_SMP 1109 void hash__early_init_mmu_secondary(void) 1110 { 1111 /* Initialize hash table for that CPU */ 1112 if (!firmware_has_feature(FW_FEATURE_LPAR)) { 1113 1114 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1115 mtspr(SPRN_SDR1, _SDR1); 1116 else 1117 set_ptcr_when_no_uv(__pa(partition_tb) | 1118 (PATB_SIZE_SHIFT - 12)); 1119 } 1120 /* Initialize SLB */ 1121 slb_initialize(); 1122 1123 if (cpu_has_feature(CPU_FTR_ARCH_206) 1124 && cpu_has_feature(CPU_FTR_HVMODE)) 1125 tlbiel_all(); 1126 1127 #ifdef CONFIG_PPC_MEM_KEYS 1128 if (mmu_has_feature(MMU_FTR_PKEY)) 1129 mtspr(SPRN_UAMOR, default_uamor); 1130 #endif 1131 } 1132 #endif /* CONFIG_SMP */ 1133 1134 /* 1135 * Called by asm hashtable.S for doing lazy icache flush 1136 */ 1137 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap) 1138 { 1139 struct page *page; 1140 1141 if (!pfn_valid(pte_pfn(pte))) 1142 return pp; 1143 1144 page = pte_page(pte); 1145 1146 /* page is dirty */ 1147 if (!test_bit(PG_dcache_clean, &page->flags) && !PageReserved(page)) { 1148 if (trap == 0x400) { 1149 flush_dcache_icache_page(page); 1150 set_bit(PG_dcache_clean, &page->flags); 1151 } else 1152 pp |= HPTE_R_N; 1153 } 1154 return pp; 1155 } 1156 1157 #ifdef CONFIG_PPC_MM_SLICES 1158 static unsigned int get_paca_psize(unsigned long addr) 1159 { 1160 unsigned char *psizes; 1161 unsigned long index, mask_index; 1162 1163 if (addr < SLICE_LOW_TOP) { 1164 psizes = get_paca()->mm_ctx_low_slices_psize; 1165 index = GET_LOW_SLICE_INDEX(addr); 1166 } else { 1167 psizes = get_paca()->mm_ctx_high_slices_psize; 1168 index = GET_HIGH_SLICE_INDEX(addr); 1169 } 1170 mask_index = index & 0x1; 1171 return (psizes[index >> 1] >> (mask_index * 4)) & 0xF; 1172 } 1173 1174 #else 1175 unsigned int get_paca_psize(unsigned long addr) 1176 { 1177 return get_paca()->mm_ctx_user_psize; 1178 } 1179 #endif 1180 1181 /* 1182 * Demote a segment to using 4k pages. 1183 * For now this makes the whole process use 4k pages. 1184 */ 1185 #ifdef CONFIG_PPC_64K_PAGES 1186 void demote_segment_4k(struct mm_struct *mm, unsigned long addr) 1187 { 1188 if (get_slice_psize(mm, addr) == MMU_PAGE_4K) 1189 return; 1190 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K); 1191 copro_flush_all_slbs(mm); 1192 if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) { 1193 1194 copy_mm_to_paca(mm); 1195 slb_flush_and_restore_bolted(); 1196 } 1197 } 1198 #endif /* CONFIG_PPC_64K_PAGES */ 1199 1200 #ifdef CONFIG_PPC_SUBPAGE_PROT 1201 /* 1202 * This looks up a 2-bit protection code for a 4k subpage of a 64k page. 1203 * Userspace sets the subpage permissions using the subpage_prot system call. 1204 * 1205 * Result is 0: full permissions, _PAGE_RW: read-only, 1206 * _PAGE_RWX: no access. 1207 */ 1208 static int subpage_protection(struct mm_struct *mm, unsigned long ea) 1209 { 1210 struct subpage_prot_table *spt = mm_ctx_subpage_prot(&mm->context); 1211 u32 spp = 0; 1212 u32 **sbpm, *sbpp; 1213 1214 if (!spt) 1215 return 0; 1216 1217 if (ea >= spt->maxaddr) 1218 return 0; 1219 if (ea < 0x100000000UL) { 1220 /* addresses below 4GB use spt->low_prot */ 1221 sbpm = spt->low_prot; 1222 } else { 1223 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT]; 1224 if (!sbpm) 1225 return 0; 1226 } 1227 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)]; 1228 if (!sbpp) 1229 return 0; 1230 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)]; 1231 1232 /* extract 2-bit bitfield for this 4k subpage */ 1233 spp >>= 30 - 2 * ((ea >> 12) & 0xf); 1234 1235 /* 1236 * 0 -> full premission 1237 * 1 -> Read only 1238 * 2 -> no access. 1239 * We return the flag that need to be cleared. 1240 */ 1241 spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0); 1242 return spp; 1243 } 1244 1245 #else /* CONFIG_PPC_SUBPAGE_PROT */ 1246 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea) 1247 { 1248 return 0; 1249 } 1250 #endif 1251 1252 void hash_failure_debug(unsigned long ea, unsigned long access, 1253 unsigned long vsid, unsigned long trap, 1254 int ssize, int psize, int lpsize, unsigned long pte) 1255 { 1256 if (!printk_ratelimit()) 1257 return; 1258 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n", 1259 ea, access, current->comm); 1260 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n", 1261 trap, vsid, ssize, psize, lpsize, pte); 1262 } 1263 1264 static void check_paca_psize(unsigned long ea, struct mm_struct *mm, 1265 int psize, bool user_region) 1266 { 1267 if (user_region) { 1268 if (psize != get_paca_psize(ea)) { 1269 copy_mm_to_paca(mm); 1270 slb_flush_and_restore_bolted(); 1271 } 1272 } else if (get_paca()->vmalloc_sllp != 1273 mmu_psize_defs[mmu_vmalloc_psize].sllp) { 1274 get_paca()->vmalloc_sllp = 1275 mmu_psize_defs[mmu_vmalloc_psize].sllp; 1276 slb_vmalloc_update(); 1277 } 1278 } 1279 1280 /* 1281 * Result code is: 1282 * 0 - handled 1283 * 1 - normal page fault 1284 * -1 - critical hash insertion error 1285 * -2 - access not permitted by subpage protection mechanism 1286 */ 1287 int hash_page_mm(struct mm_struct *mm, unsigned long ea, 1288 unsigned long access, unsigned long trap, 1289 unsigned long flags) 1290 { 1291 bool is_thp; 1292 pgd_t *pgdir; 1293 unsigned long vsid; 1294 pte_t *ptep; 1295 unsigned hugeshift; 1296 int rc, user_region = 0; 1297 int psize, ssize; 1298 1299 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n", 1300 ea, access, trap); 1301 trace_hash_fault(ea, access, trap); 1302 1303 /* Get region & vsid */ 1304 switch (get_region_id(ea)) { 1305 case USER_REGION_ID: 1306 user_region = 1; 1307 if (! mm) { 1308 DBG_LOW(" user region with no mm !\n"); 1309 rc = 1; 1310 goto bail; 1311 } 1312 psize = get_slice_psize(mm, ea); 1313 ssize = user_segment_size(ea); 1314 vsid = get_user_vsid(&mm->context, ea, ssize); 1315 break; 1316 case VMALLOC_REGION_ID: 1317 vsid = get_kernel_vsid(ea, mmu_kernel_ssize); 1318 psize = mmu_vmalloc_psize; 1319 ssize = mmu_kernel_ssize; 1320 flags |= HPTE_USE_KERNEL_KEY; 1321 break; 1322 1323 case IO_REGION_ID: 1324 vsid = get_kernel_vsid(ea, mmu_kernel_ssize); 1325 psize = mmu_io_psize; 1326 ssize = mmu_kernel_ssize; 1327 flags |= HPTE_USE_KERNEL_KEY; 1328 break; 1329 default: 1330 /* 1331 * Not a valid range 1332 * Send the problem up to do_page_fault() 1333 */ 1334 rc = 1; 1335 goto bail; 1336 } 1337 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid); 1338 1339 /* Bad address. */ 1340 if (!vsid) { 1341 DBG_LOW("Bad address!\n"); 1342 rc = 1; 1343 goto bail; 1344 } 1345 /* Get pgdir */ 1346 pgdir = mm->pgd; 1347 if (pgdir == NULL) { 1348 rc = 1; 1349 goto bail; 1350 } 1351 1352 /* Check CPU locality */ 1353 if (user_region && mm_is_thread_local(mm)) 1354 flags |= HPTE_LOCAL_UPDATE; 1355 1356 #ifndef CONFIG_PPC_64K_PAGES 1357 /* 1358 * If we use 4K pages and our psize is not 4K, then we might 1359 * be hitting a special driver mapping, and need to align the 1360 * address before we fetch the PTE. 1361 * 1362 * It could also be a hugepage mapping, in which case this is 1363 * not necessary, but it's not harmful, either. 1364 */ 1365 if (psize != MMU_PAGE_4K) 1366 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1); 1367 #endif /* CONFIG_PPC_64K_PAGES */ 1368 1369 /* Get PTE and page size from page tables */ 1370 ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift); 1371 if (ptep == NULL || !pte_present(*ptep)) { 1372 DBG_LOW(" no PTE !\n"); 1373 rc = 1; 1374 goto bail; 1375 } 1376 1377 /* 1378 * Add _PAGE_PRESENT to the required access perm. If there are parallel 1379 * updates to the pte that can possibly clear _PAGE_PTE, catch that too. 1380 * 1381 * We can safely use the return pte address in rest of the function 1382 * because we do set H_PAGE_BUSY which prevents further updates to pte 1383 * from generic code. 1384 */ 1385 access |= _PAGE_PRESENT | _PAGE_PTE; 1386 1387 /* 1388 * Pre-check access permissions (will be re-checked atomically 1389 * in __hash_page_XX but this pre-check is a fast path 1390 */ 1391 if (!check_pte_access(access, pte_val(*ptep))) { 1392 DBG_LOW(" no access !\n"); 1393 rc = 1; 1394 goto bail; 1395 } 1396 1397 if (hugeshift) { 1398 if (is_thp) 1399 rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep, 1400 trap, flags, ssize, psize); 1401 #ifdef CONFIG_HUGETLB_PAGE 1402 else 1403 rc = __hash_page_huge(ea, access, vsid, ptep, trap, 1404 flags, ssize, hugeshift, psize); 1405 #else 1406 else { 1407 /* 1408 * if we have hugeshift, and is not transhuge with 1409 * hugetlb disabled, something is really wrong. 1410 */ 1411 rc = 1; 1412 WARN_ON(1); 1413 } 1414 #endif 1415 if (current->mm == mm) 1416 check_paca_psize(ea, mm, psize, user_region); 1417 1418 goto bail; 1419 } 1420 1421 #ifndef CONFIG_PPC_64K_PAGES 1422 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep)); 1423 #else 1424 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep), 1425 pte_val(*(ptep + PTRS_PER_PTE))); 1426 #endif 1427 /* Do actual hashing */ 1428 #ifdef CONFIG_PPC_64K_PAGES 1429 /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */ 1430 if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) { 1431 demote_segment_4k(mm, ea); 1432 psize = MMU_PAGE_4K; 1433 } 1434 1435 /* 1436 * If this PTE is non-cacheable and we have restrictions on 1437 * using non cacheable large pages, then we switch to 4k 1438 */ 1439 if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) { 1440 if (user_region) { 1441 demote_segment_4k(mm, ea); 1442 psize = MMU_PAGE_4K; 1443 } else if (ea < VMALLOC_END) { 1444 /* 1445 * some driver did a non-cacheable mapping 1446 * in vmalloc space, so switch vmalloc 1447 * to 4k pages 1448 */ 1449 printk(KERN_ALERT "Reducing vmalloc segment " 1450 "to 4kB pages because of " 1451 "non-cacheable mapping\n"); 1452 psize = mmu_vmalloc_psize = MMU_PAGE_4K; 1453 copro_flush_all_slbs(mm); 1454 } 1455 } 1456 1457 #endif /* CONFIG_PPC_64K_PAGES */ 1458 1459 if (current->mm == mm) 1460 check_paca_psize(ea, mm, psize, user_region); 1461 1462 #ifdef CONFIG_PPC_64K_PAGES 1463 if (psize == MMU_PAGE_64K) 1464 rc = __hash_page_64K(ea, access, vsid, ptep, trap, 1465 flags, ssize); 1466 else 1467 #endif /* CONFIG_PPC_64K_PAGES */ 1468 { 1469 int spp = subpage_protection(mm, ea); 1470 if (access & spp) 1471 rc = -2; 1472 else 1473 rc = __hash_page_4K(ea, access, vsid, ptep, trap, 1474 flags, ssize, spp); 1475 } 1476 1477 /* 1478 * Dump some info in case of hash insertion failure, they should 1479 * never happen so it is really useful to know if/when they do 1480 */ 1481 if (rc == -1) 1482 hash_failure_debug(ea, access, vsid, trap, ssize, psize, 1483 psize, pte_val(*ptep)); 1484 #ifndef CONFIG_PPC_64K_PAGES 1485 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep)); 1486 #else 1487 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep), 1488 pte_val(*(ptep + PTRS_PER_PTE))); 1489 #endif 1490 DBG_LOW(" -> rc=%d\n", rc); 1491 1492 bail: 1493 return rc; 1494 } 1495 EXPORT_SYMBOL_GPL(hash_page_mm); 1496 1497 int hash_page(unsigned long ea, unsigned long access, unsigned long trap, 1498 unsigned long dsisr) 1499 { 1500 unsigned long flags = 0; 1501 struct mm_struct *mm = current->mm; 1502 1503 if ((get_region_id(ea) == VMALLOC_REGION_ID) || 1504 (get_region_id(ea) == IO_REGION_ID)) 1505 mm = &init_mm; 1506 1507 if (dsisr & DSISR_NOHPTE) 1508 flags |= HPTE_NOHPTE_UPDATE; 1509 1510 return hash_page_mm(mm, ea, access, trap, flags); 1511 } 1512 EXPORT_SYMBOL_GPL(hash_page); 1513 1514 DECLARE_INTERRUPT_HANDLER_RET(__do_hash_fault); 1515 DEFINE_INTERRUPT_HANDLER_RET(__do_hash_fault) 1516 { 1517 unsigned long ea = regs->dar; 1518 unsigned long dsisr = regs->dsisr; 1519 unsigned long access = _PAGE_PRESENT | _PAGE_READ; 1520 unsigned long flags = 0; 1521 struct mm_struct *mm; 1522 unsigned int region_id; 1523 long err; 1524 1525 region_id = get_region_id(ea); 1526 if ((region_id == VMALLOC_REGION_ID) || (region_id == IO_REGION_ID)) 1527 mm = &init_mm; 1528 else 1529 mm = current->mm; 1530 1531 if (dsisr & DSISR_NOHPTE) 1532 flags |= HPTE_NOHPTE_UPDATE; 1533 1534 if (dsisr & DSISR_ISSTORE) 1535 access |= _PAGE_WRITE; 1536 /* 1537 * We set _PAGE_PRIVILEGED only when 1538 * kernel mode access kernel space. 1539 * 1540 * _PAGE_PRIVILEGED is NOT set 1541 * 1) when kernel mode access user space 1542 * 2) user space access kernel space. 1543 */ 1544 access |= _PAGE_PRIVILEGED; 1545 if (user_mode(regs) || (region_id == USER_REGION_ID)) 1546 access &= ~_PAGE_PRIVILEGED; 1547 1548 if (regs->trap == 0x400) 1549 access |= _PAGE_EXEC; 1550 1551 err = hash_page_mm(mm, ea, access, regs->trap, flags); 1552 if (unlikely(err < 0)) { 1553 // failed to instert a hash PTE due to an hypervisor error 1554 if (user_mode(regs)) { 1555 if (IS_ENABLED(CONFIG_PPC_SUBPAGE_PROT) && err == -2) 1556 _exception(SIGSEGV, regs, SEGV_ACCERR, ea); 1557 else 1558 _exception(SIGBUS, regs, BUS_ADRERR, ea); 1559 } else { 1560 bad_page_fault(regs, SIGBUS); 1561 } 1562 err = 0; 1563 } 1564 1565 return err; 1566 } 1567 1568 /* 1569 * The _RAW interrupt entry checks for the in_nmi() case before 1570 * running the full handler. 1571 */ 1572 DEFINE_INTERRUPT_HANDLER_RAW(do_hash_fault) 1573 { 1574 unsigned long dsisr = regs->dsisr; 1575 long err; 1576 1577 if (unlikely(dsisr & (DSISR_BAD_FAULT_64S | DSISR_KEYFAULT))) 1578 goto page_fault; 1579 1580 /* 1581 * If we are in an "NMI" (e.g., an interrupt when soft-disabled), then 1582 * don't call hash_page, just fail the fault. This is required to 1583 * prevent re-entrancy problems in the hash code, namely perf 1584 * interrupts hitting while something holds H_PAGE_BUSY, and taking a 1585 * hash fault. See the comment in hash_preload(). 1586 * 1587 * We come here as a result of a DSI at a point where we don't want 1588 * to call hash_page, such as when we are accessing memory (possibly 1589 * user memory) inside a PMU interrupt that occurred while interrupts 1590 * were soft-disabled. We want to invoke the exception handler for 1591 * the access, or panic if there isn't a handler. 1592 */ 1593 if (unlikely(in_nmi())) { 1594 do_bad_page_fault_segv(regs); 1595 return 0; 1596 } 1597 1598 err = __do_hash_fault(regs); 1599 if (err) { 1600 page_fault: 1601 err = hash__do_page_fault(regs); 1602 } 1603 1604 return err; 1605 } 1606 1607 #ifdef CONFIG_PPC_MM_SLICES 1608 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea) 1609 { 1610 int psize = get_slice_psize(mm, ea); 1611 1612 /* We only prefault standard pages for now */ 1613 if (unlikely(psize != mm_ctx_user_psize(&mm->context))) 1614 return false; 1615 1616 /* 1617 * Don't prefault if subpage protection is enabled for the EA. 1618 */ 1619 if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea))) 1620 return false; 1621 1622 return true; 1623 } 1624 #else 1625 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea) 1626 { 1627 return true; 1628 } 1629 #endif 1630 1631 static void hash_preload(struct mm_struct *mm, pte_t *ptep, unsigned long ea, 1632 bool is_exec, unsigned long trap) 1633 { 1634 unsigned long vsid; 1635 pgd_t *pgdir; 1636 int rc, ssize, update_flags = 0; 1637 unsigned long access = _PAGE_PRESENT | _PAGE_READ | (is_exec ? _PAGE_EXEC : 0); 1638 unsigned long flags; 1639 1640 BUG_ON(get_region_id(ea) != USER_REGION_ID); 1641 1642 if (!should_hash_preload(mm, ea)) 1643 return; 1644 1645 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx," 1646 " trap=%lx\n", mm, mm->pgd, ea, access, trap); 1647 1648 /* Get Linux PTE if available */ 1649 pgdir = mm->pgd; 1650 if (pgdir == NULL) 1651 return; 1652 1653 /* Get VSID */ 1654 ssize = user_segment_size(ea); 1655 vsid = get_user_vsid(&mm->context, ea, ssize); 1656 if (!vsid) 1657 return; 1658 1659 #ifdef CONFIG_PPC_64K_PAGES 1660 /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on 1661 * a 64K kernel), then we don't preload, hash_page() will take 1662 * care of it once we actually try to access the page. 1663 * That way we don't have to duplicate all of the logic for segment 1664 * page size demotion here 1665 * Called with PTL held, hence can be sure the value won't change in 1666 * between. 1667 */ 1668 if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep)) 1669 return; 1670 #endif /* CONFIG_PPC_64K_PAGES */ 1671 1672 /* 1673 * __hash_page_* must run with interrupts off, as it sets the 1674 * H_PAGE_BUSY bit. It's possible for perf interrupts to hit at any 1675 * time and may take a hash fault reading the user stack, see 1676 * read_user_stack_slow() in the powerpc/perf code. 1677 * 1678 * If that takes a hash fault on the same page as we lock here, it 1679 * will bail out when seeing H_PAGE_BUSY set, and retry the access 1680 * leading to an infinite loop. 1681 * 1682 * Disabling interrupts here does not prevent perf interrupts, but it 1683 * will prevent them taking hash faults (see the NMI test in 1684 * do_hash_page), then read_user_stack's copy_from_user_nofault will 1685 * fail and perf will fall back to read_user_stack_slow(), which 1686 * walks the Linux page tables. 1687 * 1688 * Interrupts must also be off for the duration of the 1689 * mm_is_thread_local test and update, to prevent preempt running the 1690 * mm on another CPU (XXX: this may be racy vs kthread_use_mm). 1691 */ 1692 local_irq_save(flags); 1693 1694 /* Is that local to this CPU ? */ 1695 if (mm_is_thread_local(mm)) 1696 update_flags |= HPTE_LOCAL_UPDATE; 1697 1698 /* Hash it in */ 1699 #ifdef CONFIG_PPC_64K_PAGES 1700 if (mm_ctx_user_psize(&mm->context) == MMU_PAGE_64K) 1701 rc = __hash_page_64K(ea, access, vsid, ptep, trap, 1702 update_flags, ssize); 1703 else 1704 #endif /* CONFIG_PPC_64K_PAGES */ 1705 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags, 1706 ssize, subpage_protection(mm, ea)); 1707 1708 /* Dump some info in case of hash insertion failure, they should 1709 * never happen so it is really useful to know if/when they do 1710 */ 1711 if (rc == -1) 1712 hash_failure_debug(ea, access, vsid, trap, ssize, 1713 mm_ctx_user_psize(&mm->context), 1714 mm_ctx_user_psize(&mm->context), 1715 pte_val(*ptep)); 1716 1717 local_irq_restore(flags); 1718 } 1719 1720 /* 1721 * This is called at the end of handling a user page fault, when the 1722 * fault has been handled by updating a PTE in the linux page tables. 1723 * We use it to preload an HPTE into the hash table corresponding to 1724 * the updated linux PTE. 1725 * 1726 * This must always be called with the pte lock held. 1727 */ 1728 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, 1729 pte_t *ptep) 1730 { 1731 /* 1732 * We don't need to worry about _PAGE_PRESENT here because we are 1733 * called with either mm->page_table_lock held or ptl lock held 1734 */ 1735 unsigned long trap; 1736 bool is_exec; 1737 1738 if (radix_enabled()) 1739 return; 1740 1741 /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */ 1742 if (!pte_young(*ptep) || address >= TASK_SIZE) 1743 return; 1744 1745 /* 1746 * We try to figure out if we are coming from an instruction 1747 * access fault and pass that down to __hash_page so we avoid 1748 * double-faulting on execution of fresh text. We have to test 1749 * for regs NULL since init will get here first thing at boot. 1750 * 1751 * We also avoid filling the hash if not coming from a fault. 1752 */ 1753 1754 trap = current->thread.regs ? TRAP(current->thread.regs) : 0UL; 1755 switch (trap) { 1756 case 0x300: 1757 is_exec = false; 1758 break; 1759 case 0x400: 1760 is_exec = true; 1761 break; 1762 default: 1763 return; 1764 } 1765 1766 hash_preload(vma->vm_mm, ptep, address, is_exec, trap); 1767 } 1768 1769 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1770 static inline void tm_flush_hash_page(int local) 1771 { 1772 /* 1773 * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a 1774 * page back to a block device w/PIO could pick up transactional data 1775 * (bad!) so we force an abort here. Before the sync the page will be 1776 * made read-only, which will flush_hash_page. BIG ISSUE here: if the 1777 * kernel uses a page from userspace without unmapping it first, it may 1778 * see the speculated version. 1779 */ 1780 if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs && 1781 MSR_TM_ACTIVE(current->thread.regs->msr)) { 1782 tm_enable(); 1783 tm_abort(TM_CAUSE_TLBI); 1784 } 1785 } 1786 #else 1787 static inline void tm_flush_hash_page(int local) 1788 { 1789 } 1790 #endif 1791 1792 /* 1793 * Return the global hash slot, corresponding to the given PTE, which contains 1794 * the HPTE. 1795 */ 1796 unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift, 1797 int ssize, real_pte_t rpte, unsigned int subpg_index) 1798 { 1799 unsigned long hash, gslot, hidx; 1800 1801 hash = hpt_hash(vpn, shift, ssize); 1802 hidx = __rpte_to_hidx(rpte, subpg_index); 1803 if (hidx & _PTEIDX_SECONDARY) 1804 hash = ~hash; 1805 gslot = (hash & htab_hash_mask) * HPTES_PER_GROUP; 1806 gslot += hidx & _PTEIDX_GROUP_IX; 1807 return gslot; 1808 } 1809 1810 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize, 1811 unsigned long flags) 1812 { 1813 unsigned long index, shift, gslot; 1814 int local = flags & HPTE_LOCAL_UPDATE; 1815 1816 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn); 1817 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) { 1818 gslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index); 1819 DBG_LOW(" sub %ld: gslot=%lx\n", index, gslot); 1820 /* 1821 * We use same base page size and actual psize, because we don't 1822 * use these functions for hugepage 1823 */ 1824 mmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize, 1825 ssize, local); 1826 } pte_iterate_hashed_end(); 1827 1828 tm_flush_hash_page(local); 1829 } 1830 1831 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1832 void flush_hash_hugepage(unsigned long vsid, unsigned long addr, 1833 pmd_t *pmdp, unsigned int psize, int ssize, 1834 unsigned long flags) 1835 { 1836 int i, max_hpte_count, valid; 1837 unsigned long s_addr; 1838 unsigned char *hpte_slot_array; 1839 unsigned long hidx, shift, vpn, hash, slot; 1840 int local = flags & HPTE_LOCAL_UPDATE; 1841 1842 s_addr = addr & HPAGE_PMD_MASK; 1843 hpte_slot_array = get_hpte_slot_array(pmdp); 1844 /* 1845 * IF we try to do a HUGE PTE update after a withdraw is done. 1846 * we will find the below NULL. This happens when we do 1847 * split_huge_pmd 1848 */ 1849 if (!hpte_slot_array) 1850 return; 1851 1852 if (mmu_hash_ops.hugepage_invalidate) { 1853 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array, 1854 psize, ssize, local); 1855 goto tm_abort; 1856 } 1857 /* 1858 * No bluk hpte removal support, invalidate each entry 1859 */ 1860 shift = mmu_psize_defs[psize].shift; 1861 max_hpte_count = HPAGE_PMD_SIZE >> shift; 1862 for (i = 0; i < max_hpte_count; i++) { 1863 /* 1864 * 8 bits per each hpte entries 1865 * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit] 1866 */ 1867 valid = hpte_valid(hpte_slot_array, i); 1868 if (!valid) 1869 continue; 1870 hidx = hpte_hash_index(hpte_slot_array, i); 1871 1872 /* get the vpn */ 1873 addr = s_addr + (i * (1ul << shift)); 1874 vpn = hpt_vpn(addr, vsid, ssize); 1875 hash = hpt_hash(vpn, shift, ssize); 1876 if (hidx & _PTEIDX_SECONDARY) 1877 hash = ~hash; 1878 1879 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; 1880 slot += hidx & _PTEIDX_GROUP_IX; 1881 mmu_hash_ops.hpte_invalidate(slot, vpn, psize, 1882 MMU_PAGE_16M, ssize, local); 1883 } 1884 tm_abort: 1885 tm_flush_hash_page(local); 1886 } 1887 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1888 1889 void flush_hash_range(unsigned long number, int local) 1890 { 1891 if (mmu_hash_ops.flush_hash_range) 1892 mmu_hash_ops.flush_hash_range(number, local); 1893 else { 1894 int i; 1895 struct ppc64_tlb_batch *batch = 1896 this_cpu_ptr(&ppc64_tlb_batch); 1897 1898 for (i = 0; i < number; i++) 1899 flush_hash_page(batch->vpn[i], batch->pte[i], 1900 batch->psize, batch->ssize, local); 1901 } 1902 } 1903 1904 long hpte_insert_repeating(unsigned long hash, unsigned long vpn, 1905 unsigned long pa, unsigned long rflags, 1906 unsigned long vflags, int psize, int ssize) 1907 { 1908 unsigned long hpte_group; 1909 long slot; 1910 1911 repeat: 1912 hpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP; 1913 1914 /* Insert into the hash table, primary slot */ 1915 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags, 1916 psize, psize, ssize); 1917 1918 /* Primary is full, try the secondary */ 1919 if (unlikely(slot == -1)) { 1920 hpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP; 1921 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, 1922 vflags | HPTE_V_SECONDARY, 1923 psize, psize, ssize); 1924 if (slot == -1) { 1925 if (mftb() & 0x1) 1926 hpte_group = (hash & htab_hash_mask) * 1927 HPTES_PER_GROUP; 1928 1929 mmu_hash_ops.hpte_remove(hpte_group); 1930 goto repeat; 1931 } 1932 } 1933 1934 return slot; 1935 } 1936 1937 #ifdef CONFIG_DEBUG_PAGEALLOC 1938 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi) 1939 { 1940 unsigned long hash; 1941 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); 1942 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); 1943 unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL), HPTE_USE_KERNEL_KEY); 1944 long ret; 1945 1946 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); 1947 1948 /* Don't create HPTE entries for bad address */ 1949 if (!vsid) 1950 return; 1951 1952 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode, 1953 HPTE_V_BOLTED, 1954 mmu_linear_psize, mmu_kernel_ssize); 1955 1956 BUG_ON (ret < 0); 1957 spin_lock(&linear_map_hash_lock); 1958 BUG_ON(linear_map_hash_slots[lmi] & 0x80); 1959 linear_map_hash_slots[lmi] = ret | 0x80; 1960 spin_unlock(&linear_map_hash_lock); 1961 } 1962 1963 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi) 1964 { 1965 unsigned long hash, hidx, slot; 1966 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); 1967 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); 1968 1969 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); 1970 spin_lock(&linear_map_hash_lock); 1971 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80)); 1972 hidx = linear_map_hash_slots[lmi] & 0x7f; 1973 linear_map_hash_slots[lmi] = 0; 1974 spin_unlock(&linear_map_hash_lock); 1975 if (hidx & _PTEIDX_SECONDARY) 1976 hash = ~hash; 1977 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; 1978 slot += hidx & _PTEIDX_GROUP_IX; 1979 mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize, 1980 mmu_linear_psize, 1981 mmu_kernel_ssize, 0); 1982 } 1983 1984 void __kernel_map_pages(struct page *page, int numpages, int enable) 1985 { 1986 unsigned long flags, vaddr, lmi; 1987 int i; 1988 1989 local_irq_save(flags); 1990 for (i = 0; i < numpages; i++, page++) { 1991 vaddr = (unsigned long)page_address(page); 1992 lmi = __pa(vaddr) >> PAGE_SHIFT; 1993 if (lmi >= linear_map_hash_count) 1994 continue; 1995 if (enable) 1996 kernel_map_linear_page(vaddr, lmi); 1997 else 1998 kernel_unmap_linear_page(vaddr, lmi); 1999 } 2000 local_irq_restore(flags); 2001 } 2002 #endif /* CONFIG_DEBUG_PAGEALLOC */ 2003 2004 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base, 2005 phys_addr_t first_memblock_size) 2006 { 2007 /* 2008 * We don't currently support the first MEMBLOCK not mapping 0 2009 * physical on those processors 2010 */ 2011 BUG_ON(first_memblock_base != 0); 2012 2013 /* 2014 * On virtualized systems the first entry is our RMA region aka VRMA, 2015 * non-virtualized 64-bit hash MMU systems don't have a limitation 2016 * on real mode access. 2017 * 2018 * For guests on platforms before POWER9, we clamp the it limit to 1G 2019 * to avoid some funky things such as RTAS bugs etc... 2020 * 2021 * On POWER9 we limit to 1TB in case the host erroneously told us that 2022 * the RMA was >1TB. Effective address bits 0:23 are treated as zero 2023 * (meaning the access is aliased to zero i.e. addr = addr % 1TB) 2024 * for virtual real mode addressing and so it doesn't make sense to 2025 * have an area larger than 1TB as it can't be addressed. 2026 */ 2027 if (!early_cpu_has_feature(CPU_FTR_HVMODE)) { 2028 ppc64_rma_size = first_memblock_size; 2029 if (!early_cpu_has_feature(CPU_FTR_ARCH_300)) 2030 ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000); 2031 else 2032 ppc64_rma_size = min_t(u64, ppc64_rma_size, 2033 1UL << SID_SHIFT_1T); 2034 2035 /* Finally limit subsequent allocations */ 2036 memblock_set_current_limit(ppc64_rma_size); 2037 } else { 2038 ppc64_rma_size = ULONG_MAX; 2039 } 2040 } 2041 2042 #ifdef CONFIG_DEBUG_FS 2043 2044 static int hpt_order_get(void *data, u64 *val) 2045 { 2046 *val = ppc64_pft_size; 2047 return 0; 2048 } 2049 2050 static int hpt_order_set(void *data, u64 val) 2051 { 2052 int ret; 2053 2054 if (!mmu_hash_ops.resize_hpt) 2055 return -ENODEV; 2056 2057 cpus_read_lock(); 2058 ret = mmu_hash_ops.resize_hpt(val); 2059 cpus_read_unlock(); 2060 2061 return ret; 2062 } 2063 2064 DEFINE_DEBUGFS_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n"); 2065 2066 static int __init hash64_debugfs(void) 2067 { 2068 debugfs_create_file("hpt_order", 0600, powerpc_debugfs_root, NULL, 2069 &fops_hpt_order); 2070 return 0; 2071 } 2072 machine_device_initcall(pseries, hash64_debugfs); 2073 #endif /* CONFIG_DEBUG_FS */ 2074 2075 void __init print_system_hash_info(void) 2076 { 2077 pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); 2078 2079 if (htab_hash_mask) 2080 pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask); 2081 } 2082