1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * PowerPC64 port by Mike Corrigan and Dave Engebretsen 4 * {mikejc|engebret}@us.ibm.com 5 * 6 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com> 7 * 8 * SMP scalability work: 9 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM 10 * 11 * Module name: htab.c 12 * 13 * Description: 14 * PowerPC Hashed Page Table functions 15 */ 16 17 #undef DEBUG 18 #undef DEBUG_LOW 19 20 #define pr_fmt(fmt) "hash-mmu: " fmt 21 #include <linux/spinlock.h> 22 #include <linux/errno.h> 23 #include <linux/sched/mm.h> 24 #include <linux/proc_fs.h> 25 #include <linux/stat.h> 26 #include <linux/sysctl.h> 27 #include <linux/export.h> 28 #include <linux/ctype.h> 29 #include <linux/cache.h> 30 #include <linux/init.h> 31 #include <linux/signal.h> 32 #include <linux/memblock.h> 33 #include <linux/context_tracking.h> 34 #include <linux/libfdt.h> 35 #include <linux/pkeys.h> 36 #include <linux/hugetlb.h> 37 #include <linux/cpu.h> 38 #include <linux/pgtable.h> 39 40 #include <asm/debugfs.h> 41 #include <asm/processor.h> 42 #include <asm/mmu.h> 43 #include <asm/mmu_context.h> 44 #include <asm/page.h> 45 #include <asm/types.h> 46 #include <linux/uaccess.h> 47 #include <asm/machdep.h> 48 #include <asm/prom.h> 49 #include <asm/io.h> 50 #include <asm/eeh.h> 51 #include <asm/tlb.h> 52 #include <asm/cacheflush.h> 53 #include <asm/cputable.h> 54 #include <asm/sections.h> 55 #include <asm/copro.h> 56 #include <asm/udbg.h> 57 #include <asm/code-patching.h> 58 #include <asm/fadump.h> 59 #include <asm/firmware.h> 60 #include <asm/tm.h> 61 #include <asm/trace.h> 62 #include <asm/ps3.h> 63 #include <asm/pte-walk.h> 64 #include <asm/asm-prototypes.h> 65 #include <asm/ultravisor.h> 66 67 #include <mm/mmu_decl.h> 68 69 #include "internal.h" 70 71 72 #ifdef DEBUG 73 #define DBG(fmt...) udbg_printf(fmt) 74 #else 75 #define DBG(fmt...) 76 #endif 77 78 #ifdef DEBUG_LOW 79 #define DBG_LOW(fmt...) udbg_printf(fmt) 80 #else 81 #define DBG_LOW(fmt...) 82 #endif 83 84 #define KB (1024) 85 #define MB (1024*KB) 86 #define GB (1024L*MB) 87 88 /* 89 * Note: pte --> Linux PTE 90 * HPTE --> PowerPC Hashed Page Table Entry 91 * 92 * Execution context: 93 * htab_initialize is called with the MMU off (of course), but 94 * the kernel has been copied down to zero so it can directly 95 * reference global data. At this point it is very difficult 96 * to print debug info. 97 * 98 */ 99 100 static unsigned long _SDR1; 101 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; 102 EXPORT_SYMBOL_GPL(mmu_psize_defs); 103 104 u8 hpte_page_sizes[1 << LP_BITS]; 105 EXPORT_SYMBOL_GPL(hpte_page_sizes); 106 107 struct hash_pte *htab_address; 108 unsigned long htab_size_bytes; 109 unsigned long htab_hash_mask; 110 EXPORT_SYMBOL_GPL(htab_hash_mask); 111 int mmu_linear_psize = MMU_PAGE_4K; 112 EXPORT_SYMBOL_GPL(mmu_linear_psize); 113 int mmu_virtual_psize = MMU_PAGE_4K; 114 int mmu_vmalloc_psize = MMU_PAGE_4K; 115 #ifdef CONFIG_SPARSEMEM_VMEMMAP 116 int mmu_vmemmap_psize = MMU_PAGE_4K; 117 #endif 118 int mmu_io_psize = MMU_PAGE_4K; 119 int mmu_kernel_ssize = MMU_SEGSIZE_256M; 120 EXPORT_SYMBOL_GPL(mmu_kernel_ssize); 121 int mmu_highuser_ssize = MMU_SEGSIZE_256M; 122 u16 mmu_slb_size = 64; 123 EXPORT_SYMBOL_GPL(mmu_slb_size); 124 #ifdef CONFIG_PPC_64K_PAGES 125 int mmu_ci_restrictions; 126 #endif 127 #ifdef CONFIG_DEBUG_PAGEALLOC 128 static u8 *linear_map_hash_slots; 129 static unsigned long linear_map_hash_count; 130 static DEFINE_SPINLOCK(linear_map_hash_lock); 131 #endif /* CONFIG_DEBUG_PAGEALLOC */ 132 struct mmu_hash_ops mmu_hash_ops; 133 EXPORT_SYMBOL(mmu_hash_ops); 134 135 /* 136 * These are definitions of page sizes arrays to be used when none 137 * is provided by the firmware. 138 */ 139 140 /* 141 * Fallback (4k pages only) 142 */ 143 static struct mmu_psize_def mmu_psize_defaults[] = { 144 [MMU_PAGE_4K] = { 145 .shift = 12, 146 .sllp = 0, 147 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, 148 .avpnm = 0, 149 .tlbiel = 0, 150 }, 151 }; 152 153 /* 154 * POWER4, GPUL, POWER5 155 * 156 * Support for 16Mb large pages 157 */ 158 static struct mmu_psize_def mmu_psize_defaults_gp[] = { 159 [MMU_PAGE_4K] = { 160 .shift = 12, 161 .sllp = 0, 162 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, 163 .avpnm = 0, 164 .tlbiel = 1, 165 }, 166 [MMU_PAGE_16M] = { 167 .shift = 24, 168 .sllp = SLB_VSID_L, 169 .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0, 170 [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 }, 171 .avpnm = 0x1UL, 172 .tlbiel = 0, 173 }, 174 }; 175 176 /* 177 * 'R' and 'C' update notes: 178 * - Under pHyp or KVM, the updatepp path will not set C, thus it *will* 179 * create writeable HPTEs without C set, because the hcall H_PROTECT 180 * that we use in that case will not update C 181 * - The above is however not a problem, because we also don't do that 182 * fancy "no flush" variant of eviction and we use H_REMOVE which will 183 * do the right thing and thus we don't have the race I described earlier 184 * 185 * - Under bare metal, we do have the race, so we need R and C set 186 * - We make sure R is always set and never lost 187 * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping 188 */ 189 unsigned long htab_convert_pte_flags(unsigned long pteflags) 190 { 191 unsigned long rflags = 0; 192 193 /* _PAGE_EXEC -> NOEXEC */ 194 if ((pteflags & _PAGE_EXEC) == 0) 195 rflags |= HPTE_R_N; 196 /* 197 * PPP bits: 198 * Linux uses slb key 0 for kernel and 1 for user. 199 * kernel RW areas are mapped with PPP=0b000 200 * User area is mapped with PPP=0b010 for read/write 201 * or PPP=0b011 for read-only (including writeable but clean pages). 202 */ 203 if (pteflags & _PAGE_PRIVILEGED) { 204 /* 205 * Kernel read only mapped with ppp bits 0b110 206 */ 207 if (!(pteflags & _PAGE_WRITE)) { 208 if (mmu_has_feature(MMU_FTR_KERNEL_RO)) 209 rflags |= (HPTE_R_PP0 | 0x2); 210 else 211 rflags |= 0x3; 212 } 213 } else { 214 if (pteflags & _PAGE_RWX) 215 rflags |= 0x2; 216 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY))) 217 rflags |= 0x1; 218 } 219 /* 220 * We can't allow hardware to update hpte bits. Hence always 221 * set 'R' bit and set 'C' if it is a write fault 222 */ 223 rflags |= HPTE_R_R; 224 225 if (pteflags & _PAGE_DIRTY) 226 rflags |= HPTE_R_C; 227 /* 228 * Add in WIG bits 229 */ 230 231 if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) 232 rflags |= HPTE_R_I; 233 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT) 234 rflags |= (HPTE_R_I | HPTE_R_G); 235 else 236 /* 237 * Add memory coherence if cache inhibited is not set 238 */ 239 rflags |= HPTE_R_M; 240 241 rflags |= pte_to_hpte_pkey_bits(pteflags); 242 return rflags; 243 } 244 245 int htab_bolt_mapping(unsigned long vstart, unsigned long vend, 246 unsigned long pstart, unsigned long prot, 247 int psize, int ssize) 248 { 249 unsigned long vaddr, paddr; 250 unsigned int step, shift; 251 int ret = 0; 252 253 shift = mmu_psize_defs[psize].shift; 254 step = 1 << shift; 255 256 prot = htab_convert_pte_flags(prot); 257 258 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n", 259 vstart, vend, pstart, prot, psize, ssize); 260 261 for (vaddr = vstart, paddr = pstart; vaddr < vend; 262 vaddr += step, paddr += step) { 263 unsigned long hash, hpteg; 264 unsigned long vsid = get_kernel_vsid(vaddr, ssize); 265 unsigned long vpn = hpt_vpn(vaddr, vsid, ssize); 266 unsigned long tprot = prot; 267 bool secondary_hash = false; 268 269 /* 270 * If we hit a bad address return error. 271 */ 272 if (!vsid) 273 return -1; 274 /* Make kernel text executable */ 275 if (overlaps_kernel_text(vaddr, vaddr + step)) 276 tprot &= ~HPTE_R_N; 277 278 /* 279 * If relocatable, check if it overlaps interrupt vectors that 280 * are copied down to real 0. For relocatable kernel 281 * (e.g. kdump case) we copy interrupt vectors down to real 282 * address 0. Mark that region as executable. This is 283 * because on p8 system with relocation on exception feature 284 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence 285 * in order to execute the interrupt handlers in virtual 286 * mode the vector region need to be marked as executable. 287 */ 288 if ((PHYSICAL_START > MEMORY_START) && 289 overlaps_interrupt_vector_text(vaddr, vaddr + step)) 290 tprot &= ~HPTE_R_N; 291 292 hash = hpt_hash(vpn, shift, ssize); 293 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); 294 295 BUG_ON(!mmu_hash_ops.hpte_insert); 296 repeat: 297 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot, 298 HPTE_V_BOLTED, psize, psize, 299 ssize); 300 if (ret == -1) { 301 /* 302 * Try to to keep bolted entries in primary. 303 * Remove non bolted entries and try insert again 304 */ 305 ret = mmu_hash_ops.hpte_remove(hpteg); 306 if (ret != -1) 307 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot, 308 HPTE_V_BOLTED, psize, psize, 309 ssize); 310 if (ret == -1 && !secondary_hash) { 311 secondary_hash = true; 312 hpteg = ((~hash & htab_hash_mask) * HPTES_PER_GROUP); 313 goto repeat; 314 } 315 } 316 317 if (ret < 0) 318 break; 319 320 cond_resched(); 321 #ifdef CONFIG_DEBUG_PAGEALLOC 322 if (debug_pagealloc_enabled() && 323 (paddr >> PAGE_SHIFT) < linear_map_hash_count) 324 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80; 325 #endif /* CONFIG_DEBUG_PAGEALLOC */ 326 } 327 return ret < 0 ? ret : 0; 328 } 329 330 int htab_remove_mapping(unsigned long vstart, unsigned long vend, 331 int psize, int ssize) 332 { 333 unsigned long vaddr; 334 unsigned int step, shift; 335 int rc; 336 int ret = 0; 337 338 shift = mmu_psize_defs[psize].shift; 339 step = 1 << shift; 340 341 if (!mmu_hash_ops.hpte_removebolted) 342 return -ENODEV; 343 344 for (vaddr = vstart; vaddr < vend; vaddr += step) { 345 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize); 346 if (rc == -ENOENT) { 347 ret = -ENOENT; 348 continue; 349 } 350 if (rc < 0) 351 return rc; 352 } 353 354 return ret; 355 } 356 357 static bool disable_1tb_segments = false; 358 359 static int __init parse_disable_1tb_segments(char *p) 360 { 361 disable_1tb_segments = true; 362 return 0; 363 } 364 early_param("disable_1tb_segments", parse_disable_1tb_segments); 365 366 static int __init htab_dt_scan_seg_sizes(unsigned long node, 367 const char *uname, int depth, 368 void *data) 369 { 370 const char *type = of_get_flat_dt_prop(node, "device_type", NULL); 371 const __be32 *prop; 372 int size = 0; 373 374 /* We are scanning "cpu" nodes only */ 375 if (type == NULL || strcmp(type, "cpu") != 0) 376 return 0; 377 378 prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size); 379 if (prop == NULL) 380 return 0; 381 for (; size >= 4; size -= 4, ++prop) { 382 if (be32_to_cpu(prop[0]) == 40) { 383 DBG("1T segment support detected\n"); 384 385 if (disable_1tb_segments) { 386 DBG("1T segments disabled by command line\n"); 387 break; 388 } 389 390 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT; 391 return 1; 392 } 393 } 394 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B; 395 return 0; 396 } 397 398 static int __init get_idx_from_shift(unsigned int shift) 399 { 400 int idx = -1; 401 402 switch (shift) { 403 case 0xc: 404 idx = MMU_PAGE_4K; 405 break; 406 case 0x10: 407 idx = MMU_PAGE_64K; 408 break; 409 case 0x14: 410 idx = MMU_PAGE_1M; 411 break; 412 case 0x18: 413 idx = MMU_PAGE_16M; 414 break; 415 case 0x22: 416 idx = MMU_PAGE_16G; 417 break; 418 } 419 return idx; 420 } 421 422 static int __init htab_dt_scan_page_sizes(unsigned long node, 423 const char *uname, int depth, 424 void *data) 425 { 426 const char *type = of_get_flat_dt_prop(node, "device_type", NULL); 427 const __be32 *prop; 428 int size = 0; 429 430 /* We are scanning "cpu" nodes only */ 431 if (type == NULL || strcmp(type, "cpu") != 0) 432 return 0; 433 434 prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size); 435 if (!prop) 436 return 0; 437 438 pr_info("Page sizes from device-tree:\n"); 439 size /= 4; 440 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE); 441 while(size > 0) { 442 unsigned int base_shift = be32_to_cpu(prop[0]); 443 unsigned int slbenc = be32_to_cpu(prop[1]); 444 unsigned int lpnum = be32_to_cpu(prop[2]); 445 struct mmu_psize_def *def; 446 int idx, base_idx; 447 448 size -= 3; prop += 3; 449 base_idx = get_idx_from_shift(base_shift); 450 if (base_idx < 0) { 451 /* skip the pte encoding also */ 452 prop += lpnum * 2; size -= lpnum * 2; 453 continue; 454 } 455 def = &mmu_psize_defs[base_idx]; 456 if (base_idx == MMU_PAGE_16M) 457 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE; 458 459 def->shift = base_shift; 460 if (base_shift <= 23) 461 def->avpnm = 0; 462 else 463 def->avpnm = (1 << (base_shift - 23)) - 1; 464 def->sllp = slbenc; 465 /* 466 * We don't know for sure what's up with tlbiel, so 467 * for now we only set it for 4K and 64K pages 468 */ 469 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K) 470 def->tlbiel = 1; 471 else 472 def->tlbiel = 0; 473 474 while (size > 0 && lpnum) { 475 unsigned int shift = be32_to_cpu(prop[0]); 476 int penc = be32_to_cpu(prop[1]); 477 478 prop += 2; size -= 2; 479 lpnum--; 480 481 idx = get_idx_from_shift(shift); 482 if (idx < 0) 483 continue; 484 485 if (penc == -1) 486 pr_err("Invalid penc for base_shift=%d " 487 "shift=%d\n", base_shift, shift); 488 489 def->penc[idx] = penc; 490 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx," 491 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n", 492 base_shift, shift, def->sllp, 493 def->avpnm, def->tlbiel, def->penc[idx]); 494 } 495 } 496 497 return 1; 498 } 499 500 #ifdef CONFIG_HUGETLB_PAGE 501 /* 502 * Scan for 16G memory blocks that have been set aside for huge pages 503 * and reserve those blocks for 16G huge pages. 504 */ 505 static int __init htab_dt_scan_hugepage_blocks(unsigned long node, 506 const char *uname, int depth, 507 void *data) { 508 const char *type = of_get_flat_dt_prop(node, "device_type", NULL); 509 const __be64 *addr_prop; 510 const __be32 *page_count_prop; 511 unsigned int expected_pages; 512 long unsigned int phys_addr; 513 long unsigned int block_size; 514 515 /* We are scanning "memory" nodes only */ 516 if (type == NULL || strcmp(type, "memory") != 0) 517 return 0; 518 519 /* 520 * This property is the log base 2 of the number of virtual pages that 521 * will represent this memory block. 522 */ 523 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL); 524 if (page_count_prop == NULL) 525 return 0; 526 expected_pages = (1 << be32_to_cpu(page_count_prop[0])); 527 addr_prop = of_get_flat_dt_prop(node, "reg", NULL); 528 if (addr_prop == NULL) 529 return 0; 530 phys_addr = be64_to_cpu(addr_prop[0]); 531 block_size = be64_to_cpu(addr_prop[1]); 532 if (block_size != (16 * GB)) 533 return 0; 534 printk(KERN_INFO "Huge page(16GB) memory: " 535 "addr = 0x%lX size = 0x%lX pages = %d\n", 536 phys_addr, block_size, expected_pages); 537 if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) { 538 memblock_reserve(phys_addr, block_size * expected_pages); 539 pseries_add_gpage(phys_addr, block_size, expected_pages); 540 } 541 return 0; 542 } 543 #endif /* CONFIG_HUGETLB_PAGE */ 544 545 static void mmu_psize_set_default_penc(void) 546 { 547 int bpsize, apsize; 548 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++) 549 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++) 550 mmu_psize_defs[bpsize].penc[apsize] = -1; 551 } 552 553 #ifdef CONFIG_PPC_64K_PAGES 554 555 static bool might_have_hea(void) 556 { 557 /* 558 * The HEA ethernet adapter requires awareness of the 559 * GX bus. Without that awareness we can easily assume 560 * we will never see an HEA ethernet device. 561 */ 562 #ifdef CONFIG_IBMEBUS 563 return !cpu_has_feature(CPU_FTR_ARCH_207S) && 564 firmware_has_feature(FW_FEATURE_SPLPAR); 565 #else 566 return false; 567 #endif 568 } 569 570 #endif /* #ifdef CONFIG_PPC_64K_PAGES */ 571 572 static void __init htab_scan_page_sizes(void) 573 { 574 int rc; 575 576 /* se the invalid penc to -1 */ 577 mmu_psize_set_default_penc(); 578 579 /* Default to 4K pages only */ 580 memcpy(mmu_psize_defs, mmu_psize_defaults, 581 sizeof(mmu_psize_defaults)); 582 583 /* 584 * Try to find the available page sizes in the device-tree 585 */ 586 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL); 587 if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) { 588 /* 589 * Nothing in the device-tree, but the CPU supports 16M pages, 590 * so let's fallback on a known size list for 16M capable CPUs. 591 */ 592 memcpy(mmu_psize_defs, mmu_psize_defaults_gp, 593 sizeof(mmu_psize_defaults_gp)); 594 } 595 596 #ifdef CONFIG_HUGETLB_PAGE 597 if (!hugetlb_disabled && !early_radix_enabled() ) { 598 /* Reserve 16G huge page memory sections for huge pages */ 599 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL); 600 } 601 #endif /* CONFIG_HUGETLB_PAGE */ 602 } 603 604 /* 605 * Fill in the hpte_page_sizes[] array. 606 * We go through the mmu_psize_defs[] array looking for all the 607 * supported base/actual page size combinations. Each combination 608 * has a unique pagesize encoding (penc) value in the low bits of 609 * the LP field of the HPTE. For actual page sizes less than 1MB, 610 * some of the upper LP bits are used for RPN bits, meaning that 611 * we need to fill in several entries in hpte_page_sizes[]. 612 * 613 * In diagrammatic form, with r = RPN bits and z = page size bits: 614 * PTE LP actual page size 615 * rrrr rrrz >=8KB 616 * rrrr rrzz >=16KB 617 * rrrr rzzz >=32KB 618 * rrrr zzzz >=64KB 619 * ... 620 * 621 * The zzzz bits are implementation-specific but are chosen so that 622 * no encoding for a larger page size uses the same value in its 623 * low-order N bits as the encoding for the 2^(12+N) byte page size 624 * (if it exists). 625 */ 626 static void init_hpte_page_sizes(void) 627 { 628 long int ap, bp; 629 long int shift, penc; 630 631 for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) { 632 if (!mmu_psize_defs[bp].shift) 633 continue; /* not a supported page size */ 634 for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) { 635 penc = mmu_psize_defs[bp].penc[ap]; 636 if (penc == -1 || !mmu_psize_defs[ap].shift) 637 continue; 638 shift = mmu_psize_defs[ap].shift - LP_SHIFT; 639 if (shift <= 0) 640 continue; /* should never happen */ 641 /* 642 * For page sizes less than 1MB, this loop 643 * replicates the entry for all possible values 644 * of the rrrr bits. 645 */ 646 while (penc < (1 << LP_BITS)) { 647 hpte_page_sizes[penc] = (ap << 4) | bp; 648 penc += 1 << shift; 649 } 650 } 651 } 652 } 653 654 static void __init htab_init_page_sizes(void) 655 { 656 bool aligned = true; 657 init_hpte_page_sizes(); 658 659 if (!debug_pagealloc_enabled()) { 660 /* 661 * Pick a size for the linear mapping. Currently, we only 662 * support 16M, 1M and 4K which is the default 663 */ 664 if (IS_ENABLED(CONFIG_STRICT_KERNEL_RWX) && 665 (unsigned long)_stext % 0x1000000) { 666 if (mmu_psize_defs[MMU_PAGE_16M].shift) 667 pr_warn("Kernel not 16M aligned, disabling 16M linear map alignment\n"); 668 aligned = false; 669 } 670 671 if (mmu_psize_defs[MMU_PAGE_16M].shift && aligned) 672 mmu_linear_psize = MMU_PAGE_16M; 673 else if (mmu_psize_defs[MMU_PAGE_1M].shift) 674 mmu_linear_psize = MMU_PAGE_1M; 675 } 676 677 #ifdef CONFIG_PPC_64K_PAGES 678 /* 679 * Pick a size for the ordinary pages. Default is 4K, we support 680 * 64K for user mappings and vmalloc if supported by the processor. 681 * We only use 64k for ioremap if the processor 682 * (and firmware) support cache-inhibited large pages. 683 * If not, we use 4k and set mmu_ci_restrictions so that 684 * hash_page knows to switch processes that use cache-inhibited 685 * mappings to 4k pages. 686 */ 687 if (mmu_psize_defs[MMU_PAGE_64K].shift) { 688 mmu_virtual_psize = MMU_PAGE_64K; 689 mmu_vmalloc_psize = MMU_PAGE_64K; 690 if (mmu_linear_psize == MMU_PAGE_4K) 691 mmu_linear_psize = MMU_PAGE_64K; 692 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) { 693 /* 694 * When running on pSeries using 64k pages for ioremap 695 * would stop us accessing the HEA ethernet. So if we 696 * have the chance of ever seeing one, stay at 4k. 697 */ 698 if (!might_have_hea()) 699 mmu_io_psize = MMU_PAGE_64K; 700 } else 701 mmu_ci_restrictions = 1; 702 } 703 #endif /* CONFIG_PPC_64K_PAGES */ 704 705 #ifdef CONFIG_SPARSEMEM_VMEMMAP 706 /* 707 * We try to use 16M pages for vmemmap if that is supported 708 * and we have at least 1G of RAM at boot 709 */ 710 if (mmu_psize_defs[MMU_PAGE_16M].shift && 711 memblock_phys_mem_size() >= 0x40000000) 712 mmu_vmemmap_psize = MMU_PAGE_16M; 713 else 714 mmu_vmemmap_psize = mmu_virtual_psize; 715 #endif /* CONFIG_SPARSEMEM_VMEMMAP */ 716 717 printk(KERN_DEBUG "Page orders: linear mapping = %d, " 718 "virtual = %d, io = %d" 719 #ifdef CONFIG_SPARSEMEM_VMEMMAP 720 ", vmemmap = %d" 721 #endif 722 "\n", 723 mmu_psize_defs[mmu_linear_psize].shift, 724 mmu_psize_defs[mmu_virtual_psize].shift, 725 mmu_psize_defs[mmu_io_psize].shift 726 #ifdef CONFIG_SPARSEMEM_VMEMMAP 727 ,mmu_psize_defs[mmu_vmemmap_psize].shift 728 #endif 729 ); 730 } 731 732 static int __init htab_dt_scan_pftsize(unsigned long node, 733 const char *uname, int depth, 734 void *data) 735 { 736 const char *type = of_get_flat_dt_prop(node, "device_type", NULL); 737 const __be32 *prop; 738 739 /* We are scanning "cpu" nodes only */ 740 if (type == NULL || strcmp(type, "cpu") != 0) 741 return 0; 742 743 prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL); 744 if (prop != NULL) { 745 /* pft_size[0] is the NUMA CEC cookie */ 746 ppc64_pft_size = be32_to_cpu(prop[1]); 747 return 1; 748 } 749 return 0; 750 } 751 752 unsigned htab_shift_for_mem_size(unsigned long mem_size) 753 { 754 unsigned memshift = __ilog2(mem_size); 755 unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift; 756 unsigned pteg_shift; 757 758 /* round mem_size up to next power of 2 */ 759 if ((1UL << memshift) < mem_size) 760 memshift += 1; 761 762 /* aim for 2 pages / pteg */ 763 pteg_shift = memshift - (pshift + 1); 764 765 /* 766 * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab 767 * size permitted by the architecture. 768 */ 769 return max(pteg_shift + 7, 18U); 770 } 771 772 static unsigned long __init htab_get_table_size(void) 773 { 774 /* 775 * If hash size isn't already provided by the platform, we try to 776 * retrieve it from the device-tree. If it's not there neither, we 777 * calculate it now based on the total RAM size 778 */ 779 if (ppc64_pft_size == 0) 780 of_scan_flat_dt(htab_dt_scan_pftsize, NULL); 781 if (ppc64_pft_size) 782 return 1UL << ppc64_pft_size; 783 784 return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size()); 785 } 786 787 #ifdef CONFIG_MEMORY_HOTPLUG 788 static int resize_hpt_for_hotplug(unsigned long new_mem_size) 789 { 790 unsigned target_hpt_shift; 791 792 if (!mmu_hash_ops.resize_hpt) 793 return 0; 794 795 target_hpt_shift = htab_shift_for_mem_size(new_mem_size); 796 797 /* 798 * To avoid lots of HPT resizes if memory size is fluctuating 799 * across a boundary, we deliberately have some hysterisis 800 * here: we immediately increase the HPT size if the target 801 * shift exceeds the current shift, but we won't attempt to 802 * reduce unless the target shift is at least 2 below the 803 * current shift 804 */ 805 if (target_hpt_shift > ppc64_pft_size || 806 target_hpt_shift < ppc64_pft_size - 1) 807 return mmu_hash_ops.resize_hpt(target_hpt_shift); 808 809 return 0; 810 } 811 812 int hash__create_section_mapping(unsigned long start, unsigned long end, 813 int nid, pgprot_t prot) 814 { 815 int rc; 816 817 if (end >= H_VMALLOC_START) { 818 pr_warn("Outside the supported range\n"); 819 return -1; 820 } 821 822 resize_hpt_for_hotplug(memblock_phys_mem_size()); 823 824 rc = htab_bolt_mapping(start, end, __pa(start), 825 pgprot_val(prot), mmu_linear_psize, 826 mmu_kernel_ssize); 827 828 if (rc < 0) { 829 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize, 830 mmu_kernel_ssize); 831 BUG_ON(rc2 && (rc2 != -ENOENT)); 832 } 833 return rc; 834 } 835 836 int hash__remove_section_mapping(unsigned long start, unsigned long end) 837 { 838 int rc = htab_remove_mapping(start, end, mmu_linear_psize, 839 mmu_kernel_ssize); 840 WARN_ON(rc < 0); 841 842 if (resize_hpt_for_hotplug(memblock_phys_mem_size()) == -ENOSPC) 843 pr_warn("Hash collision while resizing HPT\n"); 844 845 return rc; 846 } 847 #endif /* CONFIG_MEMORY_HOTPLUG */ 848 849 static void __init hash_init_partition_table(phys_addr_t hash_table, 850 unsigned long htab_size) 851 { 852 mmu_partition_table_init(); 853 854 /* 855 * PS field (VRMA page size) is not used for LPID 0, hence set to 0. 856 * For now, UPRT is 0 and we have no segment table. 857 */ 858 htab_size = __ilog2(htab_size) - 18; 859 mmu_partition_table_set_entry(0, hash_table | htab_size, 0, false); 860 pr_info("Partition table %p\n", partition_tb); 861 } 862 863 static void __init htab_initialize(void) 864 { 865 unsigned long table; 866 unsigned long pteg_count; 867 unsigned long prot; 868 unsigned long base = 0, size = 0; 869 struct memblock_region *reg; 870 871 DBG(" -> htab_initialize()\n"); 872 873 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) { 874 mmu_kernel_ssize = MMU_SEGSIZE_1T; 875 mmu_highuser_ssize = MMU_SEGSIZE_1T; 876 printk(KERN_INFO "Using 1TB segments\n"); 877 } 878 879 if (stress_slb_enabled) 880 static_branch_enable(&stress_slb_key); 881 882 /* 883 * Calculate the required size of the htab. We want the number of 884 * PTEGs to equal one half the number of real pages. 885 */ 886 htab_size_bytes = htab_get_table_size(); 887 pteg_count = htab_size_bytes >> 7; 888 889 htab_hash_mask = pteg_count - 1; 890 891 if (firmware_has_feature(FW_FEATURE_LPAR) || 892 firmware_has_feature(FW_FEATURE_PS3_LV1)) { 893 /* Using a hypervisor which owns the htab */ 894 htab_address = NULL; 895 _SDR1 = 0; 896 #ifdef CONFIG_FA_DUMP 897 /* 898 * If firmware assisted dump is active firmware preserves 899 * the contents of htab along with entire partition memory. 900 * Clear the htab if firmware assisted dump is active so 901 * that we dont end up using old mappings. 902 */ 903 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all) 904 mmu_hash_ops.hpte_clear_all(); 905 #endif 906 } else { 907 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE; 908 909 #ifdef CONFIG_PPC_CELL 910 /* 911 * Cell may require the hash table down low when using the 912 * Axon IOMMU in order to fit the dynamic region over it, see 913 * comments in cell/iommu.c 914 */ 915 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) { 916 limit = 0x80000000; 917 pr_info("Hash table forced below 2G for Axon IOMMU\n"); 918 } 919 #endif /* CONFIG_PPC_CELL */ 920 921 table = memblock_phys_alloc_range(htab_size_bytes, 922 htab_size_bytes, 923 0, limit); 924 if (!table) 925 panic("ERROR: Failed to allocate %pa bytes below %pa\n", 926 &htab_size_bytes, &limit); 927 928 DBG("Hash table allocated at %lx, size: %lx\n", table, 929 htab_size_bytes); 930 931 htab_address = __va(table); 932 933 /* htab absolute addr + encoded htabsize */ 934 _SDR1 = table + __ilog2(htab_size_bytes) - 18; 935 936 /* Initialize the HPT with no entries */ 937 memset((void *)table, 0, htab_size_bytes); 938 939 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 940 /* Set SDR1 */ 941 mtspr(SPRN_SDR1, _SDR1); 942 else 943 hash_init_partition_table(table, htab_size_bytes); 944 } 945 946 prot = pgprot_val(PAGE_KERNEL); 947 948 #ifdef CONFIG_DEBUG_PAGEALLOC 949 if (debug_pagealloc_enabled()) { 950 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT; 951 linear_map_hash_slots = memblock_alloc_try_nid( 952 linear_map_hash_count, 1, MEMBLOCK_LOW_LIMIT, 953 ppc64_rma_size, NUMA_NO_NODE); 954 if (!linear_map_hash_slots) 955 panic("%s: Failed to allocate %lu bytes max_addr=%pa\n", 956 __func__, linear_map_hash_count, &ppc64_rma_size); 957 } 958 #endif /* CONFIG_DEBUG_PAGEALLOC */ 959 960 /* create bolted the linear mapping in the hash table */ 961 for_each_memblock(memory, reg) { 962 base = (unsigned long)__va(reg->base); 963 size = reg->size; 964 965 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n", 966 base, size, prot); 967 968 if ((base + size) >= H_VMALLOC_START) { 969 pr_warn("Outside the supported range\n"); 970 continue; 971 } 972 973 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base), 974 prot, mmu_linear_psize, mmu_kernel_ssize)); 975 } 976 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE); 977 978 /* 979 * If we have a memory_limit and we've allocated TCEs then we need to 980 * explicitly map the TCE area at the top of RAM. We also cope with the 981 * case that the TCEs start below memory_limit. 982 * tce_alloc_start/end are 16MB aligned so the mapping should work 983 * for either 4K or 16MB pages. 984 */ 985 if (tce_alloc_start) { 986 tce_alloc_start = (unsigned long)__va(tce_alloc_start); 987 tce_alloc_end = (unsigned long)__va(tce_alloc_end); 988 989 if (base + size >= tce_alloc_start) 990 tce_alloc_start = base + size + 1; 991 992 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end, 993 __pa(tce_alloc_start), prot, 994 mmu_linear_psize, mmu_kernel_ssize)); 995 } 996 997 998 DBG(" <- htab_initialize()\n"); 999 } 1000 #undef KB 1001 #undef MB 1002 1003 void __init hash__early_init_devtree(void) 1004 { 1005 /* Initialize segment sizes */ 1006 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL); 1007 1008 /* Initialize page sizes */ 1009 htab_scan_page_sizes(); 1010 } 1011 1012 static struct hash_mm_context init_hash_mm_context; 1013 void __init hash__early_init_mmu(void) 1014 { 1015 #ifndef CONFIG_PPC_64K_PAGES 1016 /* 1017 * We have code in __hash_page_4K() and elsewhere, which assumes it can 1018 * do the following: 1019 * new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX); 1020 * 1021 * Where the slot number is between 0-15, and values of 8-15 indicate 1022 * the secondary bucket. For that code to work H_PAGE_F_SECOND and 1023 * H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and 1024 * H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here 1025 * with a BUILD_BUG_ON(). 1026 */ 1027 BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3))); 1028 #endif /* CONFIG_PPC_64K_PAGES */ 1029 1030 htab_init_page_sizes(); 1031 1032 /* 1033 * initialize page table size 1034 */ 1035 __pte_frag_nr = H_PTE_FRAG_NR; 1036 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT; 1037 __pmd_frag_nr = H_PMD_FRAG_NR; 1038 __pmd_frag_size_shift = H_PMD_FRAG_SIZE_SHIFT; 1039 1040 __pte_index_size = H_PTE_INDEX_SIZE; 1041 __pmd_index_size = H_PMD_INDEX_SIZE; 1042 __pud_index_size = H_PUD_INDEX_SIZE; 1043 __pgd_index_size = H_PGD_INDEX_SIZE; 1044 __pud_cache_index = H_PUD_CACHE_INDEX; 1045 __pte_table_size = H_PTE_TABLE_SIZE; 1046 __pmd_table_size = H_PMD_TABLE_SIZE; 1047 __pud_table_size = H_PUD_TABLE_SIZE; 1048 __pgd_table_size = H_PGD_TABLE_SIZE; 1049 /* 1050 * 4k use hugepd format, so for hash set then to 1051 * zero 1052 */ 1053 __pmd_val_bits = HASH_PMD_VAL_BITS; 1054 __pud_val_bits = HASH_PUD_VAL_BITS; 1055 __pgd_val_bits = HASH_PGD_VAL_BITS; 1056 1057 __kernel_virt_start = H_KERN_VIRT_START; 1058 __vmalloc_start = H_VMALLOC_START; 1059 __vmalloc_end = H_VMALLOC_END; 1060 __kernel_io_start = H_KERN_IO_START; 1061 __kernel_io_end = H_KERN_IO_END; 1062 vmemmap = (struct page *)H_VMEMMAP_START; 1063 ioremap_bot = IOREMAP_BASE; 1064 1065 #ifdef CONFIG_PCI 1066 pci_io_base = ISA_IO_BASE; 1067 #endif 1068 1069 /* Select appropriate backend */ 1070 if (firmware_has_feature(FW_FEATURE_PS3_LV1)) 1071 ps3_early_mm_init(); 1072 else if (firmware_has_feature(FW_FEATURE_LPAR)) 1073 hpte_init_pseries(); 1074 else if (IS_ENABLED(CONFIG_PPC_NATIVE)) 1075 hpte_init_native(); 1076 1077 if (!mmu_hash_ops.hpte_insert) 1078 panic("hash__early_init_mmu: No MMU hash ops defined!\n"); 1079 1080 /* 1081 * Initialize the MMU Hash table and create the linear mapping 1082 * of memory. Has to be done before SLB initialization as this is 1083 * currently where the page size encoding is obtained. 1084 */ 1085 htab_initialize(); 1086 1087 init_mm.context.hash_context = &init_hash_mm_context; 1088 mm_ctx_set_slb_addr_limit(&init_mm.context, SLB_ADDR_LIMIT_DEFAULT); 1089 1090 pr_info("Initializing hash mmu with SLB\n"); 1091 /* Initialize SLB management */ 1092 slb_initialize(); 1093 1094 if (cpu_has_feature(CPU_FTR_ARCH_206) 1095 && cpu_has_feature(CPU_FTR_HVMODE)) 1096 tlbiel_all(); 1097 } 1098 1099 #ifdef CONFIG_SMP 1100 void hash__early_init_mmu_secondary(void) 1101 { 1102 /* Initialize hash table for that CPU */ 1103 if (!firmware_has_feature(FW_FEATURE_LPAR)) { 1104 1105 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1106 mtspr(SPRN_SDR1, _SDR1); 1107 else 1108 set_ptcr_when_no_uv(__pa(partition_tb) | 1109 (PATB_SIZE_SHIFT - 12)); 1110 } 1111 /* Initialize SLB */ 1112 slb_initialize(); 1113 1114 if (cpu_has_feature(CPU_FTR_ARCH_206) 1115 && cpu_has_feature(CPU_FTR_HVMODE)) 1116 tlbiel_all(); 1117 1118 if (IS_ENABLED(CONFIG_PPC_MEM_KEYS) && mmu_has_feature(MMU_FTR_PKEY)) 1119 mtspr(SPRN_UAMOR, default_uamor); 1120 } 1121 #endif /* CONFIG_SMP */ 1122 1123 /* 1124 * Called by asm hashtable.S for doing lazy icache flush 1125 */ 1126 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap) 1127 { 1128 struct page *page; 1129 1130 if (!pfn_valid(pte_pfn(pte))) 1131 return pp; 1132 1133 page = pte_page(pte); 1134 1135 /* page is dirty */ 1136 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) { 1137 if (trap == 0x400) { 1138 flush_dcache_icache_page(page); 1139 set_bit(PG_arch_1, &page->flags); 1140 } else 1141 pp |= HPTE_R_N; 1142 } 1143 return pp; 1144 } 1145 1146 #ifdef CONFIG_PPC_MM_SLICES 1147 static unsigned int get_paca_psize(unsigned long addr) 1148 { 1149 unsigned char *psizes; 1150 unsigned long index, mask_index; 1151 1152 if (addr < SLICE_LOW_TOP) { 1153 psizes = get_paca()->mm_ctx_low_slices_psize; 1154 index = GET_LOW_SLICE_INDEX(addr); 1155 } else { 1156 psizes = get_paca()->mm_ctx_high_slices_psize; 1157 index = GET_HIGH_SLICE_INDEX(addr); 1158 } 1159 mask_index = index & 0x1; 1160 return (psizes[index >> 1] >> (mask_index * 4)) & 0xF; 1161 } 1162 1163 #else 1164 unsigned int get_paca_psize(unsigned long addr) 1165 { 1166 return get_paca()->mm_ctx_user_psize; 1167 } 1168 #endif 1169 1170 /* 1171 * Demote a segment to using 4k pages. 1172 * For now this makes the whole process use 4k pages. 1173 */ 1174 #ifdef CONFIG_PPC_64K_PAGES 1175 void demote_segment_4k(struct mm_struct *mm, unsigned long addr) 1176 { 1177 if (get_slice_psize(mm, addr) == MMU_PAGE_4K) 1178 return; 1179 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K); 1180 copro_flush_all_slbs(mm); 1181 if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) { 1182 1183 copy_mm_to_paca(mm); 1184 slb_flush_and_restore_bolted(); 1185 } 1186 } 1187 #endif /* CONFIG_PPC_64K_PAGES */ 1188 1189 #ifdef CONFIG_PPC_SUBPAGE_PROT 1190 /* 1191 * This looks up a 2-bit protection code for a 4k subpage of a 64k page. 1192 * Userspace sets the subpage permissions using the subpage_prot system call. 1193 * 1194 * Result is 0: full permissions, _PAGE_RW: read-only, 1195 * _PAGE_RWX: no access. 1196 */ 1197 static int subpage_protection(struct mm_struct *mm, unsigned long ea) 1198 { 1199 struct subpage_prot_table *spt = mm_ctx_subpage_prot(&mm->context); 1200 u32 spp = 0; 1201 u32 **sbpm, *sbpp; 1202 1203 if (!spt) 1204 return 0; 1205 1206 if (ea >= spt->maxaddr) 1207 return 0; 1208 if (ea < 0x100000000UL) { 1209 /* addresses below 4GB use spt->low_prot */ 1210 sbpm = spt->low_prot; 1211 } else { 1212 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT]; 1213 if (!sbpm) 1214 return 0; 1215 } 1216 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)]; 1217 if (!sbpp) 1218 return 0; 1219 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)]; 1220 1221 /* extract 2-bit bitfield for this 4k subpage */ 1222 spp >>= 30 - 2 * ((ea >> 12) & 0xf); 1223 1224 /* 1225 * 0 -> full premission 1226 * 1 -> Read only 1227 * 2 -> no access. 1228 * We return the flag that need to be cleared. 1229 */ 1230 spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0); 1231 return spp; 1232 } 1233 1234 #else /* CONFIG_PPC_SUBPAGE_PROT */ 1235 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea) 1236 { 1237 return 0; 1238 } 1239 #endif 1240 1241 void hash_failure_debug(unsigned long ea, unsigned long access, 1242 unsigned long vsid, unsigned long trap, 1243 int ssize, int psize, int lpsize, unsigned long pte) 1244 { 1245 if (!printk_ratelimit()) 1246 return; 1247 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n", 1248 ea, access, current->comm); 1249 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n", 1250 trap, vsid, ssize, psize, lpsize, pte); 1251 } 1252 1253 static void check_paca_psize(unsigned long ea, struct mm_struct *mm, 1254 int psize, bool user_region) 1255 { 1256 if (user_region) { 1257 if (psize != get_paca_psize(ea)) { 1258 copy_mm_to_paca(mm); 1259 slb_flush_and_restore_bolted(); 1260 } 1261 } else if (get_paca()->vmalloc_sllp != 1262 mmu_psize_defs[mmu_vmalloc_psize].sllp) { 1263 get_paca()->vmalloc_sllp = 1264 mmu_psize_defs[mmu_vmalloc_psize].sllp; 1265 slb_vmalloc_update(); 1266 } 1267 } 1268 1269 /* 1270 * Result code is: 1271 * 0 - handled 1272 * 1 - normal page fault 1273 * -1 - critical hash insertion error 1274 * -2 - access not permitted by subpage protection mechanism 1275 */ 1276 int hash_page_mm(struct mm_struct *mm, unsigned long ea, 1277 unsigned long access, unsigned long trap, 1278 unsigned long flags) 1279 { 1280 bool is_thp; 1281 enum ctx_state prev_state = exception_enter(); 1282 pgd_t *pgdir; 1283 unsigned long vsid; 1284 pte_t *ptep; 1285 unsigned hugeshift; 1286 int rc, user_region = 0; 1287 int psize, ssize; 1288 1289 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n", 1290 ea, access, trap); 1291 trace_hash_fault(ea, access, trap); 1292 1293 /* Get region & vsid */ 1294 switch (get_region_id(ea)) { 1295 case USER_REGION_ID: 1296 user_region = 1; 1297 if (! mm) { 1298 DBG_LOW(" user region with no mm !\n"); 1299 rc = 1; 1300 goto bail; 1301 } 1302 psize = get_slice_psize(mm, ea); 1303 ssize = user_segment_size(ea); 1304 vsid = get_user_vsid(&mm->context, ea, ssize); 1305 break; 1306 case VMALLOC_REGION_ID: 1307 vsid = get_kernel_vsid(ea, mmu_kernel_ssize); 1308 psize = mmu_vmalloc_psize; 1309 ssize = mmu_kernel_ssize; 1310 break; 1311 1312 case IO_REGION_ID: 1313 vsid = get_kernel_vsid(ea, mmu_kernel_ssize); 1314 psize = mmu_io_psize; 1315 ssize = mmu_kernel_ssize; 1316 break; 1317 default: 1318 /* 1319 * Not a valid range 1320 * Send the problem up to do_page_fault() 1321 */ 1322 rc = 1; 1323 goto bail; 1324 } 1325 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid); 1326 1327 /* Bad address. */ 1328 if (!vsid) { 1329 DBG_LOW("Bad address!\n"); 1330 rc = 1; 1331 goto bail; 1332 } 1333 /* Get pgdir */ 1334 pgdir = mm->pgd; 1335 if (pgdir == NULL) { 1336 rc = 1; 1337 goto bail; 1338 } 1339 1340 /* Check CPU locality */ 1341 if (user_region && mm_is_thread_local(mm)) 1342 flags |= HPTE_LOCAL_UPDATE; 1343 1344 #ifndef CONFIG_PPC_64K_PAGES 1345 /* 1346 * If we use 4K pages and our psize is not 4K, then we might 1347 * be hitting a special driver mapping, and need to align the 1348 * address before we fetch the PTE. 1349 * 1350 * It could also be a hugepage mapping, in which case this is 1351 * not necessary, but it's not harmful, either. 1352 */ 1353 if (psize != MMU_PAGE_4K) 1354 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1); 1355 #endif /* CONFIG_PPC_64K_PAGES */ 1356 1357 /* Get PTE and page size from page tables */ 1358 ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift); 1359 if (ptep == NULL || !pte_present(*ptep)) { 1360 DBG_LOW(" no PTE !\n"); 1361 rc = 1; 1362 goto bail; 1363 } 1364 1365 /* 1366 * Add _PAGE_PRESENT to the required access perm. If there are parallel 1367 * updates to the pte that can possibly clear _PAGE_PTE, catch that too. 1368 * 1369 * We can safely use the return pte address in rest of the function 1370 * because we do set H_PAGE_BUSY which prevents further updates to pte 1371 * from generic code. 1372 */ 1373 access |= _PAGE_PRESENT | _PAGE_PTE; 1374 1375 /* 1376 * Pre-check access permissions (will be re-checked atomically 1377 * in __hash_page_XX but this pre-check is a fast path 1378 */ 1379 if (!check_pte_access(access, pte_val(*ptep))) { 1380 DBG_LOW(" no access !\n"); 1381 rc = 1; 1382 goto bail; 1383 } 1384 1385 if (hugeshift) { 1386 if (is_thp) 1387 rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep, 1388 trap, flags, ssize, psize); 1389 #ifdef CONFIG_HUGETLB_PAGE 1390 else 1391 rc = __hash_page_huge(ea, access, vsid, ptep, trap, 1392 flags, ssize, hugeshift, psize); 1393 #else 1394 else { 1395 /* 1396 * if we have hugeshift, and is not transhuge with 1397 * hugetlb disabled, something is really wrong. 1398 */ 1399 rc = 1; 1400 WARN_ON(1); 1401 } 1402 #endif 1403 if (current->mm == mm) 1404 check_paca_psize(ea, mm, psize, user_region); 1405 1406 goto bail; 1407 } 1408 1409 #ifndef CONFIG_PPC_64K_PAGES 1410 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep)); 1411 #else 1412 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep), 1413 pte_val(*(ptep + PTRS_PER_PTE))); 1414 #endif 1415 /* Do actual hashing */ 1416 #ifdef CONFIG_PPC_64K_PAGES 1417 /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */ 1418 if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) { 1419 demote_segment_4k(mm, ea); 1420 psize = MMU_PAGE_4K; 1421 } 1422 1423 /* 1424 * If this PTE is non-cacheable and we have restrictions on 1425 * using non cacheable large pages, then we switch to 4k 1426 */ 1427 if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) { 1428 if (user_region) { 1429 demote_segment_4k(mm, ea); 1430 psize = MMU_PAGE_4K; 1431 } else if (ea < VMALLOC_END) { 1432 /* 1433 * some driver did a non-cacheable mapping 1434 * in vmalloc space, so switch vmalloc 1435 * to 4k pages 1436 */ 1437 printk(KERN_ALERT "Reducing vmalloc segment " 1438 "to 4kB pages because of " 1439 "non-cacheable mapping\n"); 1440 psize = mmu_vmalloc_psize = MMU_PAGE_4K; 1441 copro_flush_all_slbs(mm); 1442 } 1443 } 1444 1445 #endif /* CONFIG_PPC_64K_PAGES */ 1446 1447 if (current->mm == mm) 1448 check_paca_psize(ea, mm, psize, user_region); 1449 1450 #ifdef CONFIG_PPC_64K_PAGES 1451 if (psize == MMU_PAGE_64K) 1452 rc = __hash_page_64K(ea, access, vsid, ptep, trap, 1453 flags, ssize); 1454 else 1455 #endif /* CONFIG_PPC_64K_PAGES */ 1456 { 1457 int spp = subpage_protection(mm, ea); 1458 if (access & spp) 1459 rc = -2; 1460 else 1461 rc = __hash_page_4K(ea, access, vsid, ptep, trap, 1462 flags, ssize, spp); 1463 } 1464 1465 /* 1466 * Dump some info in case of hash insertion failure, they should 1467 * never happen so it is really useful to know if/when they do 1468 */ 1469 if (rc == -1) 1470 hash_failure_debug(ea, access, vsid, trap, ssize, psize, 1471 psize, pte_val(*ptep)); 1472 #ifndef CONFIG_PPC_64K_PAGES 1473 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep)); 1474 #else 1475 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep), 1476 pte_val(*(ptep + PTRS_PER_PTE))); 1477 #endif 1478 DBG_LOW(" -> rc=%d\n", rc); 1479 1480 bail: 1481 exception_exit(prev_state); 1482 return rc; 1483 } 1484 EXPORT_SYMBOL_GPL(hash_page_mm); 1485 1486 int hash_page(unsigned long ea, unsigned long access, unsigned long trap, 1487 unsigned long dsisr) 1488 { 1489 unsigned long flags = 0; 1490 struct mm_struct *mm = current->mm; 1491 1492 if ((get_region_id(ea) == VMALLOC_REGION_ID) || 1493 (get_region_id(ea) == IO_REGION_ID)) 1494 mm = &init_mm; 1495 1496 if (dsisr & DSISR_NOHPTE) 1497 flags |= HPTE_NOHPTE_UPDATE; 1498 1499 return hash_page_mm(mm, ea, access, trap, flags); 1500 } 1501 EXPORT_SYMBOL_GPL(hash_page); 1502 1503 int __hash_page(unsigned long trap, unsigned long ea, unsigned long dsisr, 1504 unsigned long msr) 1505 { 1506 unsigned long access = _PAGE_PRESENT | _PAGE_READ; 1507 unsigned long flags = 0; 1508 struct mm_struct *mm = current->mm; 1509 unsigned int region_id = get_region_id(ea); 1510 1511 if ((region_id == VMALLOC_REGION_ID) || (region_id == IO_REGION_ID)) 1512 mm = &init_mm; 1513 1514 if (dsisr & DSISR_NOHPTE) 1515 flags |= HPTE_NOHPTE_UPDATE; 1516 1517 if (dsisr & DSISR_ISSTORE) 1518 access |= _PAGE_WRITE; 1519 /* 1520 * We set _PAGE_PRIVILEGED only when 1521 * kernel mode access kernel space. 1522 * 1523 * _PAGE_PRIVILEGED is NOT set 1524 * 1) when kernel mode access user space 1525 * 2) user space access kernel space. 1526 */ 1527 access |= _PAGE_PRIVILEGED; 1528 if ((msr & MSR_PR) || (region_id == USER_REGION_ID)) 1529 access &= ~_PAGE_PRIVILEGED; 1530 1531 if (trap == 0x400) 1532 access |= _PAGE_EXEC; 1533 1534 return hash_page_mm(mm, ea, access, trap, flags); 1535 } 1536 1537 #ifdef CONFIG_PPC_MM_SLICES 1538 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea) 1539 { 1540 int psize = get_slice_psize(mm, ea); 1541 1542 /* We only prefault standard pages for now */ 1543 if (unlikely(psize != mm_ctx_user_psize(&mm->context))) 1544 return false; 1545 1546 /* 1547 * Don't prefault if subpage protection is enabled for the EA. 1548 */ 1549 if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea))) 1550 return false; 1551 1552 return true; 1553 } 1554 #else 1555 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea) 1556 { 1557 return true; 1558 } 1559 #endif 1560 1561 static void hash_preload(struct mm_struct *mm, pte_t *ptep, unsigned long ea, 1562 bool is_exec, unsigned long trap) 1563 { 1564 unsigned long vsid; 1565 pgd_t *pgdir; 1566 int rc, ssize, update_flags = 0; 1567 unsigned long access = _PAGE_PRESENT | _PAGE_READ | (is_exec ? _PAGE_EXEC : 0); 1568 unsigned long flags; 1569 1570 BUG_ON(get_region_id(ea) != USER_REGION_ID); 1571 1572 if (!should_hash_preload(mm, ea)) 1573 return; 1574 1575 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx," 1576 " trap=%lx\n", mm, mm->pgd, ea, access, trap); 1577 1578 /* Get Linux PTE if available */ 1579 pgdir = mm->pgd; 1580 if (pgdir == NULL) 1581 return; 1582 1583 /* Get VSID */ 1584 ssize = user_segment_size(ea); 1585 vsid = get_user_vsid(&mm->context, ea, ssize); 1586 if (!vsid) 1587 return; 1588 1589 #ifdef CONFIG_PPC_64K_PAGES 1590 /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on 1591 * a 64K kernel), then we don't preload, hash_page() will take 1592 * care of it once we actually try to access the page. 1593 * That way we don't have to duplicate all of the logic for segment 1594 * page size demotion here 1595 * Called with PTL held, hence can be sure the value won't change in 1596 * between. 1597 */ 1598 if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep)) 1599 return; 1600 #endif /* CONFIG_PPC_64K_PAGES */ 1601 1602 /* 1603 * __hash_page_* must run with interrupts off, as it sets the 1604 * H_PAGE_BUSY bit. It's possible for perf interrupts to hit at any 1605 * time and may take a hash fault reading the user stack, see 1606 * read_user_stack_slow() in the powerpc/perf code. 1607 * 1608 * If that takes a hash fault on the same page as we lock here, it 1609 * will bail out when seeing H_PAGE_BUSY set, and retry the access 1610 * leading to an infinite loop. 1611 * 1612 * Disabling interrupts here does not prevent perf interrupts, but it 1613 * will prevent them taking hash faults (see the NMI test in 1614 * do_hash_page), then read_user_stack's copy_from_user_nofault will 1615 * fail and perf will fall back to read_user_stack_slow(), which 1616 * walks the Linux page tables. 1617 * 1618 * Interrupts must also be off for the duration of the 1619 * mm_is_thread_local test and update, to prevent preempt running the 1620 * mm on another CPU (XXX: this may be racy vs kthread_use_mm). 1621 */ 1622 local_irq_save(flags); 1623 1624 /* Is that local to this CPU ? */ 1625 if (mm_is_thread_local(mm)) 1626 update_flags |= HPTE_LOCAL_UPDATE; 1627 1628 /* Hash it in */ 1629 #ifdef CONFIG_PPC_64K_PAGES 1630 if (mm_ctx_user_psize(&mm->context) == MMU_PAGE_64K) 1631 rc = __hash_page_64K(ea, access, vsid, ptep, trap, 1632 update_flags, ssize); 1633 else 1634 #endif /* CONFIG_PPC_64K_PAGES */ 1635 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags, 1636 ssize, subpage_protection(mm, ea)); 1637 1638 /* Dump some info in case of hash insertion failure, they should 1639 * never happen so it is really useful to know if/when they do 1640 */ 1641 if (rc == -1) 1642 hash_failure_debug(ea, access, vsid, trap, ssize, 1643 mm_ctx_user_psize(&mm->context), 1644 mm_ctx_user_psize(&mm->context), 1645 pte_val(*ptep)); 1646 1647 local_irq_restore(flags); 1648 } 1649 1650 /* 1651 * This is called at the end of handling a user page fault, when the 1652 * fault has been handled by updating a PTE in the linux page tables. 1653 * We use it to preload an HPTE into the hash table corresponding to 1654 * the updated linux PTE. 1655 * 1656 * This must always be called with the pte lock held. 1657 */ 1658 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, 1659 pte_t *ptep) 1660 { 1661 /* 1662 * We don't need to worry about _PAGE_PRESENT here because we are 1663 * called with either mm->page_table_lock held or ptl lock held 1664 */ 1665 unsigned long trap; 1666 bool is_exec; 1667 1668 if (radix_enabled()) 1669 return; 1670 1671 /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */ 1672 if (!pte_young(*ptep) || address >= TASK_SIZE) 1673 return; 1674 1675 /* 1676 * We try to figure out if we are coming from an instruction 1677 * access fault and pass that down to __hash_page so we avoid 1678 * double-faulting on execution of fresh text. We have to test 1679 * for regs NULL since init will get here first thing at boot. 1680 * 1681 * We also avoid filling the hash if not coming from a fault. 1682 */ 1683 1684 trap = current->thread.regs ? TRAP(current->thread.regs) : 0UL; 1685 switch (trap) { 1686 case 0x300: 1687 is_exec = false; 1688 break; 1689 case 0x400: 1690 is_exec = true; 1691 break; 1692 default: 1693 return; 1694 } 1695 1696 hash_preload(vma->vm_mm, ptep, address, is_exec, trap); 1697 } 1698 1699 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1700 static inline void tm_flush_hash_page(int local) 1701 { 1702 /* 1703 * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a 1704 * page back to a block device w/PIO could pick up transactional data 1705 * (bad!) so we force an abort here. Before the sync the page will be 1706 * made read-only, which will flush_hash_page. BIG ISSUE here: if the 1707 * kernel uses a page from userspace without unmapping it first, it may 1708 * see the speculated version. 1709 */ 1710 if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs && 1711 MSR_TM_ACTIVE(current->thread.regs->msr)) { 1712 tm_enable(); 1713 tm_abort(TM_CAUSE_TLBI); 1714 } 1715 } 1716 #else 1717 static inline void tm_flush_hash_page(int local) 1718 { 1719 } 1720 #endif 1721 1722 /* 1723 * Return the global hash slot, corresponding to the given PTE, which contains 1724 * the HPTE. 1725 */ 1726 unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift, 1727 int ssize, real_pte_t rpte, unsigned int subpg_index) 1728 { 1729 unsigned long hash, gslot, hidx; 1730 1731 hash = hpt_hash(vpn, shift, ssize); 1732 hidx = __rpte_to_hidx(rpte, subpg_index); 1733 if (hidx & _PTEIDX_SECONDARY) 1734 hash = ~hash; 1735 gslot = (hash & htab_hash_mask) * HPTES_PER_GROUP; 1736 gslot += hidx & _PTEIDX_GROUP_IX; 1737 return gslot; 1738 } 1739 1740 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize, 1741 unsigned long flags) 1742 { 1743 unsigned long index, shift, gslot; 1744 int local = flags & HPTE_LOCAL_UPDATE; 1745 1746 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn); 1747 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) { 1748 gslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index); 1749 DBG_LOW(" sub %ld: gslot=%lx\n", index, gslot); 1750 /* 1751 * We use same base page size and actual psize, because we don't 1752 * use these functions for hugepage 1753 */ 1754 mmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize, 1755 ssize, local); 1756 } pte_iterate_hashed_end(); 1757 1758 tm_flush_hash_page(local); 1759 } 1760 1761 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1762 void flush_hash_hugepage(unsigned long vsid, unsigned long addr, 1763 pmd_t *pmdp, unsigned int psize, int ssize, 1764 unsigned long flags) 1765 { 1766 int i, max_hpte_count, valid; 1767 unsigned long s_addr; 1768 unsigned char *hpte_slot_array; 1769 unsigned long hidx, shift, vpn, hash, slot; 1770 int local = flags & HPTE_LOCAL_UPDATE; 1771 1772 s_addr = addr & HPAGE_PMD_MASK; 1773 hpte_slot_array = get_hpte_slot_array(pmdp); 1774 /* 1775 * IF we try to do a HUGE PTE update after a withdraw is done. 1776 * we will find the below NULL. This happens when we do 1777 * split_huge_pmd 1778 */ 1779 if (!hpte_slot_array) 1780 return; 1781 1782 if (mmu_hash_ops.hugepage_invalidate) { 1783 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array, 1784 psize, ssize, local); 1785 goto tm_abort; 1786 } 1787 /* 1788 * No bluk hpte removal support, invalidate each entry 1789 */ 1790 shift = mmu_psize_defs[psize].shift; 1791 max_hpte_count = HPAGE_PMD_SIZE >> shift; 1792 for (i = 0; i < max_hpte_count; i++) { 1793 /* 1794 * 8 bits per each hpte entries 1795 * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit] 1796 */ 1797 valid = hpte_valid(hpte_slot_array, i); 1798 if (!valid) 1799 continue; 1800 hidx = hpte_hash_index(hpte_slot_array, i); 1801 1802 /* get the vpn */ 1803 addr = s_addr + (i * (1ul << shift)); 1804 vpn = hpt_vpn(addr, vsid, ssize); 1805 hash = hpt_hash(vpn, shift, ssize); 1806 if (hidx & _PTEIDX_SECONDARY) 1807 hash = ~hash; 1808 1809 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; 1810 slot += hidx & _PTEIDX_GROUP_IX; 1811 mmu_hash_ops.hpte_invalidate(slot, vpn, psize, 1812 MMU_PAGE_16M, ssize, local); 1813 } 1814 tm_abort: 1815 tm_flush_hash_page(local); 1816 } 1817 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1818 1819 void flush_hash_range(unsigned long number, int local) 1820 { 1821 if (mmu_hash_ops.flush_hash_range) 1822 mmu_hash_ops.flush_hash_range(number, local); 1823 else { 1824 int i; 1825 struct ppc64_tlb_batch *batch = 1826 this_cpu_ptr(&ppc64_tlb_batch); 1827 1828 for (i = 0; i < number; i++) 1829 flush_hash_page(batch->vpn[i], batch->pte[i], 1830 batch->psize, batch->ssize, local); 1831 } 1832 } 1833 1834 /* 1835 * low_hash_fault is called when we the low level hash code failed 1836 * to instert a PTE due to an hypervisor error 1837 */ 1838 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc) 1839 { 1840 enum ctx_state prev_state = exception_enter(); 1841 1842 if (user_mode(regs)) { 1843 #ifdef CONFIG_PPC_SUBPAGE_PROT 1844 if (rc == -2) 1845 _exception(SIGSEGV, regs, SEGV_ACCERR, address); 1846 else 1847 #endif 1848 _exception(SIGBUS, regs, BUS_ADRERR, address); 1849 } else 1850 bad_page_fault(regs, address, SIGBUS); 1851 1852 exception_exit(prev_state); 1853 } 1854 1855 long hpte_insert_repeating(unsigned long hash, unsigned long vpn, 1856 unsigned long pa, unsigned long rflags, 1857 unsigned long vflags, int psize, int ssize) 1858 { 1859 unsigned long hpte_group; 1860 long slot; 1861 1862 repeat: 1863 hpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP; 1864 1865 /* Insert into the hash table, primary slot */ 1866 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags, 1867 psize, psize, ssize); 1868 1869 /* Primary is full, try the secondary */ 1870 if (unlikely(slot == -1)) { 1871 hpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP; 1872 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, 1873 vflags | HPTE_V_SECONDARY, 1874 psize, psize, ssize); 1875 if (slot == -1) { 1876 if (mftb() & 0x1) 1877 hpte_group = (hash & htab_hash_mask) * 1878 HPTES_PER_GROUP; 1879 1880 mmu_hash_ops.hpte_remove(hpte_group); 1881 goto repeat; 1882 } 1883 } 1884 1885 return slot; 1886 } 1887 1888 #ifdef CONFIG_DEBUG_PAGEALLOC 1889 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi) 1890 { 1891 unsigned long hash; 1892 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); 1893 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); 1894 unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL)); 1895 long ret; 1896 1897 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); 1898 1899 /* Don't create HPTE entries for bad address */ 1900 if (!vsid) 1901 return; 1902 1903 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode, 1904 HPTE_V_BOLTED, 1905 mmu_linear_psize, mmu_kernel_ssize); 1906 1907 BUG_ON (ret < 0); 1908 spin_lock(&linear_map_hash_lock); 1909 BUG_ON(linear_map_hash_slots[lmi] & 0x80); 1910 linear_map_hash_slots[lmi] = ret | 0x80; 1911 spin_unlock(&linear_map_hash_lock); 1912 } 1913 1914 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi) 1915 { 1916 unsigned long hash, hidx, slot; 1917 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); 1918 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); 1919 1920 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); 1921 spin_lock(&linear_map_hash_lock); 1922 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80)); 1923 hidx = linear_map_hash_slots[lmi] & 0x7f; 1924 linear_map_hash_slots[lmi] = 0; 1925 spin_unlock(&linear_map_hash_lock); 1926 if (hidx & _PTEIDX_SECONDARY) 1927 hash = ~hash; 1928 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; 1929 slot += hidx & _PTEIDX_GROUP_IX; 1930 mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize, 1931 mmu_linear_psize, 1932 mmu_kernel_ssize, 0); 1933 } 1934 1935 void __kernel_map_pages(struct page *page, int numpages, int enable) 1936 { 1937 unsigned long flags, vaddr, lmi; 1938 int i; 1939 1940 local_irq_save(flags); 1941 for (i = 0; i < numpages; i++, page++) { 1942 vaddr = (unsigned long)page_address(page); 1943 lmi = __pa(vaddr) >> PAGE_SHIFT; 1944 if (lmi >= linear_map_hash_count) 1945 continue; 1946 if (enable) 1947 kernel_map_linear_page(vaddr, lmi); 1948 else 1949 kernel_unmap_linear_page(vaddr, lmi); 1950 } 1951 local_irq_restore(flags); 1952 } 1953 #endif /* CONFIG_DEBUG_PAGEALLOC */ 1954 1955 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base, 1956 phys_addr_t first_memblock_size) 1957 { 1958 /* 1959 * We don't currently support the first MEMBLOCK not mapping 0 1960 * physical on those processors 1961 */ 1962 BUG_ON(first_memblock_base != 0); 1963 1964 /* 1965 * On virtualized systems the first entry is our RMA region aka VRMA, 1966 * non-virtualized 64-bit hash MMU systems don't have a limitation 1967 * on real mode access. 1968 * 1969 * For guests on platforms before POWER9, we clamp the it limit to 1G 1970 * to avoid some funky things such as RTAS bugs etc... 1971 * 1972 * On POWER9 we limit to 1TB in case the host erroneously told us that 1973 * the RMA was >1TB. Effective address bits 0:23 are treated as zero 1974 * (meaning the access is aliased to zero i.e. addr = addr % 1TB) 1975 * for virtual real mode addressing and so it doesn't make sense to 1976 * have an area larger than 1TB as it can't be addressed. 1977 */ 1978 if (!early_cpu_has_feature(CPU_FTR_HVMODE)) { 1979 ppc64_rma_size = first_memblock_size; 1980 if (!early_cpu_has_feature(CPU_FTR_ARCH_300)) 1981 ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000); 1982 else 1983 ppc64_rma_size = min_t(u64, ppc64_rma_size, 1984 1UL << SID_SHIFT_1T); 1985 1986 /* Finally limit subsequent allocations */ 1987 memblock_set_current_limit(ppc64_rma_size); 1988 } else { 1989 ppc64_rma_size = ULONG_MAX; 1990 } 1991 } 1992 1993 #ifdef CONFIG_DEBUG_FS 1994 1995 static int hpt_order_get(void *data, u64 *val) 1996 { 1997 *val = ppc64_pft_size; 1998 return 0; 1999 } 2000 2001 static int hpt_order_set(void *data, u64 val) 2002 { 2003 int ret; 2004 2005 if (!mmu_hash_ops.resize_hpt) 2006 return -ENODEV; 2007 2008 cpus_read_lock(); 2009 ret = mmu_hash_ops.resize_hpt(val); 2010 cpus_read_unlock(); 2011 2012 return ret; 2013 } 2014 2015 DEFINE_DEBUGFS_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n"); 2016 2017 static int __init hash64_debugfs(void) 2018 { 2019 debugfs_create_file("hpt_order", 0600, powerpc_debugfs_root, NULL, 2020 &fops_hpt_order); 2021 return 0; 2022 } 2023 machine_device_initcall(pseries, hash64_debugfs); 2024 #endif /* CONFIG_DEBUG_FS */ 2025 2026 void __init print_system_hash_info(void) 2027 { 2028 pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); 2029 2030 if (htab_hash_mask) 2031 pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask); 2032 } 2033