1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * PowerPC64 port by Mike Corrigan and Dave Engebretsen 4 * {mikejc|engebret}@us.ibm.com 5 * 6 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com> 7 * 8 * SMP scalability work: 9 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM 10 * 11 * Module name: htab.c 12 * 13 * Description: 14 * PowerPC Hashed Page Table functions 15 */ 16 17 #undef DEBUG 18 #undef DEBUG_LOW 19 20 #define pr_fmt(fmt) "hash-mmu: " fmt 21 #include <linux/spinlock.h> 22 #include <linux/errno.h> 23 #include <linux/sched/mm.h> 24 #include <linux/proc_fs.h> 25 #include <linux/stat.h> 26 #include <linux/sysctl.h> 27 #include <linux/export.h> 28 #include <linux/ctype.h> 29 #include <linux/cache.h> 30 #include <linux/init.h> 31 #include <linux/signal.h> 32 #include <linux/memblock.h> 33 #include <linux/context_tracking.h> 34 #include <linux/libfdt.h> 35 #include <linux/pkeys.h> 36 #include <linux/hugetlb.h> 37 #include <linux/cpu.h> 38 #include <linux/pgtable.h> 39 40 #include <asm/debugfs.h> 41 #include <asm/processor.h> 42 #include <asm/mmu.h> 43 #include <asm/mmu_context.h> 44 #include <asm/page.h> 45 #include <asm/types.h> 46 #include <linux/uaccess.h> 47 #include <asm/machdep.h> 48 #include <asm/prom.h> 49 #include <asm/io.h> 50 #include <asm/eeh.h> 51 #include <asm/tlb.h> 52 #include <asm/cacheflush.h> 53 #include <asm/cputable.h> 54 #include <asm/sections.h> 55 #include <asm/copro.h> 56 #include <asm/udbg.h> 57 #include <asm/code-patching.h> 58 #include <asm/fadump.h> 59 #include <asm/firmware.h> 60 #include <asm/tm.h> 61 #include <asm/trace.h> 62 #include <asm/ps3.h> 63 #include <asm/pte-walk.h> 64 #include <asm/asm-prototypes.h> 65 #include <asm/ultravisor.h> 66 67 #include <mm/mmu_decl.h> 68 69 #include "internal.h" 70 71 72 #ifdef DEBUG 73 #define DBG(fmt...) udbg_printf(fmt) 74 #else 75 #define DBG(fmt...) 76 #endif 77 78 #ifdef DEBUG_LOW 79 #define DBG_LOW(fmt...) udbg_printf(fmt) 80 #else 81 #define DBG_LOW(fmt...) 82 #endif 83 84 #define KB (1024) 85 #define MB (1024*KB) 86 #define GB (1024L*MB) 87 88 /* 89 * Note: pte --> Linux PTE 90 * HPTE --> PowerPC Hashed Page Table Entry 91 * 92 * Execution context: 93 * htab_initialize is called with the MMU off (of course), but 94 * the kernel has been copied down to zero so it can directly 95 * reference global data. At this point it is very difficult 96 * to print debug info. 97 * 98 */ 99 100 static unsigned long _SDR1; 101 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; 102 EXPORT_SYMBOL_GPL(mmu_psize_defs); 103 104 u8 hpte_page_sizes[1 << LP_BITS]; 105 EXPORT_SYMBOL_GPL(hpte_page_sizes); 106 107 struct hash_pte *htab_address; 108 unsigned long htab_size_bytes; 109 unsigned long htab_hash_mask; 110 EXPORT_SYMBOL_GPL(htab_hash_mask); 111 int mmu_linear_psize = MMU_PAGE_4K; 112 EXPORT_SYMBOL_GPL(mmu_linear_psize); 113 int mmu_virtual_psize = MMU_PAGE_4K; 114 int mmu_vmalloc_psize = MMU_PAGE_4K; 115 EXPORT_SYMBOL_GPL(mmu_vmalloc_psize); 116 #ifdef CONFIG_SPARSEMEM_VMEMMAP 117 int mmu_vmemmap_psize = MMU_PAGE_4K; 118 #endif 119 int mmu_io_psize = MMU_PAGE_4K; 120 int mmu_kernel_ssize = MMU_SEGSIZE_256M; 121 EXPORT_SYMBOL_GPL(mmu_kernel_ssize); 122 int mmu_highuser_ssize = MMU_SEGSIZE_256M; 123 u16 mmu_slb_size = 64; 124 EXPORT_SYMBOL_GPL(mmu_slb_size); 125 #ifdef CONFIG_PPC_64K_PAGES 126 int mmu_ci_restrictions; 127 #endif 128 #ifdef CONFIG_DEBUG_PAGEALLOC 129 static u8 *linear_map_hash_slots; 130 static unsigned long linear_map_hash_count; 131 static DEFINE_SPINLOCK(linear_map_hash_lock); 132 #endif /* CONFIG_DEBUG_PAGEALLOC */ 133 struct mmu_hash_ops mmu_hash_ops; 134 EXPORT_SYMBOL(mmu_hash_ops); 135 136 /* 137 * These are definitions of page sizes arrays to be used when none 138 * is provided by the firmware. 139 */ 140 141 /* 142 * Fallback (4k pages only) 143 */ 144 static struct mmu_psize_def mmu_psize_defaults[] = { 145 [MMU_PAGE_4K] = { 146 .shift = 12, 147 .sllp = 0, 148 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, 149 .avpnm = 0, 150 .tlbiel = 0, 151 }, 152 }; 153 154 /* 155 * POWER4, GPUL, POWER5 156 * 157 * Support for 16Mb large pages 158 */ 159 static struct mmu_psize_def mmu_psize_defaults_gp[] = { 160 [MMU_PAGE_4K] = { 161 .shift = 12, 162 .sllp = 0, 163 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, 164 .avpnm = 0, 165 .tlbiel = 1, 166 }, 167 [MMU_PAGE_16M] = { 168 .shift = 24, 169 .sllp = SLB_VSID_L, 170 .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0, 171 [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 }, 172 .avpnm = 0x1UL, 173 .tlbiel = 0, 174 }, 175 }; 176 177 /* 178 * 'R' and 'C' update notes: 179 * - Under pHyp or KVM, the updatepp path will not set C, thus it *will* 180 * create writeable HPTEs without C set, because the hcall H_PROTECT 181 * that we use in that case will not update C 182 * - The above is however not a problem, because we also don't do that 183 * fancy "no flush" variant of eviction and we use H_REMOVE which will 184 * do the right thing and thus we don't have the race I described earlier 185 * 186 * - Under bare metal, we do have the race, so we need R and C set 187 * - We make sure R is always set and never lost 188 * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping 189 */ 190 unsigned long htab_convert_pte_flags(unsigned long pteflags, unsigned long flags) 191 { 192 unsigned long rflags = 0; 193 194 /* _PAGE_EXEC -> NOEXEC */ 195 if ((pteflags & _PAGE_EXEC) == 0) 196 rflags |= HPTE_R_N; 197 /* 198 * PPP bits: 199 * Linux uses slb key 0 for kernel and 1 for user. 200 * kernel RW areas are mapped with PPP=0b000 201 * User area is mapped with PPP=0b010 for read/write 202 * or PPP=0b011 for read-only (including writeable but clean pages). 203 */ 204 if (pteflags & _PAGE_PRIVILEGED) { 205 /* 206 * Kernel read only mapped with ppp bits 0b110 207 */ 208 if (!(pteflags & _PAGE_WRITE)) { 209 if (mmu_has_feature(MMU_FTR_KERNEL_RO)) 210 rflags |= (HPTE_R_PP0 | 0x2); 211 else 212 rflags |= 0x3; 213 } 214 } else { 215 if (pteflags & _PAGE_RWX) 216 rflags |= 0x2; 217 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY))) 218 rflags |= 0x1; 219 } 220 /* 221 * We can't allow hardware to update hpte bits. Hence always 222 * set 'R' bit and set 'C' if it is a write fault 223 */ 224 rflags |= HPTE_R_R; 225 226 if (pteflags & _PAGE_DIRTY) 227 rflags |= HPTE_R_C; 228 /* 229 * Add in WIG bits 230 */ 231 232 if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) 233 rflags |= HPTE_R_I; 234 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT) 235 rflags |= (HPTE_R_I | HPTE_R_G); 236 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO) 237 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M); 238 else 239 /* 240 * Add memory coherence if cache inhibited is not set 241 */ 242 rflags |= HPTE_R_M; 243 244 rflags |= pte_to_hpte_pkey_bits(pteflags, flags); 245 return rflags; 246 } 247 248 int htab_bolt_mapping(unsigned long vstart, unsigned long vend, 249 unsigned long pstart, unsigned long prot, 250 int psize, int ssize) 251 { 252 unsigned long vaddr, paddr; 253 unsigned int step, shift; 254 int ret = 0; 255 256 shift = mmu_psize_defs[psize].shift; 257 step = 1 << shift; 258 259 prot = htab_convert_pte_flags(prot, HPTE_USE_KERNEL_KEY); 260 261 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n", 262 vstart, vend, pstart, prot, psize, ssize); 263 264 /* Carefully map only the possible range */ 265 vaddr = ALIGN(vstart, step); 266 paddr = ALIGN(pstart, step); 267 vend = ALIGN_DOWN(vend, step); 268 269 for (; vaddr < vend; vaddr += step, paddr += step) { 270 unsigned long hash, hpteg; 271 unsigned long vsid = get_kernel_vsid(vaddr, ssize); 272 unsigned long vpn = hpt_vpn(vaddr, vsid, ssize); 273 unsigned long tprot = prot; 274 bool secondary_hash = false; 275 276 /* 277 * If we hit a bad address return error. 278 */ 279 if (!vsid) 280 return -1; 281 /* Make kernel text executable */ 282 if (overlaps_kernel_text(vaddr, vaddr + step)) 283 tprot &= ~HPTE_R_N; 284 285 /* 286 * If relocatable, check if it overlaps interrupt vectors that 287 * are copied down to real 0. For relocatable kernel 288 * (e.g. kdump case) we copy interrupt vectors down to real 289 * address 0. Mark that region as executable. This is 290 * because on p8 system with relocation on exception feature 291 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence 292 * in order to execute the interrupt handlers in virtual 293 * mode the vector region need to be marked as executable. 294 */ 295 if ((PHYSICAL_START > MEMORY_START) && 296 overlaps_interrupt_vector_text(vaddr, vaddr + step)) 297 tprot &= ~HPTE_R_N; 298 299 hash = hpt_hash(vpn, shift, ssize); 300 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); 301 302 BUG_ON(!mmu_hash_ops.hpte_insert); 303 repeat: 304 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot, 305 HPTE_V_BOLTED, psize, psize, 306 ssize); 307 if (ret == -1) { 308 /* 309 * Try to to keep bolted entries in primary. 310 * Remove non bolted entries and try insert again 311 */ 312 ret = mmu_hash_ops.hpte_remove(hpteg); 313 if (ret != -1) 314 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot, 315 HPTE_V_BOLTED, psize, psize, 316 ssize); 317 if (ret == -1 && !secondary_hash) { 318 secondary_hash = true; 319 hpteg = ((~hash & htab_hash_mask) * HPTES_PER_GROUP); 320 goto repeat; 321 } 322 } 323 324 if (ret < 0) 325 break; 326 327 cond_resched(); 328 #ifdef CONFIG_DEBUG_PAGEALLOC 329 if (debug_pagealloc_enabled() && 330 (paddr >> PAGE_SHIFT) < linear_map_hash_count) 331 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80; 332 #endif /* CONFIG_DEBUG_PAGEALLOC */ 333 } 334 return ret < 0 ? ret : 0; 335 } 336 337 int htab_remove_mapping(unsigned long vstart, unsigned long vend, 338 int psize, int ssize) 339 { 340 unsigned long vaddr; 341 unsigned int step, shift; 342 int rc; 343 int ret = 0; 344 345 shift = mmu_psize_defs[psize].shift; 346 step = 1 << shift; 347 348 if (!mmu_hash_ops.hpte_removebolted) 349 return -ENODEV; 350 351 /* Unmap the full range specificied */ 352 vaddr = ALIGN_DOWN(vstart, step); 353 for (;vaddr < vend; vaddr += step) { 354 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize); 355 if (rc == -ENOENT) { 356 ret = -ENOENT; 357 continue; 358 } 359 if (rc < 0) 360 return rc; 361 } 362 363 return ret; 364 } 365 366 static bool disable_1tb_segments = false; 367 368 static int __init parse_disable_1tb_segments(char *p) 369 { 370 disable_1tb_segments = true; 371 return 0; 372 } 373 early_param("disable_1tb_segments", parse_disable_1tb_segments); 374 375 static int __init htab_dt_scan_seg_sizes(unsigned long node, 376 const char *uname, int depth, 377 void *data) 378 { 379 const char *type = of_get_flat_dt_prop(node, "device_type", NULL); 380 const __be32 *prop; 381 int size = 0; 382 383 /* We are scanning "cpu" nodes only */ 384 if (type == NULL || strcmp(type, "cpu") != 0) 385 return 0; 386 387 prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size); 388 if (prop == NULL) 389 return 0; 390 for (; size >= 4; size -= 4, ++prop) { 391 if (be32_to_cpu(prop[0]) == 40) { 392 DBG("1T segment support detected\n"); 393 394 if (disable_1tb_segments) { 395 DBG("1T segments disabled by command line\n"); 396 break; 397 } 398 399 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT; 400 return 1; 401 } 402 } 403 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B; 404 return 0; 405 } 406 407 static int __init get_idx_from_shift(unsigned int shift) 408 { 409 int idx = -1; 410 411 switch (shift) { 412 case 0xc: 413 idx = MMU_PAGE_4K; 414 break; 415 case 0x10: 416 idx = MMU_PAGE_64K; 417 break; 418 case 0x14: 419 idx = MMU_PAGE_1M; 420 break; 421 case 0x18: 422 idx = MMU_PAGE_16M; 423 break; 424 case 0x22: 425 idx = MMU_PAGE_16G; 426 break; 427 } 428 return idx; 429 } 430 431 static int __init htab_dt_scan_page_sizes(unsigned long node, 432 const char *uname, int depth, 433 void *data) 434 { 435 const char *type = of_get_flat_dt_prop(node, "device_type", NULL); 436 const __be32 *prop; 437 int size = 0; 438 439 /* We are scanning "cpu" nodes only */ 440 if (type == NULL || strcmp(type, "cpu") != 0) 441 return 0; 442 443 prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size); 444 if (!prop) 445 return 0; 446 447 pr_info("Page sizes from device-tree:\n"); 448 size /= 4; 449 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE); 450 while(size > 0) { 451 unsigned int base_shift = be32_to_cpu(prop[0]); 452 unsigned int slbenc = be32_to_cpu(prop[1]); 453 unsigned int lpnum = be32_to_cpu(prop[2]); 454 struct mmu_psize_def *def; 455 int idx, base_idx; 456 457 size -= 3; prop += 3; 458 base_idx = get_idx_from_shift(base_shift); 459 if (base_idx < 0) { 460 /* skip the pte encoding also */ 461 prop += lpnum * 2; size -= lpnum * 2; 462 continue; 463 } 464 def = &mmu_psize_defs[base_idx]; 465 if (base_idx == MMU_PAGE_16M) 466 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE; 467 468 def->shift = base_shift; 469 if (base_shift <= 23) 470 def->avpnm = 0; 471 else 472 def->avpnm = (1 << (base_shift - 23)) - 1; 473 def->sllp = slbenc; 474 /* 475 * We don't know for sure what's up with tlbiel, so 476 * for now we only set it for 4K and 64K pages 477 */ 478 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K) 479 def->tlbiel = 1; 480 else 481 def->tlbiel = 0; 482 483 while (size > 0 && lpnum) { 484 unsigned int shift = be32_to_cpu(prop[0]); 485 int penc = be32_to_cpu(prop[1]); 486 487 prop += 2; size -= 2; 488 lpnum--; 489 490 idx = get_idx_from_shift(shift); 491 if (idx < 0) 492 continue; 493 494 if (penc == -1) 495 pr_err("Invalid penc for base_shift=%d " 496 "shift=%d\n", base_shift, shift); 497 498 def->penc[idx] = penc; 499 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx," 500 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n", 501 base_shift, shift, def->sllp, 502 def->avpnm, def->tlbiel, def->penc[idx]); 503 } 504 } 505 506 return 1; 507 } 508 509 #ifdef CONFIG_HUGETLB_PAGE 510 /* 511 * Scan for 16G memory blocks that have been set aside for huge pages 512 * and reserve those blocks for 16G huge pages. 513 */ 514 static int __init htab_dt_scan_hugepage_blocks(unsigned long node, 515 const char *uname, int depth, 516 void *data) { 517 const char *type = of_get_flat_dt_prop(node, "device_type", NULL); 518 const __be64 *addr_prop; 519 const __be32 *page_count_prop; 520 unsigned int expected_pages; 521 long unsigned int phys_addr; 522 long unsigned int block_size; 523 524 /* We are scanning "memory" nodes only */ 525 if (type == NULL || strcmp(type, "memory") != 0) 526 return 0; 527 528 /* 529 * This property is the log base 2 of the number of virtual pages that 530 * will represent this memory block. 531 */ 532 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL); 533 if (page_count_prop == NULL) 534 return 0; 535 expected_pages = (1 << be32_to_cpu(page_count_prop[0])); 536 addr_prop = of_get_flat_dt_prop(node, "reg", NULL); 537 if (addr_prop == NULL) 538 return 0; 539 phys_addr = be64_to_cpu(addr_prop[0]); 540 block_size = be64_to_cpu(addr_prop[1]); 541 if (block_size != (16 * GB)) 542 return 0; 543 printk(KERN_INFO "Huge page(16GB) memory: " 544 "addr = 0x%lX size = 0x%lX pages = %d\n", 545 phys_addr, block_size, expected_pages); 546 if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) { 547 memblock_reserve(phys_addr, block_size * expected_pages); 548 pseries_add_gpage(phys_addr, block_size, expected_pages); 549 } 550 return 0; 551 } 552 #endif /* CONFIG_HUGETLB_PAGE */ 553 554 static void mmu_psize_set_default_penc(void) 555 { 556 int bpsize, apsize; 557 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++) 558 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++) 559 mmu_psize_defs[bpsize].penc[apsize] = -1; 560 } 561 562 #ifdef CONFIG_PPC_64K_PAGES 563 564 static bool might_have_hea(void) 565 { 566 /* 567 * The HEA ethernet adapter requires awareness of the 568 * GX bus. Without that awareness we can easily assume 569 * we will never see an HEA ethernet device. 570 */ 571 #ifdef CONFIG_IBMEBUS 572 return !cpu_has_feature(CPU_FTR_ARCH_207S) && 573 firmware_has_feature(FW_FEATURE_SPLPAR); 574 #else 575 return false; 576 #endif 577 } 578 579 #endif /* #ifdef CONFIG_PPC_64K_PAGES */ 580 581 static void __init htab_scan_page_sizes(void) 582 { 583 int rc; 584 585 /* se the invalid penc to -1 */ 586 mmu_psize_set_default_penc(); 587 588 /* Default to 4K pages only */ 589 memcpy(mmu_psize_defs, mmu_psize_defaults, 590 sizeof(mmu_psize_defaults)); 591 592 /* 593 * Try to find the available page sizes in the device-tree 594 */ 595 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL); 596 if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) { 597 /* 598 * Nothing in the device-tree, but the CPU supports 16M pages, 599 * so let's fallback on a known size list for 16M capable CPUs. 600 */ 601 memcpy(mmu_psize_defs, mmu_psize_defaults_gp, 602 sizeof(mmu_psize_defaults_gp)); 603 } 604 605 #ifdef CONFIG_HUGETLB_PAGE 606 if (!hugetlb_disabled && !early_radix_enabled() ) { 607 /* Reserve 16G huge page memory sections for huge pages */ 608 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL); 609 } 610 #endif /* CONFIG_HUGETLB_PAGE */ 611 } 612 613 /* 614 * Fill in the hpte_page_sizes[] array. 615 * We go through the mmu_psize_defs[] array looking for all the 616 * supported base/actual page size combinations. Each combination 617 * has a unique pagesize encoding (penc) value in the low bits of 618 * the LP field of the HPTE. For actual page sizes less than 1MB, 619 * some of the upper LP bits are used for RPN bits, meaning that 620 * we need to fill in several entries in hpte_page_sizes[]. 621 * 622 * In diagrammatic form, with r = RPN bits and z = page size bits: 623 * PTE LP actual page size 624 * rrrr rrrz >=8KB 625 * rrrr rrzz >=16KB 626 * rrrr rzzz >=32KB 627 * rrrr zzzz >=64KB 628 * ... 629 * 630 * The zzzz bits are implementation-specific but are chosen so that 631 * no encoding for a larger page size uses the same value in its 632 * low-order N bits as the encoding for the 2^(12+N) byte page size 633 * (if it exists). 634 */ 635 static void init_hpte_page_sizes(void) 636 { 637 long int ap, bp; 638 long int shift, penc; 639 640 for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) { 641 if (!mmu_psize_defs[bp].shift) 642 continue; /* not a supported page size */ 643 for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) { 644 penc = mmu_psize_defs[bp].penc[ap]; 645 if (penc == -1 || !mmu_psize_defs[ap].shift) 646 continue; 647 shift = mmu_psize_defs[ap].shift - LP_SHIFT; 648 if (shift <= 0) 649 continue; /* should never happen */ 650 /* 651 * For page sizes less than 1MB, this loop 652 * replicates the entry for all possible values 653 * of the rrrr bits. 654 */ 655 while (penc < (1 << LP_BITS)) { 656 hpte_page_sizes[penc] = (ap << 4) | bp; 657 penc += 1 << shift; 658 } 659 } 660 } 661 } 662 663 static void __init htab_init_page_sizes(void) 664 { 665 bool aligned = true; 666 init_hpte_page_sizes(); 667 668 if (!debug_pagealloc_enabled()) { 669 /* 670 * Pick a size for the linear mapping. Currently, we only 671 * support 16M, 1M and 4K which is the default 672 */ 673 if (IS_ENABLED(CONFIG_STRICT_KERNEL_RWX) && 674 (unsigned long)_stext % 0x1000000) { 675 if (mmu_psize_defs[MMU_PAGE_16M].shift) 676 pr_warn("Kernel not 16M aligned, disabling 16M linear map alignment\n"); 677 aligned = false; 678 } 679 680 if (mmu_psize_defs[MMU_PAGE_16M].shift && aligned) 681 mmu_linear_psize = MMU_PAGE_16M; 682 else if (mmu_psize_defs[MMU_PAGE_1M].shift) 683 mmu_linear_psize = MMU_PAGE_1M; 684 } 685 686 #ifdef CONFIG_PPC_64K_PAGES 687 /* 688 * Pick a size for the ordinary pages. Default is 4K, we support 689 * 64K for user mappings and vmalloc if supported by the processor. 690 * We only use 64k for ioremap if the processor 691 * (and firmware) support cache-inhibited large pages. 692 * If not, we use 4k and set mmu_ci_restrictions so that 693 * hash_page knows to switch processes that use cache-inhibited 694 * mappings to 4k pages. 695 */ 696 if (mmu_psize_defs[MMU_PAGE_64K].shift) { 697 mmu_virtual_psize = MMU_PAGE_64K; 698 mmu_vmalloc_psize = MMU_PAGE_64K; 699 if (mmu_linear_psize == MMU_PAGE_4K) 700 mmu_linear_psize = MMU_PAGE_64K; 701 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) { 702 /* 703 * When running on pSeries using 64k pages for ioremap 704 * would stop us accessing the HEA ethernet. So if we 705 * have the chance of ever seeing one, stay at 4k. 706 */ 707 if (!might_have_hea()) 708 mmu_io_psize = MMU_PAGE_64K; 709 } else 710 mmu_ci_restrictions = 1; 711 } 712 #endif /* CONFIG_PPC_64K_PAGES */ 713 714 #ifdef CONFIG_SPARSEMEM_VMEMMAP 715 /* 716 * We try to use 16M pages for vmemmap if that is supported 717 * and we have at least 1G of RAM at boot 718 */ 719 if (mmu_psize_defs[MMU_PAGE_16M].shift && 720 memblock_phys_mem_size() >= 0x40000000) 721 mmu_vmemmap_psize = MMU_PAGE_16M; 722 else 723 mmu_vmemmap_psize = mmu_virtual_psize; 724 #endif /* CONFIG_SPARSEMEM_VMEMMAP */ 725 726 printk(KERN_DEBUG "Page orders: linear mapping = %d, " 727 "virtual = %d, io = %d" 728 #ifdef CONFIG_SPARSEMEM_VMEMMAP 729 ", vmemmap = %d" 730 #endif 731 "\n", 732 mmu_psize_defs[mmu_linear_psize].shift, 733 mmu_psize_defs[mmu_virtual_psize].shift, 734 mmu_psize_defs[mmu_io_psize].shift 735 #ifdef CONFIG_SPARSEMEM_VMEMMAP 736 ,mmu_psize_defs[mmu_vmemmap_psize].shift 737 #endif 738 ); 739 } 740 741 static int __init htab_dt_scan_pftsize(unsigned long node, 742 const char *uname, int depth, 743 void *data) 744 { 745 const char *type = of_get_flat_dt_prop(node, "device_type", NULL); 746 const __be32 *prop; 747 748 /* We are scanning "cpu" nodes only */ 749 if (type == NULL || strcmp(type, "cpu") != 0) 750 return 0; 751 752 prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL); 753 if (prop != NULL) { 754 /* pft_size[0] is the NUMA CEC cookie */ 755 ppc64_pft_size = be32_to_cpu(prop[1]); 756 return 1; 757 } 758 return 0; 759 } 760 761 unsigned htab_shift_for_mem_size(unsigned long mem_size) 762 { 763 unsigned memshift = __ilog2(mem_size); 764 unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift; 765 unsigned pteg_shift; 766 767 /* round mem_size up to next power of 2 */ 768 if ((1UL << memshift) < mem_size) 769 memshift += 1; 770 771 /* aim for 2 pages / pteg */ 772 pteg_shift = memshift - (pshift + 1); 773 774 /* 775 * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab 776 * size permitted by the architecture. 777 */ 778 return max(pteg_shift + 7, 18U); 779 } 780 781 static unsigned long __init htab_get_table_size(void) 782 { 783 /* 784 * If hash size isn't already provided by the platform, we try to 785 * retrieve it from the device-tree. If it's not there neither, we 786 * calculate it now based on the total RAM size 787 */ 788 if (ppc64_pft_size == 0) 789 of_scan_flat_dt(htab_dt_scan_pftsize, NULL); 790 if (ppc64_pft_size) 791 return 1UL << ppc64_pft_size; 792 793 return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size()); 794 } 795 796 #ifdef CONFIG_MEMORY_HOTPLUG 797 static int resize_hpt_for_hotplug(unsigned long new_mem_size) 798 { 799 unsigned target_hpt_shift; 800 801 if (!mmu_hash_ops.resize_hpt) 802 return 0; 803 804 target_hpt_shift = htab_shift_for_mem_size(new_mem_size); 805 806 /* 807 * To avoid lots of HPT resizes if memory size is fluctuating 808 * across a boundary, we deliberately have some hysterisis 809 * here: we immediately increase the HPT size if the target 810 * shift exceeds the current shift, but we won't attempt to 811 * reduce unless the target shift is at least 2 below the 812 * current shift 813 */ 814 if (target_hpt_shift > ppc64_pft_size || 815 target_hpt_shift < ppc64_pft_size - 1) 816 return mmu_hash_ops.resize_hpt(target_hpt_shift); 817 818 return 0; 819 } 820 821 int hash__create_section_mapping(unsigned long start, unsigned long end, 822 int nid, pgprot_t prot) 823 { 824 int rc; 825 826 if (end >= H_VMALLOC_START) { 827 pr_warn("Outside the supported range\n"); 828 return -1; 829 } 830 831 resize_hpt_for_hotplug(memblock_phys_mem_size()); 832 833 rc = htab_bolt_mapping(start, end, __pa(start), 834 pgprot_val(prot), mmu_linear_psize, 835 mmu_kernel_ssize); 836 837 if (rc < 0) { 838 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize, 839 mmu_kernel_ssize); 840 BUG_ON(rc2 && (rc2 != -ENOENT)); 841 } 842 return rc; 843 } 844 845 int hash__remove_section_mapping(unsigned long start, unsigned long end) 846 { 847 int rc = htab_remove_mapping(start, end, mmu_linear_psize, 848 mmu_kernel_ssize); 849 850 if (resize_hpt_for_hotplug(memblock_phys_mem_size()) == -ENOSPC) 851 pr_warn("Hash collision while resizing HPT\n"); 852 853 return rc; 854 } 855 #endif /* CONFIG_MEMORY_HOTPLUG */ 856 857 static void __init hash_init_partition_table(phys_addr_t hash_table, 858 unsigned long htab_size) 859 { 860 mmu_partition_table_init(); 861 862 /* 863 * PS field (VRMA page size) is not used for LPID 0, hence set to 0. 864 * For now, UPRT is 0 and we have no segment table. 865 */ 866 htab_size = __ilog2(htab_size) - 18; 867 mmu_partition_table_set_entry(0, hash_table | htab_size, 0, false); 868 pr_info("Partition table %p\n", partition_tb); 869 } 870 871 static void __init htab_initialize(void) 872 { 873 unsigned long table; 874 unsigned long pteg_count; 875 unsigned long prot; 876 phys_addr_t base = 0, size = 0, end; 877 u64 i; 878 879 DBG(" -> htab_initialize()\n"); 880 881 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) { 882 mmu_kernel_ssize = MMU_SEGSIZE_1T; 883 mmu_highuser_ssize = MMU_SEGSIZE_1T; 884 printk(KERN_INFO "Using 1TB segments\n"); 885 } 886 887 if (stress_slb_enabled) 888 static_branch_enable(&stress_slb_key); 889 890 /* 891 * Calculate the required size of the htab. We want the number of 892 * PTEGs to equal one half the number of real pages. 893 */ 894 htab_size_bytes = htab_get_table_size(); 895 pteg_count = htab_size_bytes >> 7; 896 897 htab_hash_mask = pteg_count - 1; 898 899 if (firmware_has_feature(FW_FEATURE_LPAR) || 900 firmware_has_feature(FW_FEATURE_PS3_LV1)) { 901 /* Using a hypervisor which owns the htab */ 902 htab_address = NULL; 903 _SDR1 = 0; 904 #ifdef CONFIG_FA_DUMP 905 /* 906 * If firmware assisted dump is active firmware preserves 907 * the contents of htab along with entire partition memory. 908 * Clear the htab if firmware assisted dump is active so 909 * that we dont end up using old mappings. 910 */ 911 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all) 912 mmu_hash_ops.hpte_clear_all(); 913 #endif 914 } else { 915 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE; 916 917 #ifdef CONFIG_PPC_CELL 918 /* 919 * Cell may require the hash table down low when using the 920 * Axon IOMMU in order to fit the dynamic region over it, see 921 * comments in cell/iommu.c 922 */ 923 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) { 924 limit = 0x80000000; 925 pr_info("Hash table forced below 2G for Axon IOMMU\n"); 926 } 927 #endif /* CONFIG_PPC_CELL */ 928 929 table = memblock_phys_alloc_range(htab_size_bytes, 930 htab_size_bytes, 931 0, limit); 932 if (!table) 933 panic("ERROR: Failed to allocate %pa bytes below %pa\n", 934 &htab_size_bytes, &limit); 935 936 DBG("Hash table allocated at %lx, size: %lx\n", table, 937 htab_size_bytes); 938 939 htab_address = __va(table); 940 941 /* htab absolute addr + encoded htabsize */ 942 _SDR1 = table + __ilog2(htab_size_bytes) - 18; 943 944 /* Initialize the HPT with no entries */ 945 memset((void *)table, 0, htab_size_bytes); 946 947 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 948 /* Set SDR1 */ 949 mtspr(SPRN_SDR1, _SDR1); 950 else 951 hash_init_partition_table(table, htab_size_bytes); 952 } 953 954 prot = pgprot_val(PAGE_KERNEL); 955 956 #ifdef CONFIG_DEBUG_PAGEALLOC 957 if (debug_pagealloc_enabled()) { 958 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT; 959 linear_map_hash_slots = memblock_alloc_try_nid( 960 linear_map_hash_count, 1, MEMBLOCK_LOW_LIMIT, 961 ppc64_rma_size, NUMA_NO_NODE); 962 if (!linear_map_hash_slots) 963 panic("%s: Failed to allocate %lu bytes max_addr=%pa\n", 964 __func__, linear_map_hash_count, &ppc64_rma_size); 965 } 966 #endif /* CONFIG_DEBUG_PAGEALLOC */ 967 968 /* create bolted the linear mapping in the hash table */ 969 for_each_mem_range(i, &base, &end) { 970 size = end - base; 971 base = (unsigned long)__va(base); 972 973 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n", 974 base, size, prot); 975 976 if ((base + size) >= H_VMALLOC_START) { 977 pr_warn("Outside the supported range\n"); 978 continue; 979 } 980 981 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base), 982 prot, mmu_linear_psize, mmu_kernel_ssize)); 983 } 984 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE); 985 986 /* 987 * If we have a memory_limit and we've allocated TCEs then we need to 988 * explicitly map the TCE area at the top of RAM. We also cope with the 989 * case that the TCEs start below memory_limit. 990 * tce_alloc_start/end are 16MB aligned so the mapping should work 991 * for either 4K or 16MB pages. 992 */ 993 if (tce_alloc_start) { 994 tce_alloc_start = (unsigned long)__va(tce_alloc_start); 995 tce_alloc_end = (unsigned long)__va(tce_alloc_end); 996 997 if (base + size >= tce_alloc_start) 998 tce_alloc_start = base + size + 1; 999 1000 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end, 1001 __pa(tce_alloc_start), prot, 1002 mmu_linear_psize, mmu_kernel_ssize)); 1003 } 1004 1005 1006 DBG(" <- htab_initialize()\n"); 1007 } 1008 #undef KB 1009 #undef MB 1010 1011 void __init hash__early_init_devtree(void) 1012 { 1013 /* Initialize segment sizes */ 1014 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL); 1015 1016 /* Initialize page sizes */ 1017 htab_scan_page_sizes(); 1018 } 1019 1020 static struct hash_mm_context init_hash_mm_context; 1021 void __init hash__early_init_mmu(void) 1022 { 1023 #ifndef CONFIG_PPC_64K_PAGES 1024 /* 1025 * We have code in __hash_page_4K() and elsewhere, which assumes it can 1026 * do the following: 1027 * new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX); 1028 * 1029 * Where the slot number is between 0-15, and values of 8-15 indicate 1030 * the secondary bucket. For that code to work H_PAGE_F_SECOND and 1031 * H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and 1032 * H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here 1033 * with a BUILD_BUG_ON(). 1034 */ 1035 BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3))); 1036 #endif /* CONFIG_PPC_64K_PAGES */ 1037 1038 htab_init_page_sizes(); 1039 1040 /* 1041 * initialize page table size 1042 */ 1043 __pte_frag_nr = H_PTE_FRAG_NR; 1044 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT; 1045 __pmd_frag_nr = H_PMD_FRAG_NR; 1046 __pmd_frag_size_shift = H_PMD_FRAG_SIZE_SHIFT; 1047 1048 __pte_index_size = H_PTE_INDEX_SIZE; 1049 __pmd_index_size = H_PMD_INDEX_SIZE; 1050 __pud_index_size = H_PUD_INDEX_SIZE; 1051 __pgd_index_size = H_PGD_INDEX_SIZE; 1052 __pud_cache_index = H_PUD_CACHE_INDEX; 1053 __pte_table_size = H_PTE_TABLE_SIZE; 1054 __pmd_table_size = H_PMD_TABLE_SIZE; 1055 __pud_table_size = H_PUD_TABLE_SIZE; 1056 __pgd_table_size = H_PGD_TABLE_SIZE; 1057 /* 1058 * 4k use hugepd format, so for hash set then to 1059 * zero 1060 */ 1061 __pmd_val_bits = HASH_PMD_VAL_BITS; 1062 __pud_val_bits = HASH_PUD_VAL_BITS; 1063 __pgd_val_bits = HASH_PGD_VAL_BITS; 1064 1065 __kernel_virt_start = H_KERN_VIRT_START; 1066 __vmalloc_start = H_VMALLOC_START; 1067 __vmalloc_end = H_VMALLOC_END; 1068 __kernel_io_start = H_KERN_IO_START; 1069 __kernel_io_end = H_KERN_IO_END; 1070 vmemmap = (struct page *)H_VMEMMAP_START; 1071 ioremap_bot = IOREMAP_BASE; 1072 1073 #ifdef CONFIG_PCI 1074 pci_io_base = ISA_IO_BASE; 1075 #endif 1076 1077 /* Select appropriate backend */ 1078 if (firmware_has_feature(FW_FEATURE_PS3_LV1)) 1079 ps3_early_mm_init(); 1080 else if (firmware_has_feature(FW_FEATURE_LPAR)) 1081 hpte_init_pseries(); 1082 else if (IS_ENABLED(CONFIG_PPC_NATIVE)) 1083 hpte_init_native(); 1084 1085 if (!mmu_hash_ops.hpte_insert) 1086 panic("hash__early_init_mmu: No MMU hash ops defined!\n"); 1087 1088 /* 1089 * Initialize the MMU Hash table and create the linear mapping 1090 * of memory. Has to be done before SLB initialization as this is 1091 * currently where the page size encoding is obtained. 1092 */ 1093 htab_initialize(); 1094 1095 init_mm.context.hash_context = &init_hash_mm_context; 1096 mm_ctx_set_slb_addr_limit(&init_mm.context, SLB_ADDR_LIMIT_DEFAULT); 1097 1098 pr_info("Initializing hash mmu with SLB\n"); 1099 /* Initialize SLB management */ 1100 slb_initialize(); 1101 1102 if (cpu_has_feature(CPU_FTR_ARCH_206) 1103 && cpu_has_feature(CPU_FTR_HVMODE)) 1104 tlbiel_all(); 1105 } 1106 1107 #ifdef CONFIG_SMP 1108 void hash__early_init_mmu_secondary(void) 1109 { 1110 /* Initialize hash table for that CPU */ 1111 if (!firmware_has_feature(FW_FEATURE_LPAR)) { 1112 1113 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1114 mtspr(SPRN_SDR1, _SDR1); 1115 else 1116 set_ptcr_when_no_uv(__pa(partition_tb) | 1117 (PATB_SIZE_SHIFT - 12)); 1118 } 1119 /* Initialize SLB */ 1120 slb_initialize(); 1121 1122 if (cpu_has_feature(CPU_FTR_ARCH_206) 1123 && cpu_has_feature(CPU_FTR_HVMODE)) 1124 tlbiel_all(); 1125 1126 #ifdef CONFIG_PPC_MEM_KEYS 1127 if (mmu_has_feature(MMU_FTR_PKEY)) 1128 mtspr(SPRN_UAMOR, default_uamor); 1129 #endif 1130 } 1131 #endif /* CONFIG_SMP */ 1132 1133 /* 1134 * Called by asm hashtable.S for doing lazy icache flush 1135 */ 1136 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap) 1137 { 1138 struct page *page; 1139 1140 if (!pfn_valid(pte_pfn(pte))) 1141 return pp; 1142 1143 page = pte_page(pte); 1144 1145 /* page is dirty */ 1146 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) { 1147 if (trap == 0x400) { 1148 flush_dcache_icache_page(page); 1149 set_bit(PG_arch_1, &page->flags); 1150 } else 1151 pp |= HPTE_R_N; 1152 } 1153 return pp; 1154 } 1155 1156 #ifdef CONFIG_PPC_MM_SLICES 1157 static unsigned int get_paca_psize(unsigned long addr) 1158 { 1159 unsigned char *psizes; 1160 unsigned long index, mask_index; 1161 1162 if (addr < SLICE_LOW_TOP) { 1163 psizes = get_paca()->mm_ctx_low_slices_psize; 1164 index = GET_LOW_SLICE_INDEX(addr); 1165 } else { 1166 psizes = get_paca()->mm_ctx_high_slices_psize; 1167 index = GET_HIGH_SLICE_INDEX(addr); 1168 } 1169 mask_index = index & 0x1; 1170 return (psizes[index >> 1] >> (mask_index * 4)) & 0xF; 1171 } 1172 1173 #else 1174 unsigned int get_paca_psize(unsigned long addr) 1175 { 1176 return get_paca()->mm_ctx_user_psize; 1177 } 1178 #endif 1179 1180 /* 1181 * Demote a segment to using 4k pages. 1182 * For now this makes the whole process use 4k pages. 1183 */ 1184 #ifdef CONFIG_PPC_64K_PAGES 1185 void demote_segment_4k(struct mm_struct *mm, unsigned long addr) 1186 { 1187 if (get_slice_psize(mm, addr) == MMU_PAGE_4K) 1188 return; 1189 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K); 1190 copro_flush_all_slbs(mm); 1191 if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) { 1192 1193 copy_mm_to_paca(mm); 1194 slb_flush_and_restore_bolted(); 1195 } 1196 } 1197 #endif /* CONFIG_PPC_64K_PAGES */ 1198 1199 #ifdef CONFIG_PPC_SUBPAGE_PROT 1200 /* 1201 * This looks up a 2-bit protection code for a 4k subpage of a 64k page. 1202 * Userspace sets the subpage permissions using the subpage_prot system call. 1203 * 1204 * Result is 0: full permissions, _PAGE_RW: read-only, 1205 * _PAGE_RWX: no access. 1206 */ 1207 static int subpage_protection(struct mm_struct *mm, unsigned long ea) 1208 { 1209 struct subpage_prot_table *spt = mm_ctx_subpage_prot(&mm->context); 1210 u32 spp = 0; 1211 u32 **sbpm, *sbpp; 1212 1213 if (!spt) 1214 return 0; 1215 1216 if (ea >= spt->maxaddr) 1217 return 0; 1218 if (ea < 0x100000000UL) { 1219 /* addresses below 4GB use spt->low_prot */ 1220 sbpm = spt->low_prot; 1221 } else { 1222 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT]; 1223 if (!sbpm) 1224 return 0; 1225 } 1226 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)]; 1227 if (!sbpp) 1228 return 0; 1229 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)]; 1230 1231 /* extract 2-bit bitfield for this 4k subpage */ 1232 spp >>= 30 - 2 * ((ea >> 12) & 0xf); 1233 1234 /* 1235 * 0 -> full premission 1236 * 1 -> Read only 1237 * 2 -> no access. 1238 * We return the flag that need to be cleared. 1239 */ 1240 spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0); 1241 return spp; 1242 } 1243 1244 #else /* CONFIG_PPC_SUBPAGE_PROT */ 1245 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea) 1246 { 1247 return 0; 1248 } 1249 #endif 1250 1251 void hash_failure_debug(unsigned long ea, unsigned long access, 1252 unsigned long vsid, unsigned long trap, 1253 int ssize, int psize, int lpsize, unsigned long pte) 1254 { 1255 if (!printk_ratelimit()) 1256 return; 1257 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n", 1258 ea, access, current->comm); 1259 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n", 1260 trap, vsid, ssize, psize, lpsize, pte); 1261 } 1262 1263 static void check_paca_psize(unsigned long ea, struct mm_struct *mm, 1264 int psize, bool user_region) 1265 { 1266 if (user_region) { 1267 if (psize != get_paca_psize(ea)) { 1268 copy_mm_to_paca(mm); 1269 slb_flush_and_restore_bolted(); 1270 } 1271 } else if (get_paca()->vmalloc_sllp != 1272 mmu_psize_defs[mmu_vmalloc_psize].sllp) { 1273 get_paca()->vmalloc_sllp = 1274 mmu_psize_defs[mmu_vmalloc_psize].sllp; 1275 slb_vmalloc_update(); 1276 } 1277 } 1278 1279 /* 1280 * Result code is: 1281 * 0 - handled 1282 * 1 - normal page fault 1283 * -1 - critical hash insertion error 1284 * -2 - access not permitted by subpage protection mechanism 1285 */ 1286 int hash_page_mm(struct mm_struct *mm, unsigned long ea, 1287 unsigned long access, unsigned long trap, 1288 unsigned long flags) 1289 { 1290 bool is_thp; 1291 enum ctx_state prev_state = exception_enter(); 1292 pgd_t *pgdir; 1293 unsigned long vsid; 1294 pte_t *ptep; 1295 unsigned hugeshift; 1296 int rc, user_region = 0; 1297 int psize, ssize; 1298 1299 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n", 1300 ea, access, trap); 1301 trace_hash_fault(ea, access, trap); 1302 1303 /* Get region & vsid */ 1304 switch (get_region_id(ea)) { 1305 case USER_REGION_ID: 1306 user_region = 1; 1307 if (! mm) { 1308 DBG_LOW(" user region with no mm !\n"); 1309 rc = 1; 1310 goto bail; 1311 } 1312 psize = get_slice_psize(mm, ea); 1313 ssize = user_segment_size(ea); 1314 vsid = get_user_vsid(&mm->context, ea, ssize); 1315 break; 1316 case VMALLOC_REGION_ID: 1317 vsid = get_kernel_vsid(ea, mmu_kernel_ssize); 1318 psize = mmu_vmalloc_psize; 1319 ssize = mmu_kernel_ssize; 1320 flags |= HPTE_USE_KERNEL_KEY; 1321 break; 1322 1323 case IO_REGION_ID: 1324 vsid = get_kernel_vsid(ea, mmu_kernel_ssize); 1325 psize = mmu_io_psize; 1326 ssize = mmu_kernel_ssize; 1327 flags |= HPTE_USE_KERNEL_KEY; 1328 break; 1329 default: 1330 /* 1331 * Not a valid range 1332 * Send the problem up to do_page_fault() 1333 */ 1334 rc = 1; 1335 goto bail; 1336 } 1337 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid); 1338 1339 /* Bad address. */ 1340 if (!vsid) { 1341 DBG_LOW("Bad address!\n"); 1342 rc = 1; 1343 goto bail; 1344 } 1345 /* Get pgdir */ 1346 pgdir = mm->pgd; 1347 if (pgdir == NULL) { 1348 rc = 1; 1349 goto bail; 1350 } 1351 1352 /* Check CPU locality */ 1353 if (user_region && mm_is_thread_local(mm)) 1354 flags |= HPTE_LOCAL_UPDATE; 1355 1356 #ifndef CONFIG_PPC_64K_PAGES 1357 /* 1358 * If we use 4K pages and our psize is not 4K, then we might 1359 * be hitting a special driver mapping, and need to align the 1360 * address before we fetch the PTE. 1361 * 1362 * It could also be a hugepage mapping, in which case this is 1363 * not necessary, but it's not harmful, either. 1364 */ 1365 if (psize != MMU_PAGE_4K) 1366 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1); 1367 #endif /* CONFIG_PPC_64K_PAGES */ 1368 1369 /* Get PTE and page size from page tables */ 1370 ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift); 1371 if (ptep == NULL || !pte_present(*ptep)) { 1372 DBG_LOW(" no PTE !\n"); 1373 rc = 1; 1374 goto bail; 1375 } 1376 1377 /* 1378 * Add _PAGE_PRESENT to the required access perm. If there are parallel 1379 * updates to the pte that can possibly clear _PAGE_PTE, catch that too. 1380 * 1381 * We can safely use the return pte address in rest of the function 1382 * because we do set H_PAGE_BUSY which prevents further updates to pte 1383 * from generic code. 1384 */ 1385 access |= _PAGE_PRESENT | _PAGE_PTE; 1386 1387 /* 1388 * Pre-check access permissions (will be re-checked atomically 1389 * in __hash_page_XX but this pre-check is a fast path 1390 */ 1391 if (!check_pte_access(access, pte_val(*ptep))) { 1392 DBG_LOW(" no access !\n"); 1393 rc = 1; 1394 goto bail; 1395 } 1396 1397 if (hugeshift) { 1398 if (is_thp) 1399 rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep, 1400 trap, flags, ssize, psize); 1401 #ifdef CONFIG_HUGETLB_PAGE 1402 else 1403 rc = __hash_page_huge(ea, access, vsid, ptep, trap, 1404 flags, ssize, hugeshift, psize); 1405 #else 1406 else { 1407 /* 1408 * if we have hugeshift, and is not transhuge with 1409 * hugetlb disabled, something is really wrong. 1410 */ 1411 rc = 1; 1412 WARN_ON(1); 1413 } 1414 #endif 1415 if (current->mm == mm) 1416 check_paca_psize(ea, mm, psize, user_region); 1417 1418 goto bail; 1419 } 1420 1421 #ifndef CONFIG_PPC_64K_PAGES 1422 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep)); 1423 #else 1424 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep), 1425 pte_val(*(ptep + PTRS_PER_PTE))); 1426 #endif 1427 /* Do actual hashing */ 1428 #ifdef CONFIG_PPC_64K_PAGES 1429 /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */ 1430 if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) { 1431 demote_segment_4k(mm, ea); 1432 psize = MMU_PAGE_4K; 1433 } 1434 1435 /* 1436 * If this PTE is non-cacheable and we have restrictions on 1437 * using non cacheable large pages, then we switch to 4k 1438 */ 1439 if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) { 1440 if (user_region) { 1441 demote_segment_4k(mm, ea); 1442 psize = MMU_PAGE_4K; 1443 } else if (ea < VMALLOC_END) { 1444 /* 1445 * some driver did a non-cacheable mapping 1446 * in vmalloc space, so switch vmalloc 1447 * to 4k pages 1448 */ 1449 printk(KERN_ALERT "Reducing vmalloc segment " 1450 "to 4kB pages because of " 1451 "non-cacheable mapping\n"); 1452 psize = mmu_vmalloc_psize = MMU_PAGE_4K; 1453 copro_flush_all_slbs(mm); 1454 } 1455 } 1456 1457 #endif /* CONFIG_PPC_64K_PAGES */ 1458 1459 if (current->mm == mm) 1460 check_paca_psize(ea, mm, psize, user_region); 1461 1462 #ifdef CONFIG_PPC_64K_PAGES 1463 if (psize == MMU_PAGE_64K) 1464 rc = __hash_page_64K(ea, access, vsid, ptep, trap, 1465 flags, ssize); 1466 else 1467 #endif /* CONFIG_PPC_64K_PAGES */ 1468 { 1469 int spp = subpage_protection(mm, ea); 1470 if (access & spp) 1471 rc = -2; 1472 else 1473 rc = __hash_page_4K(ea, access, vsid, ptep, trap, 1474 flags, ssize, spp); 1475 } 1476 1477 /* 1478 * Dump some info in case of hash insertion failure, they should 1479 * never happen so it is really useful to know if/when they do 1480 */ 1481 if (rc == -1) 1482 hash_failure_debug(ea, access, vsid, trap, ssize, psize, 1483 psize, pte_val(*ptep)); 1484 #ifndef CONFIG_PPC_64K_PAGES 1485 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep)); 1486 #else 1487 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep), 1488 pte_val(*(ptep + PTRS_PER_PTE))); 1489 #endif 1490 DBG_LOW(" -> rc=%d\n", rc); 1491 1492 bail: 1493 exception_exit(prev_state); 1494 return rc; 1495 } 1496 EXPORT_SYMBOL_GPL(hash_page_mm); 1497 1498 int hash_page(unsigned long ea, unsigned long access, unsigned long trap, 1499 unsigned long dsisr) 1500 { 1501 unsigned long flags = 0; 1502 struct mm_struct *mm = current->mm; 1503 1504 if ((get_region_id(ea) == VMALLOC_REGION_ID) || 1505 (get_region_id(ea) == IO_REGION_ID)) 1506 mm = &init_mm; 1507 1508 if (dsisr & DSISR_NOHPTE) 1509 flags |= HPTE_NOHPTE_UPDATE; 1510 1511 return hash_page_mm(mm, ea, access, trap, flags); 1512 } 1513 EXPORT_SYMBOL_GPL(hash_page); 1514 1515 int __hash_page(unsigned long trap, unsigned long ea, unsigned long dsisr, 1516 unsigned long msr) 1517 { 1518 unsigned long access = _PAGE_PRESENT | _PAGE_READ; 1519 unsigned long flags = 0; 1520 struct mm_struct *mm = current->mm; 1521 unsigned int region_id = get_region_id(ea); 1522 1523 if ((region_id == VMALLOC_REGION_ID) || (region_id == IO_REGION_ID)) 1524 mm = &init_mm; 1525 1526 if (dsisr & DSISR_NOHPTE) 1527 flags |= HPTE_NOHPTE_UPDATE; 1528 1529 if (dsisr & DSISR_ISSTORE) 1530 access |= _PAGE_WRITE; 1531 /* 1532 * We set _PAGE_PRIVILEGED only when 1533 * kernel mode access kernel space. 1534 * 1535 * _PAGE_PRIVILEGED is NOT set 1536 * 1) when kernel mode access user space 1537 * 2) user space access kernel space. 1538 */ 1539 access |= _PAGE_PRIVILEGED; 1540 if ((msr & MSR_PR) || (region_id == USER_REGION_ID)) 1541 access &= ~_PAGE_PRIVILEGED; 1542 1543 if (trap == 0x400) 1544 access |= _PAGE_EXEC; 1545 1546 return hash_page_mm(mm, ea, access, trap, flags); 1547 } 1548 1549 #ifdef CONFIG_PPC_MM_SLICES 1550 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea) 1551 { 1552 int psize = get_slice_psize(mm, ea); 1553 1554 /* We only prefault standard pages for now */ 1555 if (unlikely(psize != mm_ctx_user_psize(&mm->context))) 1556 return false; 1557 1558 /* 1559 * Don't prefault if subpage protection is enabled for the EA. 1560 */ 1561 if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea))) 1562 return false; 1563 1564 return true; 1565 } 1566 #else 1567 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea) 1568 { 1569 return true; 1570 } 1571 #endif 1572 1573 static void hash_preload(struct mm_struct *mm, pte_t *ptep, unsigned long ea, 1574 bool is_exec, unsigned long trap) 1575 { 1576 unsigned long vsid; 1577 pgd_t *pgdir; 1578 int rc, ssize, update_flags = 0; 1579 unsigned long access = _PAGE_PRESENT | _PAGE_READ | (is_exec ? _PAGE_EXEC : 0); 1580 unsigned long flags; 1581 1582 BUG_ON(get_region_id(ea) != USER_REGION_ID); 1583 1584 if (!should_hash_preload(mm, ea)) 1585 return; 1586 1587 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx," 1588 " trap=%lx\n", mm, mm->pgd, ea, access, trap); 1589 1590 /* Get Linux PTE if available */ 1591 pgdir = mm->pgd; 1592 if (pgdir == NULL) 1593 return; 1594 1595 /* Get VSID */ 1596 ssize = user_segment_size(ea); 1597 vsid = get_user_vsid(&mm->context, ea, ssize); 1598 if (!vsid) 1599 return; 1600 1601 #ifdef CONFIG_PPC_64K_PAGES 1602 /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on 1603 * a 64K kernel), then we don't preload, hash_page() will take 1604 * care of it once we actually try to access the page. 1605 * That way we don't have to duplicate all of the logic for segment 1606 * page size demotion here 1607 * Called with PTL held, hence can be sure the value won't change in 1608 * between. 1609 */ 1610 if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep)) 1611 return; 1612 #endif /* CONFIG_PPC_64K_PAGES */ 1613 1614 /* 1615 * __hash_page_* must run with interrupts off, as it sets the 1616 * H_PAGE_BUSY bit. It's possible for perf interrupts to hit at any 1617 * time and may take a hash fault reading the user stack, see 1618 * read_user_stack_slow() in the powerpc/perf code. 1619 * 1620 * If that takes a hash fault on the same page as we lock here, it 1621 * will bail out when seeing H_PAGE_BUSY set, and retry the access 1622 * leading to an infinite loop. 1623 * 1624 * Disabling interrupts here does not prevent perf interrupts, but it 1625 * will prevent them taking hash faults (see the NMI test in 1626 * do_hash_page), then read_user_stack's copy_from_user_nofault will 1627 * fail and perf will fall back to read_user_stack_slow(), which 1628 * walks the Linux page tables. 1629 * 1630 * Interrupts must also be off for the duration of the 1631 * mm_is_thread_local test and update, to prevent preempt running the 1632 * mm on another CPU (XXX: this may be racy vs kthread_use_mm). 1633 */ 1634 local_irq_save(flags); 1635 1636 /* Is that local to this CPU ? */ 1637 if (mm_is_thread_local(mm)) 1638 update_flags |= HPTE_LOCAL_UPDATE; 1639 1640 /* Hash it in */ 1641 #ifdef CONFIG_PPC_64K_PAGES 1642 if (mm_ctx_user_psize(&mm->context) == MMU_PAGE_64K) 1643 rc = __hash_page_64K(ea, access, vsid, ptep, trap, 1644 update_flags, ssize); 1645 else 1646 #endif /* CONFIG_PPC_64K_PAGES */ 1647 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags, 1648 ssize, subpage_protection(mm, ea)); 1649 1650 /* Dump some info in case of hash insertion failure, they should 1651 * never happen so it is really useful to know if/when they do 1652 */ 1653 if (rc == -1) 1654 hash_failure_debug(ea, access, vsid, trap, ssize, 1655 mm_ctx_user_psize(&mm->context), 1656 mm_ctx_user_psize(&mm->context), 1657 pte_val(*ptep)); 1658 1659 local_irq_restore(flags); 1660 } 1661 1662 /* 1663 * This is called at the end of handling a user page fault, when the 1664 * fault has been handled by updating a PTE in the linux page tables. 1665 * We use it to preload an HPTE into the hash table corresponding to 1666 * the updated linux PTE. 1667 * 1668 * This must always be called with the pte lock held. 1669 */ 1670 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, 1671 pte_t *ptep) 1672 { 1673 /* 1674 * We don't need to worry about _PAGE_PRESENT here because we are 1675 * called with either mm->page_table_lock held or ptl lock held 1676 */ 1677 unsigned long trap; 1678 bool is_exec; 1679 1680 if (radix_enabled()) 1681 return; 1682 1683 /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */ 1684 if (!pte_young(*ptep) || address >= TASK_SIZE) 1685 return; 1686 1687 /* 1688 * We try to figure out if we are coming from an instruction 1689 * access fault and pass that down to __hash_page so we avoid 1690 * double-faulting on execution of fresh text. We have to test 1691 * for regs NULL since init will get here first thing at boot. 1692 * 1693 * We also avoid filling the hash if not coming from a fault. 1694 */ 1695 1696 trap = current->thread.regs ? TRAP(current->thread.regs) : 0UL; 1697 switch (trap) { 1698 case 0x300: 1699 is_exec = false; 1700 break; 1701 case 0x400: 1702 is_exec = true; 1703 break; 1704 default: 1705 return; 1706 } 1707 1708 hash_preload(vma->vm_mm, ptep, address, is_exec, trap); 1709 } 1710 1711 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1712 static inline void tm_flush_hash_page(int local) 1713 { 1714 /* 1715 * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a 1716 * page back to a block device w/PIO could pick up transactional data 1717 * (bad!) so we force an abort here. Before the sync the page will be 1718 * made read-only, which will flush_hash_page. BIG ISSUE here: if the 1719 * kernel uses a page from userspace without unmapping it first, it may 1720 * see the speculated version. 1721 */ 1722 if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs && 1723 MSR_TM_ACTIVE(current->thread.regs->msr)) { 1724 tm_enable(); 1725 tm_abort(TM_CAUSE_TLBI); 1726 } 1727 } 1728 #else 1729 static inline void tm_flush_hash_page(int local) 1730 { 1731 } 1732 #endif 1733 1734 /* 1735 * Return the global hash slot, corresponding to the given PTE, which contains 1736 * the HPTE. 1737 */ 1738 unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift, 1739 int ssize, real_pte_t rpte, unsigned int subpg_index) 1740 { 1741 unsigned long hash, gslot, hidx; 1742 1743 hash = hpt_hash(vpn, shift, ssize); 1744 hidx = __rpte_to_hidx(rpte, subpg_index); 1745 if (hidx & _PTEIDX_SECONDARY) 1746 hash = ~hash; 1747 gslot = (hash & htab_hash_mask) * HPTES_PER_GROUP; 1748 gslot += hidx & _PTEIDX_GROUP_IX; 1749 return gslot; 1750 } 1751 1752 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize, 1753 unsigned long flags) 1754 { 1755 unsigned long index, shift, gslot; 1756 int local = flags & HPTE_LOCAL_UPDATE; 1757 1758 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn); 1759 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) { 1760 gslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index); 1761 DBG_LOW(" sub %ld: gslot=%lx\n", index, gslot); 1762 /* 1763 * We use same base page size and actual psize, because we don't 1764 * use these functions for hugepage 1765 */ 1766 mmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize, 1767 ssize, local); 1768 } pte_iterate_hashed_end(); 1769 1770 tm_flush_hash_page(local); 1771 } 1772 1773 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1774 void flush_hash_hugepage(unsigned long vsid, unsigned long addr, 1775 pmd_t *pmdp, unsigned int psize, int ssize, 1776 unsigned long flags) 1777 { 1778 int i, max_hpte_count, valid; 1779 unsigned long s_addr; 1780 unsigned char *hpte_slot_array; 1781 unsigned long hidx, shift, vpn, hash, slot; 1782 int local = flags & HPTE_LOCAL_UPDATE; 1783 1784 s_addr = addr & HPAGE_PMD_MASK; 1785 hpte_slot_array = get_hpte_slot_array(pmdp); 1786 /* 1787 * IF we try to do a HUGE PTE update after a withdraw is done. 1788 * we will find the below NULL. This happens when we do 1789 * split_huge_pmd 1790 */ 1791 if (!hpte_slot_array) 1792 return; 1793 1794 if (mmu_hash_ops.hugepage_invalidate) { 1795 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array, 1796 psize, ssize, local); 1797 goto tm_abort; 1798 } 1799 /* 1800 * No bluk hpte removal support, invalidate each entry 1801 */ 1802 shift = mmu_psize_defs[psize].shift; 1803 max_hpte_count = HPAGE_PMD_SIZE >> shift; 1804 for (i = 0; i < max_hpte_count; i++) { 1805 /* 1806 * 8 bits per each hpte entries 1807 * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit] 1808 */ 1809 valid = hpte_valid(hpte_slot_array, i); 1810 if (!valid) 1811 continue; 1812 hidx = hpte_hash_index(hpte_slot_array, i); 1813 1814 /* get the vpn */ 1815 addr = s_addr + (i * (1ul << shift)); 1816 vpn = hpt_vpn(addr, vsid, ssize); 1817 hash = hpt_hash(vpn, shift, ssize); 1818 if (hidx & _PTEIDX_SECONDARY) 1819 hash = ~hash; 1820 1821 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; 1822 slot += hidx & _PTEIDX_GROUP_IX; 1823 mmu_hash_ops.hpte_invalidate(slot, vpn, psize, 1824 MMU_PAGE_16M, ssize, local); 1825 } 1826 tm_abort: 1827 tm_flush_hash_page(local); 1828 } 1829 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1830 1831 void flush_hash_range(unsigned long number, int local) 1832 { 1833 if (mmu_hash_ops.flush_hash_range) 1834 mmu_hash_ops.flush_hash_range(number, local); 1835 else { 1836 int i; 1837 struct ppc64_tlb_batch *batch = 1838 this_cpu_ptr(&ppc64_tlb_batch); 1839 1840 for (i = 0; i < number; i++) 1841 flush_hash_page(batch->vpn[i], batch->pte[i], 1842 batch->psize, batch->ssize, local); 1843 } 1844 } 1845 1846 /* 1847 * low_hash_fault is called when we the low level hash code failed 1848 * to instert a PTE due to an hypervisor error 1849 */ 1850 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc) 1851 { 1852 enum ctx_state prev_state = exception_enter(); 1853 1854 if (user_mode(regs)) { 1855 #ifdef CONFIG_PPC_SUBPAGE_PROT 1856 if (rc == -2) 1857 _exception(SIGSEGV, regs, SEGV_ACCERR, address); 1858 else 1859 #endif 1860 _exception(SIGBUS, regs, BUS_ADRERR, address); 1861 } else 1862 bad_page_fault(regs, address, SIGBUS); 1863 1864 exception_exit(prev_state); 1865 } 1866 1867 long hpte_insert_repeating(unsigned long hash, unsigned long vpn, 1868 unsigned long pa, unsigned long rflags, 1869 unsigned long vflags, int psize, int ssize) 1870 { 1871 unsigned long hpte_group; 1872 long slot; 1873 1874 repeat: 1875 hpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP; 1876 1877 /* Insert into the hash table, primary slot */ 1878 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags, 1879 psize, psize, ssize); 1880 1881 /* Primary is full, try the secondary */ 1882 if (unlikely(slot == -1)) { 1883 hpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP; 1884 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, 1885 vflags | HPTE_V_SECONDARY, 1886 psize, psize, ssize); 1887 if (slot == -1) { 1888 if (mftb() & 0x1) 1889 hpte_group = (hash & htab_hash_mask) * 1890 HPTES_PER_GROUP; 1891 1892 mmu_hash_ops.hpte_remove(hpte_group); 1893 goto repeat; 1894 } 1895 } 1896 1897 return slot; 1898 } 1899 1900 #ifdef CONFIG_DEBUG_PAGEALLOC 1901 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi) 1902 { 1903 unsigned long hash; 1904 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); 1905 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); 1906 unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL), HPTE_USE_KERNEL_KEY); 1907 long ret; 1908 1909 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); 1910 1911 /* Don't create HPTE entries for bad address */ 1912 if (!vsid) 1913 return; 1914 1915 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode, 1916 HPTE_V_BOLTED, 1917 mmu_linear_psize, mmu_kernel_ssize); 1918 1919 BUG_ON (ret < 0); 1920 spin_lock(&linear_map_hash_lock); 1921 BUG_ON(linear_map_hash_slots[lmi] & 0x80); 1922 linear_map_hash_slots[lmi] = ret | 0x80; 1923 spin_unlock(&linear_map_hash_lock); 1924 } 1925 1926 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi) 1927 { 1928 unsigned long hash, hidx, slot; 1929 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); 1930 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); 1931 1932 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); 1933 spin_lock(&linear_map_hash_lock); 1934 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80)); 1935 hidx = linear_map_hash_slots[lmi] & 0x7f; 1936 linear_map_hash_slots[lmi] = 0; 1937 spin_unlock(&linear_map_hash_lock); 1938 if (hidx & _PTEIDX_SECONDARY) 1939 hash = ~hash; 1940 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; 1941 slot += hidx & _PTEIDX_GROUP_IX; 1942 mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize, 1943 mmu_linear_psize, 1944 mmu_kernel_ssize, 0); 1945 } 1946 1947 void __kernel_map_pages(struct page *page, int numpages, int enable) 1948 { 1949 unsigned long flags, vaddr, lmi; 1950 int i; 1951 1952 local_irq_save(flags); 1953 for (i = 0; i < numpages; i++, page++) { 1954 vaddr = (unsigned long)page_address(page); 1955 lmi = __pa(vaddr) >> PAGE_SHIFT; 1956 if (lmi >= linear_map_hash_count) 1957 continue; 1958 if (enable) 1959 kernel_map_linear_page(vaddr, lmi); 1960 else 1961 kernel_unmap_linear_page(vaddr, lmi); 1962 } 1963 local_irq_restore(flags); 1964 } 1965 #endif /* CONFIG_DEBUG_PAGEALLOC */ 1966 1967 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base, 1968 phys_addr_t first_memblock_size) 1969 { 1970 /* 1971 * We don't currently support the first MEMBLOCK not mapping 0 1972 * physical on those processors 1973 */ 1974 BUG_ON(first_memblock_base != 0); 1975 1976 /* 1977 * On virtualized systems the first entry is our RMA region aka VRMA, 1978 * non-virtualized 64-bit hash MMU systems don't have a limitation 1979 * on real mode access. 1980 * 1981 * For guests on platforms before POWER9, we clamp the it limit to 1G 1982 * to avoid some funky things such as RTAS bugs etc... 1983 * 1984 * On POWER9 we limit to 1TB in case the host erroneously told us that 1985 * the RMA was >1TB. Effective address bits 0:23 are treated as zero 1986 * (meaning the access is aliased to zero i.e. addr = addr % 1TB) 1987 * for virtual real mode addressing and so it doesn't make sense to 1988 * have an area larger than 1TB as it can't be addressed. 1989 */ 1990 if (!early_cpu_has_feature(CPU_FTR_HVMODE)) { 1991 ppc64_rma_size = first_memblock_size; 1992 if (!early_cpu_has_feature(CPU_FTR_ARCH_300)) 1993 ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000); 1994 else 1995 ppc64_rma_size = min_t(u64, ppc64_rma_size, 1996 1UL << SID_SHIFT_1T); 1997 1998 /* Finally limit subsequent allocations */ 1999 memblock_set_current_limit(ppc64_rma_size); 2000 } else { 2001 ppc64_rma_size = ULONG_MAX; 2002 } 2003 } 2004 2005 #ifdef CONFIG_DEBUG_FS 2006 2007 static int hpt_order_get(void *data, u64 *val) 2008 { 2009 *val = ppc64_pft_size; 2010 return 0; 2011 } 2012 2013 static int hpt_order_set(void *data, u64 val) 2014 { 2015 int ret; 2016 2017 if (!mmu_hash_ops.resize_hpt) 2018 return -ENODEV; 2019 2020 cpus_read_lock(); 2021 ret = mmu_hash_ops.resize_hpt(val); 2022 cpus_read_unlock(); 2023 2024 return ret; 2025 } 2026 2027 DEFINE_DEBUGFS_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n"); 2028 2029 static int __init hash64_debugfs(void) 2030 { 2031 debugfs_create_file("hpt_order", 0600, powerpc_debugfs_root, NULL, 2032 &fops_hpt_order); 2033 return 0; 2034 } 2035 machine_device_initcall(pseries, hash64_debugfs); 2036 #endif /* CONFIG_DEBUG_FS */ 2037 2038 void __init print_system_hash_info(void) 2039 { 2040 pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); 2041 2042 if (htab_hash_mask) 2043 pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask); 2044 } 2045