1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * PowerPC version 4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Adapted for Power Macintosh by Paul Mackerras. 8 * Low-level exception handlers and MMU support 9 * rewritten by Paul Mackerras. 10 * Copyright (C) 1996 Paul Mackerras. 11 * 12 * This file contains low-level assembler routines for managing 13 * the PowerPC MMU hash table. (PPC 8xx processors don't use a 14 * hash table, so this file is not used on them.) 15 */ 16 17#include <linux/pgtable.h> 18#include <linux/init.h> 19#include <asm/reg.h> 20#include <asm/page.h> 21#include <asm/cputable.h> 22#include <asm/ppc_asm.h> 23#include <asm/thread_info.h> 24#include <asm/asm-offsets.h> 25#include <asm/export.h> 26#include <asm/feature-fixups.h> 27#include <asm/code-patching-asm.h> 28 29#ifdef CONFIG_PTE_64BIT 30#define PTE_FLAGS_OFFSET 4 /* offset of PTE flags, in bytes */ 31#else 32#define PTE_FLAGS_OFFSET 0 33#endif 34 35/* 36 * Load a PTE into the hash table, if possible. 37 * The address is in r4, and r3 contains an access flag: 38 * _PAGE_RW (0x400) if a write. 39 * r9 contains the SRR1 value, from which we use the MSR_PR bit. 40 * SPRG_THREAD contains the physical address of the current task's thread. 41 * 42 * Returns to the caller if the access is illegal or there is no 43 * mapping for the address. Otherwise it places an appropriate PTE 44 * in the hash table and returns from the exception. 45 * Uses r0, r3 - r6, r8, r10, ctr, lr. 46 */ 47 .text 48_GLOBAL(hash_page) 49#ifdef CONFIG_SMP 50 lis r8, (mmu_hash_lock - PAGE_OFFSET)@h 51 ori r8, r8, (mmu_hash_lock - PAGE_OFFSET)@l 52 lis r0,0x0fff 53 b 10f 5411: lwz r6,0(r8) 55 cmpwi 0,r6,0 56 bne 11b 5710: lwarx r6,0,r8 58 cmpwi 0,r6,0 59 bne- 11b 60 stwcx. r0,0,r8 61 bne- 10b 62 isync 63#endif 64 /* Get PTE (linux-style) and check access */ 65 lis r0, TASK_SIZE@h /* check if kernel address */ 66 cmplw 0,r4,r0 67 mfspr r8,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ 68 ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */ 69 lwz r5,PGDIR(r8) /* virt page-table root */ 70 blt+ 112f /* assume user more likely */ 71 lis r5,swapper_pg_dir@ha /* if kernel address, use */ 72 addi r5,r5,swapper_pg_dir@l /* kernel page table */ 73 rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */ 74112: tophys(r5, r5) 75#ifndef CONFIG_PTE_64BIT 76 rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */ 77 lwz r8,0(r5) /* get pmd entry */ 78 rlwinm. r8,r8,0,0,19 /* extract address of pte page */ 79#else 80 rlwinm r8,r4,13,19,29 /* Compute pgdir/pmd offset */ 81 lwzx r8,r8,r5 /* Get L1 entry */ 82 rlwinm. r8,r8,0,0,20 /* extract pt base address */ 83#endif 84#ifdef CONFIG_SMP 85 beq- .Lhash_page_out /* return if no mapping */ 86#else 87 /* XXX it seems like the 601 will give a machine fault on the 88 rfi if its alignment is wrong (bottom 4 bits of address are 89 8 or 0xc) and we have had a not-taken conditional branch 90 to the address following the rfi. */ 91 beqlr- 92#endif 93#ifndef CONFIG_PTE_64BIT 94 rlwimi r8,r4,22,20,29 /* insert next 10 bits of address */ 95#else 96 rlwimi r8,r4,23,20,28 /* compute pte address */ 97 /* 98 * If PTE_64BIT is set, the low word is the flags word; use that 99 * word for locking since it contains all the interesting bits. 100 */ 101 addi r8,r8,PTE_FLAGS_OFFSET 102#endif 103 104 /* 105 * Update the linux PTE atomically. We do the lwarx up-front 106 * because almost always, there won't be a permission violation 107 * and there won't already be an HPTE, and thus we will have 108 * to update the PTE to set _PAGE_HASHPTE. -- paulus. 109 */ 110.Lretry: 111 lwarx r6,0,r8 /* get linux-style pte, flag word */ 112#ifdef CONFIG_PPC_KUAP 113 mfsrin r5,r4 114 rlwinm r0,r9,28,_PAGE_RW /* MSR[PR] => _PAGE_RW */ 115 rlwinm r5,r5,12,_PAGE_RW /* Ks => _PAGE_RW */ 116 andc r5,r5,r0 /* Ks & ~MSR[PR] */ 117 andc r5,r6,r5 /* Clear _PAGE_RW when Ks = 1 && MSR[PR] = 0 */ 118 andc. r5,r3,r5 /* check access & ~permission */ 119#else 120 andc. r5,r3,r6 /* check access & ~permission */ 121#endif 122 rlwinm r0,r3,32-3,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */ 123 ori r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE 124#ifdef CONFIG_SMP 125 bne- .Lhash_page_out /* return if access not permitted */ 126#else 127 bnelr- 128#endif 129 or r5,r0,r6 /* set accessed/dirty bits */ 130#ifdef CONFIG_PTE_64BIT 131#ifdef CONFIG_SMP 132 subf r10,r6,r8 /* create false data dependency */ 133 subi r10,r10,PTE_FLAGS_OFFSET 134 lwzx r10,r6,r10 /* Get upper PTE word */ 135#else 136 lwz r10,-PTE_FLAGS_OFFSET(r8) 137#endif /* CONFIG_SMP */ 138#endif /* CONFIG_PTE_64BIT */ 139 stwcx. r5,0,r8 /* attempt to update PTE */ 140 bne- .Lretry /* retry if someone got there first */ 141 142 mfsrin r3,r4 /* get segment reg for segment */ 143#ifndef CONFIG_VMAP_STACK 144 mfctr r0 145 stw r0,_CTR(r11) 146#endif 147 bl create_hpte /* add the hash table entry */ 148 149#ifdef CONFIG_SMP 150 eieio 151 lis r8, (mmu_hash_lock - PAGE_OFFSET)@ha 152 li r0,0 153 stw r0, (mmu_hash_lock - PAGE_OFFSET)@l(r8) 154#endif 155 156#ifdef CONFIG_VMAP_STACK 157 b fast_hash_page_return 158#else 159 /* Return from the exception */ 160 lwz r5,_CTR(r11) 161 mtctr r5 162 lwz r0,GPR0(r11) 163 lwz r8,GPR8(r11) 164 b fast_exception_return 165#endif 166 167#ifdef CONFIG_SMP 168.Lhash_page_out: 169 eieio 170 lis r8, (mmu_hash_lock - PAGE_OFFSET)@ha 171 li r0,0 172 stw r0, (mmu_hash_lock - PAGE_OFFSET)@l(r8) 173 blr 174#endif /* CONFIG_SMP */ 175_ASM_NOKPROBE_SYMBOL(hash_page) 176 177/* 178 * Add an entry for a particular page to the hash table. 179 * 180 * add_hash_page(unsigned context, unsigned long va, unsigned long pmdval) 181 * 182 * We assume any necessary modifications to the pte (e.g. setting 183 * the accessed bit) have already been done and that there is actually 184 * a hash table in use (i.e. we're not on a 603). 185 */ 186_GLOBAL(add_hash_page) 187 mflr r0 188 stw r0,4(r1) 189 190#ifdef CONFIG_SMP 191 lwz r8,TASK_CPU(r2) /* to go in mmu_hash_lock */ 192 oris r8,r8,12 193#endif /* CONFIG_SMP */ 194 195 /* 196 * We disable interrupts here, even on UP, because we don't 197 * want to race with hash_page, and because we want the 198 * _PAGE_HASHPTE bit to be a reliable indication of whether 199 * the HPTE exists (or at least whether one did once). 200 * We also turn off the MMU for data accesses so that we 201 * we can't take a hash table miss (assuming the code is 202 * covered by a BAT). -- paulus 203 */ 204 mfmsr r9 205 rlwinm r0,r9,0,17,15 /* clear bit 16 (MSR_EE) */ 206 rlwinm r0,r0,0,28,26 /* clear MSR_DR */ 207 mtmsr r0 208 isync 209 210#ifdef CONFIG_SMP 211 lis r6, (mmu_hash_lock - PAGE_OFFSET)@ha 212 addi r6, r6, (mmu_hash_lock - PAGE_OFFSET)@l 21310: lwarx r0,0,r6 /* take the mmu_hash_lock */ 214 cmpi 0,r0,0 215 bne- 11f 216 stwcx. r8,0,r6 217 beq+ 12f 21811: lwz r0,0(r6) 219 cmpi 0,r0,0 220 beq 10b 221 b 11b 22212: isync 223#endif 224 225 /* 226 * Fetch the linux pte and test and set _PAGE_HASHPTE atomically. 227 * If _PAGE_HASHPTE was already set, we don't replace the existing 228 * HPTE, so we just unlock and return. 229 */ 230 mr r8,r5 231#ifndef CONFIG_PTE_64BIT 232 rlwimi r8,r4,22,20,29 233#else 234 rlwimi r8,r4,23,20,28 235 addi r8,r8,PTE_FLAGS_OFFSET 236#endif 2371: lwarx r6,0,r8 238 andi. r0,r6,_PAGE_HASHPTE 239 bne 9f /* if HASHPTE already set, done */ 240#ifdef CONFIG_PTE_64BIT 241#ifdef CONFIG_SMP 242 subf r10,r6,r8 /* create false data dependency */ 243 subi r10,r10,PTE_FLAGS_OFFSET 244 lwzx r10,r6,r10 /* Get upper PTE word */ 245#else 246 lwz r10,-PTE_FLAGS_OFFSET(r8) 247#endif /* CONFIG_SMP */ 248#endif /* CONFIG_PTE_64BIT */ 249 ori r5,r6,_PAGE_HASHPTE 250 stwcx. r5,0,r8 251 bne- 1b 252 253 /* Convert context and va to VSID */ 254 mulli r3,r3,897*16 /* multiply context by context skew */ 255 rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */ 256 mulli r0,r0,0x111 /* multiply by ESID skew */ 257 add r3,r3,r0 /* note create_hpte trims to 24 bits */ 258 259 bl create_hpte 260 2619: 262#ifdef CONFIG_SMP 263 lis r6, (mmu_hash_lock - PAGE_OFFSET)@ha 264 addi r6, r6, (mmu_hash_lock - PAGE_OFFSET)@l 265 eieio 266 li r0,0 267 stw r0,0(r6) /* clear mmu_hash_lock */ 268#endif 269 270 /* reenable interrupts and DR */ 271 mtmsr r9 272 isync 273 274 lwz r0,4(r1) 275 mtlr r0 276 blr 277_ASM_NOKPROBE_SYMBOL(add_hash_page) 278 279/* 280 * This routine adds a hardware PTE to the hash table. 281 * It is designed to be called with the MMU either on or off. 282 * r3 contains the VSID, r4 contains the virtual address, 283 * r5 contains the linux PTE, r6 contains the old value of the 284 * linux PTE (before setting _PAGE_HASHPTE). r10 contains the 285 * upper half of the PTE if CONFIG_PTE_64BIT. 286 * On SMP, the caller should have the mmu_hash_lock held. 287 * We assume that the caller has (or will) set the _PAGE_HASHPTE 288 * bit in the linux PTE in memory. The value passed in r6 should 289 * be the old linux PTE value; if it doesn't have _PAGE_HASHPTE set 290 * this routine will skip the search for an existing HPTE. 291 * This procedure modifies r0, r3 - r6, r8, cr0. 292 * -- paulus. 293 * 294 * For speed, 4 of the instructions get patched once the size and 295 * physical address of the hash table are known. These definitions 296 * of Hash_base and Hash_bits below are for the early hash table. 297 */ 298Hash_base = early_hash 299Hash_bits = 12 /* e.g. 256kB hash table */ 300Hash_msk = (((1 << Hash_bits) - 1) * 64) 301 302/* defines for the PTE format for 32-bit PPCs */ 303#define HPTE_SIZE 8 304#define PTEG_SIZE 64 305#define LG_PTEG_SIZE 6 306#define LDPTEu lwzu 307#define LDPTE lwz 308#define STPTE stw 309#define CMPPTE cmpw 310#define PTE_H 0x40 311#define PTE_V 0x80000000 312#define TST_V(r) rlwinm. r,r,0,0,0 313#define SET_V(r) oris r,r,PTE_V@h 314#define CLR_V(r,t) rlwinm r,r,0,1,31 315 316#define HASH_LEFT 31-(LG_PTEG_SIZE+Hash_bits-1) 317#define HASH_RIGHT 31-LG_PTEG_SIZE 318 319__REF 320_GLOBAL(create_hpte) 321 /* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */ 322 rlwinm r8,r5,32-9,30,30 /* _PAGE_RW -> PP msb */ 323 rlwinm r0,r5,32-6,30,30 /* _PAGE_DIRTY -> PP msb */ 324 and r8,r8,r0 /* writable if _RW & _DIRTY */ 325 rlwimi r5,r5,32-1,30,30 /* _PAGE_USER -> PP msb */ 326 rlwimi r5,r5,32-2,31,31 /* _PAGE_USER -> PP lsb */ 327 ori r8,r8,0xe04 /* clear out reserved bits */ 328 andc r8,r5,r8 /* PP = user? (rw&dirty? 1: 3): 0 */ 329BEGIN_FTR_SECTION 330 rlwinm r8,r8,0,~_PAGE_COHERENT /* clear M (coherence not required) */ 331END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT) 332#ifdef CONFIG_PTE_64BIT 333 /* Put the XPN bits into the PTE */ 334 rlwimi r8,r10,8,20,22 335 rlwimi r8,r10,2,29,29 336#endif 337 338 /* Construct the high word of the PPC-style PTE (r5) */ 339 rlwinm r5,r3,7,1,24 /* put VSID in 0x7fffff80 bits */ 340 rlwimi r5,r4,10,26,31 /* put in API (abbrev page index) */ 341 SET_V(r5) /* set V (valid) bit */ 342 343 patch_site 0f, patch__hash_page_A0 344 patch_site 1f, patch__hash_page_A1 345 patch_site 2f, patch__hash_page_A2 346 /* Get the address of the primary PTE group in the hash table (r3) */ 3470: lis r0, (Hash_base - PAGE_OFFSET)@h /* base address of hash table */ 3481: rlwimi r0,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */ 3492: rlwinm r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */ 350 xor r3,r3,r0 /* make primary hash */ 351 li r0,8 /* PTEs/group */ 352 353 /* 354 * Test the _PAGE_HASHPTE bit in the old linux PTE, and skip the search 355 * if it is clear, meaning that the HPTE isn't there already... 356 */ 357 andi. r6,r6,_PAGE_HASHPTE 358 beq+ 10f /* no PTE: go look for an empty slot */ 359 tlbie r4 360 361 /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */ 362 mtctr r0 363 addi r4,r3,-HPTE_SIZE 3641: LDPTEu r6,HPTE_SIZE(r4) /* get next PTE */ 365 CMPPTE 0,r6,r5 366 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ 367 beq+ .Lfound_slot 368 369 patch_site 0f, patch__hash_page_B 370 /* Search the secondary PTEG for a matching PTE */ 371 ori r5,r5,PTE_H /* set H (secondary hash) bit */ 3720: xoris r4,r3,Hash_msk>>16 /* compute secondary hash */ 373 xori r4,r4,(-PTEG_SIZE & 0xffff) 374 addi r4,r4,-HPTE_SIZE 375 mtctr r0 3762: LDPTEu r6,HPTE_SIZE(r4) 377 CMPPTE 0,r6,r5 378 bdnzf 2,2b 379 beq+ .Lfound_slot 380 xori r5,r5,PTE_H /* clear H bit again */ 381 382 /* Search the primary PTEG for an empty slot */ 38310: mtctr r0 384 addi r4,r3,-HPTE_SIZE /* search primary PTEG */ 3851: LDPTEu r6,HPTE_SIZE(r4) /* get next PTE */ 386 TST_V(r6) /* test valid bit */ 387 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ 388 beq+ .Lfound_empty 389 390 patch_site 0f, patch__hash_page_C 391 /* Search the secondary PTEG for an empty slot */ 392 ori r5,r5,PTE_H /* set H (secondary hash) bit */ 3930: xoris r4,r3,Hash_msk>>16 /* compute secondary hash */ 394 xori r4,r4,(-PTEG_SIZE & 0xffff) 395 addi r4,r4,-HPTE_SIZE 396 mtctr r0 3972: LDPTEu r6,HPTE_SIZE(r4) 398 TST_V(r6) 399 bdnzf 2,2b 400 beq+ .Lfound_empty 401 xori r5,r5,PTE_H /* clear H bit again */ 402 403 /* 404 * Choose an arbitrary slot in the primary PTEG to overwrite. 405 * Since both the primary and secondary PTEGs are full, and we 406 * have no information that the PTEs in the primary PTEG are 407 * more important or useful than those in the secondary PTEG, 408 * and we know there is a definite (although small) speed 409 * advantage to putting the PTE in the primary PTEG, we always 410 * put the PTE in the primary PTEG. 411 */ 412 413 lis r4, (next_slot - PAGE_OFFSET)@ha /* get next evict slot */ 414 lwz r6, (next_slot - PAGE_OFFSET)@l(r4) 415 addi r6,r6,HPTE_SIZE /* search for candidate */ 416 andi. r6,r6,7*HPTE_SIZE 417 stw r6,next_slot@l(r4) 418 add r4,r3,r6 419 420#ifndef CONFIG_SMP 421 /* Store PTE in PTEG */ 422.Lfound_empty: 423 STPTE r5,0(r4) 424.Lfound_slot: 425 STPTE r8,HPTE_SIZE/2(r4) 426 427#else /* CONFIG_SMP */ 428/* 429 * Between the tlbie above and updating the hash table entry below, 430 * another CPU could read the hash table entry and put it in its TLB. 431 * There are 3 cases: 432 * 1. using an empty slot 433 * 2. updating an earlier entry to change permissions (i.e. enable write) 434 * 3. taking over the PTE for an unrelated address 435 * 436 * In each case it doesn't really matter if the other CPUs have the old 437 * PTE in their TLB. So we don't need to bother with another tlbie here, 438 * which is convenient as we've overwritten the register that had the 439 * address. :-) The tlbie above is mainly to make sure that this CPU comes 440 * and gets the new PTE from the hash table. 441 * 442 * We do however have to make sure that the PTE is never in an invalid 443 * state with the V bit set. 444 */ 445.Lfound_empty: 446.Lfound_slot: 447 CLR_V(r5,r0) /* clear V (valid) bit in PTE */ 448 STPTE r5,0(r4) 449 sync 450 TLBSYNC 451 STPTE r8,HPTE_SIZE/2(r4) /* put in correct RPN, WIMG, PP bits */ 452 sync 453 SET_V(r5) 454 STPTE r5,0(r4) /* finally set V bit in PTE */ 455#endif /* CONFIG_SMP */ 456 457 sync /* make sure pte updates get to memory */ 458 blr 459 .previous 460_ASM_NOKPROBE_SYMBOL(create_hpte) 461 462 .section .bss 463 .align 2 464next_slot: 465 .space 4 466 .previous 467 468/* 469 * Flush the entry for a particular page from the hash table. 470 * 471 * flush_hash_pages(unsigned context, unsigned long va, unsigned long pmdval, 472 * int count) 473 * 474 * We assume that there is a hash table in use (Hash != 0). 475 */ 476__REF 477_GLOBAL(flush_hash_pages) 478 /* 479 * We disable interrupts here, even on UP, because we want 480 * the _PAGE_HASHPTE bit to be a reliable indication of 481 * whether the HPTE exists (or at least whether one did once). 482 * We also turn off the MMU for data accesses so that we 483 * we can't take a hash table miss (assuming the code is 484 * covered by a BAT). -- paulus 485 */ 486 mfmsr r10 487 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ 488 rlwinm r0,r0,0,28,26 /* clear MSR_DR */ 489 mtmsr r0 490 isync 491 492 /* First find a PTE in the range that has _PAGE_HASHPTE set */ 493#ifndef CONFIG_PTE_64BIT 494 rlwimi r5,r4,22,20,29 495#else 496 rlwimi r5,r4,23,20,28 497 addi r5,r5,PTE_FLAGS_OFFSET 498#endif 4991: lwz r0,0(r5) 500 cmpwi cr1,r6,1 501 andi. r0,r0,_PAGE_HASHPTE 502 bne 2f 503 ble cr1,19f 504 addi r4,r4,0x1000 505 addi r5,r5,PTE_SIZE 506 addi r6,r6,-1 507 b 1b 508 509 /* Convert context and va to VSID */ 5102: mulli r3,r3,897*16 /* multiply context by context skew */ 511 rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */ 512 mulli r0,r0,0x111 /* multiply by ESID skew */ 513 add r3,r3,r0 /* note code below trims to 24 bits */ 514 515 /* Construct the high word of the PPC-style PTE (r11) */ 516 rlwinm r11,r3,7,1,24 /* put VSID in 0x7fffff80 bits */ 517 rlwimi r11,r4,10,26,31 /* put in API (abbrev page index) */ 518 SET_V(r11) /* set V (valid) bit */ 519 520#ifdef CONFIG_SMP 521 lis r9, (mmu_hash_lock - PAGE_OFFSET)@ha 522 addi r9, r9, (mmu_hash_lock - PAGE_OFFSET)@l 523 tophys (r8, r2) 524 lwz r8, TASK_CPU(r8) 525 oris r8,r8,9 52610: lwarx r0,0,r9 527 cmpi 0,r0,0 528 bne- 11f 529 stwcx. r8,0,r9 530 beq+ 12f 53111: lwz r0,0(r9) 532 cmpi 0,r0,0 533 beq 10b 534 b 11b 53512: isync 536#endif 537 538 /* 539 * Check the _PAGE_HASHPTE bit in the linux PTE. If it is 540 * already clear, we're done (for this pte). If not, 541 * clear it (atomically) and proceed. -- paulus. 542 */ 54333: lwarx r8,0,r5 /* fetch the pte flags word */ 544 andi. r0,r8,_PAGE_HASHPTE 545 beq 8f /* done if HASHPTE is already clear */ 546 rlwinm r8,r8,0,31,29 /* clear HASHPTE bit */ 547 stwcx. r8,0,r5 /* update the pte */ 548 bne- 33b 549 550 patch_site 0f, patch__flush_hash_A0 551 patch_site 1f, patch__flush_hash_A1 552 patch_site 2f, patch__flush_hash_A2 553 /* Get the address of the primary PTE group in the hash table (r3) */ 5540: lis r8, (Hash_base - PAGE_OFFSET)@h /* base address of hash table */ 5551: rlwimi r8,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */ 5562: rlwinm r0,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */ 557 xor r8,r0,r8 /* make primary hash */ 558 559 /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */ 560 li r0,8 /* PTEs/group */ 561 mtctr r0 562 addi r12,r8,-HPTE_SIZE 5631: LDPTEu r0,HPTE_SIZE(r12) /* get next PTE */ 564 CMPPTE 0,r0,r11 565 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ 566 beq+ 3f 567 568 patch_site 0f, patch__flush_hash_B 569 /* Search the secondary PTEG for a matching PTE */ 570 ori r11,r11,PTE_H /* set H (secondary hash) bit */ 571 li r0,8 /* PTEs/group */ 5720: xoris r12,r8,Hash_msk>>16 /* compute secondary hash */ 573 xori r12,r12,(-PTEG_SIZE & 0xffff) 574 addi r12,r12,-HPTE_SIZE 575 mtctr r0 5762: LDPTEu r0,HPTE_SIZE(r12) 577 CMPPTE 0,r0,r11 578 bdnzf 2,2b 579 xori r11,r11,PTE_H /* clear H again */ 580 bne- 4f /* should rarely fail to find it */ 581 5823: li r0,0 583 STPTE r0,0(r12) /* invalidate entry */ 5844: sync 585 tlbie r4 /* in hw tlb too */ 586 sync 587 5888: ble cr1,9f /* if all ptes checked */ 58981: addi r6,r6,-1 590 addi r5,r5,PTE_SIZE 591 addi r4,r4,0x1000 592 lwz r0,0(r5) /* check next pte */ 593 cmpwi cr1,r6,1 594 andi. r0,r0,_PAGE_HASHPTE 595 bne 33b 596 bgt cr1,81b 597 5989: 599#ifdef CONFIG_SMP 600 TLBSYNC 601 li r0,0 602 stw r0,0(r9) /* clear mmu_hash_lock */ 603#endif 604 60519: mtmsr r10 606 isync 607 blr 608 .previous 609EXPORT_SYMBOL(flush_hash_pages) 610_ASM_NOKPROBE_SYMBOL(flush_hash_pages) 611