1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * PowerPC version 4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Adapted for Power Macintosh by Paul Mackerras. 8 * Low-level exception handlers and MMU support 9 * rewritten by Paul Mackerras. 10 * Copyright (C) 1996 Paul Mackerras. 11 * 12 * This file contains low-level assembler routines for managing 13 * the PowerPC MMU hash table. (PPC 8xx processors don't use a 14 * hash table, so this file is not used on them.) 15 */ 16 17#include <linux/pgtable.h> 18#include <linux/init.h> 19#include <asm/reg.h> 20#include <asm/page.h> 21#include <asm/cputable.h> 22#include <asm/ppc_asm.h> 23#include <asm/thread_info.h> 24#include <asm/asm-offsets.h> 25#include <asm/export.h> 26#include <asm/feature-fixups.h> 27#include <asm/code-patching-asm.h> 28 29#ifdef CONFIG_PTE_64BIT 30#define PTE_FLAGS_OFFSET 4 /* offset of PTE flags, in bytes */ 31#else 32#define PTE_FLAGS_OFFSET 0 33#endif 34 35/* 36 * Load a PTE into the hash table, if possible. 37 * The address is in r4, and r3 contains an access flag: 38 * _PAGE_RW (0x400) if a write. 39 * r9 contains the SRR1 value, from which we use the MSR_PR bit. 40 * SPRG_THREAD contains the physical address of the current task's thread. 41 * 42 * Returns to the caller if the access is illegal or there is no 43 * mapping for the address. Otherwise it places an appropriate PTE 44 * in the hash table and returns from the exception. 45 * Uses r0, r3 - r6, r8, r10, ctr, lr. 46 */ 47 .text 48_GLOBAL(hash_page) 49#ifdef CONFIG_SMP 50 lis r8, (mmu_hash_lock - PAGE_OFFSET)@h 51 ori r8, r8, (mmu_hash_lock - PAGE_OFFSET)@l 52 lis r0,0x0fff 53 b 10f 5411: lwz r6,0(r8) 55 cmpwi 0,r6,0 56 bne 11b 5710: lwarx r6,0,r8 58 cmpwi 0,r6,0 59 bne- 11b 60 stwcx. r0,0,r8 61 bne- 10b 62 isync 63#endif 64 /* Get PTE (linux-style) and check access */ 65 lis r0, TASK_SIZE@h /* check if kernel address */ 66 cmplw 0,r4,r0 67 mfspr r8,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ 68 ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */ 69 lwz r5,PGDIR(r8) /* virt page-table root */ 70 blt+ 112f /* assume user more likely */ 71 lis r5,swapper_pg_dir@ha /* if kernel address, use */ 72 addi r5,r5,swapper_pg_dir@l /* kernel page table */ 73 rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */ 74112: tophys(r5, r5) 75#ifndef CONFIG_PTE_64BIT 76 rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */ 77 lwz r8,0(r5) /* get pmd entry */ 78 rlwinm. r8,r8,0,0,19 /* extract address of pte page */ 79#else 80 rlwinm r8,r4,13,19,29 /* Compute pgdir/pmd offset */ 81 lwzx r8,r8,r5 /* Get L1 entry */ 82 rlwinm. r8,r8,0,0,20 /* extract pt base address */ 83#endif 84#ifdef CONFIG_SMP 85 beq- .Lhash_page_out /* return if no mapping */ 86#else 87 /* XXX it seems like the 601 will give a machine fault on the 88 rfi if its alignment is wrong (bottom 4 bits of address are 89 8 or 0xc) and we have had a not-taken conditional branch 90 to the address following the rfi. */ 91 beqlr- 92#endif 93#ifndef CONFIG_PTE_64BIT 94 rlwimi r8,r4,22,20,29 /* insert next 10 bits of address */ 95#else 96 rlwimi r8,r4,23,20,28 /* compute pte address */ 97 /* 98 * If PTE_64BIT is set, the low word is the flags word; use that 99 * word for locking since it contains all the interesting bits. 100 */ 101 addi r8,r8,PTE_FLAGS_OFFSET 102#endif 103 104 /* 105 * Update the linux PTE atomically. We do the lwarx up-front 106 * because almost always, there won't be a permission violation 107 * and there won't already be an HPTE, and thus we will have 108 * to update the PTE to set _PAGE_HASHPTE. -- paulus. 109 */ 110.Lretry: 111 lwarx r6,0,r8 /* get linux-style pte, flag word */ 112#ifdef CONFIG_PPC_KUAP 113 mfsrin r5,r4 114 rlwinm r0,r9,28,_PAGE_RW /* MSR[PR] => _PAGE_RW */ 115 rlwinm r5,r5,12,_PAGE_RW /* Ks => _PAGE_RW */ 116 andc r5,r5,r0 /* Ks & ~MSR[PR] */ 117 andc r5,r6,r5 /* Clear _PAGE_RW when Ks = 1 && MSR[PR] = 0 */ 118 andc. r5,r3,r5 /* check access & ~permission */ 119#else 120 andc. r5,r3,r6 /* check access & ~permission */ 121#endif 122 rlwinm r0,r3,32-3,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */ 123 ori r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE 124#ifdef CONFIG_SMP 125 bne- .Lhash_page_out /* return if access not permitted */ 126#else 127 bnelr- 128#endif 129 or r5,r0,r6 /* set accessed/dirty bits */ 130#ifdef CONFIG_PTE_64BIT 131#ifdef CONFIG_SMP 132 subf r10,r6,r8 /* create false data dependency */ 133 subi r10,r10,PTE_FLAGS_OFFSET 134 lwzx r10,r6,r10 /* Get upper PTE word */ 135#else 136 lwz r10,-PTE_FLAGS_OFFSET(r8) 137#endif /* CONFIG_SMP */ 138#endif /* CONFIG_PTE_64BIT */ 139 stwcx. r5,0,r8 /* attempt to update PTE */ 140 bne- .Lretry /* retry if someone got there first */ 141 142 mfsrin r3,r4 /* get segment reg for segment */ 143 bl create_hpte /* add the hash table entry */ 144 145#ifdef CONFIG_SMP 146 eieio 147 lis r8, (mmu_hash_lock - PAGE_OFFSET)@ha 148 li r0,0 149 stw r0, (mmu_hash_lock - PAGE_OFFSET)@l(r8) 150#endif 151 b fast_hash_page_return 152 153#ifdef CONFIG_SMP 154.Lhash_page_out: 155 eieio 156 lis r8, (mmu_hash_lock - PAGE_OFFSET)@ha 157 li r0,0 158 stw r0, (mmu_hash_lock - PAGE_OFFSET)@l(r8) 159 blr 160#endif /* CONFIG_SMP */ 161_ASM_NOKPROBE_SYMBOL(hash_page) 162 163/* 164 * Add an entry for a particular page to the hash table. 165 * 166 * add_hash_page(unsigned context, unsigned long va, unsigned long pmdval) 167 * 168 * We assume any necessary modifications to the pte (e.g. setting 169 * the accessed bit) have already been done and that there is actually 170 * a hash table in use (i.e. we're not on a 603). 171 */ 172_GLOBAL(add_hash_page) 173 mflr r0 174 stw r0,4(r1) 175 176#ifdef CONFIG_SMP 177 lwz r8,TASK_CPU(r2) /* to go in mmu_hash_lock */ 178 oris r8,r8,12 179#endif /* CONFIG_SMP */ 180 181 /* 182 * We disable interrupts here, even on UP, because we don't 183 * want to race with hash_page, and because we want the 184 * _PAGE_HASHPTE bit to be a reliable indication of whether 185 * the HPTE exists (or at least whether one did once). 186 * We also turn off the MMU for data accesses so that we 187 * we can't take a hash table miss (assuming the code is 188 * covered by a BAT). -- paulus 189 */ 190 mfmsr r9 191 rlwinm r0,r9,0,17,15 /* clear bit 16 (MSR_EE) */ 192 rlwinm r0,r0,0,28,26 /* clear MSR_DR */ 193 mtmsr r0 194 isync 195 196#ifdef CONFIG_SMP 197 lis r6, (mmu_hash_lock - PAGE_OFFSET)@ha 198 addi r6, r6, (mmu_hash_lock - PAGE_OFFSET)@l 19910: lwarx r0,0,r6 /* take the mmu_hash_lock */ 200 cmpi 0,r0,0 201 bne- 11f 202 stwcx. r8,0,r6 203 beq+ 12f 20411: lwz r0,0(r6) 205 cmpi 0,r0,0 206 beq 10b 207 b 11b 20812: isync 209#endif 210 211 /* 212 * Fetch the linux pte and test and set _PAGE_HASHPTE atomically. 213 * If _PAGE_HASHPTE was already set, we don't replace the existing 214 * HPTE, so we just unlock and return. 215 */ 216 mr r8,r5 217#ifndef CONFIG_PTE_64BIT 218 rlwimi r8,r4,22,20,29 219#else 220 rlwimi r8,r4,23,20,28 221 addi r8,r8,PTE_FLAGS_OFFSET 222#endif 2231: lwarx r6,0,r8 224 andi. r0,r6,_PAGE_HASHPTE 225 bne 9f /* if HASHPTE already set, done */ 226#ifdef CONFIG_PTE_64BIT 227#ifdef CONFIG_SMP 228 subf r10,r6,r8 /* create false data dependency */ 229 subi r10,r10,PTE_FLAGS_OFFSET 230 lwzx r10,r6,r10 /* Get upper PTE word */ 231#else 232 lwz r10,-PTE_FLAGS_OFFSET(r8) 233#endif /* CONFIG_SMP */ 234#endif /* CONFIG_PTE_64BIT */ 235 ori r5,r6,_PAGE_HASHPTE 236 stwcx. r5,0,r8 237 bne- 1b 238 239 /* Convert context and va to VSID */ 240 mulli r3,r3,897*16 /* multiply context by context skew */ 241 rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */ 242 mulli r0,r0,0x111 /* multiply by ESID skew */ 243 add r3,r3,r0 /* note create_hpte trims to 24 bits */ 244 245 bl create_hpte 246 2479: 248#ifdef CONFIG_SMP 249 lis r6, (mmu_hash_lock - PAGE_OFFSET)@ha 250 addi r6, r6, (mmu_hash_lock - PAGE_OFFSET)@l 251 eieio 252 li r0,0 253 stw r0,0(r6) /* clear mmu_hash_lock */ 254#endif 255 256 /* reenable interrupts and DR */ 257 mtmsr r9 258 isync 259 260 lwz r0,4(r1) 261 mtlr r0 262 blr 263_ASM_NOKPROBE_SYMBOL(add_hash_page) 264 265/* 266 * This routine adds a hardware PTE to the hash table. 267 * It is designed to be called with the MMU either on or off. 268 * r3 contains the VSID, r4 contains the virtual address, 269 * r5 contains the linux PTE, r6 contains the old value of the 270 * linux PTE (before setting _PAGE_HASHPTE). r10 contains the 271 * upper half of the PTE if CONFIG_PTE_64BIT. 272 * On SMP, the caller should have the mmu_hash_lock held. 273 * We assume that the caller has (or will) set the _PAGE_HASHPTE 274 * bit in the linux PTE in memory. The value passed in r6 should 275 * be the old linux PTE value; if it doesn't have _PAGE_HASHPTE set 276 * this routine will skip the search for an existing HPTE. 277 * This procedure modifies r0, r3 - r6, r8, cr0. 278 * -- paulus. 279 * 280 * For speed, 4 of the instructions get patched once the size and 281 * physical address of the hash table are known. These definitions 282 * of Hash_base and Hash_bits below are for the early hash table. 283 */ 284Hash_base = early_hash 285Hash_bits = 12 /* e.g. 256kB hash table */ 286Hash_msk = (((1 << Hash_bits) - 1) * 64) 287 288/* defines for the PTE format for 32-bit PPCs */ 289#define HPTE_SIZE 8 290#define PTEG_SIZE 64 291#define LG_PTEG_SIZE 6 292#define LDPTEu lwzu 293#define LDPTE lwz 294#define STPTE stw 295#define CMPPTE cmpw 296#define PTE_H 0x40 297#define PTE_V 0x80000000 298#define TST_V(r) rlwinm. r,r,0,0,0 299#define SET_V(r) oris r,r,PTE_V@h 300#define CLR_V(r,t) rlwinm r,r,0,1,31 301 302#define HASH_LEFT 31-(LG_PTEG_SIZE+Hash_bits-1) 303#define HASH_RIGHT 31-LG_PTEG_SIZE 304 305__REF 306_GLOBAL(create_hpte) 307 /* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */ 308 rlwinm r8,r5,32-9,30,30 /* _PAGE_RW -> PP msb */ 309 rlwinm r0,r5,32-6,30,30 /* _PAGE_DIRTY -> PP msb */ 310 and r8,r8,r0 /* writable if _RW & _DIRTY */ 311 rlwimi r5,r5,32-1,30,30 /* _PAGE_USER -> PP msb */ 312 rlwimi r5,r5,32-2,31,31 /* _PAGE_USER -> PP lsb */ 313 ori r8,r8,0xe04 /* clear out reserved bits */ 314 andc r8,r5,r8 /* PP = user? (rw&dirty? 1: 3): 0 */ 315BEGIN_FTR_SECTION 316 rlwinm r8,r8,0,~_PAGE_COHERENT /* clear M (coherence not required) */ 317END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT) 318#ifdef CONFIG_PTE_64BIT 319 /* Put the XPN bits into the PTE */ 320 rlwimi r8,r10,8,20,22 321 rlwimi r8,r10,2,29,29 322#endif 323 324 /* Construct the high word of the PPC-style PTE (r5) */ 325 rlwinm r5,r3,7,1,24 /* put VSID in 0x7fffff80 bits */ 326 rlwimi r5,r4,10,26,31 /* put in API (abbrev page index) */ 327 SET_V(r5) /* set V (valid) bit */ 328 329 patch_site 0f, patch__hash_page_A0 330 patch_site 1f, patch__hash_page_A1 331 patch_site 2f, patch__hash_page_A2 332 /* Get the address of the primary PTE group in the hash table (r3) */ 3330: lis r0, (Hash_base - PAGE_OFFSET)@h /* base address of hash table */ 3341: rlwimi r0,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */ 3352: rlwinm r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */ 336 xor r3,r3,r0 /* make primary hash */ 337 li r0,8 /* PTEs/group */ 338 339 /* 340 * Test the _PAGE_HASHPTE bit in the old linux PTE, and skip the search 341 * if it is clear, meaning that the HPTE isn't there already... 342 */ 343 andi. r6,r6,_PAGE_HASHPTE 344 beq+ 10f /* no PTE: go look for an empty slot */ 345 tlbie r4 346 347 /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */ 348 mtctr r0 349 addi r4,r3,-HPTE_SIZE 3501: LDPTEu r6,HPTE_SIZE(r4) /* get next PTE */ 351 CMPPTE 0,r6,r5 352 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ 353 beq+ .Lfound_slot 354 355 patch_site 0f, patch__hash_page_B 356 /* Search the secondary PTEG for a matching PTE */ 357 ori r5,r5,PTE_H /* set H (secondary hash) bit */ 3580: xoris r4,r3,Hash_msk>>16 /* compute secondary hash */ 359 xori r4,r4,(-PTEG_SIZE & 0xffff) 360 addi r4,r4,-HPTE_SIZE 361 mtctr r0 3622: LDPTEu r6,HPTE_SIZE(r4) 363 CMPPTE 0,r6,r5 364 bdnzf 2,2b 365 beq+ .Lfound_slot 366 xori r5,r5,PTE_H /* clear H bit again */ 367 368 /* Search the primary PTEG for an empty slot */ 36910: mtctr r0 370 addi r4,r3,-HPTE_SIZE /* search primary PTEG */ 3711: LDPTEu r6,HPTE_SIZE(r4) /* get next PTE */ 372 TST_V(r6) /* test valid bit */ 373 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ 374 beq+ .Lfound_empty 375 376 patch_site 0f, patch__hash_page_C 377 /* Search the secondary PTEG for an empty slot */ 378 ori r5,r5,PTE_H /* set H (secondary hash) bit */ 3790: xoris r4,r3,Hash_msk>>16 /* compute secondary hash */ 380 xori r4,r4,(-PTEG_SIZE & 0xffff) 381 addi r4,r4,-HPTE_SIZE 382 mtctr r0 3832: LDPTEu r6,HPTE_SIZE(r4) 384 TST_V(r6) 385 bdnzf 2,2b 386 beq+ .Lfound_empty 387 xori r5,r5,PTE_H /* clear H bit again */ 388 389 /* 390 * Choose an arbitrary slot in the primary PTEG to overwrite. 391 * Since both the primary and secondary PTEGs are full, and we 392 * have no information that the PTEs in the primary PTEG are 393 * more important or useful than those in the secondary PTEG, 394 * and we know there is a definite (although small) speed 395 * advantage to putting the PTE in the primary PTEG, we always 396 * put the PTE in the primary PTEG. 397 */ 398 399 lis r4, (next_slot - PAGE_OFFSET)@ha /* get next evict slot */ 400 lwz r6, (next_slot - PAGE_OFFSET)@l(r4) 401 addi r6,r6,HPTE_SIZE /* search for candidate */ 402 andi. r6,r6,7*HPTE_SIZE 403 stw r6,next_slot@l(r4) 404 add r4,r3,r6 405 406#ifndef CONFIG_SMP 407 /* Store PTE in PTEG */ 408.Lfound_empty: 409 STPTE r5,0(r4) 410.Lfound_slot: 411 STPTE r8,HPTE_SIZE/2(r4) 412 413#else /* CONFIG_SMP */ 414/* 415 * Between the tlbie above and updating the hash table entry below, 416 * another CPU could read the hash table entry and put it in its TLB. 417 * There are 3 cases: 418 * 1. using an empty slot 419 * 2. updating an earlier entry to change permissions (i.e. enable write) 420 * 3. taking over the PTE for an unrelated address 421 * 422 * In each case it doesn't really matter if the other CPUs have the old 423 * PTE in their TLB. So we don't need to bother with another tlbie here, 424 * which is convenient as we've overwritten the register that had the 425 * address. :-) The tlbie above is mainly to make sure that this CPU comes 426 * and gets the new PTE from the hash table. 427 * 428 * We do however have to make sure that the PTE is never in an invalid 429 * state with the V bit set. 430 */ 431.Lfound_empty: 432.Lfound_slot: 433 CLR_V(r5,r0) /* clear V (valid) bit in PTE */ 434 STPTE r5,0(r4) 435 sync 436 TLBSYNC 437 STPTE r8,HPTE_SIZE/2(r4) /* put in correct RPN, WIMG, PP bits */ 438 sync 439 SET_V(r5) 440 STPTE r5,0(r4) /* finally set V bit in PTE */ 441#endif /* CONFIG_SMP */ 442 443 sync /* make sure pte updates get to memory */ 444 blr 445 .previous 446_ASM_NOKPROBE_SYMBOL(create_hpte) 447 448 .section .bss 449 .align 2 450next_slot: 451 .space 4 452 .previous 453 454/* 455 * Flush the entry for a particular page from the hash table. 456 * 457 * flush_hash_pages(unsigned context, unsigned long va, unsigned long pmdval, 458 * int count) 459 * 460 * We assume that there is a hash table in use (Hash != 0). 461 */ 462__REF 463_GLOBAL(flush_hash_pages) 464 /* 465 * We disable interrupts here, even on UP, because we want 466 * the _PAGE_HASHPTE bit to be a reliable indication of 467 * whether the HPTE exists (or at least whether one did once). 468 * We also turn off the MMU for data accesses so that we 469 * we can't take a hash table miss (assuming the code is 470 * covered by a BAT). -- paulus 471 */ 472 mfmsr r10 473 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ 474 rlwinm r0,r0,0,28,26 /* clear MSR_DR */ 475 mtmsr r0 476 isync 477 478 /* First find a PTE in the range that has _PAGE_HASHPTE set */ 479#ifndef CONFIG_PTE_64BIT 480 rlwimi r5,r4,22,20,29 481#else 482 rlwimi r5,r4,23,20,28 483 addi r5,r5,PTE_FLAGS_OFFSET 484#endif 4851: lwz r0,0(r5) 486 cmpwi cr1,r6,1 487 andi. r0,r0,_PAGE_HASHPTE 488 bne 2f 489 ble cr1,19f 490 addi r4,r4,0x1000 491 addi r5,r5,PTE_SIZE 492 addi r6,r6,-1 493 b 1b 494 495 /* Convert context and va to VSID */ 4962: mulli r3,r3,897*16 /* multiply context by context skew */ 497 rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */ 498 mulli r0,r0,0x111 /* multiply by ESID skew */ 499 add r3,r3,r0 /* note code below trims to 24 bits */ 500 501 /* Construct the high word of the PPC-style PTE (r11) */ 502 rlwinm r11,r3,7,1,24 /* put VSID in 0x7fffff80 bits */ 503 rlwimi r11,r4,10,26,31 /* put in API (abbrev page index) */ 504 SET_V(r11) /* set V (valid) bit */ 505 506#ifdef CONFIG_SMP 507 lis r9, (mmu_hash_lock - PAGE_OFFSET)@ha 508 addi r9, r9, (mmu_hash_lock - PAGE_OFFSET)@l 509 tophys (r8, r2) 510 lwz r8, TASK_CPU(r8) 511 oris r8,r8,9 51210: lwarx r0,0,r9 513 cmpi 0,r0,0 514 bne- 11f 515 stwcx. r8,0,r9 516 beq+ 12f 51711: lwz r0,0(r9) 518 cmpi 0,r0,0 519 beq 10b 520 b 11b 52112: isync 522#endif 523 524 /* 525 * Check the _PAGE_HASHPTE bit in the linux PTE. If it is 526 * already clear, we're done (for this pte). If not, 527 * clear it (atomically) and proceed. -- paulus. 528 */ 52933: lwarx r8,0,r5 /* fetch the pte flags word */ 530 andi. r0,r8,_PAGE_HASHPTE 531 beq 8f /* done if HASHPTE is already clear */ 532 rlwinm r8,r8,0,31,29 /* clear HASHPTE bit */ 533 stwcx. r8,0,r5 /* update the pte */ 534 bne- 33b 535 536 patch_site 0f, patch__flush_hash_A0 537 patch_site 1f, patch__flush_hash_A1 538 patch_site 2f, patch__flush_hash_A2 539 /* Get the address of the primary PTE group in the hash table (r3) */ 5400: lis r8, (Hash_base - PAGE_OFFSET)@h /* base address of hash table */ 5411: rlwimi r8,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */ 5422: rlwinm r0,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */ 543 xor r8,r0,r8 /* make primary hash */ 544 545 /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */ 546 li r0,8 /* PTEs/group */ 547 mtctr r0 548 addi r12,r8,-HPTE_SIZE 5491: LDPTEu r0,HPTE_SIZE(r12) /* get next PTE */ 550 CMPPTE 0,r0,r11 551 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ 552 beq+ 3f 553 554 patch_site 0f, patch__flush_hash_B 555 /* Search the secondary PTEG for a matching PTE */ 556 ori r11,r11,PTE_H /* set H (secondary hash) bit */ 557 li r0,8 /* PTEs/group */ 5580: xoris r12,r8,Hash_msk>>16 /* compute secondary hash */ 559 xori r12,r12,(-PTEG_SIZE & 0xffff) 560 addi r12,r12,-HPTE_SIZE 561 mtctr r0 5622: LDPTEu r0,HPTE_SIZE(r12) 563 CMPPTE 0,r0,r11 564 bdnzf 2,2b 565 xori r11,r11,PTE_H /* clear H again */ 566 bne- 4f /* should rarely fail to find it */ 567 5683: li r0,0 569 STPTE r0,0(r12) /* invalidate entry */ 5704: sync 571 tlbie r4 /* in hw tlb too */ 572 sync 573 5748: ble cr1,9f /* if all ptes checked */ 57581: addi r6,r6,-1 576 addi r5,r5,PTE_SIZE 577 addi r4,r4,0x1000 578 lwz r0,0(r5) /* check next pte */ 579 cmpwi cr1,r6,1 580 andi. r0,r0,_PAGE_HASHPTE 581 bne 33b 582 bgt cr1,81b 583 5849: 585#ifdef CONFIG_SMP 586 TLBSYNC 587 li r0,0 588 stw r0,0(r9) /* clear mmu_hash_lock */ 589#endif 590 59119: mtmsr r10 592 isync 593 blr 594 .previous 595EXPORT_SYMBOL(flush_hash_pages) 596_ASM_NOKPROBE_SYMBOL(flush_hash_pages) 597