1 /* 2 * Single-step support. 3 * 4 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 #include <linux/kernel.h> 12 #include <linux/kprobes.h> 13 #include <linux/ptrace.h> 14 #include <linux/prefetch.h> 15 #include <asm/sstep.h> 16 #include <asm/processor.h> 17 #include <linux/uaccess.h> 18 #include <asm/cpu_has_feature.h> 19 #include <asm/cputable.h> 20 21 extern char system_call_common[]; 22 23 #ifdef CONFIG_PPC64 24 /* Bits in SRR1 that are copied from MSR */ 25 #define MSR_MASK 0xffffffff87c0ffffUL 26 #else 27 #define MSR_MASK 0x87c0ffff 28 #endif 29 30 /* Bits in XER */ 31 #define XER_SO 0x80000000U 32 #define XER_OV 0x40000000U 33 #define XER_CA 0x20000000U 34 #define XER_OV32 0x00080000U 35 #define XER_CA32 0x00040000U 36 37 #ifdef CONFIG_PPC_FPU 38 /* 39 * Functions in ldstfp.S 40 */ 41 extern void get_fpr(int rn, double *p); 42 extern void put_fpr(int rn, const double *p); 43 extern void get_vr(int rn, __vector128 *p); 44 extern void put_vr(int rn, __vector128 *p); 45 extern void load_vsrn(int vsr, const void *p); 46 extern void store_vsrn(int vsr, void *p); 47 extern void conv_sp_to_dp(const float *sp, double *dp); 48 extern void conv_dp_to_sp(const double *dp, float *sp); 49 #endif 50 51 #ifdef __powerpc64__ 52 /* 53 * Functions in quad.S 54 */ 55 extern int do_lq(unsigned long ea, unsigned long *regs); 56 extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1); 57 extern int do_lqarx(unsigned long ea, unsigned long *regs); 58 extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1, 59 unsigned int *crp); 60 #endif 61 62 #ifdef __LITTLE_ENDIAN__ 63 #define IS_LE 1 64 #define IS_BE 0 65 #else 66 #define IS_LE 0 67 #define IS_BE 1 68 #endif 69 70 /* 71 * Emulate the truncation of 64 bit values in 32-bit mode. 72 */ 73 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr, 74 unsigned long val) 75 { 76 #ifdef __powerpc64__ 77 if ((msr & MSR_64BIT) == 0) 78 val &= 0xffffffffUL; 79 #endif 80 return val; 81 } 82 83 /* 84 * Determine whether a conditional branch instruction would branch. 85 */ 86 static nokprobe_inline int branch_taken(unsigned int instr, 87 const struct pt_regs *regs, 88 struct instruction_op *op) 89 { 90 unsigned int bo = (instr >> 21) & 0x1f; 91 unsigned int bi; 92 93 if ((bo & 4) == 0) { 94 /* decrement counter */ 95 op->type |= DECCTR; 96 if (((bo >> 1) & 1) ^ (regs->ctr == 1)) 97 return 0; 98 } 99 if ((bo & 0x10) == 0) { 100 /* check bit from CR */ 101 bi = (instr >> 16) & 0x1f; 102 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1)) 103 return 0; 104 } 105 return 1; 106 } 107 108 static nokprobe_inline long address_ok(struct pt_regs *regs, 109 unsigned long ea, int nb) 110 { 111 if (!user_mode(regs)) 112 return 1; 113 if (__access_ok(ea, nb, USER_DS)) 114 return 1; 115 if (__access_ok(ea, 1, USER_DS)) 116 /* Access overlaps the end of the user region */ 117 regs->dar = USER_DS.seg; 118 else 119 regs->dar = ea; 120 return 0; 121 } 122 123 /* 124 * Calculate effective address for a D-form instruction 125 */ 126 static nokprobe_inline unsigned long dform_ea(unsigned int instr, 127 const struct pt_regs *regs) 128 { 129 int ra; 130 unsigned long ea; 131 132 ra = (instr >> 16) & 0x1f; 133 ea = (signed short) instr; /* sign-extend */ 134 if (ra) 135 ea += regs->gpr[ra]; 136 137 return ea; 138 } 139 140 #ifdef __powerpc64__ 141 /* 142 * Calculate effective address for a DS-form instruction 143 */ 144 static nokprobe_inline unsigned long dsform_ea(unsigned int instr, 145 const struct pt_regs *regs) 146 { 147 int ra; 148 unsigned long ea; 149 150 ra = (instr >> 16) & 0x1f; 151 ea = (signed short) (instr & ~3); /* sign-extend */ 152 if (ra) 153 ea += regs->gpr[ra]; 154 155 return ea; 156 } 157 158 /* 159 * Calculate effective address for a DQ-form instruction 160 */ 161 static nokprobe_inline unsigned long dqform_ea(unsigned int instr, 162 const struct pt_regs *regs) 163 { 164 int ra; 165 unsigned long ea; 166 167 ra = (instr >> 16) & 0x1f; 168 ea = (signed short) (instr & ~0xf); /* sign-extend */ 169 if (ra) 170 ea += regs->gpr[ra]; 171 172 return ea; 173 } 174 #endif /* __powerpc64 */ 175 176 /* 177 * Calculate effective address for an X-form instruction 178 */ 179 static nokprobe_inline unsigned long xform_ea(unsigned int instr, 180 const struct pt_regs *regs) 181 { 182 int ra, rb; 183 unsigned long ea; 184 185 ra = (instr >> 16) & 0x1f; 186 rb = (instr >> 11) & 0x1f; 187 ea = regs->gpr[rb]; 188 if (ra) 189 ea += regs->gpr[ra]; 190 191 return ea; 192 } 193 194 /* 195 * Return the largest power of 2, not greater than sizeof(unsigned long), 196 * such that x is a multiple of it. 197 */ 198 static nokprobe_inline unsigned long max_align(unsigned long x) 199 { 200 x |= sizeof(unsigned long); 201 return x & -x; /* isolates rightmost bit */ 202 } 203 204 static nokprobe_inline unsigned long byterev_2(unsigned long x) 205 { 206 return ((x >> 8) & 0xff) | ((x & 0xff) << 8); 207 } 208 209 static nokprobe_inline unsigned long byterev_4(unsigned long x) 210 { 211 return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) | 212 ((x & 0xff00) << 8) | ((x & 0xff) << 24); 213 } 214 215 #ifdef __powerpc64__ 216 static nokprobe_inline unsigned long byterev_8(unsigned long x) 217 { 218 return (byterev_4(x) << 32) | byterev_4(x >> 32); 219 } 220 #endif 221 222 static nokprobe_inline void do_byte_reverse(void *ptr, int nb) 223 { 224 switch (nb) { 225 case 2: 226 *(u16 *)ptr = byterev_2(*(u16 *)ptr); 227 break; 228 case 4: 229 *(u32 *)ptr = byterev_4(*(u32 *)ptr); 230 break; 231 #ifdef __powerpc64__ 232 case 8: 233 *(unsigned long *)ptr = byterev_8(*(unsigned long *)ptr); 234 break; 235 case 16: { 236 unsigned long *up = (unsigned long *)ptr; 237 unsigned long tmp; 238 tmp = byterev_8(up[0]); 239 up[0] = byterev_8(up[1]); 240 up[1] = tmp; 241 break; 242 } 243 #endif 244 default: 245 WARN_ON_ONCE(1); 246 } 247 } 248 249 static nokprobe_inline int read_mem_aligned(unsigned long *dest, 250 unsigned long ea, int nb, 251 struct pt_regs *regs) 252 { 253 int err = 0; 254 unsigned long x = 0; 255 256 switch (nb) { 257 case 1: 258 err = __get_user(x, (unsigned char __user *) ea); 259 break; 260 case 2: 261 err = __get_user(x, (unsigned short __user *) ea); 262 break; 263 case 4: 264 err = __get_user(x, (unsigned int __user *) ea); 265 break; 266 #ifdef __powerpc64__ 267 case 8: 268 err = __get_user(x, (unsigned long __user *) ea); 269 break; 270 #endif 271 } 272 if (!err) 273 *dest = x; 274 else 275 regs->dar = ea; 276 return err; 277 } 278 279 /* 280 * Copy from userspace to a buffer, using the largest possible 281 * aligned accesses, up to sizeof(long). 282 */ 283 static nokprobe_inline int copy_mem_in(u8 *dest, unsigned long ea, int nb, 284 struct pt_regs *regs) 285 { 286 int err = 0; 287 int c; 288 289 for (; nb > 0; nb -= c) { 290 c = max_align(ea); 291 if (c > nb) 292 c = max_align(nb); 293 switch (c) { 294 case 1: 295 err = __get_user(*dest, (unsigned char __user *) ea); 296 break; 297 case 2: 298 err = __get_user(*(u16 *)dest, 299 (unsigned short __user *) ea); 300 break; 301 case 4: 302 err = __get_user(*(u32 *)dest, 303 (unsigned int __user *) ea); 304 break; 305 #ifdef __powerpc64__ 306 case 8: 307 err = __get_user(*(unsigned long *)dest, 308 (unsigned long __user *) ea); 309 break; 310 #endif 311 } 312 if (err) { 313 regs->dar = ea; 314 return err; 315 } 316 dest += c; 317 ea += c; 318 } 319 return 0; 320 } 321 322 static nokprobe_inline int read_mem_unaligned(unsigned long *dest, 323 unsigned long ea, int nb, 324 struct pt_regs *regs) 325 { 326 union { 327 unsigned long ul; 328 u8 b[sizeof(unsigned long)]; 329 } u; 330 int i; 331 int err; 332 333 u.ul = 0; 334 i = IS_BE ? sizeof(unsigned long) - nb : 0; 335 err = copy_mem_in(&u.b[i], ea, nb, regs); 336 if (!err) 337 *dest = u.ul; 338 return err; 339 } 340 341 /* 342 * Read memory at address ea for nb bytes, return 0 for success 343 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8. 344 * If nb < sizeof(long), the result is right-justified on BE systems. 345 */ 346 static int read_mem(unsigned long *dest, unsigned long ea, int nb, 347 struct pt_regs *regs) 348 { 349 if (!address_ok(regs, ea, nb)) 350 return -EFAULT; 351 if ((ea & (nb - 1)) == 0) 352 return read_mem_aligned(dest, ea, nb, regs); 353 return read_mem_unaligned(dest, ea, nb, regs); 354 } 355 NOKPROBE_SYMBOL(read_mem); 356 357 static nokprobe_inline int write_mem_aligned(unsigned long val, 358 unsigned long ea, int nb, 359 struct pt_regs *regs) 360 { 361 int err = 0; 362 363 switch (nb) { 364 case 1: 365 err = __put_user(val, (unsigned char __user *) ea); 366 break; 367 case 2: 368 err = __put_user(val, (unsigned short __user *) ea); 369 break; 370 case 4: 371 err = __put_user(val, (unsigned int __user *) ea); 372 break; 373 #ifdef __powerpc64__ 374 case 8: 375 err = __put_user(val, (unsigned long __user *) ea); 376 break; 377 #endif 378 } 379 if (err) 380 regs->dar = ea; 381 return err; 382 } 383 384 /* 385 * Copy from a buffer to userspace, using the largest possible 386 * aligned accesses, up to sizeof(long). 387 */ 388 static nokprobe_inline int copy_mem_out(u8 *dest, unsigned long ea, int nb, 389 struct pt_regs *regs) 390 { 391 int err = 0; 392 int c; 393 394 for (; nb > 0; nb -= c) { 395 c = max_align(ea); 396 if (c > nb) 397 c = max_align(nb); 398 switch (c) { 399 case 1: 400 err = __put_user(*dest, (unsigned char __user *) ea); 401 break; 402 case 2: 403 err = __put_user(*(u16 *)dest, 404 (unsigned short __user *) ea); 405 break; 406 case 4: 407 err = __put_user(*(u32 *)dest, 408 (unsigned int __user *) ea); 409 break; 410 #ifdef __powerpc64__ 411 case 8: 412 err = __put_user(*(unsigned long *)dest, 413 (unsigned long __user *) ea); 414 break; 415 #endif 416 } 417 if (err) { 418 regs->dar = ea; 419 return err; 420 } 421 dest += c; 422 ea += c; 423 } 424 return 0; 425 } 426 427 static nokprobe_inline int write_mem_unaligned(unsigned long val, 428 unsigned long ea, int nb, 429 struct pt_regs *regs) 430 { 431 union { 432 unsigned long ul; 433 u8 b[sizeof(unsigned long)]; 434 } u; 435 int i; 436 437 u.ul = val; 438 i = IS_BE ? sizeof(unsigned long) - nb : 0; 439 return copy_mem_out(&u.b[i], ea, nb, regs); 440 } 441 442 /* 443 * Write memory at address ea for nb bytes, return 0 for success 444 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8. 445 */ 446 static int write_mem(unsigned long val, unsigned long ea, int nb, 447 struct pt_regs *regs) 448 { 449 if (!address_ok(regs, ea, nb)) 450 return -EFAULT; 451 if ((ea & (nb - 1)) == 0) 452 return write_mem_aligned(val, ea, nb, regs); 453 return write_mem_unaligned(val, ea, nb, regs); 454 } 455 NOKPROBE_SYMBOL(write_mem); 456 457 #ifdef CONFIG_PPC_FPU 458 /* 459 * These access either the real FP register or the image in the 460 * thread_struct, depending on regs->msr & MSR_FP. 461 */ 462 static int do_fp_load(struct instruction_op *op, unsigned long ea, 463 struct pt_regs *regs, bool cross_endian) 464 { 465 int err, rn, nb; 466 union { 467 int i; 468 unsigned int u; 469 float f; 470 double d[2]; 471 unsigned long l[2]; 472 u8 b[2 * sizeof(double)]; 473 } u; 474 475 nb = GETSIZE(op->type); 476 if (!address_ok(regs, ea, nb)) 477 return -EFAULT; 478 rn = op->reg; 479 err = copy_mem_in(u.b, ea, nb, regs); 480 if (err) 481 return err; 482 if (unlikely(cross_endian)) { 483 do_byte_reverse(u.b, min(nb, 8)); 484 if (nb == 16) 485 do_byte_reverse(&u.b[8], 8); 486 } 487 preempt_disable(); 488 if (nb == 4) { 489 if (op->type & FPCONV) 490 conv_sp_to_dp(&u.f, &u.d[0]); 491 else if (op->type & SIGNEXT) 492 u.l[0] = u.i; 493 else 494 u.l[0] = u.u; 495 } 496 if (regs->msr & MSR_FP) 497 put_fpr(rn, &u.d[0]); 498 else 499 current->thread.TS_FPR(rn) = u.l[0]; 500 if (nb == 16) { 501 /* lfdp */ 502 rn |= 1; 503 if (regs->msr & MSR_FP) 504 put_fpr(rn, &u.d[1]); 505 else 506 current->thread.TS_FPR(rn) = u.l[1]; 507 } 508 preempt_enable(); 509 return 0; 510 } 511 NOKPROBE_SYMBOL(do_fp_load); 512 513 static int do_fp_store(struct instruction_op *op, unsigned long ea, 514 struct pt_regs *regs, bool cross_endian) 515 { 516 int rn, nb; 517 union { 518 unsigned int u; 519 float f; 520 double d[2]; 521 unsigned long l[2]; 522 u8 b[2 * sizeof(double)]; 523 } u; 524 525 nb = GETSIZE(op->type); 526 if (!address_ok(regs, ea, nb)) 527 return -EFAULT; 528 rn = op->reg; 529 preempt_disable(); 530 if (regs->msr & MSR_FP) 531 get_fpr(rn, &u.d[0]); 532 else 533 u.l[0] = current->thread.TS_FPR(rn); 534 if (nb == 4) { 535 if (op->type & FPCONV) 536 conv_dp_to_sp(&u.d[0], &u.f); 537 else 538 u.u = u.l[0]; 539 } 540 if (nb == 16) { 541 rn |= 1; 542 if (regs->msr & MSR_FP) 543 get_fpr(rn, &u.d[1]); 544 else 545 u.l[1] = current->thread.TS_FPR(rn); 546 } 547 preempt_enable(); 548 if (unlikely(cross_endian)) { 549 do_byte_reverse(u.b, min(nb, 8)); 550 if (nb == 16) 551 do_byte_reverse(&u.b[8], 8); 552 } 553 return copy_mem_out(u.b, ea, nb, regs); 554 } 555 NOKPROBE_SYMBOL(do_fp_store); 556 #endif 557 558 #ifdef CONFIG_ALTIVEC 559 /* For Altivec/VMX, no need to worry about alignment */ 560 static nokprobe_inline int do_vec_load(int rn, unsigned long ea, 561 int size, struct pt_regs *regs, 562 bool cross_endian) 563 { 564 int err; 565 union { 566 __vector128 v; 567 u8 b[sizeof(__vector128)]; 568 } u = {}; 569 570 if (!address_ok(regs, ea & ~0xfUL, 16)) 571 return -EFAULT; 572 /* align to multiple of size */ 573 ea &= ~(size - 1); 574 err = copy_mem_in(&u.b[ea & 0xf], ea, size, regs); 575 if (err) 576 return err; 577 if (unlikely(cross_endian)) 578 do_byte_reverse(&u.b[ea & 0xf], size); 579 preempt_disable(); 580 if (regs->msr & MSR_VEC) 581 put_vr(rn, &u.v); 582 else 583 current->thread.vr_state.vr[rn] = u.v; 584 preempt_enable(); 585 return 0; 586 } 587 588 static nokprobe_inline int do_vec_store(int rn, unsigned long ea, 589 int size, struct pt_regs *regs, 590 bool cross_endian) 591 { 592 union { 593 __vector128 v; 594 u8 b[sizeof(__vector128)]; 595 } u; 596 597 if (!address_ok(regs, ea & ~0xfUL, 16)) 598 return -EFAULT; 599 /* align to multiple of size */ 600 ea &= ~(size - 1); 601 602 preempt_disable(); 603 if (regs->msr & MSR_VEC) 604 get_vr(rn, &u.v); 605 else 606 u.v = current->thread.vr_state.vr[rn]; 607 preempt_enable(); 608 if (unlikely(cross_endian)) 609 do_byte_reverse(&u.b[ea & 0xf], size); 610 return copy_mem_out(&u.b[ea & 0xf], ea, size, regs); 611 } 612 #endif /* CONFIG_ALTIVEC */ 613 614 #ifdef __powerpc64__ 615 static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea, 616 int reg, bool cross_endian) 617 { 618 int err; 619 620 if (!address_ok(regs, ea, 16)) 621 return -EFAULT; 622 /* if aligned, should be atomic */ 623 if ((ea & 0xf) == 0) { 624 err = do_lq(ea, ®s->gpr[reg]); 625 } else { 626 err = read_mem(®s->gpr[reg + IS_LE], ea, 8, regs); 627 if (!err) 628 err = read_mem(®s->gpr[reg + IS_BE], ea + 8, 8, regs); 629 } 630 if (!err && unlikely(cross_endian)) 631 do_byte_reverse(®s->gpr[reg], 16); 632 return err; 633 } 634 635 static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea, 636 int reg, bool cross_endian) 637 { 638 int err; 639 unsigned long vals[2]; 640 641 if (!address_ok(regs, ea, 16)) 642 return -EFAULT; 643 vals[0] = regs->gpr[reg]; 644 vals[1] = regs->gpr[reg + 1]; 645 if (unlikely(cross_endian)) 646 do_byte_reverse(vals, 16); 647 648 /* if aligned, should be atomic */ 649 if ((ea & 0xf) == 0) 650 return do_stq(ea, vals[0], vals[1]); 651 652 err = write_mem(vals[IS_LE], ea, 8, regs); 653 if (!err) 654 err = write_mem(vals[IS_BE], ea + 8, 8, regs); 655 return err; 656 } 657 #endif /* __powerpc64 */ 658 659 #ifdef CONFIG_VSX 660 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg, 661 const void *mem, bool rev) 662 { 663 int size, read_size; 664 int i, j; 665 const unsigned int *wp; 666 const unsigned short *hp; 667 const unsigned char *bp; 668 669 size = GETSIZE(op->type); 670 reg->d[0] = reg->d[1] = 0; 671 672 switch (op->element_size) { 673 case 16: 674 /* whole vector; lxv[x] or lxvl[l] */ 675 if (size == 0) 676 break; 677 memcpy(reg, mem, size); 678 if (IS_LE && (op->vsx_flags & VSX_LDLEFT)) 679 rev = !rev; 680 if (rev) 681 do_byte_reverse(reg, 16); 682 break; 683 case 8: 684 /* scalar loads, lxvd2x, lxvdsx */ 685 read_size = (size >= 8) ? 8 : size; 686 i = IS_LE ? 8 : 8 - read_size; 687 memcpy(®->b[i], mem, read_size); 688 if (rev) 689 do_byte_reverse(®->b[i], 8); 690 if (size < 8) { 691 if (op->type & SIGNEXT) { 692 /* size == 4 is the only case here */ 693 reg->d[IS_LE] = (signed int) reg->d[IS_LE]; 694 } else if (op->vsx_flags & VSX_FPCONV) { 695 preempt_disable(); 696 conv_sp_to_dp(®->fp[1 + IS_LE], 697 ®->dp[IS_LE]); 698 preempt_enable(); 699 } 700 } else { 701 if (size == 16) { 702 unsigned long v = *(unsigned long *)(mem + 8); 703 reg->d[IS_BE] = !rev ? v : byterev_8(v); 704 } else if (op->vsx_flags & VSX_SPLAT) 705 reg->d[IS_BE] = reg->d[IS_LE]; 706 } 707 break; 708 case 4: 709 /* lxvw4x, lxvwsx */ 710 wp = mem; 711 for (j = 0; j < size / 4; ++j) { 712 i = IS_LE ? 3 - j : j; 713 reg->w[i] = !rev ? *wp++ : byterev_4(*wp++); 714 } 715 if (op->vsx_flags & VSX_SPLAT) { 716 u32 val = reg->w[IS_LE ? 3 : 0]; 717 for (; j < 4; ++j) { 718 i = IS_LE ? 3 - j : j; 719 reg->w[i] = val; 720 } 721 } 722 break; 723 case 2: 724 /* lxvh8x */ 725 hp = mem; 726 for (j = 0; j < size / 2; ++j) { 727 i = IS_LE ? 7 - j : j; 728 reg->h[i] = !rev ? *hp++ : byterev_2(*hp++); 729 } 730 break; 731 case 1: 732 /* lxvb16x */ 733 bp = mem; 734 for (j = 0; j < size; ++j) { 735 i = IS_LE ? 15 - j : j; 736 reg->b[i] = *bp++; 737 } 738 break; 739 } 740 } 741 EXPORT_SYMBOL_GPL(emulate_vsx_load); 742 NOKPROBE_SYMBOL(emulate_vsx_load); 743 744 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg, 745 void *mem, bool rev) 746 { 747 int size, write_size; 748 int i, j; 749 union vsx_reg buf; 750 unsigned int *wp; 751 unsigned short *hp; 752 unsigned char *bp; 753 754 size = GETSIZE(op->type); 755 756 switch (op->element_size) { 757 case 16: 758 /* stxv, stxvx, stxvl, stxvll */ 759 if (size == 0) 760 break; 761 if (IS_LE && (op->vsx_flags & VSX_LDLEFT)) 762 rev = !rev; 763 if (rev) { 764 /* reverse 16 bytes */ 765 buf.d[0] = byterev_8(reg->d[1]); 766 buf.d[1] = byterev_8(reg->d[0]); 767 reg = &buf; 768 } 769 memcpy(mem, reg, size); 770 break; 771 case 8: 772 /* scalar stores, stxvd2x */ 773 write_size = (size >= 8) ? 8 : size; 774 i = IS_LE ? 8 : 8 - write_size; 775 if (size < 8 && op->vsx_flags & VSX_FPCONV) { 776 buf.d[0] = buf.d[1] = 0; 777 preempt_disable(); 778 conv_dp_to_sp(®->dp[IS_LE], &buf.fp[1 + IS_LE]); 779 preempt_enable(); 780 reg = &buf; 781 } 782 memcpy(mem, ®->b[i], write_size); 783 if (size == 16) 784 memcpy(mem + 8, ®->d[IS_BE], 8); 785 if (unlikely(rev)) { 786 do_byte_reverse(mem, write_size); 787 if (size == 16) 788 do_byte_reverse(mem + 8, 8); 789 } 790 break; 791 case 4: 792 /* stxvw4x */ 793 wp = mem; 794 for (j = 0; j < size / 4; ++j) { 795 i = IS_LE ? 3 - j : j; 796 *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]); 797 } 798 break; 799 case 2: 800 /* stxvh8x */ 801 hp = mem; 802 for (j = 0; j < size / 2; ++j) { 803 i = IS_LE ? 7 - j : j; 804 *hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]); 805 } 806 break; 807 case 1: 808 /* stvxb16x */ 809 bp = mem; 810 for (j = 0; j < size; ++j) { 811 i = IS_LE ? 15 - j : j; 812 *bp++ = reg->b[i]; 813 } 814 break; 815 } 816 } 817 EXPORT_SYMBOL_GPL(emulate_vsx_store); 818 NOKPROBE_SYMBOL(emulate_vsx_store); 819 820 static nokprobe_inline int do_vsx_load(struct instruction_op *op, 821 unsigned long ea, struct pt_regs *regs, 822 bool cross_endian) 823 { 824 int reg = op->reg; 825 u8 mem[16]; 826 union vsx_reg buf; 827 int size = GETSIZE(op->type); 828 829 if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs)) 830 return -EFAULT; 831 832 emulate_vsx_load(op, &buf, mem, cross_endian); 833 preempt_disable(); 834 if (reg < 32) { 835 /* FP regs + extensions */ 836 if (regs->msr & MSR_FP) { 837 load_vsrn(reg, &buf); 838 } else { 839 current->thread.fp_state.fpr[reg][0] = buf.d[0]; 840 current->thread.fp_state.fpr[reg][1] = buf.d[1]; 841 } 842 } else { 843 if (regs->msr & MSR_VEC) 844 load_vsrn(reg, &buf); 845 else 846 current->thread.vr_state.vr[reg - 32] = buf.v; 847 } 848 preempt_enable(); 849 return 0; 850 } 851 852 static nokprobe_inline int do_vsx_store(struct instruction_op *op, 853 unsigned long ea, struct pt_regs *regs, 854 bool cross_endian) 855 { 856 int reg = op->reg; 857 u8 mem[16]; 858 union vsx_reg buf; 859 int size = GETSIZE(op->type); 860 861 if (!address_ok(regs, ea, size)) 862 return -EFAULT; 863 864 preempt_disable(); 865 if (reg < 32) { 866 /* FP regs + extensions */ 867 if (regs->msr & MSR_FP) { 868 store_vsrn(reg, &buf); 869 } else { 870 buf.d[0] = current->thread.fp_state.fpr[reg][0]; 871 buf.d[1] = current->thread.fp_state.fpr[reg][1]; 872 } 873 } else { 874 if (regs->msr & MSR_VEC) 875 store_vsrn(reg, &buf); 876 else 877 buf.v = current->thread.vr_state.vr[reg - 32]; 878 } 879 preempt_enable(); 880 emulate_vsx_store(op, &buf, mem, cross_endian); 881 return copy_mem_out(mem, ea, size, regs); 882 } 883 #endif /* CONFIG_VSX */ 884 885 int emulate_dcbz(unsigned long ea, struct pt_regs *regs) 886 { 887 int err; 888 unsigned long i, size; 889 890 #ifdef __powerpc64__ 891 size = ppc64_caches.l1d.block_size; 892 if (!(regs->msr & MSR_64BIT)) 893 ea &= 0xffffffffUL; 894 #else 895 size = L1_CACHE_BYTES; 896 #endif 897 ea &= ~(size - 1); 898 if (!address_ok(regs, ea, size)) 899 return -EFAULT; 900 for (i = 0; i < size; i += sizeof(long)) { 901 err = __put_user(0, (unsigned long __user *) (ea + i)); 902 if (err) { 903 regs->dar = ea; 904 return err; 905 } 906 } 907 return 0; 908 } 909 NOKPROBE_SYMBOL(emulate_dcbz); 910 911 #define __put_user_asmx(x, addr, err, op, cr) \ 912 __asm__ __volatile__( \ 913 "1: " op " %2,0,%3\n" \ 914 " mfcr %1\n" \ 915 "2:\n" \ 916 ".section .fixup,\"ax\"\n" \ 917 "3: li %0,%4\n" \ 918 " b 2b\n" \ 919 ".previous\n" \ 920 EX_TABLE(1b, 3b) \ 921 : "=r" (err), "=r" (cr) \ 922 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err)) 923 924 #define __get_user_asmx(x, addr, err, op) \ 925 __asm__ __volatile__( \ 926 "1: "op" %1,0,%2\n" \ 927 "2:\n" \ 928 ".section .fixup,\"ax\"\n" \ 929 "3: li %0,%3\n" \ 930 " b 2b\n" \ 931 ".previous\n" \ 932 EX_TABLE(1b, 3b) \ 933 : "=r" (err), "=r" (x) \ 934 : "r" (addr), "i" (-EFAULT), "0" (err)) 935 936 #define __cacheop_user_asmx(addr, err, op) \ 937 __asm__ __volatile__( \ 938 "1: "op" 0,%1\n" \ 939 "2:\n" \ 940 ".section .fixup,\"ax\"\n" \ 941 "3: li %0,%3\n" \ 942 " b 2b\n" \ 943 ".previous\n" \ 944 EX_TABLE(1b, 3b) \ 945 : "=r" (err) \ 946 : "r" (addr), "i" (-EFAULT), "0" (err)) 947 948 static nokprobe_inline void set_cr0(const struct pt_regs *regs, 949 struct instruction_op *op) 950 { 951 long val = op->val; 952 953 op->type |= SETCC; 954 op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000); 955 #ifdef __powerpc64__ 956 if (!(regs->msr & MSR_64BIT)) 957 val = (int) val; 958 #endif 959 if (val < 0) 960 op->ccval |= 0x80000000; 961 else if (val > 0) 962 op->ccval |= 0x40000000; 963 else 964 op->ccval |= 0x20000000; 965 } 966 967 static nokprobe_inline void set_ca32(struct instruction_op *op, bool val) 968 { 969 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 970 if (val) 971 op->xerval |= XER_CA32; 972 else 973 op->xerval &= ~XER_CA32; 974 } 975 } 976 977 static nokprobe_inline void add_with_carry(const struct pt_regs *regs, 978 struct instruction_op *op, int rd, 979 unsigned long val1, unsigned long val2, 980 unsigned long carry_in) 981 { 982 unsigned long val = val1 + val2; 983 984 if (carry_in) 985 ++val; 986 op->type = COMPUTE + SETREG + SETXER; 987 op->reg = rd; 988 op->val = val; 989 #ifdef __powerpc64__ 990 if (!(regs->msr & MSR_64BIT)) { 991 val = (unsigned int) val; 992 val1 = (unsigned int) val1; 993 } 994 #endif 995 op->xerval = regs->xer; 996 if (val < val1 || (carry_in && val == val1)) 997 op->xerval |= XER_CA; 998 else 999 op->xerval &= ~XER_CA; 1000 1001 set_ca32(op, (unsigned int)val < (unsigned int)val1 || 1002 (carry_in && (unsigned int)val == (unsigned int)val1)); 1003 } 1004 1005 static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs, 1006 struct instruction_op *op, 1007 long v1, long v2, int crfld) 1008 { 1009 unsigned int crval, shift; 1010 1011 op->type = COMPUTE + SETCC; 1012 crval = (regs->xer >> 31) & 1; /* get SO bit */ 1013 if (v1 < v2) 1014 crval |= 8; 1015 else if (v1 > v2) 1016 crval |= 4; 1017 else 1018 crval |= 2; 1019 shift = (7 - crfld) * 4; 1020 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift); 1021 } 1022 1023 static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs, 1024 struct instruction_op *op, 1025 unsigned long v1, 1026 unsigned long v2, int crfld) 1027 { 1028 unsigned int crval, shift; 1029 1030 op->type = COMPUTE + SETCC; 1031 crval = (regs->xer >> 31) & 1; /* get SO bit */ 1032 if (v1 < v2) 1033 crval |= 8; 1034 else if (v1 > v2) 1035 crval |= 4; 1036 else 1037 crval |= 2; 1038 shift = (7 - crfld) * 4; 1039 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift); 1040 } 1041 1042 static nokprobe_inline void do_cmpb(const struct pt_regs *regs, 1043 struct instruction_op *op, 1044 unsigned long v1, unsigned long v2) 1045 { 1046 unsigned long long out_val, mask; 1047 int i; 1048 1049 out_val = 0; 1050 for (i = 0; i < 8; i++) { 1051 mask = 0xffUL << (i * 8); 1052 if ((v1 & mask) == (v2 & mask)) 1053 out_val |= mask; 1054 } 1055 op->val = out_val; 1056 } 1057 1058 /* 1059 * The size parameter is used to adjust the equivalent popcnt instruction. 1060 * popcntb = 8, popcntw = 32, popcntd = 64 1061 */ 1062 static nokprobe_inline void do_popcnt(const struct pt_regs *regs, 1063 struct instruction_op *op, 1064 unsigned long v1, int size) 1065 { 1066 unsigned long long out = v1; 1067 1068 out -= (out >> 1) & 0x5555555555555555ULL; 1069 out = (0x3333333333333333ULL & out) + 1070 (0x3333333333333333ULL & (out >> 2)); 1071 out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0fULL; 1072 1073 if (size == 8) { /* popcntb */ 1074 op->val = out; 1075 return; 1076 } 1077 out += out >> 8; 1078 out += out >> 16; 1079 if (size == 32) { /* popcntw */ 1080 op->val = out & 0x0000003f0000003fULL; 1081 return; 1082 } 1083 1084 out = (out + (out >> 32)) & 0x7f; 1085 op->val = out; /* popcntd */ 1086 } 1087 1088 #ifdef CONFIG_PPC64 1089 static nokprobe_inline void do_bpermd(const struct pt_regs *regs, 1090 struct instruction_op *op, 1091 unsigned long v1, unsigned long v2) 1092 { 1093 unsigned char perm, idx; 1094 unsigned int i; 1095 1096 perm = 0; 1097 for (i = 0; i < 8; i++) { 1098 idx = (v1 >> (i * 8)) & 0xff; 1099 if (idx < 64) 1100 if (v2 & PPC_BIT(idx)) 1101 perm |= 1 << i; 1102 } 1103 op->val = perm; 1104 } 1105 #endif /* CONFIG_PPC64 */ 1106 /* 1107 * The size parameter adjusts the equivalent prty instruction. 1108 * prtyw = 32, prtyd = 64 1109 */ 1110 static nokprobe_inline void do_prty(const struct pt_regs *regs, 1111 struct instruction_op *op, 1112 unsigned long v, int size) 1113 { 1114 unsigned long long res = v ^ (v >> 8); 1115 1116 res ^= res >> 16; 1117 if (size == 32) { /* prtyw */ 1118 op->val = res & 0x0000000100000001ULL; 1119 return; 1120 } 1121 1122 res ^= res >> 32; 1123 op->val = res & 1; /*prtyd */ 1124 } 1125 1126 static nokprobe_inline int trap_compare(long v1, long v2) 1127 { 1128 int ret = 0; 1129 1130 if (v1 < v2) 1131 ret |= 0x10; 1132 else if (v1 > v2) 1133 ret |= 0x08; 1134 else 1135 ret |= 0x04; 1136 if ((unsigned long)v1 < (unsigned long)v2) 1137 ret |= 0x02; 1138 else if ((unsigned long)v1 > (unsigned long)v2) 1139 ret |= 0x01; 1140 return ret; 1141 } 1142 1143 /* 1144 * Elements of 32-bit rotate and mask instructions. 1145 */ 1146 #define MASK32(mb, me) ((0xffffffffUL >> (mb)) + \ 1147 ((signed long)-0x80000000L >> (me)) + ((me) >= (mb))) 1148 #ifdef __powerpc64__ 1149 #define MASK64_L(mb) (~0UL >> (mb)) 1150 #define MASK64_R(me) ((signed long)-0x8000000000000000L >> (me)) 1151 #define MASK64(mb, me) (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb))) 1152 #define DATA32(x) (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32)) 1153 #else 1154 #define DATA32(x) (x) 1155 #endif 1156 #define ROTATE(x, n) ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x)) 1157 1158 /* 1159 * Decode an instruction, and return information about it in *op 1160 * without changing *regs. 1161 * Integer arithmetic and logical instructions, branches, and barrier 1162 * instructions can be emulated just using the information in *op. 1163 * 1164 * Return value is 1 if the instruction can be emulated just by 1165 * updating *regs with the information in *op, -1 if we need the 1166 * GPRs but *regs doesn't contain the full register set, or 0 1167 * otherwise. 1168 */ 1169 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, 1170 unsigned int instr) 1171 { 1172 unsigned int opcode, ra, rb, rd, spr, u; 1173 unsigned long int imm; 1174 unsigned long int val, val2; 1175 unsigned int mb, me, sh; 1176 long ival; 1177 1178 op->type = COMPUTE; 1179 1180 opcode = instr >> 26; 1181 switch (opcode) { 1182 case 16: /* bc */ 1183 op->type = BRANCH; 1184 imm = (signed short)(instr & 0xfffc); 1185 if ((instr & 2) == 0) 1186 imm += regs->nip; 1187 op->val = truncate_if_32bit(regs->msr, imm); 1188 if (instr & 1) 1189 op->type |= SETLK; 1190 if (branch_taken(instr, regs, op)) 1191 op->type |= BRTAKEN; 1192 return 1; 1193 #ifdef CONFIG_PPC64 1194 case 17: /* sc */ 1195 if ((instr & 0xfe2) == 2) 1196 op->type = SYSCALL; 1197 else 1198 op->type = UNKNOWN; 1199 return 0; 1200 #endif 1201 case 18: /* b */ 1202 op->type = BRANCH | BRTAKEN; 1203 imm = instr & 0x03fffffc; 1204 if (imm & 0x02000000) 1205 imm -= 0x04000000; 1206 if ((instr & 2) == 0) 1207 imm += regs->nip; 1208 op->val = truncate_if_32bit(regs->msr, imm); 1209 if (instr & 1) 1210 op->type |= SETLK; 1211 return 1; 1212 case 19: 1213 switch ((instr >> 1) & 0x3ff) { 1214 case 0: /* mcrf */ 1215 op->type = COMPUTE + SETCC; 1216 rd = 7 - ((instr >> 23) & 0x7); 1217 ra = 7 - ((instr >> 18) & 0x7); 1218 rd *= 4; 1219 ra *= 4; 1220 val = (regs->ccr >> ra) & 0xf; 1221 op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd); 1222 return 1; 1223 1224 case 16: /* bclr */ 1225 case 528: /* bcctr */ 1226 op->type = BRANCH; 1227 imm = (instr & 0x400)? regs->ctr: regs->link; 1228 op->val = truncate_if_32bit(regs->msr, imm); 1229 if (instr & 1) 1230 op->type |= SETLK; 1231 if (branch_taken(instr, regs, op)) 1232 op->type |= BRTAKEN; 1233 return 1; 1234 1235 case 18: /* rfid, scary */ 1236 if (regs->msr & MSR_PR) 1237 goto priv; 1238 op->type = RFI; 1239 return 0; 1240 1241 case 150: /* isync */ 1242 op->type = BARRIER | BARRIER_ISYNC; 1243 return 1; 1244 1245 case 33: /* crnor */ 1246 case 129: /* crandc */ 1247 case 193: /* crxor */ 1248 case 225: /* crnand */ 1249 case 257: /* crand */ 1250 case 289: /* creqv */ 1251 case 417: /* crorc */ 1252 case 449: /* cror */ 1253 op->type = COMPUTE + SETCC; 1254 ra = (instr >> 16) & 0x1f; 1255 rb = (instr >> 11) & 0x1f; 1256 rd = (instr >> 21) & 0x1f; 1257 ra = (regs->ccr >> (31 - ra)) & 1; 1258 rb = (regs->ccr >> (31 - rb)) & 1; 1259 val = (instr >> (6 + ra * 2 + rb)) & 1; 1260 op->ccval = (regs->ccr & ~(1UL << (31 - rd))) | 1261 (val << (31 - rd)); 1262 return 1; 1263 } 1264 break; 1265 case 31: 1266 switch ((instr >> 1) & 0x3ff) { 1267 case 598: /* sync */ 1268 op->type = BARRIER + BARRIER_SYNC; 1269 #ifdef __powerpc64__ 1270 switch ((instr >> 21) & 3) { 1271 case 1: /* lwsync */ 1272 op->type = BARRIER + BARRIER_LWSYNC; 1273 break; 1274 case 2: /* ptesync */ 1275 op->type = BARRIER + BARRIER_PTESYNC; 1276 break; 1277 } 1278 #endif 1279 return 1; 1280 1281 case 854: /* eieio */ 1282 op->type = BARRIER + BARRIER_EIEIO; 1283 return 1; 1284 } 1285 break; 1286 } 1287 1288 /* Following cases refer to regs->gpr[], so we need all regs */ 1289 if (!FULL_REGS(regs)) 1290 return -1; 1291 1292 rd = (instr >> 21) & 0x1f; 1293 ra = (instr >> 16) & 0x1f; 1294 rb = (instr >> 11) & 0x1f; 1295 1296 switch (opcode) { 1297 #ifdef __powerpc64__ 1298 case 2: /* tdi */ 1299 if (rd & trap_compare(regs->gpr[ra], (short) instr)) 1300 goto trap; 1301 return 1; 1302 #endif 1303 case 3: /* twi */ 1304 if (rd & trap_compare((int)regs->gpr[ra], (short) instr)) 1305 goto trap; 1306 return 1; 1307 1308 case 7: /* mulli */ 1309 op->val = regs->gpr[ra] * (short) instr; 1310 goto compute_done; 1311 1312 case 8: /* subfic */ 1313 imm = (short) instr; 1314 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1); 1315 return 1; 1316 1317 case 10: /* cmpli */ 1318 imm = (unsigned short) instr; 1319 val = regs->gpr[ra]; 1320 #ifdef __powerpc64__ 1321 if ((rd & 1) == 0) 1322 val = (unsigned int) val; 1323 #endif 1324 do_cmp_unsigned(regs, op, val, imm, rd >> 2); 1325 return 1; 1326 1327 case 11: /* cmpi */ 1328 imm = (short) instr; 1329 val = regs->gpr[ra]; 1330 #ifdef __powerpc64__ 1331 if ((rd & 1) == 0) 1332 val = (int) val; 1333 #endif 1334 do_cmp_signed(regs, op, val, imm, rd >> 2); 1335 return 1; 1336 1337 case 12: /* addic */ 1338 imm = (short) instr; 1339 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0); 1340 return 1; 1341 1342 case 13: /* addic. */ 1343 imm = (short) instr; 1344 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0); 1345 set_cr0(regs, op); 1346 return 1; 1347 1348 case 14: /* addi */ 1349 imm = (short) instr; 1350 if (ra) 1351 imm += regs->gpr[ra]; 1352 op->val = imm; 1353 goto compute_done; 1354 1355 case 15: /* addis */ 1356 imm = ((short) instr) << 16; 1357 if (ra) 1358 imm += regs->gpr[ra]; 1359 op->val = imm; 1360 goto compute_done; 1361 1362 case 19: 1363 if (((instr >> 1) & 0x1f) == 2) { 1364 /* addpcis */ 1365 imm = (short) (instr & 0xffc1); /* d0 + d2 fields */ 1366 imm |= (instr >> 15) & 0x3e; /* d1 field */ 1367 op->val = regs->nip + (imm << 16) + 4; 1368 goto compute_done; 1369 } 1370 op->type = UNKNOWN; 1371 return 0; 1372 1373 case 20: /* rlwimi */ 1374 mb = (instr >> 6) & 0x1f; 1375 me = (instr >> 1) & 0x1f; 1376 val = DATA32(regs->gpr[rd]); 1377 imm = MASK32(mb, me); 1378 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm); 1379 goto logical_done; 1380 1381 case 21: /* rlwinm */ 1382 mb = (instr >> 6) & 0x1f; 1383 me = (instr >> 1) & 0x1f; 1384 val = DATA32(regs->gpr[rd]); 1385 op->val = ROTATE(val, rb) & MASK32(mb, me); 1386 goto logical_done; 1387 1388 case 23: /* rlwnm */ 1389 mb = (instr >> 6) & 0x1f; 1390 me = (instr >> 1) & 0x1f; 1391 rb = regs->gpr[rb] & 0x1f; 1392 val = DATA32(regs->gpr[rd]); 1393 op->val = ROTATE(val, rb) & MASK32(mb, me); 1394 goto logical_done; 1395 1396 case 24: /* ori */ 1397 op->val = regs->gpr[rd] | (unsigned short) instr; 1398 goto logical_done_nocc; 1399 1400 case 25: /* oris */ 1401 imm = (unsigned short) instr; 1402 op->val = regs->gpr[rd] | (imm << 16); 1403 goto logical_done_nocc; 1404 1405 case 26: /* xori */ 1406 op->val = regs->gpr[rd] ^ (unsigned short) instr; 1407 goto logical_done_nocc; 1408 1409 case 27: /* xoris */ 1410 imm = (unsigned short) instr; 1411 op->val = regs->gpr[rd] ^ (imm << 16); 1412 goto logical_done_nocc; 1413 1414 case 28: /* andi. */ 1415 op->val = regs->gpr[rd] & (unsigned short) instr; 1416 set_cr0(regs, op); 1417 goto logical_done_nocc; 1418 1419 case 29: /* andis. */ 1420 imm = (unsigned short) instr; 1421 op->val = regs->gpr[rd] & (imm << 16); 1422 set_cr0(regs, op); 1423 goto logical_done_nocc; 1424 1425 #ifdef __powerpc64__ 1426 case 30: /* rld* */ 1427 mb = ((instr >> 6) & 0x1f) | (instr & 0x20); 1428 val = regs->gpr[rd]; 1429 if ((instr & 0x10) == 0) { 1430 sh = rb | ((instr & 2) << 4); 1431 val = ROTATE(val, sh); 1432 switch ((instr >> 2) & 3) { 1433 case 0: /* rldicl */ 1434 val &= MASK64_L(mb); 1435 break; 1436 case 1: /* rldicr */ 1437 val &= MASK64_R(mb); 1438 break; 1439 case 2: /* rldic */ 1440 val &= MASK64(mb, 63 - sh); 1441 break; 1442 case 3: /* rldimi */ 1443 imm = MASK64(mb, 63 - sh); 1444 val = (regs->gpr[ra] & ~imm) | 1445 (val & imm); 1446 } 1447 op->val = val; 1448 goto logical_done; 1449 } else { 1450 sh = regs->gpr[rb] & 0x3f; 1451 val = ROTATE(val, sh); 1452 switch ((instr >> 1) & 7) { 1453 case 0: /* rldcl */ 1454 op->val = val & MASK64_L(mb); 1455 goto logical_done; 1456 case 1: /* rldcr */ 1457 op->val = val & MASK64_R(mb); 1458 goto logical_done; 1459 } 1460 } 1461 #endif 1462 op->type = UNKNOWN; /* illegal instruction */ 1463 return 0; 1464 1465 case 31: 1466 /* isel occupies 32 minor opcodes */ 1467 if (((instr >> 1) & 0x1f) == 15) { 1468 mb = (instr >> 6) & 0x1f; /* bc field */ 1469 val = (regs->ccr >> (31 - mb)) & 1; 1470 val2 = (ra) ? regs->gpr[ra] : 0; 1471 1472 op->val = (val) ? val2 : regs->gpr[rb]; 1473 goto compute_done; 1474 } 1475 1476 switch ((instr >> 1) & 0x3ff) { 1477 case 4: /* tw */ 1478 if (rd == 0x1f || 1479 (rd & trap_compare((int)regs->gpr[ra], 1480 (int)regs->gpr[rb]))) 1481 goto trap; 1482 return 1; 1483 #ifdef __powerpc64__ 1484 case 68: /* td */ 1485 if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb])) 1486 goto trap; 1487 return 1; 1488 #endif 1489 case 83: /* mfmsr */ 1490 if (regs->msr & MSR_PR) 1491 goto priv; 1492 op->type = MFMSR; 1493 op->reg = rd; 1494 return 0; 1495 case 146: /* mtmsr */ 1496 if (regs->msr & MSR_PR) 1497 goto priv; 1498 op->type = MTMSR; 1499 op->reg = rd; 1500 op->val = 0xffffffff & ~(MSR_ME | MSR_LE); 1501 return 0; 1502 #ifdef CONFIG_PPC64 1503 case 178: /* mtmsrd */ 1504 if (regs->msr & MSR_PR) 1505 goto priv; 1506 op->type = MTMSR; 1507 op->reg = rd; 1508 /* only MSR_EE and MSR_RI get changed if bit 15 set */ 1509 /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */ 1510 imm = (instr & 0x10000)? 0x8002: 0xefffffffffffeffeUL; 1511 op->val = imm; 1512 return 0; 1513 #endif 1514 1515 case 19: /* mfcr */ 1516 imm = 0xffffffffUL; 1517 if ((instr >> 20) & 1) { 1518 imm = 0xf0000000UL; 1519 for (sh = 0; sh < 8; ++sh) { 1520 if (instr & (0x80000 >> sh)) 1521 break; 1522 imm >>= 4; 1523 } 1524 } 1525 op->val = regs->ccr & imm; 1526 goto compute_done; 1527 1528 case 144: /* mtcrf */ 1529 op->type = COMPUTE + SETCC; 1530 imm = 0xf0000000UL; 1531 val = regs->gpr[rd]; 1532 op->ccval = regs->ccr; 1533 for (sh = 0; sh < 8; ++sh) { 1534 if (instr & (0x80000 >> sh)) 1535 op->ccval = (op->ccval & ~imm) | 1536 (val & imm); 1537 imm >>= 4; 1538 } 1539 return 1; 1540 1541 case 339: /* mfspr */ 1542 spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0); 1543 op->type = MFSPR; 1544 op->reg = rd; 1545 op->spr = spr; 1546 if (spr == SPRN_XER || spr == SPRN_LR || 1547 spr == SPRN_CTR) 1548 return 1; 1549 return 0; 1550 1551 case 467: /* mtspr */ 1552 spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0); 1553 op->type = MTSPR; 1554 op->val = regs->gpr[rd]; 1555 op->spr = spr; 1556 if (spr == SPRN_XER || spr == SPRN_LR || 1557 spr == SPRN_CTR) 1558 return 1; 1559 return 0; 1560 1561 /* 1562 * Compare instructions 1563 */ 1564 case 0: /* cmp */ 1565 val = regs->gpr[ra]; 1566 val2 = regs->gpr[rb]; 1567 #ifdef __powerpc64__ 1568 if ((rd & 1) == 0) { 1569 /* word (32-bit) compare */ 1570 val = (int) val; 1571 val2 = (int) val2; 1572 } 1573 #endif 1574 do_cmp_signed(regs, op, val, val2, rd >> 2); 1575 return 1; 1576 1577 case 32: /* cmpl */ 1578 val = regs->gpr[ra]; 1579 val2 = regs->gpr[rb]; 1580 #ifdef __powerpc64__ 1581 if ((rd & 1) == 0) { 1582 /* word (32-bit) compare */ 1583 val = (unsigned int) val; 1584 val2 = (unsigned int) val2; 1585 } 1586 #endif 1587 do_cmp_unsigned(regs, op, val, val2, rd >> 2); 1588 return 1; 1589 1590 case 508: /* cmpb */ 1591 do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]); 1592 goto logical_done_nocc; 1593 1594 /* 1595 * Arithmetic instructions 1596 */ 1597 case 8: /* subfc */ 1598 add_with_carry(regs, op, rd, ~regs->gpr[ra], 1599 regs->gpr[rb], 1); 1600 goto arith_done; 1601 #ifdef __powerpc64__ 1602 case 9: /* mulhdu */ 1603 asm("mulhdu %0,%1,%2" : "=r" (op->val) : 1604 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); 1605 goto arith_done; 1606 #endif 1607 case 10: /* addc */ 1608 add_with_carry(regs, op, rd, regs->gpr[ra], 1609 regs->gpr[rb], 0); 1610 goto arith_done; 1611 1612 case 11: /* mulhwu */ 1613 asm("mulhwu %0,%1,%2" : "=r" (op->val) : 1614 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); 1615 goto arith_done; 1616 1617 case 40: /* subf */ 1618 op->val = regs->gpr[rb] - regs->gpr[ra]; 1619 goto arith_done; 1620 #ifdef __powerpc64__ 1621 case 73: /* mulhd */ 1622 asm("mulhd %0,%1,%2" : "=r" (op->val) : 1623 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); 1624 goto arith_done; 1625 #endif 1626 case 75: /* mulhw */ 1627 asm("mulhw %0,%1,%2" : "=r" (op->val) : 1628 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); 1629 goto arith_done; 1630 1631 case 104: /* neg */ 1632 op->val = -regs->gpr[ra]; 1633 goto arith_done; 1634 1635 case 136: /* subfe */ 1636 add_with_carry(regs, op, rd, ~regs->gpr[ra], 1637 regs->gpr[rb], regs->xer & XER_CA); 1638 goto arith_done; 1639 1640 case 138: /* adde */ 1641 add_with_carry(regs, op, rd, regs->gpr[ra], 1642 regs->gpr[rb], regs->xer & XER_CA); 1643 goto arith_done; 1644 1645 case 200: /* subfze */ 1646 add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L, 1647 regs->xer & XER_CA); 1648 goto arith_done; 1649 1650 case 202: /* addze */ 1651 add_with_carry(regs, op, rd, regs->gpr[ra], 0L, 1652 regs->xer & XER_CA); 1653 goto arith_done; 1654 1655 case 232: /* subfme */ 1656 add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L, 1657 regs->xer & XER_CA); 1658 goto arith_done; 1659 #ifdef __powerpc64__ 1660 case 233: /* mulld */ 1661 op->val = regs->gpr[ra] * regs->gpr[rb]; 1662 goto arith_done; 1663 #endif 1664 case 234: /* addme */ 1665 add_with_carry(regs, op, rd, regs->gpr[ra], -1L, 1666 regs->xer & XER_CA); 1667 goto arith_done; 1668 1669 case 235: /* mullw */ 1670 op->val = (long)(int) regs->gpr[ra] * 1671 (int) regs->gpr[rb]; 1672 1673 goto arith_done; 1674 1675 case 266: /* add */ 1676 op->val = regs->gpr[ra] + regs->gpr[rb]; 1677 goto arith_done; 1678 #ifdef __powerpc64__ 1679 case 457: /* divdu */ 1680 op->val = regs->gpr[ra] / regs->gpr[rb]; 1681 goto arith_done; 1682 #endif 1683 case 459: /* divwu */ 1684 op->val = (unsigned int) regs->gpr[ra] / 1685 (unsigned int) regs->gpr[rb]; 1686 goto arith_done; 1687 #ifdef __powerpc64__ 1688 case 489: /* divd */ 1689 op->val = (long int) regs->gpr[ra] / 1690 (long int) regs->gpr[rb]; 1691 goto arith_done; 1692 #endif 1693 case 491: /* divw */ 1694 op->val = (int) regs->gpr[ra] / 1695 (int) regs->gpr[rb]; 1696 goto arith_done; 1697 1698 1699 /* 1700 * Logical instructions 1701 */ 1702 case 26: /* cntlzw */ 1703 val = (unsigned int) regs->gpr[rd]; 1704 op->val = ( val ? __builtin_clz(val) : 32 ); 1705 goto logical_done; 1706 #ifdef __powerpc64__ 1707 case 58: /* cntlzd */ 1708 val = regs->gpr[rd]; 1709 op->val = ( val ? __builtin_clzl(val) : 64 ); 1710 goto logical_done; 1711 #endif 1712 case 28: /* and */ 1713 op->val = regs->gpr[rd] & regs->gpr[rb]; 1714 goto logical_done; 1715 1716 case 60: /* andc */ 1717 op->val = regs->gpr[rd] & ~regs->gpr[rb]; 1718 goto logical_done; 1719 1720 case 122: /* popcntb */ 1721 do_popcnt(regs, op, regs->gpr[rd], 8); 1722 goto logical_done_nocc; 1723 1724 case 124: /* nor */ 1725 op->val = ~(regs->gpr[rd] | regs->gpr[rb]); 1726 goto logical_done; 1727 1728 case 154: /* prtyw */ 1729 do_prty(regs, op, regs->gpr[rd], 32); 1730 goto logical_done_nocc; 1731 1732 case 186: /* prtyd */ 1733 do_prty(regs, op, regs->gpr[rd], 64); 1734 goto logical_done_nocc; 1735 #ifdef CONFIG_PPC64 1736 case 252: /* bpermd */ 1737 do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]); 1738 goto logical_done_nocc; 1739 #endif 1740 case 284: /* xor */ 1741 op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]); 1742 goto logical_done; 1743 1744 case 316: /* xor */ 1745 op->val = regs->gpr[rd] ^ regs->gpr[rb]; 1746 goto logical_done; 1747 1748 case 378: /* popcntw */ 1749 do_popcnt(regs, op, regs->gpr[rd], 32); 1750 goto logical_done_nocc; 1751 1752 case 412: /* orc */ 1753 op->val = regs->gpr[rd] | ~regs->gpr[rb]; 1754 goto logical_done; 1755 1756 case 444: /* or */ 1757 op->val = regs->gpr[rd] | regs->gpr[rb]; 1758 goto logical_done; 1759 1760 case 476: /* nand */ 1761 op->val = ~(regs->gpr[rd] & regs->gpr[rb]); 1762 goto logical_done; 1763 #ifdef CONFIG_PPC64 1764 case 506: /* popcntd */ 1765 do_popcnt(regs, op, regs->gpr[rd], 64); 1766 goto logical_done_nocc; 1767 #endif 1768 case 922: /* extsh */ 1769 op->val = (signed short) regs->gpr[rd]; 1770 goto logical_done; 1771 1772 case 954: /* extsb */ 1773 op->val = (signed char) regs->gpr[rd]; 1774 goto logical_done; 1775 #ifdef __powerpc64__ 1776 case 986: /* extsw */ 1777 op->val = (signed int) regs->gpr[rd]; 1778 goto logical_done; 1779 #endif 1780 1781 /* 1782 * Shift instructions 1783 */ 1784 case 24: /* slw */ 1785 sh = regs->gpr[rb] & 0x3f; 1786 if (sh < 32) 1787 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL; 1788 else 1789 op->val = 0; 1790 goto logical_done; 1791 1792 case 536: /* srw */ 1793 sh = regs->gpr[rb] & 0x3f; 1794 if (sh < 32) 1795 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh; 1796 else 1797 op->val = 0; 1798 goto logical_done; 1799 1800 case 792: /* sraw */ 1801 op->type = COMPUTE + SETREG + SETXER; 1802 sh = regs->gpr[rb] & 0x3f; 1803 ival = (signed int) regs->gpr[rd]; 1804 op->val = ival >> (sh < 32 ? sh : 31); 1805 op->xerval = regs->xer; 1806 if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0)) 1807 op->xerval |= XER_CA; 1808 else 1809 op->xerval &= ~XER_CA; 1810 set_ca32(op, op->xerval & XER_CA); 1811 goto logical_done; 1812 1813 case 824: /* srawi */ 1814 op->type = COMPUTE + SETREG + SETXER; 1815 sh = rb; 1816 ival = (signed int) regs->gpr[rd]; 1817 op->val = ival >> sh; 1818 op->xerval = regs->xer; 1819 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0) 1820 op->xerval |= XER_CA; 1821 else 1822 op->xerval &= ~XER_CA; 1823 set_ca32(op, op->xerval & XER_CA); 1824 goto logical_done; 1825 1826 #ifdef __powerpc64__ 1827 case 27: /* sld */ 1828 sh = regs->gpr[rb] & 0x7f; 1829 if (sh < 64) 1830 op->val = regs->gpr[rd] << sh; 1831 else 1832 op->val = 0; 1833 goto logical_done; 1834 1835 case 539: /* srd */ 1836 sh = regs->gpr[rb] & 0x7f; 1837 if (sh < 64) 1838 op->val = regs->gpr[rd] >> sh; 1839 else 1840 op->val = 0; 1841 goto logical_done; 1842 1843 case 794: /* srad */ 1844 op->type = COMPUTE + SETREG + SETXER; 1845 sh = regs->gpr[rb] & 0x7f; 1846 ival = (signed long int) regs->gpr[rd]; 1847 op->val = ival >> (sh < 64 ? sh : 63); 1848 op->xerval = regs->xer; 1849 if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0)) 1850 op->xerval |= XER_CA; 1851 else 1852 op->xerval &= ~XER_CA; 1853 set_ca32(op, op->xerval & XER_CA); 1854 goto logical_done; 1855 1856 case 826: /* sradi with sh_5 = 0 */ 1857 case 827: /* sradi with sh_5 = 1 */ 1858 op->type = COMPUTE + SETREG + SETXER; 1859 sh = rb | ((instr & 2) << 4); 1860 ival = (signed long int) regs->gpr[rd]; 1861 op->val = ival >> sh; 1862 op->xerval = regs->xer; 1863 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0) 1864 op->xerval |= XER_CA; 1865 else 1866 op->xerval &= ~XER_CA; 1867 set_ca32(op, op->xerval & XER_CA); 1868 goto logical_done; 1869 #endif /* __powerpc64__ */ 1870 1871 /* 1872 * Cache instructions 1873 */ 1874 case 54: /* dcbst */ 1875 op->type = MKOP(CACHEOP, DCBST, 0); 1876 op->ea = xform_ea(instr, regs); 1877 return 0; 1878 1879 case 86: /* dcbf */ 1880 op->type = MKOP(CACHEOP, DCBF, 0); 1881 op->ea = xform_ea(instr, regs); 1882 return 0; 1883 1884 case 246: /* dcbtst */ 1885 op->type = MKOP(CACHEOP, DCBTST, 0); 1886 op->ea = xform_ea(instr, regs); 1887 op->reg = rd; 1888 return 0; 1889 1890 case 278: /* dcbt */ 1891 op->type = MKOP(CACHEOP, DCBTST, 0); 1892 op->ea = xform_ea(instr, regs); 1893 op->reg = rd; 1894 return 0; 1895 1896 case 982: /* icbi */ 1897 op->type = MKOP(CACHEOP, ICBI, 0); 1898 op->ea = xform_ea(instr, regs); 1899 return 0; 1900 1901 case 1014: /* dcbz */ 1902 op->type = MKOP(CACHEOP, DCBZ, 0); 1903 op->ea = xform_ea(instr, regs); 1904 return 0; 1905 } 1906 break; 1907 } 1908 1909 /* 1910 * Loads and stores. 1911 */ 1912 op->type = UNKNOWN; 1913 op->update_reg = ra; 1914 op->reg = rd; 1915 op->val = regs->gpr[rd]; 1916 u = (instr >> 20) & UPDATE; 1917 op->vsx_flags = 0; 1918 1919 switch (opcode) { 1920 case 31: 1921 u = instr & UPDATE; 1922 op->ea = xform_ea(instr, regs); 1923 switch ((instr >> 1) & 0x3ff) { 1924 case 20: /* lwarx */ 1925 op->type = MKOP(LARX, 0, 4); 1926 break; 1927 1928 case 150: /* stwcx. */ 1929 op->type = MKOP(STCX, 0, 4); 1930 break; 1931 1932 #ifdef __powerpc64__ 1933 case 84: /* ldarx */ 1934 op->type = MKOP(LARX, 0, 8); 1935 break; 1936 1937 case 214: /* stdcx. */ 1938 op->type = MKOP(STCX, 0, 8); 1939 break; 1940 1941 case 52: /* lbarx */ 1942 op->type = MKOP(LARX, 0, 1); 1943 break; 1944 1945 case 694: /* stbcx. */ 1946 op->type = MKOP(STCX, 0, 1); 1947 break; 1948 1949 case 116: /* lharx */ 1950 op->type = MKOP(LARX, 0, 2); 1951 break; 1952 1953 case 726: /* sthcx. */ 1954 op->type = MKOP(STCX, 0, 2); 1955 break; 1956 1957 case 276: /* lqarx */ 1958 if (!((rd & 1) || rd == ra || rd == rb)) 1959 op->type = MKOP(LARX, 0, 16); 1960 break; 1961 1962 case 182: /* stqcx. */ 1963 if (!(rd & 1)) 1964 op->type = MKOP(STCX, 0, 16); 1965 break; 1966 #endif 1967 1968 case 23: /* lwzx */ 1969 case 55: /* lwzux */ 1970 op->type = MKOP(LOAD, u, 4); 1971 break; 1972 1973 case 87: /* lbzx */ 1974 case 119: /* lbzux */ 1975 op->type = MKOP(LOAD, u, 1); 1976 break; 1977 1978 #ifdef CONFIG_ALTIVEC 1979 /* 1980 * Note: for the load/store vector element instructions, 1981 * bits of the EA say which field of the VMX register to use. 1982 */ 1983 case 7: /* lvebx */ 1984 op->type = MKOP(LOAD_VMX, 0, 1); 1985 op->element_size = 1; 1986 break; 1987 1988 case 39: /* lvehx */ 1989 op->type = MKOP(LOAD_VMX, 0, 2); 1990 op->element_size = 2; 1991 break; 1992 1993 case 71: /* lvewx */ 1994 op->type = MKOP(LOAD_VMX, 0, 4); 1995 op->element_size = 4; 1996 break; 1997 1998 case 103: /* lvx */ 1999 case 359: /* lvxl */ 2000 op->type = MKOP(LOAD_VMX, 0, 16); 2001 op->element_size = 16; 2002 break; 2003 2004 case 135: /* stvebx */ 2005 op->type = MKOP(STORE_VMX, 0, 1); 2006 op->element_size = 1; 2007 break; 2008 2009 case 167: /* stvehx */ 2010 op->type = MKOP(STORE_VMX, 0, 2); 2011 op->element_size = 2; 2012 break; 2013 2014 case 199: /* stvewx */ 2015 op->type = MKOP(STORE_VMX, 0, 4); 2016 op->element_size = 4; 2017 break; 2018 2019 case 231: /* stvx */ 2020 case 487: /* stvxl */ 2021 op->type = MKOP(STORE_VMX, 0, 16); 2022 break; 2023 #endif /* CONFIG_ALTIVEC */ 2024 2025 #ifdef __powerpc64__ 2026 case 21: /* ldx */ 2027 case 53: /* ldux */ 2028 op->type = MKOP(LOAD, u, 8); 2029 break; 2030 2031 case 149: /* stdx */ 2032 case 181: /* stdux */ 2033 op->type = MKOP(STORE, u, 8); 2034 break; 2035 #endif 2036 2037 case 151: /* stwx */ 2038 case 183: /* stwux */ 2039 op->type = MKOP(STORE, u, 4); 2040 break; 2041 2042 case 215: /* stbx */ 2043 case 247: /* stbux */ 2044 op->type = MKOP(STORE, u, 1); 2045 break; 2046 2047 case 279: /* lhzx */ 2048 case 311: /* lhzux */ 2049 op->type = MKOP(LOAD, u, 2); 2050 break; 2051 2052 #ifdef __powerpc64__ 2053 case 341: /* lwax */ 2054 case 373: /* lwaux */ 2055 op->type = MKOP(LOAD, SIGNEXT | u, 4); 2056 break; 2057 #endif 2058 2059 case 343: /* lhax */ 2060 case 375: /* lhaux */ 2061 op->type = MKOP(LOAD, SIGNEXT | u, 2); 2062 break; 2063 2064 case 407: /* sthx */ 2065 case 439: /* sthux */ 2066 op->type = MKOP(STORE, u, 2); 2067 break; 2068 2069 #ifdef __powerpc64__ 2070 case 532: /* ldbrx */ 2071 op->type = MKOP(LOAD, BYTEREV, 8); 2072 break; 2073 2074 #endif 2075 case 533: /* lswx */ 2076 op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f); 2077 break; 2078 2079 case 534: /* lwbrx */ 2080 op->type = MKOP(LOAD, BYTEREV, 4); 2081 break; 2082 2083 case 597: /* lswi */ 2084 if (rb == 0) 2085 rb = 32; /* # bytes to load */ 2086 op->type = MKOP(LOAD_MULTI, 0, rb); 2087 op->ea = ra ? regs->gpr[ra] : 0; 2088 break; 2089 2090 #ifdef CONFIG_PPC_FPU 2091 case 535: /* lfsx */ 2092 case 567: /* lfsux */ 2093 op->type = MKOP(LOAD_FP, u | FPCONV, 4); 2094 break; 2095 2096 case 599: /* lfdx */ 2097 case 631: /* lfdux */ 2098 op->type = MKOP(LOAD_FP, u, 8); 2099 break; 2100 2101 case 663: /* stfsx */ 2102 case 695: /* stfsux */ 2103 op->type = MKOP(STORE_FP, u | FPCONV, 4); 2104 break; 2105 2106 case 727: /* stfdx */ 2107 case 759: /* stfdux */ 2108 op->type = MKOP(STORE_FP, u, 8); 2109 break; 2110 2111 #ifdef __powerpc64__ 2112 case 791: /* lfdpx */ 2113 op->type = MKOP(LOAD_FP, 0, 16); 2114 break; 2115 2116 case 855: /* lfiwax */ 2117 op->type = MKOP(LOAD_FP, SIGNEXT, 4); 2118 break; 2119 2120 case 887: /* lfiwzx */ 2121 op->type = MKOP(LOAD_FP, 0, 4); 2122 break; 2123 2124 case 919: /* stfdpx */ 2125 op->type = MKOP(STORE_FP, 0, 16); 2126 break; 2127 2128 case 983: /* stfiwx */ 2129 op->type = MKOP(STORE_FP, 0, 4); 2130 break; 2131 #endif /* __powerpc64 */ 2132 #endif /* CONFIG_PPC_FPU */ 2133 2134 #ifdef __powerpc64__ 2135 case 660: /* stdbrx */ 2136 op->type = MKOP(STORE, BYTEREV, 8); 2137 op->val = byterev_8(regs->gpr[rd]); 2138 break; 2139 2140 #endif 2141 case 661: /* stswx */ 2142 op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f); 2143 break; 2144 2145 case 662: /* stwbrx */ 2146 op->type = MKOP(STORE, BYTEREV, 4); 2147 op->val = byterev_4(regs->gpr[rd]); 2148 break; 2149 2150 case 725: /* stswi */ 2151 if (rb == 0) 2152 rb = 32; /* # bytes to store */ 2153 op->type = MKOP(STORE_MULTI, 0, rb); 2154 op->ea = ra ? regs->gpr[ra] : 0; 2155 break; 2156 2157 case 790: /* lhbrx */ 2158 op->type = MKOP(LOAD, BYTEREV, 2); 2159 break; 2160 2161 case 918: /* sthbrx */ 2162 op->type = MKOP(STORE, BYTEREV, 2); 2163 op->val = byterev_2(regs->gpr[rd]); 2164 break; 2165 2166 #ifdef CONFIG_VSX 2167 case 12: /* lxsiwzx */ 2168 op->reg = rd | ((instr & 1) << 5); 2169 op->type = MKOP(LOAD_VSX, 0, 4); 2170 op->element_size = 8; 2171 break; 2172 2173 case 76: /* lxsiwax */ 2174 op->reg = rd | ((instr & 1) << 5); 2175 op->type = MKOP(LOAD_VSX, SIGNEXT, 4); 2176 op->element_size = 8; 2177 break; 2178 2179 case 140: /* stxsiwx */ 2180 op->reg = rd | ((instr & 1) << 5); 2181 op->type = MKOP(STORE_VSX, 0, 4); 2182 op->element_size = 8; 2183 break; 2184 2185 case 268: /* lxvx */ 2186 op->reg = rd | ((instr & 1) << 5); 2187 op->type = MKOP(LOAD_VSX, 0, 16); 2188 op->element_size = 16; 2189 op->vsx_flags = VSX_CHECK_VEC; 2190 break; 2191 2192 case 269: /* lxvl */ 2193 case 301: { /* lxvll */ 2194 int nb; 2195 op->reg = rd | ((instr & 1) << 5); 2196 op->ea = ra ? regs->gpr[ra] : 0; 2197 nb = regs->gpr[rb] & 0xff; 2198 if (nb > 16) 2199 nb = 16; 2200 op->type = MKOP(LOAD_VSX, 0, nb); 2201 op->element_size = 16; 2202 op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) | 2203 VSX_CHECK_VEC; 2204 break; 2205 } 2206 case 332: /* lxvdsx */ 2207 op->reg = rd | ((instr & 1) << 5); 2208 op->type = MKOP(LOAD_VSX, 0, 8); 2209 op->element_size = 8; 2210 op->vsx_flags = VSX_SPLAT; 2211 break; 2212 2213 case 364: /* lxvwsx */ 2214 op->reg = rd | ((instr & 1) << 5); 2215 op->type = MKOP(LOAD_VSX, 0, 4); 2216 op->element_size = 4; 2217 op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC; 2218 break; 2219 2220 case 396: /* stxvx */ 2221 op->reg = rd | ((instr & 1) << 5); 2222 op->type = MKOP(STORE_VSX, 0, 16); 2223 op->element_size = 16; 2224 op->vsx_flags = VSX_CHECK_VEC; 2225 break; 2226 2227 case 397: /* stxvl */ 2228 case 429: { /* stxvll */ 2229 int nb; 2230 op->reg = rd | ((instr & 1) << 5); 2231 op->ea = ra ? regs->gpr[ra] : 0; 2232 nb = regs->gpr[rb] & 0xff; 2233 if (nb > 16) 2234 nb = 16; 2235 op->type = MKOP(STORE_VSX, 0, nb); 2236 op->element_size = 16; 2237 op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) | 2238 VSX_CHECK_VEC; 2239 break; 2240 } 2241 case 524: /* lxsspx */ 2242 op->reg = rd | ((instr & 1) << 5); 2243 op->type = MKOP(LOAD_VSX, 0, 4); 2244 op->element_size = 8; 2245 op->vsx_flags = VSX_FPCONV; 2246 break; 2247 2248 case 588: /* lxsdx */ 2249 op->reg = rd | ((instr & 1) << 5); 2250 op->type = MKOP(LOAD_VSX, 0, 8); 2251 op->element_size = 8; 2252 break; 2253 2254 case 652: /* stxsspx */ 2255 op->reg = rd | ((instr & 1) << 5); 2256 op->type = MKOP(STORE_VSX, 0, 4); 2257 op->element_size = 8; 2258 op->vsx_flags = VSX_FPCONV; 2259 break; 2260 2261 case 716: /* stxsdx */ 2262 op->reg = rd | ((instr & 1) << 5); 2263 op->type = MKOP(STORE_VSX, 0, 8); 2264 op->element_size = 8; 2265 break; 2266 2267 case 780: /* lxvw4x */ 2268 op->reg = rd | ((instr & 1) << 5); 2269 op->type = MKOP(LOAD_VSX, 0, 16); 2270 op->element_size = 4; 2271 break; 2272 2273 case 781: /* lxsibzx */ 2274 op->reg = rd | ((instr & 1) << 5); 2275 op->type = MKOP(LOAD_VSX, 0, 1); 2276 op->element_size = 8; 2277 op->vsx_flags = VSX_CHECK_VEC; 2278 break; 2279 2280 case 812: /* lxvh8x */ 2281 op->reg = rd | ((instr & 1) << 5); 2282 op->type = MKOP(LOAD_VSX, 0, 16); 2283 op->element_size = 2; 2284 op->vsx_flags = VSX_CHECK_VEC; 2285 break; 2286 2287 case 813: /* lxsihzx */ 2288 op->reg = rd | ((instr & 1) << 5); 2289 op->type = MKOP(LOAD_VSX, 0, 2); 2290 op->element_size = 8; 2291 op->vsx_flags = VSX_CHECK_VEC; 2292 break; 2293 2294 case 844: /* lxvd2x */ 2295 op->reg = rd | ((instr & 1) << 5); 2296 op->type = MKOP(LOAD_VSX, 0, 16); 2297 op->element_size = 8; 2298 break; 2299 2300 case 876: /* lxvb16x */ 2301 op->reg = rd | ((instr & 1) << 5); 2302 op->type = MKOP(LOAD_VSX, 0, 16); 2303 op->element_size = 1; 2304 op->vsx_flags = VSX_CHECK_VEC; 2305 break; 2306 2307 case 908: /* stxvw4x */ 2308 op->reg = rd | ((instr & 1) << 5); 2309 op->type = MKOP(STORE_VSX, 0, 16); 2310 op->element_size = 4; 2311 break; 2312 2313 case 909: /* stxsibx */ 2314 op->reg = rd | ((instr & 1) << 5); 2315 op->type = MKOP(STORE_VSX, 0, 1); 2316 op->element_size = 8; 2317 op->vsx_flags = VSX_CHECK_VEC; 2318 break; 2319 2320 case 940: /* stxvh8x */ 2321 op->reg = rd | ((instr & 1) << 5); 2322 op->type = MKOP(STORE_VSX, 0, 16); 2323 op->element_size = 2; 2324 op->vsx_flags = VSX_CHECK_VEC; 2325 break; 2326 2327 case 941: /* stxsihx */ 2328 op->reg = rd | ((instr & 1) << 5); 2329 op->type = MKOP(STORE_VSX, 0, 2); 2330 op->element_size = 8; 2331 op->vsx_flags = VSX_CHECK_VEC; 2332 break; 2333 2334 case 972: /* stxvd2x */ 2335 op->reg = rd | ((instr & 1) << 5); 2336 op->type = MKOP(STORE_VSX, 0, 16); 2337 op->element_size = 8; 2338 break; 2339 2340 case 1004: /* stxvb16x */ 2341 op->reg = rd | ((instr & 1) << 5); 2342 op->type = MKOP(STORE_VSX, 0, 16); 2343 op->element_size = 1; 2344 op->vsx_flags = VSX_CHECK_VEC; 2345 break; 2346 2347 #endif /* CONFIG_VSX */ 2348 } 2349 break; 2350 2351 case 32: /* lwz */ 2352 case 33: /* lwzu */ 2353 op->type = MKOP(LOAD, u, 4); 2354 op->ea = dform_ea(instr, regs); 2355 break; 2356 2357 case 34: /* lbz */ 2358 case 35: /* lbzu */ 2359 op->type = MKOP(LOAD, u, 1); 2360 op->ea = dform_ea(instr, regs); 2361 break; 2362 2363 case 36: /* stw */ 2364 case 37: /* stwu */ 2365 op->type = MKOP(STORE, u, 4); 2366 op->ea = dform_ea(instr, regs); 2367 break; 2368 2369 case 38: /* stb */ 2370 case 39: /* stbu */ 2371 op->type = MKOP(STORE, u, 1); 2372 op->ea = dform_ea(instr, regs); 2373 break; 2374 2375 case 40: /* lhz */ 2376 case 41: /* lhzu */ 2377 op->type = MKOP(LOAD, u, 2); 2378 op->ea = dform_ea(instr, regs); 2379 break; 2380 2381 case 42: /* lha */ 2382 case 43: /* lhau */ 2383 op->type = MKOP(LOAD, SIGNEXT | u, 2); 2384 op->ea = dform_ea(instr, regs); 2385 break; 2386 2387 case 44: /* sth */ 2388 case 45: /* sthu */ 2389 op->type = MKOP(STORE, u, 2); 2390 op->ea = dform_ea(instr, regs); 2391 break; 2392 2393 case 46: /* lmw */ 2394 if (ra >= rd) 2395 break; /* invalid form, ra in range to load */ 2396 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd)); 2397 op->ea = dform_ea(instr, regs); 2398 break; 2399 2400 case 47: /* stmw */ 2401 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd)); 2402 op->ea = dform_ea(instr, regs); 2403 break; 2404 2405 #ifdef CONFIG_PPC_FPU 2406 case 48: /* lfs */ 2407 case 49: /* lfsu */ 2408 op->type = MKOP(LOAD_FP, u | FPCONV, 4); 2409 op->ea = dform_ea(instr, regs); 2410 break; 2411 2412 case 50: /* lfd */ 2413 case 51: /* lfdu */ 2414 op->type = MKOP(LOAD_FP, u, 8); 2415 op->ea = dform_ea(instr, regs); 2416 break; 2417 2418 case 52: /* stfs */ 2419 case 53: /* stfsu */ 2420 op->type = MKOP(STORE_FP, u | FPCONV, 4); 2421 op->ea = dform_ea(instr, regs); 2422 break; 2423 2424 case 54: /* stfd */ 2425 case 55: /* stfdu */ 2426 op->type = MKOP(STORE_FP, u, 8); 2427 op->ea = dform_ea(instr, regs); 2428 break; 2429 #endif 2430 2431 #ifdef __powerpc64__ 2432 case 56: /* lq */ 2433 if (!((rd & 1) || (rd == ra))) 2434 op->type = MKOP(LOAD, 0, 16); 2435 op->ea = dqform_ea(instr, regs); 2436 break; 2437 #endif 2438 2439 #ifdef CONFIG_VSX 2440 case 57: /* lfdp, lxsd, lxssp */ 2441 op->ea = dsform_ea(instr, regs); 2442 switch (instr & 3) { 2443 case 0: /* lfdp */ 2444 if (rd & 1) 2445 break; /* reg must be even */ 2446 op->type = MKOP(LOAD_FP, 0, 16); 2447 break; 2448 case 2: /* lxsd */ 2449 op->reg = rd + 32; 2450 op->type = MKOP(LOAD_VSX, 0, 8); 2451 op->element_size = 8; 2452 op->vsx_flags = VSX_CHECK_VEC; 2453 break; 2454 case 3: /* lxssp */ 2455 op->reg = rd + 32; 2456 op->type = MKOP(LOAD_VSX, 0, 4); 2457 op->element_size = 8; 2458 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC; 2459 break; 2460 } 2461 break; 2462 #endif /* CONFIG_VSX */ 2463 2464 #ifdef __powerpc64__ 2465 case 58: /* ld[u], lwa */ 2466 op->ea = dsform_ea(instr, regs); 2467 switch (instr & 3) { 2468 case 0: /* ld */ 2469 op->type = MKOP(LOAD, 0, 8); 2470 break; 2471 case 1: /* ldu */ 2472 op->type = MKOP(LOAD, UPDATE, 8); 2473 break; 2474 case 2: /* lwa */ 2475 op->type = MKOP(LOAD, SIGNEXT, 4); 2476 break; 2477 } 2478 break; 2479 #endif 2480 2481 #ifdef CONFIG_VSX 2482 case 61: /* stfdp, lxv, stxsd, stxssp, stxv */ 2483 switch (instr & 7) { 2484 case 0: /* stfdp with LSB of DS field = 0 */ 2485 case 4: /* stfdp with LSB of DS field = 1 */ 2486 op->ea = dsform_ea(instr, regs); 2487 op->type = MKOP(STORE_FP, 0, 16); 2488 break; 2489 2490 case 1: /* lxv */ 2491 op->ea = dqform_ea(instr, regs); 2492 if (instr & 8) 2493 op->reg = rd + 32; 2494 op->type = MKOP(LOAD_VSX, 0, 16); 2495 op->element_size = 16; 2496 op->vsx_flags = VSX_CHECK_VEC; 2497 break; 2498 2499 case 2: /* stxsd with LSB of DS field = 0 */ 2500 case 6: /* stxsd with LSB of DS field = 1 */ 2501 op->ea = dsform_ea(instr, regs); 2502 op->reg = rd + 32; 2503 op->type = MKOP(STORE_VSX, 0, 8); 2504 op->element_size = 8; 2505 op->vsx_flags = VSX_CHECK_VEC; 2506 break; 2507 2508 case 3: /* stxssp with LSB of DS field = 0 */ 2509 case 7: /* stxssp with LSB of DS field = 1 */ 2510 op->ea = dsform_ea(instr, regs); 2511 op->reg = rd + 32; 2512 op->type = MKOP(STORE_VSX, 0, 4); 2513 op->element_size = 8; 2514 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC; 2515 break; 2516 2517 case 5: /* stxv */ 2518 op->ea = dqform_ea(instr, regs); 2519 if (instr & 8) 2520 op->reg = rd + 32; 2521 op->type = MKOP(STORE_VSX, 0, 16); 2522 op->element_size = 16; 2523 op->vsx_flags = VSX_CHECK_VEC; 2524 break; 2525 } 2526 break; 2527 #endif /* CONFIG_VSX */ 2528 2529 #ifdef __powerpc64__ 2530 case 62: /* std[u] */ 2531 op->ea = dsform_ea(instr, regs); 2532 switch (instr & 3) { 2533 case 0: /* std */ 2534 op->type = MKOP(STORE, 0, 8); 2535 break; 2536 case 1: /* stdu */ 2537 op->type = MKOP(STORE, UPDATE, 8); 2538 break; 2539 case 2: /* stq */ 2540 if (!(rd & 1)) 2541 op->type = MKOP(STORE, 0, 16); 2542 break; 2543 } 2544 break; 2545 #endif /* __powerpc64__ */ 2546 2547 } 2548 2549 #ifdef CONFIG_VSX 2550 if ((GETTYPE(op->type) == LOAD_VSX || 2551 GETTYPE(op->type) == STORE_VSX) && 2552 !cpu_has_feature(CPU_FTR_VSX)) { 2553 return -1; 2554 } 2555 #endif /* CONFIG_VSX */ 2556 2557 return 0; 2558 2559 logical_done: 2560 if (instr & 1) 2561 set_cr0(regs, op); 2562 logical_done_nocc: 2563 op->reg = ra; 2564 op->type |= SETREG; 2565 return 1; 2566 2567 arith_done: 2568 if (instr & 1) 2569 set_cr0(regs, op); 2570 compute_done: 2571 op->reg = rd; 2572 op->type |= SETREG; 2573 return 1; 2574 2575 priv: 2576 op->type = INTERRUPT | 0x700; 2577 op->val = SRR1_PROGPRIV; 2578 return 0; 2579 2580 trap: 2581 op->type = INTERRUPT | 0x700; 2582 op->val = SRR1_PROGTRAP; 2583 return 0; 2584 } 2585 EXPORT_SYMBOL_GPL(analyse_instr); 2586 NOKPROBE_SYMBOL(analyse_instr); 2587 2588 /* 2589 * For PPC32 we always use stwu with r1 to change the stack pointer. 2590 * So this emulated store may corrupt the exception frame, now we 2591 * have to provide the exception frame trampoline, which is pushed 2592 * below the kprobed function stack. So we only update gpr[1] but 2593 * don't emulate the real store operation. We will do real store 2594 * operation safely in exception return code by checking this flag. 2595 */ 2596 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs) 2597 { 2598 #ifdef CONFIG_PPC32 2599 /* 2600 * Check if we will touch kernel stack overflow 2601 */ 2602 if (ea - STACK_INT_FRAME_SIZE <= current->thread.ksp_limit) { 2603 printk(KERN_CRIT "Can't kprobe this since kernel stack would overflow.\n"); 2604 return -EINVAL; 2605 } 2606 #endif /* CONFIG_PPC32 */ 2607 /* 2608 * Check if we already set since that means we'll 2609 * lose the previous value. 2610 */ 2611 WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE)); 2612 set_thread_flag(TIF_EMULATE_STACK_STORE); 2613 return 0; 2614 } 2615 2616 static nokprobe_inline void do_signext(unsigned long *valp, int size) 2617 { 2618 switch (size) { 2619 case 2: 2620 *valp = (signed short) *valp; 2621 break; 2622 case 4: 2623 *valp = (signed int) *valp; 2624 break; 2625 } 2626 } 2627 2628 static nokprobe_inline void do_byterev(unsigned long *valp, int size) 2629 { 2630 switch (size) { 2631 case 2: 2632 *valp = byterev_2(*valp); 2633 break; 2634 case 4: 2635 *valp = byterev_4(*valp); 2636 break; 2637 #ifdef __powerpc64__ 2638 case 8: 2639 *valp = byterev_8(*valp); 2640 break; 2641 #endif 2642 } 2643 } 2644 2645 /* 2646 * Emulate an instruction that can be executed just by updating 2647 * fields in *regs. 2648 */ 2649 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op) 2650 { 2651 unsigned long next_pc; 2652 2653 next_pc = truncate_if_32bit(regs->msr, regs->nip + 4); 2654 switch (GETTYPE(op->type)) { 2655 case COMPUTE: 2656 if (op->type & SETREG) 2657 regs->gpr[op->reg] = op->val; 2658 if (op->type & SETCC) 2659 regs->ccr = op->ccval; 2660 if (op->type & SETXER) 2661 regs->xer = op->xerval; 2662 break; 2663 2664 case BRANCH: 2665 if (op->type & SETLK) 2666 regs->link = next_pc; 2667 if (op->type & BRTAKEN) 2668 next_pc = op->val; 2669 if (op->type & DECCTR) 2670 --regs->ctr; 2671 break; 2672 2673 case BARRIER: 2674 switch (op->type & BARRIER_MASK) { 2675 case BARRIER_SYNC: 2676 mb(); 2677 break; 2678 case BARRIER_ISYNC: 2679 isync(); 2680 break; 2681 case BARRIER_EIEIO: 2682 eieio(); 2683 break; 2684 case BARRIER_LWSYNC: 2685 asm volatile("lwsync" : : : "memory"); 2686 break; 2687 case BARRIER_PTESYNC: 2688 asm volatile("ptesync" : : : "memory"); 2689 break; 2690 } 2691 break; 2692 2693 case MFSPR: 2694 switch (op->spr) { 2695 case SPRN_XER: 2696 regs->gpr[op->reg] = regs->xer & 0xffffffffUL; 2697 break; 2698 case SPRN_LR: 2699 regs->gpr[op->reg] = regs->link; 2700 break; 2701 case SPRN_CTR: 2702 regs->gpr[op->reg] = regs->ctr; 2703 break; 2704 default: 2705 WARN_ON_ONCE(1); 2706 } 2707 break; 2708 2709 case MTSPR: 2710 switch (op->spr) { 2711 case SPRN_XER: 2712 regs->xer = op->val & 0xffffffffUL; 2713 break; 2714 case SPRN_LR: 2715 regs->link = op->val; 2716 break; 2717 case SPRN_CTR: 2718 regs->ctr = op->val; 2719 break; 2720 default: 2721 WARN_ON_ONCE(1); 2722 } 2723 break; 2724 2725 default: 2726 WARN_ON_ONCE(1); 2727 } 2728 regs->nip = next_pc; 2729 } 2730 NOKPROBE_SYMBOL(emulate_update_regs); 2731 2732 /* 2733 * Emulate a previously-analysed load or store instruction. 2734 * Return values are: 2735 * 0 = instruction emulated successfully 2736 * -EFAULT = address out of range or access faulted (regs->dar 2737 * contains the faulting address) 2738 * -EACCES = misaligned access, instruction requires alignment 2739 * -EINVAL = unknown operation in *op 2740 */ 2741 int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op) 2742 { 2743 int err, size, type; 2744 int i, rd, nb; 2745 unsigned int cr; 2746 unsigned long val; 2747 unsigned long ea; 2748 bool cross_endian; 2749 2750 err = 0; 2751 size = GETSIZE(op->type); 2752 type = GETTYPE(op->type); 2753 cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE); 2754 ea = truncate_if_32bit(regs->msr, op->ea); 2755 2756 switch (type) { 2757 case LARX: 2758 if (ea & (size - 1)) 2759 return -EACCES; /* can't handle misaligned */ 2760 if (!address_ok(regs, ea, size)) 2761 return -EFAULT; 2762 err = 0; 2763 val = 0; 2764 switch (size) { 2765 #ifdef __powerpc64__ 2766 case 1: 2767 __get_user_asmx(val, ea, err, "lbarx"); 2768 break; 2769 case 2: 2770 __get_user_asmx(val, ea, err, "lharx"); 2771 break; 2772 #endif 2773 case 4: 2774 __get_user_asmx(val, ea, err, "lwarx"); 2775 break; 2776 #ifdef __powerpc64__ 2777 case 8: 2778 __get_user_asmx(val, ea, err, "ldarx"); 2779 break; 2780 case 16: 2781 err = do_lqarx(ea, ®s->gpr[op->reg]); 2782 break; 2783 #endif 2784 default: 2785 return -EINVAL; 2786 } 2787 if (err) { 2788 regs->dar = ea; 2789 break; 2790 } 2791 if (size < 16) 2792 regs->gpr[op->reg] = val; 2793 break; 2794 2795 case STCX: 2796 if (ea & (size - 1)) 2797 return -EACCES; /* can't handle misaligned */ 2798 if (!address_ok(regs, ea, size)) 2799 return -EFAULT; 2800 err = 0; 2801 switch (size) { 2802 #ifdef __powerpc64__ 2803 case 1: 2804 __put_user_asmx(op->val, ea, err, "stbcx.", cr); 2805 break; 2806 case 2: 2807 __put_user_asmx(op->val, ea, err, "stbcx.", cr); 2808 break; 2809 #endif 2810 case 4: 2811 __put_user_asmx(op->val, ea, err, "stwcx.", cr); 2812 break; 2813 #ifdef __powerpc64__ 2814 case 8: 2815 __put_user_asmx(op->val, ea, err, "stdcx.", cr); 2816 break; 2817 case 16: 2818 err = do_stqcx(ea, regs->gpr[op->reg], 2819 regs->gpr[op->reg + 1], &cr); 2820 break; 2821 #endif 2822 default: 2823 return -EINVAL; 2824 } 2825 if (!err) 2826 regs->ccr = (regs->ccr & 0x0fffffff) | 2827 (cr & 0xe0000000) | 2828 ((regs->xer >> 3) & 0x10000000); 2829 else 2830 regs->dar = ea; 2831 break; 2832 2833 case LOAD: 2834 #ifdef __powerpc64__ 2835 if (size == 16) { 2836 err = emulate_lq(regs, ea, op->reg, cross_endian); 2837 break; 2838 } 2839 #endif 2840 err = read_mem(®s->gpr[op->reg], ea, size, regs); 2841 if (!err) { 2842 if (op->type & SIGNEXT) 2843 do_signext(®s->gpr[op->reg], size); 2844 if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV)) 2845 do_byterev(®s->gpr[op->reg], size); 2846 } 2847 break; 2848 2849 #ifdef CONFIG_PPC_FPU 2850 case LOAD_FP: 2851 /* 2852 * If the instruction is in userspace, we can emulate it even 2853 * if the VMX state is not live, because we have the state 2854 * stored in the thread_struct. If the instruction is in 2855 * the kernel, we must not touch the state in the thread_struct. 2856 */ 2857 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP)) 2858 return 0; 2859 err = do_fp_load(op, ea, regs, cross_endian); 2860 break; 2861 #endif 2862 #ifdef CONFIG_ALTIVEC 2863 case LOAD_VMX: 2864 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC)) 2865 return 0; 2866 err = do_vec_load(op->reg, ea, size, regs, cross_endian); 2867 break; 2868 #endif 2869 #ifdef CONFIG_VSX 2870 case LOAD_VSX: { 2871 unsigned long msrbit = MSR_VSX; 2872 2873 /* 2874 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX 2875 * when the target of the instruction is a vector register. 2876 */ 2877 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC)) 2878 msrbit = MSR_VEC; 2879 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit)) 2880 return 0; 2881 err = do_vsx_load(op, ea, regs, cross_endian); 2882 break; 2883 } 2884 #endif 2885 case LOAD_MULTI: 2886 if (!address_ok(regs, ea, size)) 2887 return -EFAULT; 2888 rd = op->reg; 2889 for (i = 0; i < size; i += 4) { 2890 unsigned int v32 = 0; 2891 2892 nb = size - i; 2893 if (nb > 4) 2894 nb = 4; 2895 err = copy_mem_in((u8 *) &v32, ea, nb, regs); 2896 if (err) 2897 break; 2898 if (unlikely(cross_endian)) 2899 v32 = byterev_4(v32); 2900 regs->gpr[rd] = v32; 2901 ea += 4; 2902 /* reg number wraps from 31 to 0 for lsw[ix] */ 2903 rd = (rd + 1) & 0x1f; 2904 } 2905 break; 2906 2907 case STORE: 2908 #ifdef __powerpc64__ 2909 if (size == 16) { 2910 err = emulate_stq(regs, ea, op->reg, cross_endian); 2911 break; 2912 } 2913 #endif 2914 if ((op->type & UPDATE) && size == sizeof(long) && 2915 op->reg == 1 && op->update_reg == 1 && 2916 !(regs->msr & MSR_PR) && 2917 ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) { 2918 err = handle_stack_update(ea, regs); 2919 break; 2920 } 2921 if (unlikely(cross_endian)) 2922 do_byterev(&op->val, size); 2923 err = write_mem(op->val, ea, size, regs); 2924 break; 2925 2926 #ifdef CONFIG_PPC_FPU 2927 case STORE_FP: 2928 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP)) 2929 return 0; 2930 err = do_fp_store(op, ea, regs, cross_endian); 2931 break; 2932 #endif 2933 #ifdef CONFIG_ALTIVEC 2934 case STORE_VMX: 2935 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC)) 2936 return 0; 2937 err = do_vec_store(op->reg, ea, size, regs, cross_endian); 2938 break; 2939 #endif 2940 #ifdef CONFIG_VSX 2941 case STORE_VSX: { 2942 unsigned long msrbit = MSR_VSX; 2943 2944 /* 2945 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX 2946 * when the target of the instruction is a vector register. 2947 */ 2948 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC)) 2949 msrbit = MSR_VEC; 2950 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit)) 2951 return 0; 2952 err = do_vsx_store(op, ea, regs, cross_endian); 2953 break; 2954 } 2955 #endif 2956 case STORE_MULTI: 2957 if (!address_ok(regs, ea, size)) 2958 return -EFAULT; 2959 rd = op->reg; 2960 for (i = 0; i < size; i += 4) { 2961 unsigned int v32 = regs->gpr[rd]; 2962 2963 nb = size - i; 2964 if (nb > 4) 2965 nb = 4; 2966 if (unlikely(cross_endian)) 2967 v32 = byterev_4(v32); 2968 err = copy_mem_out((u8 *) &v32, ea, nb, regs); 2969 if (err) 2970 break; 2971 ea += 4; 2972 /* reg number wraps from 31 to 0 for stsw[ix] */ 2973 rd = (rd + 1) & 0x1f; 2974 } 2975 break; 2976 2977 default: 2978 return -EINVAL; 2979 } 2980 2981 if (err) 2982 return err; 2983 2984 if (op->type & UPDATE) 2985 regs->gpr[op->update_reg] = op->ea; 2986 2987 return 0; 2988 } 2989 NOKPROBE_SYMBOL(emulate_loadstore); 2990 2991 /* 2992 * Emulate instructions that cause a transfer of control, 2993 * loads and stores, and a few other instructions. 2994 * Returns 1 if the step was emulated, 0 if not, 2995 * or -1 if the instruction is one that should not be stepped, 2996 * such as an rfid, or a mtmsrd that would clear MSR_RI. 2997 */ 2998 int emulate_step(struct pt_regs *regs, unsigned int instr) 2999 { 3000 struct instruction_op op; 3001 int r, err, type; 3002 unsigned long val; 3003 unsigned long ea; 3004 3005 r = analyse_instr(&op, regs, instr); 3006 if (r < 0) 3007 return r; 3008 if (r > 0) { 3009 emulate_update_regs(regs, &op); 3010 return 1; 3011 } 3012 3013 err = 0; 3014 type = GETTYPE(op.type); 3015 3016 if (OP_IS_LOAD_STORE(type)) { 3017 err = emulate_loadstore(regs, &op); 3018 if (err) 3019 return 0; 3020 goto instr_done; 3021 } 3022 3023 switch (type) { 3024 case CACHEOP: 3025 ea = truncate_if_32bit(regs->msr, op.ea); 3026 if (!address_ok(regs, ea, 8)) 3027 return 0; 3028 switch (op.type & CACHEOP_MASK) { 3029 case DCBST: 3030 __cacheop_user_asmx(ea, err, "dcbst"); 3031 break; 3032 case DCBF: 3033 __cacheop_user_asmx(ea, err, "dcbf"); 3034 break; 3035 case DCBTST: 3036 if (op.reg == 0) 3037 prefetchw((void *) ea); 3038 break; 3039 case DCBT: 3040 if (op.reg == 0) 3041 prefetch((void *) ea); 3042 break; 3043 case ICBI: 3044 __cacheop_user_asmx(ea, err, "icbi"); 3045 break; 3046 case DCBZ: 3047 err = emulate_dcbz(ea, regs); 3048 break; 3049 } 3050 if (err) { 3051 regs->dar = ea; 3052 return 0; 3053 } 3054 goto instr_done; 3055 3056 case MFMSR: 3057 regs->gpr[op.reg] = regs->msr & MSR_MASK; 3058 goto instr_done; 3059 3060 case MTMSR: 3061 val = regs->gpr[op.reg]; 3062 if ((val & MSR_RI) == 0) 3063 /* can't step mtmsr[d] that would clear MSR_RI */ 3064 return -1; 3065 /* here op.val is the mask of bits to change */ 3066 regs->msr = (regs->msr & ~op.val) | (val & op.val); 3067 goto instr_done; 3068 3069 #ifdef CONFIG_PPC64 3070 case SYSCALL: /* sc */ 3071 /* 3072 * N.B. this uses knowledge about how the syscall 3073 * entry code works. If that is changed, this will 3074 * need to be changed also. 3075 */ 3076 if (regs->gpr[0] == 0x1ebe && 3077 cpu_has_feature(CPU_FTR_REAL_LE)) { 3078 regs->msr ^= MSR_LE; 3079 goto instr_done; 3080 } 3081 regs->gpr[9] = regs->gpr[13]; 3082 regs->gpr[10] = MSR_KERNEL; 3083 regs->gpr[11] = regs->nip + 4; 3084 regs->gpr[12] = regs->msr & MSR_MASK; 3085 regs->gpr[13] = (unsigned long) get_paca(); 3086 regs->nip = (unsigned long) &system_call_common; 3087 regs->msr = MSR_KERNEL; 3088 return 1; 3089 3090 case RFI: 3091 return -1; 3092 #endif 3093 } 3094 return 0; 3095 3096 instr_done: 3097 regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4); 3098 return 1; 3099 } 3100 NOKPROBE_SYMBOL(emulate_step); 3101