1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Single-step support. 4 * 5 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM 6 */ 7 #include <linux/kernel.h> 8 #include <linux/kprobes.h> 9 #include <linux/ptrace.h> 10 #include <linux/prefetch.h> 11 #include <asm/sstep.h> 12 #include <asm/processor.h> 13 #include <linux/uaccess.h> 14 #include <asm/cpu_has_feature.h> 15 #include <asm/cputable.h> 16 #include <asm/disassemble.h> 17 18 extern char system_call_common[]; 19 extern char system_call_vectored_emulate[]; 20 21 #ifdef CONFIG_PPC64 22 /* Bits in SRR1 that are copied from MSR */ 23 #define MSR_MASK 0xffffffff87c0ffffUL 24 #else 25 #define MSR_MASK 0x87c0ffff 26 #endif 27 28 /* Bits in XER */ 29 #define XER_SO 0x80000000U 30 #define XER_OV 0x40000000U 31 #define XER_CA 0x20000000U 32 #define XER_OV32 0x00080000U 33 #define XER_CA32 0x00040000U 34 35 #ifdef CONFIG_VSX 36 #define VSX_REGISTER_XTP(rd) ((((rd) & 1) << 5) | ((rd) & 0xfe)) 37 #endif 38 39 #ifdef CONFIG_PPC_FPU 40 /* 41 * Functions in ldstfp.S 42 */ 43 extern void get_fpr(int rn, double *p); 44 extern void put_fpr(int rn, const double *p); 45 extern void get_vr(int rn, __vector128 *p); 46 extern void put_vr(int rn, __vector128 *p); 47 extern void load_vsrn(int vsr, const void *p); 48 extern void store_vsrn(int vsr, void *p); 49 extern void conv_sp_to_dp(const float *sp, double *dp); 50 extern void conv_dp_to_sp(const double *dp, float *sp); 51 #endif 52 53 #ifdef __powerpc64__ 54 /* 55 * Functions in quad.S 56 */ 57 extern int do_lq(unsigned long ea, unsigned long *regs); 58 extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1); 59 extern int do_lqarx(unsigned long ea, unsigned long *regs); 60 extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1, 61 unsigned int *crp); 62 #endif 63 64 #ifdef __LITTLE_ENDIAN__ 65 #define IS_LE 1 66 #define IS_BE 0 67 #else 68 #define IS_LE 0 69 #define IS_BE 1 70 #endif 71 72 /* 73 * Emulate the truncation of 64 bit values in 32-bit mode. 74 */ 75 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr, 76 unsigned long val) 77 { 78 #ifdef __powerpc64__ 79 if ((msr & MSR_64BIT) == 0) 80 val &= 0xffffffffUL; 81 #endif 82 return val; 83 } 84 85 /* 86 * Determine whether a conditional branch instruction would branch. 87 */ 88 static nokprobe_inline int branch_taken(unsigned int instr, 89 const struct pt_regs *regs, 90 struct instruction_op *op) 91 { 92 unsigned int bo = (instr >> 21) & 0x1f; 93 unsigned int bi; 94 95 if ((bo & 4) == 0) { 96 /* decrement counter */ 97 op->type |= DECCTR; 98 if (((bo >> 1) & 1) ^ (regs->ctr == 1)) 99 return 0; 100 } 101 if ((bo & 0x10) == 0) { 102 /* check bit from CR */ 103 bi = (instr >> 16) & 0x1f; 104 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1)) 105 return 0; 106 } 107 return 1; 108 } 109 110 static nokprobe_inline long address_ok(struct pt_regs *regs, 111 unsigned long ea, int nb) 112 { 113 if (!user_mode(regs)) 114 return 1; 115 if (__access_ok(ea, nb)) 116 return 1; 117 if (__access_ok(ea, 1)) 118 /* Access overlaps the end of the user region */ 119 regs->dar = TASK_SIZE_MAX - 1; 120 else 121 regs->dar = ea; 122 return 0; 123 } 124 125 /* 126 * Calculate effective address for a D-form instruction 127 */ 128 static nokprobe_inline unsigned long dform_ea(unsigned int instr, 129 const struct pt_regs *regs) 130 { 131 int ra; 132 unsigned long ea; 133 134 ra = (instr >> 16) & 0x1f; 135 ea = (signed short) instr; /* sign-extend */ 136 if (ra) 137 ea += regs->gpr[ra]; 138 139 return ea; 140 } 141 142 #ifdef __powerpc64__ 143 /* 144 * Calculate effective address for a DS-form instruction 145 */ 146 static nokprobe_inline unsigned long dsform_ea(unsigned int instr, 147 const struct pt_regs *regs) 148 { 149 int ra; 150 unsigned long ea; 151 152 ra = (instr >> 16) & 0x1f; 153 ea = (signed short) (instr & ~3); /* sign-extend */ 154 if (ra) 155 ea += regs->gpr[ra]; 156 157 return ea; 158 } 159 160 /* 161 * Calculate effective address for a DQ-form instruction 162 */ 163 static nokprobe_inline unsigned long dqform_ea(unsigned int instr, 164 const struct pt_regs *regs) 165 { 166 int ra; 167 unsigned long ea; 168 169 ra = (instr >> 16) & 0x1f; 170 ea = (signed short) (instr & ~0xf); /* sign-extend */ 171 if (ra) 172 ea += regs->gpr[ra]; 173 174 return ea; 175 } 176 #endif /* __powerpc64 */ 177 178 /* 179 * Calculate effective address for an X-form instruction 180 */ 181 static nokprobe_inline unsigned long xform_ea(unsigned int instr, 182 const struct pt_regs *regs) 183 { 184 int ra, rb; 185 unsigned long ea; 186 187 ra = (instr >> 16) & 0x1f; 188 rb = (instr >> 11) & 0x1f; 189 ea = regs->gpr[rb]; 190 if (ra) 191 ea += regs->gpr[ra]; 192 193 return ea; 194 } 195 196 /* 197 * Calculate effective address for a MLS:D-form / 8LS:D-form 198 * prefixed instruction 199 */ 200 static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned int instr, 201 unsigned int suffix, 202 const struct pt_regs *regs) 203 { 204 int ra, prefix_r; 205 unsigned int dd; 206 unsigned long ea, d0, d1, d; 207 208 prefix_r = GET_PREFIX_R(instr); 209 ra = GET_PREFIX_RA(suffix); 210 211 d0 = instr & 0x3ffff; 212 d1 = suffix & 0xffff; 213 d = (d0 << 16) | d1; 214 215 /* 216 * sign extend a 34 bit number 217 */ 218 dd = (unsigned int)(d >> 2); 219 ea = (signed int)dd; 220 ea = (ea << 2) | (d & 0x3); 221 222 if (!prefix_r && ra) 223 ea += regs->gpr[ra]; 224 else if (!prefix_r && !ra) 225 ; /* Leave ea as is */ 226 else if (prefix_r) 227 ea += regs->nip; 228 229 /* 230 * (prefix_r && ra) is an invalid form. Should already be 231 * checked for by caller! 232 */ 233 234 return ea; 235 } 236 237 /* 238 * Return the largest power of 2, not greater than sizeof(unsigned long), 239 * such that x is a multiple of it. 240 */ 241 static nokprobe_inline unsigned long max_align(unsigned long x) 242 { 243 x |= sizeof(unsigned long); 244 return x & -x; /* isolates rightmost bit */ 245 } 246 247 static nokprobe_inline unsigned long byterev_2(unsigned long x) 248 { 249 return ((x >> 8) & 0xff) | ((x & 0xff) << 8); 250 } 251 252 static nokprobe_inline unsigned long byterev_4(unsigned long x) 253 { 254 return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) | 255 ((x & 0xff00) << 8) | ((x & 0xff) << 24); 256 } 257 258 #ifdef __powerpc64__ 259 static nokprobe_inline unsigned long byterev_8(unsigned long x) 260 { 261 return (byterev_4(x) << 32) | byterev_4(x >> 32); 262 } 263 #endif 264 265 static nokprobe_inline void do_byte_reverse(void *ptr, int nb) 266 { 267 switch (nb) { 268 case 2: 269 *(u16 *)ptr = byterev_2(*(u16 *)ptr); 270 break; 271 case 4: 272 *(u32 *)ptr = byterev_4(*(u32 *)ptr); 273 break; 274 #ifdef __powerpc64__ 275 case 8: 276 *(unsigned long *)ptr = byterev_8(*(unsigned long *)ptr); 277 break; 278 case 16: { 279 unsigned long *up = (unsigned long *)ptr; 280 unsigned long tmp; 281 tmp = byterev_8(up[0]); 282 up[0] = byterev_8(up[1]); 283 up[1] = tmp; 284 break; 285 } 286 case 32: { 287 unsigned long *up = (unsigned long *)ptr; 288 unsigned long tmp; 289 290 tmp = byterev_8(up[0]); 291 up[0] = byterev_8(up[3]); 292 up[3] = tmp; 293 tmp = byterev_8(up[2]); 294 up[2] = byterev_8(up[1]); 295 up[1] = tmp; 296 break; 297 } 298 299 #endif 300 default: 301 WARN_ON_ONCE(1); 302 } 303 } 304 305 static nokprobe_inline int read_mem_aligned(unsigned long *dest, 306 unsigned long ea, int nb, 307 struct pt_regs *regs) 308 { 309 int err = 0; 310 unsigned long x = 0; 311 312 switch (nb) { 313 case 1: 314 err = __get_user(x, (unsigned char __user *) ea); 315 break; 316 case 2: 317 err = __get_user(x, (unsigned short __user *) ea); 318 break; 319 case 4: 320 err = __get_user(x, (unsigned int __user *) ea); 321 break; 322 #ifdef __powerpc64__ 323 case 8: 324 err = __get_user(x, (unsigned long __user *) ea); 325 break; 326 #endif 327 } 328 if (!err) 329 *dest = x; 330 else 331 regs->dar = ea; 332 return err; 333 } 334 335 /* 336 * Copy from userspace to a buffer, using the largest possible 337 * aligned accesses, up to sizeof(long). 338 */ 339 static nokprobe_inline int copy_mem_in(u8 *dest, unsigned long ea, int nb, 340 struct pt_regs *regs) 341 { 342 int err = 0; 343 int c; 344 345 for (; nb > 0; nb -= c) { 346 c = max_align(ea); 347 if (c > nb) 348 c = max_align(nb); 349 switch (c) { 350 case 1: 351 err = __get_user(*dest, (unsigned char __user *) ea); 352 break; 353 case 2: 354 err = __get_user(*(u16 *)dest, 355 (unsigned short __user *) ea); 356 break; 357 case 4: 358 err = __get_user(*(u32 *)dest, 359 (unsigned int __user *) ea); 360 break; 361 #ifdef __powerpc64__ 362 case 8: 363 err = __get_user(*(unsigned long *)dest, 364 (unsigned long __user *) ea); 365 break; 366 #endif 367 } 368 if (err) { 369 regs->dar = ea; 370 return err; 371 } 372 dest += c; 373 ea += c; 374 } 375 return 0; 376 } 377 378 static nokprobe_inline int read_mem_unaligned(unsigned long *dest, 379 unsigned long ea, int nb, 380 struct pt_regs *regs) 381 { 382 union { 383 unsigned long ul; 384 u8 b[sizeof(unsigned long)]; 385 } u; 386 int i; 387 int err; 388 389 u.ul = 0; 390 i = IS_BE ? sizeof(unsigned long) - nb : 0; 391 err = copy_mem_in(&u.b[i], ea, nb, regs); 392 if (!err) 393 *dest = u.ul; 394 return err; 395 } 396 397 /* 398 * Read memory at address ea for nb bytes, return 0 for success 399 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8. 400 * If nb < sizeof(long), the result is right-justified on BE systems. 401 */ 402 static int read_mem(unsigned long *dest, unsigned long ea, int nb, 403 struct pt_regs *regs) 404 { 405 if (!address_ok(regs, ea, nb)) 406 return -EFAULT; 407 if ((ea & (nb - 1)) == 0) 408 return read_mem_aligned(dest, ea, nb, regs); 409 return read_mem_unaligned(dest, ea, nb, regs); 410 } 411 NOKPROBE_SYMBOL(read_mem); 412 413 static nokprobe_inline int write_mem_aligned(unsigned long val, 414 unsigned long ea, int nb, 415 struct pt_regs *regs) 416 { 417 int err = 0; 418 419 switch (nb) { 420 case 1: 421 err = __put_user(val, (unsigned char __user *) ea); 422 break; 423 case 2: 424 err = __put_user(val, (unsigned short __user *) ea); 425 break; 426 case 4: 427 err = __put_user(val, (unsigned int __user *) ea); 428 break; 429 #ifdef __powerpc64__ 430 case 8: 431 err = __put_user(val, (unsigned long __user *) ea); 432 break; 433 #endif 434 } 435 if (err) 436 regs->dar = ea; 437 return err; 438 } 439 440 /* 441 * Copy from a buffer to userspace, using the largest possible 442 * aligned accesses, up to sizeof(long). 443 */ 444 static nokprobe_inline int copy_mem_out(u8 *dest, unsigned long ea, int nb, 445 struct pt_regs *regs) 446 { 447 int err = 0; 448 int c; 449 450 for (; nb > 0; nb -= c) { 451 c = max_align(ea); 452 if (c > nb) 453 c = max_align(nb); 454 switch (c) { 455 case 1: 456 err = __put_user(*dest, (unsigned char __user *) ea); 457 break; 458 case 2: 459 err = __put_user(*(u16 *)dest, 460 (unsigned short __user *) ea); 461 break; 462 case 4: 463 err = __put_user(*(u32 *)dest, 464 (unsigned int __user *) ea); 465 break; 466 #ifdef __powerpc64__ 467 case 8: 468 err = __put_user(*(unsigned long *)dest, 469 (unsigned long __user *) ea); 470 break; 471 #endif 472 } 473 if (err) { 474 regs->dar = ea; 475 return err; 476 } 477 dest += c; 478 ea += c; 479 } 480 return 0; 481 } 482 483 static nokprobe_inline int write_mem_unaligned(unsigned long val, 484 unsigned long ea, int nb, 485 struct pt_regs *regs) 486 { 487 union { 488 unsigned long ul; 489 u8 b[sizeof(unsigned long)]; 490 } u; 491 int i; 492 493 u.ul = val; 494 i = IS_BE ? sizeof(unsigned long) - nb : 0; 495 return copy_mem_out(&u.b[i], ea, nb, regs); 496 } 497 498 /* 499 * Write memory at address ea for nb bytes, return 0 for success 500 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8. 501 */ 502 static int write_mem(unsigned long val, unsigned long ea, int nb, 503 struct pt_regs *regs) 504 { 505 if (!address_ok(regs, ea, nb)) 506 return -EFAULT; 507 if ((ea & (nb - 1)) == 0) 508 return write_mem_aligned(val, ea, nb, regs); 509 return write_mem_unaligned(val, ea, nb, regs); 510 } 511 NOKPROBE_SYMBOL(write_mem); 512 513 #ifdef CONFIG_PPC_FPU 514 /* 515 * These access either the real FP register or the image in the 516 * thread_struct, depending on regs->msr & MSR_FP. 517 */ 518 static int do_fp_load(struct instruction_op *op, unsigned long ea, 519 struct pt_regs *regs, bool cross_endian) 520 { 521 int err, rn, nb; 522 union { 523 int i; 524 unsigned int u; 525 float f; 526 double d[2]; 527 unsigned long l[2]; 528 u8 b[2 * sizeof(double)]; 529 } u; 530 531 nb = GETSIZE(op->type); 532 if (!address_ok(regs, ea, nb)) 533 return -EFAULT; 534 rn = op->reg; 535 err = copy_mem_in(u.b, ea, nb, regs); 536 if (err) 537 return err; 538 if (unlikely(cross_endian)) { 539 do_byte_reverse(u.b, min(nb, 8)); 540 if (nb == 16) 541 do_byte_reverse(&u.b[8], 8); 542 } 543 preempt_disable(); 544 if (nb == 4) { 545 if (op->type & FPCONV) 546 conv_sp_to_dp(&u.f, &u.d[0]); 547 else if (op->type & SIGNEXT) 548 u.l[0] = u.i; 549 else 550 u.l[0] = u.u; 551 } 552 if (regs->msr & MSR_FP) 553 put_fpr(rn, &u.d[0]); 554 else 555 current->thread.TS_FPR(rn) = u.l[0]; 556 if (nb == 16) { 557 /* lfdp */ 558 rn |= 1; 559 if (regs->msr & MSR_FP) 560 put_fpr(rn, &u.d[1]); 561 else 562 current->thread.TS_FPR(rn) = u.l[1]; 563 } 564 preempt_enable(); 565 return 0; 566 } 567 NOKPROBE_SYMBOL(do_fp_load); 568 569 static int do_fp_store(struct instruction_op *op, unsigned long ea, 570 struct pt_regs *regs, bool cross_endian) 571 { 572 int rn, nb; 573 union { 574 unsigned int u; 575 float f; 576 double d[2]; 577 unsigned long l[2]; 578 u8 b[2 * sizeof(double)]; 579 } u; 580 581 nb = GETSIZE(op->type); 582 if (!address_ok(regs, ea, nb)) 583 return -EFAULT; 584 rn = op->reg; 585 preempt_disable(); 586 if (regs->msr & MSR_FP) 587 get_fpr(rn, &u.d[0]); 588 else 589 u.l[0] = current->thread.TS_FPR(rn); 590 if (nb == 4) { 591 if (op->type & FPCONV) 592 conv_dp_to_sp(&u.d[0], &u.f); 593 else 594 u.u = u.l[0]; 595 } 596 if (nb == 16) { 597 rn |= 1; 598 if (regs->msr & MSR_FP) 599 get_fpr(rn, &u.d[1]); 600 else 601 u.l[1] = current->thread.TS_FPR(rn); 602 } 603 preempt_enable(); 604 if (unlikely(cross_endian)) { 605 do_byte_reverse(u.b, min(nb, 8)); 606 if (nb == 16) 607 do_byte_reverse(&u.b[8], 8); 608 } 609 return copy_mem_out(u.b, ea, nb, regs); 610 } 611 NOKPROBE_SYMBOL(do_fp_store); 612 #endif 613 614 #ifdef CONFIG_ALTIVEC 615 /* For Altivec/VMX, no need to worry about alignment */ 616 static nokprobe_inline int do_vec_load(int rn, unsigned long ea, 617 int size, struct pt_regs *regs, 618 bool cross_endian) 619 { 620 int err; 621 union { 622 __vector128 v; 623 u8 b[sizeof(__vector128)]; 624 } u = {}; 625 626 if (!address_ok(regs, ea & ~0xfUL, 16)) 627 return -EFAULT; 628 /* align to multiple of size */ 629 ea &= ~(size - 1); 630 err = copy_mem_in(&u.b[ea & 0xf], ea, size, regs); 631 if (err) 632 return err; 633 if (unlikely(cross_endian)) 634 do_byte_reverse(&u.b[ea & 0xf], size); 635 preempt_disable(); 636 if (regs->msr & MSR_VEC) 637 put_vr(rn, &u.v); 638 else 639 current->thread.vr_state.vr[rn] = u.v; 640 preempt_enable(); 641 return 0; 642 } 643 644 static nokprobe_inline int do_vec_store(int rn, unsigned long ea, 645 int size, struct pt_regs *regs, 646 bool cross_endian) 647 { 648 union { 649 __vector128 v; 650 u8 b[sizeof(__vector128)]; 651 } u; 652 653 if (!address_ok(regs, ea & ~0xfUL, 16)) 654 return -EFAULT; 655 /* align to multiple of size */ 656 ea &= ~(size - 1); 657 658 preempt_disable(); 659 if (regs->msr & MSR_VEC) 660 get_vr(rn, &u.v); 661 else 662 u.v = current->thread.vr_state.vr[rn]; 663 preempt_enable(); 664 if (unlikely(cross_endian)) 665 do_byte_reverse(&u.b[ea & 0xf], size); 666 return copy_mem_out(&u.b[ea & 0xf], ea, size, regs); 667 } 668 #endif /* CONFIG_ALTIVEC */ 669 670 #ifdef __powerpc64__ 671 static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea, 672 int reg, bool cross_endian) 673 { 674 int err; 675 676 if (!address_ok(regs, ea, 16)) 677 return -EFAULT; 678 /* if aligned, should be atomic */ 679 if ((ea & 0xf) == 0) { 680 err = do_lq(ea, ®s->gpr[reg]); 681 } else { 682 err = read_mem(®s->gpr[reg + IS_LE], ea, 8, regs); 683 if (!err) 684 err = read_mem(®s->gpr[reg + IS_BE], ea + 8, 8, regs); 685 } 686 if (!err && unlikely(cross_endian)) 687 do_byte_reverse(®s->gpr[reg], 16); 688 return err; 689 } 690 691 static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea, 692 int reg, bool cross_endian) 693 { 694 int err; 695 unsigned long vals[2]; 696 697 if (!address_ok(regs, ea, 16)) 698 return -EFAULT; 699 vals[0] = regs->gpr[reg]; 700 vals[1] = regs->gpr[reg + 1]; 701 if (unlikely(cross_endian)) 702 do_byte_reverse(vals, 16); 703 704 /* if aligned, should be atomic */ 705 if ((ea & 0xf) == 0) 706 return do_stq(ea, vals[0], vals[1]); 707 708 err = write_mem(vals[IS_LE], ea, 8, regs); 709 if (!err) 710 err = write_mem(vals[IS_BE], ea + 8, 8, regs); 711 return err; 712 } 713 #endif /* __powerpc64 */ 714 715 #ifdef CONFIG_VSX 716 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg, 717 const void *mem, bool rev) 718 { 719 int size, read_size; 720 int i, j; 721 const unsigned int *wp; 722 const unsigned short *hp; 723 const unsigned char *bp; 724 725 size = GETSIZE(op->type); 726 reg->d[0] = reg->d[1] = 0; 727 728 switch (op->element_size) { 729 case 32: 730 /* [p]lxvp[x] */ 731 case 16: 732 /* whole vector; lxv[x] or lxvl[l] */ 733 if (size == 0) 734 break; 735 memcpy(reg, mem, size); 736 if (IS_LE && (op->vsx_flags & VSX_LDLEFT)) 737 rev = !rev; 738 if (rev) 739 do_byte_reverse(reg, size); 740 break; 741 case 8: 742 /* scalar loads, lxvd2x, lxvdsx */ 743 read_size = (size >= 8) ? 8 : size; 744 i = IS_LE ? 8 : 8 - read_size; 745 memcpy(®->b[i], mem, read_size); 746 if (rev) 747 do_byte_reverse(®->b[i], 8); 748 if (size < 8) { 749 if (op->type & SIGNEXT) { 750 /* size == 4 is the only case here */ 751 reg->d[IS_LE] = (signed int) reg->d[IS_LE]; 752 } else if (op->vsx_flags & VSX_FPCONV) { 753 preempt_disable(); 754 conv_sp_to_dp(®->fp[1 + IS_LE], 755 ®->dp[IS_LE]); 756 preempt_enable(); 757 } 758 } else { 759 if (size == 16) { 760 unsigned long v = *(unsigned long *)(mem + 8); 761 reg->d[IS_BE] = !rev ? v : byterev_8(v); 762 } else if (op->vsx_flags & VSX_SPLAT) 763 reg->d[IS_BE] = reg->d[IS_LE]; 764 } 765 break; 766 case 4: 767 /* lxvw4x, lxvwsx */ 768 wp = mem; 769 for (j = 0; j < size / 4; ++j) { 770 i = IS_LE ? 3 - j : j; 771 reg->w[i] = !rev ? *wp++ : byterev_4(*wp++); 772 } 773 if (op->vsx_flags & VSX_SPLAT) { 774 u32 val = reg->w[IS_LE ? 3 : 0]; 775 for (; j < 4; ++j) { 776 i = IS_LE ? 3 - j : j; 777 reg->w[i] = val; 778 } 779 } 780 break; 781 case 2: 782 /* lxvh8x */ 783 hp = mem; 784 for (j = 0; j < size / 2; ++j) { 785 i = IS_LE ? 7 - j : j; 786 reg->h[i] = !rev ? *hp++ : byterev_2(*hp++); 787 } 788 break; 789 case 1: 790 /* lxvb16x */ 791 bp = mem; 792 for (j = 0; j < size; ++j) { 793 i = IS_LE ? 15 - j : j; 794 reg->b[i] = *bp++; 795 } 796 break; 797 } 798 } 799 EXPORT_SYMBOL_GPL(emulate_vsx_load); 800 NOKPROBE_SYMBOL(emulate_vsx_load); 801 802 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg, 803 void *mem, bool rev) 804 { 805 int size, write_size; 806 int i, j; 807 union vsx_reg buf; 808 unsigned int *wp; 809 unsigned short *hp; 810 unsigned char *bp; 811 812 size = GETSIZE(op->type); 813 814 switch (op->element_size) { 815 case 32: 816 /* [p]stxvp[x] */ 817 if (size == 0) 818 break; 819 if (rev) { 820 /* reverse 32 bytes */ 821 union vsx_reg buf32[2]; 822 buf32[0].d[0] = byterev_8(reg[1].d[1]); 823 buf32[0].d[1] = byterev_8(reg[1].d[0]); 824 buf32[1].d[0] = byterev_8(reg[0].d[1]); 825 buf32[1].d[1] = byterev_8(reg[0].d[0]); 826 memcpy(mem, buf32, size); 827 } else { 828 memcpy(mem, reg, size); 829 } 830 break; 831 case 16: 832 /* stxv, stxvx, stxvl, stxvll */ 833 if (size == 0) 834 break; 835 if (IS_LE && (op->vsx_flags & VSX_LDLEFT)) 836 rev = !rev; 837 if (rev) { 838 /* reverse 16 bytes */ 839 buf.d[0] = byterev_8(reg->d[1]); 840 buf.d[1] = byterev_8(reg->d[0]); 841 reg = &buf; 842 } 843 memcpy(mem, reg, size); 844 break; 845 case 8: 846 /* scalar stores, stxvd2x */ 847 write_size = (size >= 8) ? 8 : size; 848 i = IS_LE ? 8 : 8 - write_size; 849 if (size < 8 && op->vsx_flags & VSX_FPCONV) { 850 buf.d[0] = buf.d[1] = 0; 851 preempt_disable(); 852 conv_dp_to_sp(®->dp[IS_LE], &buf.fp[1 + IS_LE]); 853 preempt_enable(); 854 reg = &buf; 855 } 856 memcpy(mem, ®->b[i], write_size); 857 if (size == 16) 858 memcpy(mem + 8, ®->d[IS_BE], 8); 859 if (unlikely(rev)) { 860 do_byte_reverse(mem, write_size); 861 if (size == 16) 862 do_byte_reverse(mem + 8, 8); 863 } 864 break; 865 case 4: 866 /* stxvw4x */ 867 wp = mem; 868 for (j = 0; j < size / 4; ++j) { 869 i = IS_LE ? 3 - j : j; 870 *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]); 871 } 872 break; 873 case 2: 874 /* stxvh8x */ 875 hp = mem; 876 for (j = 0; j < size / 2; ++j) { 877 i = IS_LE ? 7 - j : j; 878 *hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]); 879 } 880 break; 881 case 1: 882 /* stvxb16x */ 883 bp = mem; 884 for (j = 0; j < size; ++j) { 885 i = IS_LE ? 15 - j : j; 886 *bp++ = reg->b[i]; 887 } 888 break; 889 } 890 } 891 EXPORT_SYMBOL_GPL(emulate_vsx_store); 892 NOKPROBE_SYMBOL(emulate_vsx_store); 893 894 static nokprobe_inline int do_vsx_load(struct instruction_op *op, 895 unsigned long ea, struct pt_regs *regs, 896 bool cross_endian) 897 { 898 int reg = op->reg; 899 int i, j, nr_vsx_regs; 900 u8 mem[32]; 901 union vsx_reg buf[2]; 902 int size = GETSIZE(op->type); 903 904 if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs)) 905 return -EFAULT; 906 907 nr_vsx_regs = max(1ul, size / sizeof(__vector128)); 908 emulate_vsx_load(op, buf, mem, cross_endian); 909 preempt_disable(); 910 if (reg < 32) { 911 /* FP regs + extensions */ 912 if (regs->msr & MSR_FP) { 913 for (i = 0; i < nr_vsx_regs; i++) { 914 j = IS_LE ? nr_vsx_regs - i - 1 : i; 915 load_vsrn(reg + i, &buf[j].v); 916 } 917 } else { 918 for (i = 0; i < nr_vsx_regs; i++) { 919 j = IS_LE ? nr_vsx_regs - i - 1 : i; 920 current->thread.fp_state.fpr[reg + i][0] = buf[j].d[0]; 921 current->thread.fp_state.fpr[reg + i][1] = buf[j].d[1]; 922 } 923 } 924 } else { 925 if (regs->msr & MSR_VEC) { 926 for (i = 0; i < nr_vsx_regs; i++) { 927 j = IS_LE ? nr_vsx_regs - i - 1 : i; 928 load_vsrn(reg + i, &buf[j].v); 929 } 930 } else { 931 for (i = 0; i < nr_vsx_regs; i++) { 932 j = IS_LE ? nr_vsx_regs - i - 1 : i; 933 current->thread.vr_state.vr[reg - 32 + i] = buf[j].v; 934 } 935 } 936 } 937 preempt_enable(); 938 return 0; 939 } 940 941 static nokprobe_inline int do_vsx_store(struct instruction_op *op, 942 unsigned long ea, struct pt_regs *regs, 943 bool cross_endian) 944 { 945 int reg = op->reg; 946 int i, j, nr_vsx_regs; 947 u8 mem[32]; 948 union vsx_reg buf[2]; 949 int size = GETSIZE(op->type); 950 951 if (!address_ok(regs, ea, size)) 952 return -EFAULT; 953 954 nr_vsx_regs = max(1ul, size / sizeof(__vector128)); 955 preempt_disable(); 956 if (reg < 32) { 957 /* FP regs + extensions */ 958 if (regs->msr & MSR_FP) { 959 for (i = 0; i < nr_vsx_regs; i++) { 960 j = IS_LE ? nr_vsx_regs - i - 1 : i; 961 store_vsrn(reg + i, &buf[j].v); 962 } 963 } else { 964 for (i = 0; i < nr_vsx_regs; i++) { 965 j = IS_LE ? nr_vsx_regs - i - 1 : i; 966 buf[j].d[0] = current->thread.fp_state.fpr[reg + i][0]; 967 buf[j].d[1] = current->thread.fp_state.fpr[reg + i][1]; 968 } 969 } 970 } else { 971 if (regs->msr & MSR_VEC) { 972 for (i = 0; i < nr_vsx_regs; i++) { 973 j = IS_LE ? nr_vsx_regs - i - 1 : i; 974 store_vsrn(reg + i, &buf[j].v); 975 } 976 } else { 977 for (i = 0; i < nr_vsx_regs; i++) { 978 j = IS_LE ? nr_vsx_regs - i - 1 : i; 979 buf[j].v = current->thread.vr_state.vr[reg - 32 + i]; 980 } 981 } 982 } 983 preempt_enable(); 984 emulate_vsx_store(op, buf, mem, cross_endian); 985 return copy_mem_out(mem, ea, size, regs); 986 } 987 #endif /* CONFIG_VSX */ 988 989 int emulate_dcbz(unsigned long ea, struct pt_regs *regs) 990 { 991 int err; 992 unsigned long i, size; 993 994 #ifdef __powerpc64__ 995 size = ppc64_caches.l1d.block_size; 996 if (!(regs->msr & MSR_64BIT)) 997 ea &= 0xffffffffUL; 998 #else 999 size = L1_CACHE_BYTES; 1000 #endif 1001 ea &= ~(size - 1); 1002 if (!address_ok(regs, ea, size)) 1003 return -EFAULT; 1004 for (i = 0; i < size; i += sizeof(long)) { 1005 err = __put_user(0, (unsigned long __user *) (ea + i)); 1006 if (err) { 1007 regs->dar = ea; 1008 return err; 1009 } 1010 } 1011 return 0; 1012 } 1013 NOKPROBE_SYMBOL(emulate_dcbz); 1014 1015 #define __put_user_asmx(x, addr, err, op, cr) \ 1016 __asm__ __volatile__( \ 1017 "1: " op " %2,0,%3\n" \ 1018 " mfcr %1\n" \ 1019 "2:\n" \ 1020 ".section .fixup,\"ax\"\n" \ 1021 "3: li %0,%4\n" \ 1022 " b 2b\n" \ 1023 ".previous\n" \ 1024 EX_TABLE(1b, 3b) \ 1025 : "=r" (err), "=r" (cr) \ 1026 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err)) 1027 1028 #define __get_user_asmx(x, addr, err, op) \ 1029 __asm__ __volatile__( \ 1030 "1: "op" %1,0,%2\n" \ 1031 "2:\n" \ 1032 ".section .fixup,\"ax\"\n" \ 1033 "3: li %0,%3\n" \ 1034 " b 2b\n" \ 1035 ".previous\n" \ 1036 EX_TABLE(1b, 3b) \ 1037 : "=r" (err), "=r" (x) \ 1038 : "r" (addr), "i" (-EFAULT), "0" (err)) 1039 1040 #define __cacheop_user_asmx(addr, err, op) \ 1041 __asm__ __volatile__( \ 1042 "1: "op" 0,%1\n" \ 1043 "2:\n" \ 1044 ".section .fixup,\"ax\"\n" \ 1045 "3: li %0,%3\n" \ 1046 " b 2b\n" \ 1047 ".previous\n" \ 1048 EX_TABLE(1b, 3b) \ 1049 : "=r" (err) \ 1050 : "r" (addr), "i" (-EFAULT), "0" (err)) 1051 1052 static nokprobe_inline void set_cr0(const struct pt_regs *regs, 1053 struct instruction_op *op) 1054 { 1055 long val = op->val; 1056 1057 op->type |= SETCC; 1058 op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000); 1059 #ifdef __powerpc64__ 1060 if (!(regs->msr & MSR_64BIT)) 1061 val = (int) val; 1062 #endif 1063 if (val < 0) 1064 op->ccval |= 0x80000000; 1065 else if (val > 0) 1066 op->ccval |= 0x40000000; 1067 else 1068 op->ccval |= 0x20000000; 1069 } 1070 1071 static nokprobe_inline void set_ca32(struct instruction_op *op, bool val) 1072 { 1073 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 1074 if (val) 1075 op->xerval |= XER_CA32; 1076 else 1077 op->xerval &= ~XER_CA32; 1078 } 1079 } 1080 1081 static nokprobe_inline void add_with_carry(const struct pt_regs *regs, 1082 struct instruction_op *op, int rd, 1083 unsigned long val1, unsigned long val2, 1084 unsigned long carry_in) 1085 { 1086 unsigned long val = val1 + val2; 1087 1088 if (carry_in) 1089 ++val; 1090 op->type = COMPUTE + SETREG + SETXER; 1091 op->reg = rd; 1092 op->val = val; 1093 #ifdef __powerpc64__ 1094 if (!(regs->msr & MSR_64BIT)) { 1095 val = (unsigned int) val; 1096 val1 = (unsigned int) val1; 1097 } 1098 #endif 1099 op->xerval = regs->xer; 1100 if (val < val1 || (carry_in && val == val1)) 1101 op->xerval |= XER_CA; 1102 else 1103 op->xerval &= ~XER_CA; 1104 1105 set_ca32(op, (unsigned int)val < (unsigned int)val1 || 1106 (carry_in && (unsigned int)val == (unsigned int)val1)); 1107 } 1108 1109 static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs, 1110 struct instruction_op *op, 1111 long v1, long v2, int crfld) 1112 { 1113 unsigned int crval, shift; 1114 1115 op->type = COMPUTE + SETCC; 1116 crval = (regs->xer >> 31) & 1; /* get SO bit */ 1117 if (v1 < v2) 1118 crval |= 8; 1119 else if (v1 > v2) 1120 crval |= 4; 1121 else 1122 crval |= 2; 1123 shift = (7 - crfld) * 4; 1124 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift); 1125 } 1126 1127 static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs, 1128 struct instruction_op *op, 1129 unsigned long v1, 1130 unsigned long v2, int crfld) 1131 { 1132 unsigned int crval, shift; 1133 1134 op->type = COMPUTE + SETCC; 1135 crval = (regs->xer >> 31) & 1; /* get SO bit */ 1136 if (v1 < v2) 1137 crval |= 8; 1138 else if (v1 > v2) 1139 crval |= 4; 1140 else 1141 crval |= 2; 1142 shift = (7 - crfld) * 4; 1143 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift); 1144 } 1145 1146 static nokprobe_inline void do_cmpb(const struct pt_regs *regs, 1147 struct instruction_op *op, 1148 unsigned long v1, unsigned long v2) 1149 { 1150 unsigned long long out_val, mask; 1151 int i; 1152 1153 out_val = 0; 1154 for (i = 0; i < 8; i++) { 1155 mask = 0xffUL << (i * 8); 1156 if ((v1 & mask) == (v2 & mask)) 1157 out_val |= mask; 1158 } 1159 op->val = out_val; 1160 } 1161 1162 /* 1163 * The size parameter is used to adjust the equivalent popcnt instruction. 1164 * popcntb = 8, popcntw = 32, popcntd = 64 1165 */ 1166 static nokprobe_inline void do_popcnt(const struct pt_regs *regs, 1167 struct instruction_op *op, 1168 unsigned long v1, int size) 1169 { 1170 unsigned long long out = v1; 1171 1172 out -= (out >> 1) & 0x5555555555555555ULL; 1173 out = (0x3333333333333333ULL & out) + 1174 (0x3333333333333333ULL & (out >> 2)); 1175 out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0fULL; 1176 1177 if (size == 8) { /* popcntb */ 1178 op->val = out; 1179 return; 1180 } 1181 out += out >> 8; 1182 out += out >> 16; 1183 if (size == 32) { /* popcntw */ 1184 op->val = out & 0x0000003f0000003fULL; 1185 return; 1186 } 1187 1188 out = (out + (out >> 32)) & 0x7f; 1189 op->val = out; /* popcntd */ 1190 } 1191 1192 #ifdef CONFIG_PPC64 1193 static nokprobe_inline void do_bpermd(const struct pt_regs *regs, 1194 struct instruction_op *op, 1195 unsigned long v1, unsigned long v2) 1196 { 1197 unsigned char perm, idx; 1198 unsigned int i; 1199 1200 perm = 0; 1201 for (i = 0; i < 8; i++) { 1202 idx = (v1 >> (i * 8)) & 0xff; 1203 if (idx < 64) 1204 if (v2 & PPC_BIT(idx)) 1205 perm |= 1 << i; 1206 } 1207 op->val = perm; 1208 } 1209 #endif /* CONFIG_PPC64 */ 1210 /* 1211 * The size parameter adjusts the equivalent prty instruction. 1212 * prtyw = 32, prtyd = 64 1213 */ 1214 static nokprobe_inline void do_prty(const struct pt_regs *regs, 1215 struct instruction_op *op, 1216 unsigned long v, int size) 1217 { 1218 unsigned long long res = v ^ (v >> 8); 1219 1220 res ^= res >> 16; 1221 if (size == 32) { /* prtyw */ 1222 op->val = res & 0x0000000100000001ULL; 1223 return; 1224 } 1225 1226 res ^= res >> 32; 1227 op->val = res & 1; /*prtyd */ 1228 } 1229 1230 static nokprobe_inline int trap_compare(long v1, long v2) 1231 { 1232 int ret = 0; 1233 1234 if (v1 < v2) 1235 ret |= 0x10; 1236 else if (v1 > v2) 1237 ret |= 0x08; 1238 else 1239 ret |= 0x04; 1240 if ((unsigned long)v1 < (unsigned long)v2) 1241 ret |= 0x02; 1242 else if ((unsigned long)v1 > (unsigned long)v2) 1243 ret |= 0x01; 1244 return ret; 1245 } 1246 1247 /* 1248 * Elements of 32-bit rotate and mask instructions. 1249 */ 1250 #define MASK32(mb, me) ((0xffffffffUL >> (mb)) + \ 1251 ((signed long)-0x80000000L >> (me)) + ((me) >= (mb))) 1252 #ifdef __powerpc64__ 1253 #define MASK64_L(mb) (~0UL >> (mb)) 1254 #define MASK64_R(me) ((signed long)-0x8000000000000000L >> (me)) 1255 #define MASK64(mb, me) (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb))) 1256 #define DATA32(x) (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32)) 1257 #else 1258 #define DATA32(x) (x) 1259 #endif 1260 #define ROTATE(x, n) ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x)) 1261 1262 /* 1263 * Decode an instruction, and return information about it in *op 1264 * without changing *regs. 1265 * Integer arithmetic and logical instructions, branches, and barrier 1266 * instructions can be emulated just using the information in *op. 1267 * 1268 * Return value is 1 if the instruction can be emulated just by 1269 * updating *regs with the information in *op, -1 if we need the 1270 * GPRs but *regs doesn't contain the full register set, or 0 1271 * otherwise. 1272 */ 1273 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, 1274 struct ppc_inst instr) 1275 { 1276 #ifdef CONFIG_PPC64 1277 unsigned int suffixopcode, prefixtype, prefix_r; 1278 #endif 1279 unsigned int opcode, ra, rb, rc, rd, spr, u; 1280 unsigned long int imm; 1281 unsigned long int val, val2; 1282 unsigned int mb, me, sh; 1283 unsigned int word, suffix; 1284 long ival; 1285 1286 word = ppc_inst_val(instr); 1287 suffix = ppc_inst_suffix(instr); 1288 1289 op->type = COMPUTE; 1290 1291 opcode = ppc_inst_primary_opcode(instr); 1292 switch (opcode) { 1293 case 16: /* bc */ 1294 op->type = BRANCH; 1295 imm = (signed short)(word & 0xfffc); 1296 if ((word & 2) == 0) 1297 imm += regs->nip; 1298 op->val = truncate_if_32bit(regs->msr, imm); 1299 if (word & 1) 1300 op->type |= SETLK; 1301 if (branch_taken(word, regs, op)) 1302 op->type |= BRTAKEN; 1303 return 1; 1304 #ifdef CONFIG_PPC64 1305 case 17: /* sc */ 1306 if ((word & 0xfe2) == 2) 1307 op->type = SYSCALL; 1308 else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && 1309 (word & 0xfe3) == 1) { /* scv */ 1310 op->type = SYSCALL_VECTORED_0; 1311 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1312 goto unknown_opcode; 1313 } else 1314 op->type = UNKNOWN; 1315 return 0; 1316 #endif 1317 case 18: /* b */ 1318 op->type = BRANCH | BRTAKEN; 1319 imm = word & 0x03fffffc; 1320 if (imm & 0x02000000) 1321 imm -= 0x04000000; 1322 if ((word & 2) == 0) 1323 imm += regs->nip; 1324 op->val = truncate_if_32bit(regs->msr, imm); 1325 if (word & 1) 1326 op->type |= SETLK; 1327 return 1; 1328 case 19: 1329 switch ((word >> 1) & 0x3ff) { 1330 case 0: /* mcrf */ 1331 op->type = COMPUTE + SETCC; 1332 rd = 7 - ((word >> 23) & 0x7); 1333 ra = 7 - ((word >> 18) & 0x7); 1334 rd *= 4; 1335 ra *= 4; 1336 val = (regs->ccr >> ra) & 0xf; 1337 op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd); 1338 return 1; 1339 1340 case 16: /* bclr */ 1341 case 528: /* bcctr */ 1342 op->type = BRANCH; 1343 imm = (word & 0x400)? regs->ctr: regs->link; 1344 op->val = truncate_if_32bit(regs->msr, imm); 1345 if (word & 1) 1346 op->type |= SETLK; 1347 if (branch_taken(word, regs, op)) 1348 op->type |= BRTAKEN; 1349 return 1; 1350 1351 case 18: /* rfid, scary */ 1352 if (regs->msr & MSR_PR) 1353 goto priv; 1354 op->type = RFI; 1355 return 0; 1356 1357 case 150: /* isync */ 1358 op->type = BARRIER | BARRIER_ISYNC; 1359 return 1; 1360 1361 case 33: /* crnor */ 1362 case 129: /* crandc */ 1363 case 193: /* crxor */ 1364 case 225: /* crnand */ 1365 case 257: /* crand */ 1366 case 289: /* creqv */ 1367 case 417: /* crorc */ 1368 case 449: /* cror */ 1369 op->type = COMPUTE + SETCC; 1370 ra = (word >> 16) & 0x1f; 1371 rb = (word >> 11) & 0x1f; 1372 rd = (word >> 21) & 0x1f; 1373 ra = (regs->ccr >> (31 - ra)) & 1; 1374 rb = (regs->ccr >> (31 - rb)) & 1; 1375 val = (word >> (6 + ra * 2 + rb)) & 1; 1376 op->ccval = (regs->ccr & ~(1UL << (31 - rd))) | 1377 (val << (31 - rd)); 1378 return 1; 1379 } 1380 break; 1381 case 31: 1382 switch ((word >> 1) & 0x3ff) { 1383 case 598: /* sync */ 1384 op->type = BARRIER + BARRIER_SYNC; 1385 #ifdef __powerpc64__ 1386 switch ((word >> 21) & 3) { 1387 case 1: /* lwsync */ 1388 op->type = BARRIER + BARRIER_LWSYNC; 1389 break; 1390 case 2: /* ptesync */ 1391 op->type = BARRIER + BARRIER_PTESYNC; 1392 break; 1393 } 1394 #endif 1395 return 1; 1396 1397 case 854: /* eieio */ 1398 op->type = BARRIER + BARRIER_EIEIO; 1399 return 1; 1400 } 1401 break; 1402 } 1403 1404 /* Following cases refer to regs->gpr[], so we need all regs */ 1405 if (!FULL_REGS(regs)) 1406 return -1; 1407 1408 rd = (word >> 21) & 0x1f; 1409 ra = (word >> 16) & 0x1f; 1410 rb = (word >> 11) & 0x1f; 1411 rc = (word >> 6) & 0x1f; 1412 1413 switch (opcode) { 1414 #ifdef __powerpc64__ 1415 case 1: 1416 if (!cpu_has_feature(CPU_FTR_ARCH_31)) 1417 goto unknown_opcode; 1418 1419 prefix_r = GET_PREFIX_R(word); 1420 ra = GET_PREFIX_RA(suffix); 1421 rd = (suffix >> 21) & 0x1f; 1422 op->reg = rd; 1423 op->val = regs->gpr[rd]; 1424 suffixopcode = get_op(suffix); 1425 prefixtype = (word >> 24) & 0x3; 1426 switch (prefixtype) { 1427 case 2: 1428 if (prefix_r && ra) 1429 return 0; 1430 switch (suffixopcode) { 1431 case 14: /* paddi */ 1432 op->type = COMPUTE | PREFIXED; 1433 op->val = mlsd_8lsd_ea(word, suffix, regs); 1434 goto compute_done; 1435 } 1436 } 1437 break; 1438 case 2: /* tdi */ 1439 if (rd & trap_compare(regs->gpr[ra], (short) word)) 1440 goto trap; 1441 return 1; 1442 #endif 1443 case 3: /* twi */ 1444 if (rd & trap_compare((int)regs->gpr[ra], (short) word)) 1445 goto trap; 1446 return 1; 1447 1448 #ifdef __powerpc64__ 1449 case 4: 1450 /* 1451 * There are very many instructions with this primary opcode 1452 * introduced in the ISA as early as v2.03. However, the ones 1453 * we currently emulate were all introduced with ISA 3.0 1454 */ 1455 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1456 goto unknown_opcode; 1457 1458 switch (word & 0x3f) { 1459 case 48: /* maddhd */ 1460 asm volatile(PPC_MADDHD(%0, %1, %2, %3) : 1461 "=r" (op->val) : "r" (regs->gpr[ra]), 1462 "r" (regs->gpr[rb]), "r" (regs->gpr[rc])); 1463 goto compute_done; 1464 1465 case 49: /* maddhdu */ 1466 asm volatile(PPC_MADDHDU(%0, %1, %2, %3) : 1467 "=r" (op->val) : "r" (regs->gpr[ra]), 1468 "r" (regs->gpr[rb]), "r" (regs->gpr[rc])); 1469 goto compute_done; 1470 1471 case 51: /* maddld */ 1472 asm volatile(PPC_MADDLD(%0, %1, %2, %3) : 1473 "=r" (op->val) : "r" (regs->gpr[ra]), 1474 "r" (regs->gpr[rb]), "r" (regs->gpr[rc])); 1475 goto compute_done; 1476 } 1477 1478 /* 1479 * There are other instructions from ISA 3.0 with the same 1480 * primary opcode which do not have emulation support yet. 1481 */ 1482 goto unknown_opcode; 1483 #endif 1484 1485 case 7: /* mulli */ 1486 op->val = regs->gpr[ra] * (short) word; 1487 goto compute_done; 1488 1489 case 8: /* subfic */ 1490 imm = (short) word; 1491 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1); 1492 return 1; 1493 1494 case 10: /* cmpli */ 1495 imm = (unsigned short) word; 1496 val = regs->gpr[ra]; 1497 #ifdef __powerpc64__ 1498 if ((rd & 1) == 0) 1499 val = (unsigned int) val; 1500 #endif 1501 do_cmp_unsigned(regs, op, val, imm, rd >> 2); 1502 return 1; 1503 1504 case 11: /* cmpi */ 1505 imm = (short) word; 1506 val = regs->gpr[ra]; 1507 #ifdef __powerpc64__ 1508 if ((rd & 1) == 0) 1509 val = (int) val; 1510 #endif 1511 do_cmp_signed(regs, op, val, imm, rd >> 2); 1512 return 1; 1513 1514 case 12: /* addic */ 1515 imm = (short) word; 1516 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0); 1517 return 1; 1518 1519 case 13: /* addic. */ 1520 imm = (short) word; 1521 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0); 1522 set_cr0(regs, op); 1523 return 1; 1524 1525 case 14: /* addi */ 1526 imm = (short) word; 1527 if (ra) 1528 imm += regs->gpr[ra]; 1529 op->val = imm; 1530 goto compute_done; 1531 1532 case 15: /* addis */ 1533 imm = ((short) word) << 16; 1534 if (ra) 1535 imm += regs->gpr[ra]; 1536 op->val = imm; 1537 goto compute_done; 1538 1539 case 19: 1540 if (((word >> 1) & 0x1f) == 2) { 1541 /* addpcis */ 1542 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1543 goto unknown_opcode; 1544 imm = (short) (word & 0xffc1); /* d0 + d2 fields */ 1545 imm |= (word >> 15) & 0x3e; /* d1 field */ 1546 op->val = regs->nip + (imm << 16) + 4; 1547 goto compute_done; 1548 } 1549 op->type = UNKNOWN; 1550 return 0; 1551 1552 case 20: /* rlwimi */ 1553 mb = (word >> 6) & 0x1f; 1554 me = (word >> 1) & 0x1f; 1555 val = DATA32(regs->gpr[rd]); 1556 imm = MASK32(mb, me); 1557 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm); 1558 goto logical_done; 1559 1560 case 21: /* rlwinm */ 1561 mb = (word >> 6) & 0x1f; 1562 me = (word >> 1) & 0x1f; 1563 val = DATA32(regs->gpr[rd]); 1564 op->val = ROTATE(val, rb) & MASK32(mb, me); 1565 goto logical_done; 1566 1567 case 23: /* rlwnm */ 1568 mb = (word >> 6) & 0x1f; 1569 me = (word >> 1) & 0x1f; 1570 rb = regs->gpr[rb] & 0x1f; 1571 val = DATA32(regs->gpr[rd]); 1572 op->val = ROTATE(val, rb) & MASK32(mb, me); 1573 goto logical_done; 1574 1575 case 24: /* ori */ 1576 op->val = regs->gpr[rd] | (unsigned short) word; 1577 goto logical_done_nocc; 1578 1579 case 25: /* oris */ 1580 imm = (unsigned short) word; 1581 op->val = regs->gpr[rd] | (imm << 16); 1582 goto logical_done_nocc; 1583 1584 case 26: /* xori */ 1585 op->val = regs->gpr[rd] ^ (unsigned short) word; 1586 goto logical_done_nocc; 1587 1588 case 27: /* xoris */ 1589 imm = (unsigned short) word; 1590 op->val = regs->gpr[rd] ^ (imm << 16); 1591 goto logical_done_nocc; 1592 1593 case 28: /* andi. */ 1594 op->val = regs->gpr[rd] & (unsigned short) word; 1595 set_cr0(regs, op); 1596 goto logical_done_nocc; 1597 1598 case 29: /* andis. */ 1599 imm = (unsigned short) word; 1600 op->val = regs->gpr[rd] & (imm << 16); 1601 set_cr0(regs, op); 1602 goto logical_done_nocc; 1603 1604 #ifdef __powerpc64__ 1605 case 30: /* rld* */ 1606 mb = ((word >> 6) & 0x1f) | (word & 0x20); 1607 val = regs->gpr[rd]; 1608 if ((word & 0x10) == 0) { 1609 sh = rb | ((word & 2) << 4); 1610 val = ROTATE(val, sh); 1611 switch ((word >> 2) & 3) { 1612 case 0: /* rldicl */ 1613 val &= MASK64_L(mb); 1614 break; 1615 case 1: /* rldicr */ 1616 val &= MASK64_R(mb); 1617 break; 1618 case 2: /* rldic */ 1619 val &= MASK64(mb, 63 - sh); 1620 break; 1621 case 3: /* rldimi */ 1622 imm = MASK64(mb, 63 - sh); 1623 val = (regs->gpr[ra] & ~imm) | 1624 (val & imm); 1625 } 1626 op->val = val; 1627 goto logical_done; 1628 } else { 1629 sh = regs->gpr[rb] & 0x3f; 1630 val = ROTATE(val, sh); 1631 switch ((word >> 1) & 7) { 1632 case 0: /* rldcl */ 1633 op->val = val & MASK64_L(mb); 1634 goto logical_done; 1635 case 1: /* rldcr */ 1636 op->val = val & MASK64_R(mb); 1637 goto logical_done; 1638 } 1639 } 1640 #endif 1641 op->type = UNKNOWN; /* illegal instruction */ 1642 return 0; 1643 1644 case 31: 1645 /* isel occupies 32 minor opcodes */ 1646 if (((word >> 1) & 0x1f) == 15) { 1647 mb = (word >> 6) & 0x1f; /* bc field */ 1648 val = (regs->ccr >> (31 - mb)) & 1; 1649 val2 = (ra) ? regs->gpr[ra] : 0; 1650 1651 op->val = (val) ? val2 : regs->gpr[rb]; 1652 goto compute_done; 1653 } 1654 1655 switch ((word >> 1) & 0x3ff) { 1656 case 4: /* tw */ 1657 if (rd == 0x1f || 1658 (rd & trap_compare((int)regs->gpr[ra], 1659 (int)regs->gpr[rb]))) 1660 goto trap; 1661 return 1; 1662 #ifdef __powerpc64__ 1663 case 68: /* td */ 1664 if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb])) 1665 goto trap; 1666 return 1; 1667 #endif 1668 case 83: /* mfmsr */ 1669 if (regs->msr & MSR_PR) 1670 goto priv; 1671 op->type = MFMSR; 1672 op->reg = rd; 1673 return 0; 1674 case 146: /* mtmsr */ 1675 if (regs->msr & MSR_PR) 1676 goto priv; 1677 op->type = MTMSR; 1678 op->reg = rd; 1679 op->val = 0xffffffff & ~(MSR_ME | MSR_LE); 1680 return 0; 1681 #ifdef CONFIG_PPC64 1682 case 178: /* mtmsrd */ 1683 if (regs->msr & MSR_PR) 1684 goto priv; 1685 op->type = MTMSR; 1686 op->reg = rd; 1687 /* only MSR_EE and MSR_RI get changed if bit 15 set */ 1688 /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */ 1689 imm = (word & 0x10000)? 0x8002: 0xefffffffffffeffeUL; 1690 op->val = imm; 1691 return 0; 1692 #endif 1693 1694 case 19: /* mfcr */ 1695 imm = 0xffffffffUL; 1696 if ((word >> 20) & 1) { 1697 imm = 0xf0000000UL; 1698 for (sh = 0; sh < 8; ++sh) { 1699 if (word & (0x80000 >> sh)) 1700 break; 1701 imm >>= 4; 1702 } 1703 } 1704 op->val = regs->ccr & imm; 1705 goto compute_done; 1706 1707 case 144: /* mtcrf */ 1708 op->type = COMPUTE + SETCC; 1709 imm = 0xf0000000UL; 1710 val = regs->gpr[rd]; 1711 op->ccval = regs->ccr; 1712 for (sh = 0; sh < 8; ++sh) { 1713 if (word & (0x80000 >> sh)) 1714 op->ccval = (op->ccval & ~imm) | 1715 (val & imm); 1716 imm >>= 4; 1717 } 1718 return 1; 1719 1720 case 339: /* mfspr */ 1721 spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0); 1722 op->type = MFSPR; 1723 op->reg = rd; 1724 op->spr = spr; 1725 if (spr == SPRN_XER || spr == SPRN_LR || 1726 spr == SPRN_CTR) 1727 return 1; 1728 return 0; 1729 1730 case 467: /* mtspr */ 1731 spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0); 1732 op->type = MTSPR; 1733 op->val = regs->gpr[rd]; 1734 op->spr = spr; 1735 if (spr == SPRN_XER || spr == SPRN_LR || 1736 spr == SPRN_CTR) 1737 return 1; 1738 return 0; 1739 1740 /* 1741 * Compare instructions 1742 */ 1743 case 0: /* cmp */ 1744 val = regs->gpr[ra]; 1745 val2 = regs->gpr[rb]; 1746 #ifdef __powerpc64__ 1747 if ((rd & 1) == 0) { 1748 /* word (32-bit) compare */ 1749 val = (int) val; 1750 val2 = (int) val2; 1751 } 1752 #endif 1753 do_cmp_signed(regs, op, val, val2, rd >> 2); 1754 return 1; 1755 1756 case 32: /* cmpl */ 1757 val = regs->gpr[ra]; 1758 val2 = regs->gpr[rb]; 1759 #ifdef __powerpc64__ 1760 if ((rd & 1) == 0) { 1761 /* word (32-bit) compare */ 1762 val = (unsigned int) val; 1763 val2 = (unsigned int) val2; 1764 } 1765 #endif 1766 do_cmp_unsigned(regs, op, val, val2, rd >> 2); 1767 return 1; 1768 1769 case 508: /* cmpb */ 1770 do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]); 1771 goto logical_done_nocc; 1772 1773 /* 1774 * Arithmetic instructions 1775 */ 1776 case 8: /* subfc */ 1777 add_with_carry(regs, op, rd, ~regs->gpr[ra], 1778 regs->gpr[rb], 1); 1779 goto arith_done; 1780 #ifdef __powerpc64__ 1781 case 9: /* mulhdu */ 1782 asm("mulhdu %0,%1,%2" : "=r" (op->val) : 1783 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); 1784 goto arith_done; 1785 #endif 1786 case 10: /* addc */ 1787 add_with_carry(regs, op, rd, regs->gpr[ra], 1788 regs->gpr[rb], 0); 1789 goto arith_done; 1790 1791 case 11: /* mulhwu */ 1792 asm("mulhwu %0,%1,%2" : "=r" (op->val) : 1793 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); 1794 goto arith_done; 1795 1796 case 40: /* subf */ 1797 op->val = regs->gpr[rb] - regs->gpr[ra]; 1798 goto arith_done; 1799 #ifdef __powerpc64__ 1800 case 73: /* mulhd */ 1801 asm("mulhd %0,%1,%2" : "=r" (op->val) : 1802 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); 1803 goto arith_done; 1804 #endif 1805 case 75: /* mulhw */ 1806 asm("mulhw %0,%1,%2" : "=r" (op->val) : 1807 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); 1808 goto arith_done; 1809 1810 case 104: /* neg */ 1811 op->val = -regs->gpr[ra]; 1812 goto arith_done; 1813 1814 case 136: /* subfe */ 1815 add_with_carry(regs, op, rd, ~regs->gpr[ra], 1816 regs->gpr[rb], regs->xer & XER_CA); 1817 goto arith_done; 1818 1819 case 138: /* adde */ 1820 add_with_carry(regs, op, rd, regs->gpr[ra], 1821 regs->gpr[rb], regs->xer & XER_CA); 1822 goto arith_done; 1823 1824 case 200: /* subfze */ 1825 add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L, 1826 regs->xer & XER_CA); 1827 goto arith_done; 1828 1829 case 202: /* addze */ 1830 add_with_carry(regs, op, rd, regs->gpr[ra], 0L, 1831 regs->xer & XER_CA); 1832 goto arith_done; 1833 1834 case 232: /* subfme */ 1835 add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L, 1836 regs->xer & XER_CA); 1837 goto arith_done; 1838 #ifdef __powerpc64__ 1839 case 233: /* mulld */ 1840 op->val = regs->gpr[ra] * regs->gpr[rb]; 1841 goto arith_done; 1842 #endif 1843 case 234: /* addme */ 1844 add_with_carry(regs, op, rd, regs->gpr[ra], -1L, 1845 regs->xer & XER_CA); 1846 goto arith_done; 1847 1848 case 235: /* mullw */ 1849 op->val = (long)(int) regs->gpr[ra] * 1850 (int) regs->gpr[rb]; 1851 1852 goto arith_done; 1853 #ifdef __powerpc64__ 1854 case 265: /* modud */ 1855 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1856 goto unknown_opcode; 1857 op->val = regs->gpr[ra] % regs->gpr[rb]; 1858 goto compute_done; 1859 #endif 1860 case 266: /* add */ 1861 op->val = regs->gpr[ra] + regs->gpr[rb]; 1862 goto arith_done; 1863 1864 case 267: /* moduw */ 1865 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1866 goto unknown_opcode; 1867 op->val = (unsigned int) regs->gpr[ra] % 1868 (unsigned int) regs->gpr[rb]; 1869 goto compute_done; 1870 #ifdef __powerpc64__ 1871 case 457: /* divdu */ 1872 op->val = regs->gpr[ra] / regs->gpr[rb]; 1873 goto arith_done; 1874 #endif 1875 case 459: /* divwu */ 1876 op->val = (unsigned int) regs->gpr[ra] / 1877 (unsigned int) regs->gpr[rb]; 1878 goto arith_done; 1879 #ifdef __powerpc64__ 1880 case 489: /* divd */ 1881 op->val = (long int) regs->gpr[ra] / 1882 (long int) regs->gpr[rb]; 1883 goto arith_done; 1884 #endif 1885 case 491: /* divw */ 1886 op->val = (int) regs->gpr[ra] / 1887 (int) regs->gpr[rb]; 1888 goto arith_done; 1889 #ifdef __powerpc64__ 1890 case 425: /* divde[.] */ 1891 asm volatile(PPC_DIVDE(%0, %1, %2) : 1892 "=r" (op->val) : "r" (regs->gpr[ra]), 1893 "r" (regs->gpr[rb])); 1894 goto arith_done; 1895 case 393: /* divdeu[.] */ 1896 asm volatile(PPC_DIVDEU(%0, %1, %2) : 1897 "=r" (op->val) : "r" (regs->gpr[ra]), 1898 "r" (regs->gpr[rb])); 1899 goto arith_done; 1900 #endif 1901 case 755: /* darn */ 1902 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1903 goto unknown_opcode; 1904 switch (ra & 0x3) { 1905 case 0: 1906 /* 32-bit conditioned */ 1907 asm volatile(PPC_DARN(%0, 0) : "=r" (op->val)); 1908 goto compute_done; 1909 1910 case 1: 1911 /* 64-bit conditioned */ 1912 asm volatile(PPC_DARN(%0, 1) : "=r" (op->val)); 1913 goto compute_done; 1914 1915 case 2: 1916 /* 64-bit raw */ 1917 asm volatile(PPC_DARN(%0, 2) : "=r" (op->val)); 1918 goto compute_done; 1919 } 1920 1921 goto unknown_opcode; 1922 #ifdef __powerpc64__ 1923 case 777: /* modsd */ 1924 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1925 goto unknown_opcode; 1926 op->val = (long int) regs->gpr[ra] % 1927 (long int) regs->gpr[rb]; 1928 goto compute_done; 1929 #endif 1930 case 779: /* modsw */ 1931 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1932 goto unknown_opcode; 1933 op->val = (int) regs->gpr[ra] % 1934 (int) regs->gpr[rb]; 1935 goto compute_done; 1936 1937 1938 /* 1939 * Logical instructions 1940 */ 1941 case 26: /* cntlzw */ 1942 val = (unsigned int) regs->gpr[rd]; 1943 op->val = ( val ? __builtin_clz(val) : 32 ); 1944 goto logical_done; 1945 #ifdef __powerpc64__ 1946 case 58: /* cntlzd */ 1947 val = regs->gpr[rd]; 1948 op->val = ( val ? __builtin_clzl(val) : 64 ); 1949 goto logical_done; 1950 #endif 1951 case 28: /* and */ 1952 op->val = regs->gpr[rd] & regs->gpr[rb]; 1953 goto logical_done; 1954 1955 case 60: /* andc */ 1956 op->val = regs->gpr[rd] & ~regs->gpr[rb]; 1957 goto logical_done; 1958 1959 case 122: /* popcntb */ 1960 do_popcnt(regs, op, regs->gpr[rd], 8); 1961 goto logical_done_nocc; 1962 1963 case 124: /* nor */ 1964 op->val = ~(regs->gpr[rd] | regs->gpr[rb]); 1965 goto logical_done; 1966 1967 case 154: /* prtyw */ 1968 do_prty(regs, op, regs->gpr[rd], 32); 1969 goto logical_done_nocc; 1970 1971 case 186: /* prtyd */ 1972 do_prty(regs, op, regs->gpr[rd], 64); 1973 goto logical_done_nocc; 1974 #ifdef CONFIG_PPC64 1975 case 252: /* bpermd */ 1976 do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]); 1977 goto logical_done_nocc; 1978 #endif 1979 case 284: /* xor */ 1980 op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]); 1981 goto logical_done; 1982 1983 case 316: /* xor */ 1984 op->val = regs->gpr[rd] ^ regs->gpr[rb]; 1985 goto logical_done; 1986 1987 case 378: /* popcntw */ 1988 do_popcnt(regs, op, regs->gpr[rd], 32); 1989 goto logical_done_nocc; 1990 1991 case 412: /* orc */ 1992 op->val = regs->gpr[rd] | ~regs->gpr[rb]; 1993 goto logical_done; 1994 1995 case 444: /* or */ 1996 op->val = regs->gpr[rd] | regs->gpr[rb]; 1997 goto logical_done; 1998 1999 case 476: /* nand */ 2000 op->val = ~(regs->gpr[rd] & regs->gpr[rb]); 2001 goto logical_done; 2002 #ifdef CONFIG_PPC64 2003 case 506: /* popcntd */ 2004 do_popcnt(regs, op, regs->gpr[rd], 64); 2005 goto logical_done_nocc; 2006 #endif 2007 case 538: /* cnttzw */ 2008 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 2009 goto unknown_opcode; 2010 val = (unsigned int) regs->gpr[rd]; 2011 op->val = (val ? __builtin_ctz(val) : 32); 2012 goto logical_done; 2013 #ifdef __powerpc64__ 2014 case 570: /* cnttzd */ 2015 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 2016 goto unknown_opcode; 2017 val = regs->gpr[rd]; 2018 op->val = (val ? __builtin_ctzl(val) : 64); 2019 goto logical_done; 2020 #endif 2021 case 922: /* extsh */ 2022 op->val = (signed short) regs->gpr[rd]; 2023 goto logical_done; 2024 2025 case 954: /* extsb */ 2026 op->val = (signed char) regs->gpr[rd]; 2027 goto logical_done; 2028 #ifdef __powerpc64__ 2029 case 986: /* extsw */ 2030 op->val = (signed int) regs->gpr[rd]; 2031 goto logical_done; 2032 #endif 2033 2034 /* 2035 * Shift instructions 2036 */ 2037 case 24: /* slw */ 2038 sh = regs->gpr[rb] & 0x3f; 2039 if (sh < 32) 2040 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL; 2041 else 2042 op->val = 0; 2043 goto logical_done; 2044 2045 case 536: /* srw */ 2046 sh = regs->gpr[rb] & 0x3f; 2047 if (sh < 32) 2048 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh; 2049 else 2050 op->val = 0; 2051 goto logical_done; 2052 2053 case 792: /* sraw */ 2054 op->type = COMPUTE + SETREG + SETXER; 2055 sh = regs->gpr[rb] & 0x3f; 2056 ival = (signed int) regs->gpr[rd]; 2057 op->val = ival >> (sh < 32 ? sh : 31); 2058 op->xerval = regs->xer; 2059 if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0)) 2060 op->xerval |= XER_CA; 2061 else 2062 op->xerval &= ~XER_CA; 2063 set_ca32(op, op->xerval & XER_CA); 2064 goto logical_done; 2065 2066 case 824: /* srawi */ 2067 op->type = COMPUTE + SETREG + SETXER; 2068 sh = rb; 2069 ival = (signed int) regs->gpr[rd]; 2070 op->val = ival >> sh; 2071 op->xerval = regs->xer; 2072 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0) 2073 op->xerval |= XER_CA; 2074 else 2075 op->xerval &= ~XER_CA; 2076 set_ca32(op, op->xerval & XER_CA); 2077 goto logical_done; 2078 2079 #ifdef __powerpc64__ 2080 case 27: /* sld */ 2081 sh = regs->gpr[rb] & 0x7f; 2082 if (sh < 64) 2083 op->val = regs->gpr[rd] << sh; 2084 else 2085 op->val = 0; 2086 goto logical_done; 2087 2088 case 539: /* srd */ 2089 sh = regs->gpr[rb] & 0x7f; 2090 if (sh < 64) 2091 op->val = regs->gpr[rd] >> sh; 2092 else 2093 op->val = 0; 2094 goto logical_done; 2095 2096 case 794: /* srad */ 2097 op->type = COMPUTE + SETREG + SETXER; 2098 sh = regs->gpr[rb] & 0x7f; 2099 ival = (signed long int) regs->gpr[rd]; 2100 op->val = ival >> (sh < 64 ? sh : 63); 2101 op->xerval = regs->xer; 2102 if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0)) 2103 op->xerval |= XER_CA; 2104 else 2105 op->xerval &= ~XER_CA; 2106 set_ca32(op, op->xerval & XER_CA); 2107 goto logical_done; 2108 2109 case 826: /* sradi with sh_5 = 0 */ 2110 case 827: /* sradi with sh_5 = 1 */ 2111 op->type = COMPUTE + SETREG + SETXER; 2112 sh = rb | ((word & 2) << 4); 2113 ival = (signed long int) regs->gpr[rd]; 2114 op->val = ival >> sh; 2115 op->xerval = regs->xer; 2116 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0) 2117 op->xerval |= XER_CA; 2118 else 2119 op->xerval &= ~XER_CA; 2120 set_ca32(op, op->xerval & XER_CA); 2121 goto logical_done; 2122 2123 case 890: /* extswsli with sh_5 = 0 */ 2124 case 891: /* extswsli with sh_5 = 1 */ 2125 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 2126 goto unknown_opcode; 2127 op->type = COMPUTE + SETREG; 2128 sh = rb | ((word & 2) << 4); 2129 val = (signed int) regs->gpr[rd]; 2130 if (sh) 2131 op->val = ROTATE(val, sh) & MASK64(0, 63 - sh); 2132 else 2133 op->val = val; 2134 goto logical_done; 2135 2136 #endif /* __powerpc64__ */ 2137 2138 /* 2139 * Cache instructions 2140 */ 2141 case 54: /* dcbst */ 2142 op->type = MKOP(CACHEOP, DCBST, 0); 2143 op->ea = xform_ea(word, regs); 2144 return 0; 2145 2146 case 86: /* dcbf */ 2147 op->type = MKOP(CACHEOP, DCBF, 0); 2148 op->ea = xform_ea(word, regs); 2149 return 0; 2150 2151 case 246: /* dcbtst */ 2152 op->type = MKOP(CACHEOP, DCBTST, 0); 2153 op->ea = xform_ea(word, regs); 2154 op->reg = rd; 2155 return 0; 2156 2157 case 278: /* dcbt */ 2158 op->type = MKOP(CACHEOP, DCBTST, 0); 2159 op->ea = xform_ea(word, regs); 2160 op->reg = rd; 2161 return 0; 2162 2163 case 982: /* icbi */ 2164 op->type = MKOP(CACHEOP, ICBI, 0); 2165 op->ea = xform_ea(word, regs); 2166 return 0; 2167 2168 case 1014: /* dcbz */ 2169 op->type = MKOP(CACHEOP, DCBZ, 0); 2170 op->ea = xform_ea(word, regs); 2171 return 0; 2172 } 2173 break; 2174 } 2175 2176 /* 2177 * Loads and stores. 2178 */ 2179 op->type = UNKNOWN; 2180 op->update_reg = ra; 2181 op->reg = rd; 2182 op->val = regs->gpr[rd]; 2183 u = (word >> 20) & UPDATE; 2184 op->vsx_flags = 0; 2185 2186 switch (opcode) { 2187 case 31: 2188 u = word & UPDATE; 2189 op->ea = xform_ea(word, regs); 2190 switch ((word >> 1) & 0x3ff) { 2191 case 20: /* lwarx */ 2192 op->type = MKOP(LARX, 0, 4); 2193 break; 2194 2195 case 150: /* stwcx. */ 2196 op->type = MKOP(STCX, 0, 4); 2197 break; 2198 2199 #ifdef __powerpc64__ 2200 case 84: /* ldarx */ 2201 op->type = MKOP(LARX, 0, 8); 2202 break; 2203 2204 case 214: /* stdcx. */ 2205 op->type = MKOP(STCX, 0, 8); 2206 break; 2207 2208 case 52: /* lbarx */ 2209 op->type = MKOP(LARX, 0, 1); 2210 break; 2211 2212 case 694: /* stbcx. */ 2213 op->type = MKOP(STCX, 0, 1); 2214 break; 2215 2216 case 116: /* lharx */ 2217 op->type = MKOP(LARX, 0, 2); 2218 break; 2219 2220 case 726: /* sthcx. */ 2221 op->type = MKOP(STCX, 0, 2); 2222 break; 2223 2224 case 276: /* lqarx */ 2225 if (!((rd & 1) || rd == ra || rd == rb)) 2226 op->type = MKOP(LARX, 0, 16); 2227 break; 2228 2229 case 182: /* stqcx. */ 2230 if (!(rd & 1)) 2231 op->type = MKOP(STCX, 0, 16); 2232 break; 2233 #endif 2234 2235 case 23: /* lwzx */ 2236 case 55: /* lwzux */ 2237 op->type = MKOP(LOAD, u, 4); 2238 break; 2239 2240 case 87: /* lbzx */ 2241 case 119: /* lbzux */ 2242 op->type = MKOP(LOAD, u, 1); 2243 break; 2244 2245 #ifdef CONFIG_ALTIVEC 2246 /* 2247 * Note: for the load/store vector element instructions, 2248 * bits of the EA say which field of the VMX register to use. 2249 */ 2250 case 7: /* lvebx */ 2251 op->type = MKOP(LOAD_VMX, 0, 1); 2252 op->element_size = 1; 2253 break; 2254 2255 case 39: /* lvehx */ 2256 op->type = MKOP(LOAD_VMX, 0, 2); 2257 op->element_size = 2; 2258 break; 2259 2260 case 71: /* lvewx */ 2261 op->type = MKOP(LOAD_VMX, 0, 4); 2262 op->element_size = 4; 2263 break; 2264 2265 case 103: /* lvx */ 2266 case 359: /* lvxl */ 2267 op->type = MKOP(LOAD_VMX, 0, 16); 2268 op->element_size = 16; 2269 break; 2270 2271 case 135: /* stvebx */ 2272 op->type = MKOP(STORE_VMX, 0, 1); 2273 op->element_size = 1; 2274 break; 2275 2276 case 167: /* stvehx */ 2277 op->type = MKOP(STORE_VMX, 0, 2); 2278 op->element_size = 2; 2279 break; 2280 2281 case 199: /* stvewx */ 2282 op->type = MKOP(STORE_VMX, 0, 4); 2283 op->element_size = 4; 2284 break; 2285 2286 case 231: /* stvx */ 2287 case 487: /* stvxl */ 2288 op->type = MKOP(STORE_VMX, 0, 16); 2289 break; 2290 #endif /* CONFIG_ALTIVEC */ 2291 2292 #ifdef __powerpc64__ 2293 case 21: /* ldx */ 2294 case 53: /* ldux */ 2295 op->type = MKOP(LOAD, u, 8); 2296 break; 2297 2298 case 149: /* stdx */ 2299 case 181: /* stdux */ 2300 op->type = MKOP(STORE, u, 8); 2301 break; 2302 #endif 2303 2304 case 151: /* stwx */ 2305 case 183: /* stwux */ 2306 op->type = MKOP(STORE, u, 4); 2307 break; 2308 2309 case 215: /* stbx */ 2310 case 247: /* stbux */ 2311 op->type = MKOP(STORE, u, 1); 2312 break; 2313 2314 case 279: /* lhzx */ 2315 case 311: /* lhzux */ 2316 op->type = MKOP(LOAD, u, 2); 2317 break; 2318 2319 #ifdef __powerpc64__ 2320 case 341: /* lwax */ 2321 case 373: /* lwaux */ 2322 op->type = MKOP(LOAD, SIGNEXT | u, 4); 2323 break; 2324 #endif 2325 2326 case 343: /* lhax */ 2327 case 375: /* lhaux */ 2328 op->type = MKOP(LOAD, SIGNEXT | u, 2); 2329 break; 2330 2331 case 407: /* sthx */ 2332 case 439: /* sthux */ 2333 op->type = MKOP(STORE, u, 2); 2334 break; 2335 2336 #ifdef __powerpc64__ 2337 case 532: /* ldbrx */ 2338 op->type = MKOP(LOAD, BYTEREV, 8); 2339 break; 2340 2341 #endif 2342 case 533: /* lswx */ 2343 op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f); 2344 break; 2345 2346 case 534: /* lwbrx */ 2347 op->type = MKOP(LOAD, BYTEREV, 4); 2348 break; 2349 2350 case 597: /* lswi */ 2351 if (rb == 0) 2352 rb = 32; /* # bytes to load */ 2353 op->type = MKOP(LOAD_MULTI, 0, rb); 2354 op->ea = ra ? regs->gpr[ra] : 0; 2355 break; 2356 2357 #ifdef CONFIG_PPC_FPU 2358 case 535: /* lfsx */ 2359 case 567: /* lfsux */ 2360 op->type = MKOP(LOAD_FP, u | FPCONV, 4); 2361 break; 2362 2363 case 599: /* lfdx */ 2364 case 631: /* lfdux */ 2365 op->type = MKOP(LOAD_FP, u, 8); 2366 break; 2367 2368 case 663: /* stfsx */ 2369 case 695: /* stfsux */ 2370 op->type = MKOP(STORE_FP, u | FPCONV, 4); 2371 break; 2372 2373 case 727: /* stfdx */ 2374 case 759: /* stfdux */ 2375 op->type = MKOP(STORE_FP, u, 8); 2376 break; 2377 2378 #ifdef __powerpc64__ 2379 case 791: /* lfdpx */ 2380 op->type = MKOP(LOAD_FP, 0, 16); 2381 break; 2382 2383 case 855: /* lfiwax */ 2384 op->type = MKOP(LOAD_FP, SIGNEXT, 4); 2385 break; 2386 2387 case 887: /* lfiwzx */ 2388 op->type = MKOP(LOAD_FP, 0, 4); 2389 break; 2390 2391 case 919: /* stfdpx */ 2392 op->type = MKOP(STORE_FP, 0, 16); 2393 break; 2394 2395 case 983: /* stfiwx */ 2396 op->type = MKOP(STORE_FP, 0, 4); 2397 break; 2398 #endif /* __powerpc64 */ 2399 #endif /* CONFIG_PPC_FPU */ 2400 2401 #ifdef __powerpc64__ 2402 case 660: /* stdbrx */ 2403 op->type = MKOP(STORE, BYTEREV, 8); 2404 op->val = byterev_8(regs->gpr[rd]); 2405 break; 2406 2407 #endif 2408 case 661: /* stswx */ 2409 op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f); 2410 break; 2411 2412 case 662: /* stwbrx */ 2413 op->type = MKOP(STORE, BYTEREV, 4); 2414 op->val = byterev_4(regs->gpr[rd]); 2415 break; 2416 2417 case 725: /* stswi */ 2418 if (rb == 0) 2419 rb = 32; /* # bytes to store */ 2420 op->type = MKOP(STORE_MULTI, 0, rb); 2421 op->ea = ra ? regs->gpr[ra] : 0; 2422 break; 2423 2424 case 790: /* lhbrx */ 2425 op->type = MKOP(LOAD, BYTEREV, 2); 2426 break; 2427 2428 case 918: /* sthbrx */ 2429 op->type = MKOP(STORE, BYTEREV, 2); 2430 op->val = byterev_2(regs->gpr[rd]); 2431 break; 2432 2433 #ifdef CONFIG_VSX 2434 case 12: /* lxsiwzx */ 2435 op->reg = rd | ((word & 1) << 5); 2436 op->type = MKOP(LOAD_VSX, 0, 4); 2437 op->element_size = 8; 2438 break; 2439 2440 case 76: /* lxsiwax */ 2441 op->reg = rd | ((word & 1) << 5); 2442 op->type = MKOP(LOAD_VSX, SIGNEXT, 4); 2443 op->element_size = 8; 2444 break; 2445 2446 case 140: /* stxsiwx */ 2447 op->reg = rd | ((word & 1) << 5); 2448 op->type = MKOP(STORE_VSX, 0, 4); 2449 op->element_size = 8; 2450 break; 2451 2452 case 268: /* lxvx */ 2453 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 2454 goto unknown_opcode; 2455 op->reg = rd | ((word & 1) << 5); 2456 op->type = MKOP(LOAD_VSX, 0, 16); 2457 op->element_size = 16; 2458 op->vsx_flags = VSX_CHECK_VEC; 2459 break; 2460 2461 case 269: /* lxvl */ 2462 case 301: { /* lxvll */ 2463 int nb; 2464 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 2465 goto unknown_opcode; 2466 op->reg = rd | ((word & 1) << 5); 2467 op->ea = ra ? regs->gpr[ra] : 0; 2468 nb = regs->gpr[rb] & 0xff; 2469 if (nb > 16) 2470 nb = 16; 2471 op->type = MKOP(LOAD_VSX, 0, nb); 2472 op->element_size = 16; 2473 op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) | 2474 VSX_CHECK_VEC; 2475 break; 2476 } 2477 case 332: /* lxvdsx */ 2478 op->reg = rd | ((word & 1) << 5); 2479 op->type = MKOP(LOAD_VSX, 0, 8); 2480 op->element_size = 8; 2481 op->vsx_flags = VSX_SPLAT; 2482 break; 2483 2484 case 333: /* lxvpx */ 2485 if (!cpu_has_feature(CPU_FTR_ARCH_31)) 2486 goto unknown_opcode; 2487 op->reg = VSX_REGISTER_XTP(rd); 2488 op->type = MKOP(LOAD_VSX, 0, 32); 2489 op->element_size = 32; 2490 break; 2491 2492 case 364: /* lxvwsx */ 2493 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 2494 goto unknown_opcode; 2495 op->reg = rd | ((word & 1) << 5); 2496 op->type = MKOP(LOAD_VSX, 0, 4); 2497 op->element_size = 4; 2498 op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC; 2499 break; 2500 2501 case 396: /* stxvx */ 2502 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 2503 goto unknown_opcode; 2504 op->reg = rd | ((word & 1) << 5); 2505 op->type = MKOP(STORE_VSX, 0, 16); 2506 op->element_size = 16; 2507 op->vsx_flags = VSX_CHECK_VEC; 2508 break; 2509 2510 case 397: /* stxvl */ 2511 case 429: { /* stxvll */ 2512 int nb; 2513 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 2514 goto unknown_opcode; 2515 op->reg = rd | ((word & 1) << 5); 2516 op->ea = ra ? regs->gpr[ra] : 0; 2517 nb = regs->gpr[rb] & 0xff; 2518 if (nb > 16) 2519 nb = 16; 2520 op->type = MKOP(STORE_VSX, 0, nb); 2521 op->element_size = 16; 2522 op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) | 2523 VSX_CHECK_VEC; 2524 break; 2525 } 2526 case 461: /* stxvpx */ 2527 if (!cpu_has_feature(CPU_FTR_ARCH_31)) 2528 goto unknown_opcode; 2529 op->reg = VSX_REGISTER_XTP(rd); 2530 op->type = MKOP(STORE_VSX, 0, 32); 2531 op->element_size = 32; 2532 break; 2533 case 524: /* lxsspx */ 2534 op->reg = rd | ((word & 1) << 5); 2535 op->type = MKOP(LOAD_VSX, 0, 4); 2536 op->element_size = 8; 2537 op->vsx_flags = VSX_FPCONV; 2538 break; 2539 2540 case 588: /* lxsdx */ 2541 op->reg = rd | ((word & 1) << 5); 2542 op->type = MKOP(LOAD_VSX, 0, 8); 2543 op->element_size = 8; 2544 break; 2545 2546 case 652: /* stxsspx */ 2547 op->reg = rd | ((word & 1) << 5); 2548 op->type = MKOP(STORE_VSX, 0, 4); 2549 op->element_size = 8; 2550 op->vsx_flags = VSX_FPCONV; 2551 break; 2552 2553 case 716: /* stxsdx */ 2554 op->reg = rd | ((word & 1) << 5); 2555 op->type = MKOP(STORE_VSX, 0, 8); 2556 op->element_size = 8; 2557 break; 2558 2559 case 780: /* lxvw4x */ 2560 op->reg = rd | ((word & 1) << 5); 2561 op->type = MKOP(LOAD_VSX, 0, 16); 2562 op->element_size = 4; 2563 break; 2564 2565 case 781: /* lxsibzx */ 2566 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 2567 goto unknown_opcode; 2568 op->reg = rd | ((word & 1) << 5); 2569 op->type = MKOP(LOAD_VSX, 0, 1); 2570 op->element_size = 8; 2571 op->vsx_flags = VSX_CHECK_VEC; 2572 break; 2573 2574 case 812: /* lxvh8x */ 2575 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 2576 goto unknown_opcode; 2577 op->reg = rd | ((word & 1) << 5); 2578 op->type = MKOP(LOAD_VSX, 0, 16); 2579 op->element_size = 2; 2580 op->vsx_flags = VSX_CHECK_VEC; 2581 break; 2582 2583 case 813: /* lxsihzx */ 2584 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 2585 goto unknown_opcode; 2586 op->reg = rd | ((word & 1) << 5); 2587 op->type = MKOP(LOAD_VSX, 0, 2); 2588 op->element_size = 8; 2589 op->vsx_flags = VSX_CHECK_VEC; 2590 break; 2591 2592 case 844: /* lxvd2x */ 2593 op->reg = rd | ((word & 1) << 5); 2594 op->type = MKOP(LOAD_VSX, 0, 16); 2595 op->element_size = 8; 2596 break; 2597 2598 case 876: /* lxvb16x */ 2599 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 2600 goto unknown_opcode; 2601 op->reg = rd | ((word & 1) << 5); 2602 op->type = MKOP(LOAD_VSX, 0, 16); 2603 op->element_size = 1; 2604 op->vsx_flags = VSX_CHECK_VEC; 2605 break; 2606 2607 case 908: /* stxvw4x */ 2608 op->reg = rd | ((word & 1) << 5); 2609 op->type = MKOP(STORE_VSX, 0, 16); 2610 op->element_size = 4; 2611 break; 2612 2613 case 909: /* stxsibx */ 2614 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 2615 goto unknown_opcode; 2616 op->reg = rd | ((word & 1) << 5); 2617 op->type = MKOP(STORE_VSX, 0, 1); 2618 op->element_size = 8; 2619 op->vsx_flags = VSX_CHECK_VEC; 2620 break; 2621 2622 case 940: /* stxvh8x */ 2623 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 2624 goto unknown_opcode; 2625 op->reg = rd | ((word & 1) << 5); 2626 op->type = MKOP(STORE_VSX, 0, 16); 2627 op->element_size = 2; 2628 op->vsx_flags = VSX_CHECK_VEC; 2629 break; 2630 2631 case 941: /* stxsihx */ 2632 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 2633 goto unknown_opcode; 2634 op->reg = rd | ((word & 1) << 5); 2635 op->type = MKOP(STORE_VSX, 0, 2); 2636 op->element_size = 8; 2637 op->vsx_flags = VSX_CHECK_VEC; 2638 break; 2639 2640 case 972: /* stxvd2x */ 2641 op->reg = rd | ((word & 1) << 5); 2642 op->type = MKOP(STORE_VSX, 0, 16); 2643 op->element_size = 8; 2644 break; 2645 2646 case 1004: /* stxvb16x */ 2647 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 2648 goto unknown_opcode; 2649 op->reg = rd | ((word & 1) << 5); 2650 op->type = MKOP(STORE_VSX, 0, 16); 2651 op->element_size = 1; 2652 op->vsx_flags = VSX_CHECK_VEC; 2653 break; 2654 2655 #endif /* CONFIG_VSX */ 2656 } 2657 break; 2658 2659 case 32: /* lwz */ 2660 case 33: /* lwzu */ 2661 op->type = MKOP(LOAD, u, 4); 2662 op->ea = dform_ea(word, regs); 2663 break; 2664 2665 case 34: /* lbz */ 2666 case 35: /* lbzu */ 2667 op->type = MKOP(LOAD, u, 1); 2668 op->ea = dform_ea(word, regs); 2669 break; 2670 2671 case 36: /* stw */ 2672 case 37: /* stwu */ 2673 op->type = MKOP(STORE, u, 4); 2674 op->ea = dform_ea(word, regs); 2675 break; 2676 2677 case 38: /* stb */ 2678 case 39: /* stbu */ 2679 op->type = MKOP(STORE, u, 1); 2680 op->ea = dform_ea(word, regs); 2681 break; 2682 2683 case 40: /* lhz */ 2684 case 41: /* lhzu */ 2685 op->type = MKOP(LOAD, u, 2); 2686 op->ea = dform_ea(word, regs); 2687 break; 2688 2689 case 42: /* lha */ 2690 case 43: /* lhau */ 2691 op->type = MKOP(LOAD, SIGNEXT | u, 2); 2692 op->ea = dform_ea(word, regs); 2693 break; 2694 2695 case 44: /* sth */ 2696 case 45: /* sthu */ 2697 op->type = MKOP(STORE, u, 2); 2698 op->ea = dform_ea(word, regs); 2699 break; 2700 2701 case 46: /* lmw */ 2702 if (ra >= rd) 2703 break; /* invalid form, ra in range to load */ 2704 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd)); 2705 op->ea = dform_ea(word, regs); 2706 break; 2707 2708 case 47: /* stmw */ 2709 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd)); 2710 op->ea = dform_ea(word, regs); 2711 break; 2712 2713 #ifdef CONFIG_PPC_FPU 2714 case 48: /* lfs */ 2715 case 49: /* lfsu */ 2716 op->type = MKOP(LOAD_FP, u | FPCONV, 4); 2717 op->ea = dform_ea(word, regs); 2718 break; 2719 2720 case 50: /* lfd */ 2721 case 51: /* lfdu */ 2722 op->type = MKOP(LOAD_FP, u, 8); 2723 op->ea = dform_ea(word, regs); 2724 break; 2725 2726 case 52: /* stfs */ 2727 case 53: /* stfsu */ 2728 op->type = MKOP(STORE_FP, u | FPCONV, 4); 2729 op->ea = dform_ea(word, regs); 2730 break; 2731 2732 case 54: /* stfd */ 2733 case 55: /* stfdu */ 2734 op->type = MKOP(STORE_FP, u, 8); 2735 op->ea = dform_ea(word, regs); 2736 break; 2737 #endif 2738 2739 #ifdef __powerpc64__ 2740 case 56: /* lq */ 2741 if (!((rd & 1) || (rd == ra))) 2742 op->type = MKOP(LOAD, 0, 16); 2743 op->ea = dqform_ea(word, regs); 2744 break; 2745 #endif 2746 2747 #ifdef CONFIG_VSX 2748 case 57: /* lfdp, lxsd, lxssp */ 2749 op->ea = dsform_ea(word, regs); 2750 switch (word & 3) { 2751 case 0: /* lfdp */ 2752 if (rd & 1) 2753 break; /* reg must be even */ 2754 op->type = MKOP(LOAD_FP, 0, 16); 2755 break; 2756 case 2: /* lxsd */ 2757 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 2758 goto unknown_opcode; 2759 op->reg = rd + 32; 2760 op->type = MKOP(LOAD_VSX, 0, 8); 2761 op->element_size = 8; 2762 op->vsx_flags = VSX_CHECK_VEC; 2763 break; 2764 case 3: /* lxssp */ 2765 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 2766 goto unknown_opcode; 2767 op->reg = rd + 32; 2768 op->type = MKOP(LOAD_VSX, 0, 4); 2769 op->element_size = 8; 2770 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC; 2771 break; 2772 } 2773 break; 2774 #endif /* CONFIG_VSX */ 2775 2776 #ifdef __powerpc64__ 2777 case 58: /* ld[u], lwa */ 2778 op->ea = dsform_ea(word, regs); 2779 switch (word & 3) { 2780 case 0: /* ld */ 2781 op->type = MKOP(LOAD, 0, 8); 2782 break; 2783 case 1: /* ldu */ 2784 op->type = MKOP(LOAD, UPDATE, 8); 2785 break; 2786 case 2: /* lwa */ 2787 op->type = MKOP(LOAD, SIGNEXT, 4); 2788 break; 2789 } 2790 break; 2791 #endif 2792 2793 #ifdef CONFIG_VSX 2794 case 6: 2795 if (!cpu_has_feature(CPU_FTR_ARCH_31)) 2796 goto unknown_opcode; 2797 op->ea = dqform_ea(word, regs); 2798 op->reg = VSX_REGISTER_XTP(rd); 2799 op->element_size = 32; 2800 switch (word & 0xf) { 2801 case 0: /* lxvp */ 2802 op->type = MKOP(LOAD_VSX, 0, 32); 2803 break; 2804 case 1: /* stxvp */ 2805 op->type = MKOP(STORE_VSX, 0, 32); 2806 break; 2807 } 2808 break; 2809 2810 case 61: /* stfdp, lxv, stxsd, stxssp, stxv */ 2811 switch (word & 7) { 2812 case 0: /* stfdp with LSB of DS field = 0 */ 2813 case 4: /* stfdp with LSB of DS field = 1 */ 2814 op->ea = dsform_ea(word, regs); 2815 op->type = MKOP(STORE_FP, 0, 16); 2816 break; 2817 2818 case 1: /* lxv */ 2819 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 2820 goto unknown_opcode; 2821 op->ea = dqform_ea(word, regs); 2822 if (word & 8) 2823 op->reg = rd + 32; 2824 op->type = MKOP(LOAD_VSX, 0, 16); 2825 op->element_size = 16; 2826 op->vsx_flags = VSX_CHECK_VEC; 2827 break; 2828 2829 case 2: /* stxsd with LSB of DS field = 0 */ 2830 case 6: /* stxsd with LSB of DS field = 1 */ 2831 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 2832 goto unknown_opcode; 2833 op->ea = dsform_ea(word, regs); 2834 op->reg = rd + 32; 2835 op->type = MKOP(STORE_VSX, 0, 8); 2836 op->element_size = 8; 2837 op->vsx_flags = VSX_CHECK_VEC; 2838 break; 2839 2840 case 3: /* stxssp with LSB of DS field = 0 */ 2841 case 7: /* stxssp with LSB of DS field = 1 */ 2842 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 2843 goto unknown_opcode; 2844 op->ea = dsform_ea(word, regs); 2845 op->reg = rd + 32; 2846 op->type = MKOP(STORE_VSX, 0, 4); 2847 op->element_size = 8; 2848 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC; 2849 break; 2850 2851 case 5: /* stxv */ 2852 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 2853 goto unknown_opcode; 2854 op->ea = dqform_ea(word, regs); 2855 if (word & 8) 2856 op->reg = rd + 32; 2857 op->type = MKOP(STORE_VSX, 0, 16); 2858 op->element_size = 16; 2859 op->vsx_flags = VSX_CHECK_VEC; 2860 break; 2861 } 2862 break; 2863 #endif /* CONFIG_VSX */ 2864 2865 #ifdef __powerpc64__ 2866 case 62: /* std[u] */ 2867 op->ea = dsform_ea(word, regs); 2868 switch (word & 3) { 2869 case 0: /* std */ 2870 op->type = MKOP(STORE, 0, 8); 2871 break; 2872 case 1: /* stdu */ 2873 op->type = MKOP(STORE, UPDATE, 8); 2874 break; 2875 case 2: /* stq */ 2876 if (!(rd & 1)) 2877 op->type = MKOP(STORE, 0, 16); 2878 break; 2879 } 2880 break; 2881 case 1: /* Prefixed instructions */ 2882 if (!cpu_has_feature(CPU_FTR_ARCH_31)) 2883 goto unknown_opcode; 2884 2885 prefix_r = GET_PREFIX_R(word); 2886 ra = GET_PREFIX_RA(suffix); 2887 op->update_reg = ra; 2888 rd = (suffix >> 21) & 0x1f; 2889 op->reg = rd; 2890 op->val = regs->gpr[rd]; 2891 2892 suffixopcode = get_op(suffix); 2893 prefixtype = (word >> 24) & 0x3; 2894 switch (prefixtype) { 2895 case 0: /* Type 00 Eight-Byte Load/Store */ 2896 if (prefix_r && ra) 2897 break; 2898 op->ea = mlsd_8lsd_ea(word, suffix, regs); 2899 switch (suffixopcode) { 2900 case 41: /* plwa */ 2901 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4); 2902 break; 2903 #ifdef CONFIG_VSX 2904 case 42: /* plxsd */ 2905 op->reg = rd + 32; 2906 op->type = MKOP(LOAD_VSX, PREFIXED, 8); 2907 op->element_size = 8; 2908 op->vsx_flags = VSX_CHECK_VEC; 2909 break; 2910 case 43: /* plxssp */ 2911 op->reg = rd + 32; 2912 op->type = MKOP(LOAD_VSX, PREFIXED, 4); 2913 op->element_size = 8; 2914 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC; 2915 break; 2916 case 46: /* pstxsd */ 2917 op->reg = rd + 32; 2918 op->type = MKOP(STORE_VSX, PREFIXED, 8); 2919 op->element_size = 8; 2920 op->vsx_flags = VSX_CHECK_VEC; 2921 break; 2922 case 47: /* pstxssp */ 2923 op->reg = rd + 32; 2924 op->type = MKOP(STORE_VSX, PREFIXED, 4); 2925 op->element_size = 8; 2926 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC; 2927 break; 2928 case 51: /* plxv1 */ 2929 op->reg += 32; 2930 fallthrough; 2931 case 50: /* plxv0 */ 2932 op->type = MKOP(LOAD_VSX, PREFIXED, 16); 2933 op->element_size = 16; 2934 op->vsx_flags = VSX_CHECK_VEC; 2935 break; 2936 case 55: /* pstxv1 */ 2937 op->reg = rd + 32; 2938 fallthrough; 2939 case 54: /* pstxv0 */ 2940 op->type = MKOP(STORE_VSX, PREFIXED, 16); 2941 op->element_size = 16; 2942 op->vsx_flags = VSX_CHECK_VEC; 2943 break; 2944 #endif /* CONFIG_VSX */ 2945 case 56: /* plq */ 2946 op->type = MKOP(LOAD, PREFIXED, 16); 2947 break; 2948 case 57: /* pld */ 2949 op->type = MKOP(LOAD, PREFIXED, 8); 2950 break; 2951 #ifdef CONFIG_VSX 2952 case 58: /* plxvp */ 2953 op->reg = VSX_REGISTER_XTP(rd); 2954 op->type = MKOP(LOAD_VSX, PREFIXED, 32); 2955 op->element_size = 32; 2956 break; 2957 #endif /* CONFIG_VSX */ 2958 case 60: /* pstq */ 2959 op->type = MKOP(STORE, PREFIXED, 16); 2960 break; 2961 case 61: /* pstd */ 2962 op->type = MKOP(STORE, PREFIXED, 8); 2963 break; 2964 #ifdef CONFIG_VSX 2965 case 62: /* pstxvp */ 2966 op->reg = VSX_REGISTER_XTP(rd); 2967 op->type = MKOP(STORE_VSX, PREFIXED, 32); 2968 op->element_size = 32; 2969 break; 2970 #endif /* CONFIG_VSX */ 2971 } 2972 break; 2973 case 1: /* Type 01 Eight-Byte Register-to-Register */ 2974 break; 2975 case 2: /* Type 10 Modified Load/Store */ 2976 if (prefix_r && ra) 2977 break; 2978 op->ea = mlsd_8lsd_ea(word, suffix, regs); 2979 switch (suffixopcode) { 2980 case 32: /* plwz */ 2981 op->type = MKOP(LOAD, PREFIXED, 4); 2982 break; 2983 case 34: /* plbz */ 2984 op->type = MKOP(LOAD, PREFIXED, 1); 2985 break; 2986 case 36: /* pstw */ 2987 op->type = MKOP(STORE, PREFIXED, 4); 2988 break; 2989 case 38: /* pstb */ 2990 op->type = MKOP(STORE, PREFIXED, 1); 2991 break; 2992 case 40: /* plhz */ 2993 op->type = MKOP(LOAD, PREFIXED, 2); 2994 break; 2995 case 42: /* plha */ 2996 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 2); 2997 break; 2998 case 44: /* psth */ 2999 op->type = MKOP(STORE, PREFIXED, 2); 3000 break; 3001 case 48: /* plfs */ 3002 op->type = MKOP(LOAD_FP, PREFIXED | FPCONV, 4); 3003 break; 3004 case 50: /* plfd */ 3005 op->type = MKOP(LOAD_FP, PREFIXED, 8); 3006 break; 3007 case 52: /* pstfs */ 3008 op->type = MKOP(STORE_FP, PREFIXED | FPCONV, 4); 3009 break; 3010 case 54: /* pstfd */ 3011 op->type = MKOP(STORE_FP, PREFIXED, 8); 3012 break; 3013 } 3014 break; 3015 case 3: /* Type 11 Modified Register-to-Register */ 3016 break; 3017 } 3018 #endif /* __powerpc64__ */ 3019 3020 } 3021 3022 if (OP_IS_LOAD_STORE(op->type) && (op->type & UPDATE)) { 3023 switch (GETTYPE(op->type)) { 3024 case LOAD: 3025 if (ra == rd) 3026 goto unknown_opcode; 3027 fallthrough; 3028 case STORE: 3029 case LOAD_FP: 3030 case STORE_FP: 3031 if (ra == 0) 3032 goto unknown_opcode; 3033 } 3034 } 3035 3036 #ifdef CONFIG_VSX 3037 if ((GETTYPE(op->type) == LOAD_VSX || 3038 GETTYPE(op->type) == STORE_VSX) && 3039 !cpu_has_feature(CPU_FTR_VSX)) { 3040 return -1; 3041 } 3042 #endif /* CONFIG_VSX */ 3043 3044 return 0; 3045 3046 unknown_opcode: 3047 op->type = UNKNOWN; 3048 return 0; 3049 3050 logical_done: 3051 if (word & 1) 3052 set_cr0(regs, op); 3053 logical_done_nocc: 3054 op->reg = ra; 3055 op->type |= SETREG; 3056 return 1; 3057 3058 arith_done: 3059 if (word & 1) 3060 set_cr0(regs, op); 3061 compute_done: 3062 op->reg = rd; 3063 op->type |= SETREG; 3064 return 1; 3065 3066 priv: 3067 op->type = INTERRUPT | 0x700; 3068 op->val = SRR1_PROGPRIV; 3069 return 0; 3070 3071 trap: 3072 op->type = INTERRUPT | 0x700; 3073 op->val = SRR1_PROGTRAP; 3074 return 0; 3075 } 3076 EXPORT_SYMBOL_GPL(analyse_instr); 3077 NOKPROBE_SYMBOL(analyse_instr); 3078 3079 /* 3080 * For PPC32 we always use stwu with r1 to change the stack pointer. 3081 * So this emulated store may corrupt the exception frame, now we 3082 * have to provide the exception frame trampoline, which is pushed 3083 * below the kprobed function stack. So we only update gpr[1] but 3084 * don't emulate the real store operation. We will do real store 3085 * operation safely in exception return code by checking this flag. 3086 */ 3087 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs) 3088 { 3089 #ifdef CONFIG_PPC32 3090 /* 3091 * Check if we will touch kernel stack overflow 3092 */ 3093 if (ea - STACK_INT_FRAME_SIZE <= current->thread.ksp_limit) { 3094 printk(KERN_CRIT "Can't kprobe this since kernel stack would overflow.\n"); 3095 return -EINVAL; 3096 } 3097 #endif /* CONFIG_PPC32 */ 3098 /* 3099 * Check if we already set since that means we'll 3100 * lose the previous value. 3101 */ 3102 WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE)); 3103 set_thread_flag(TIF_EMULATE_STACK_STORE); 3104 return 0; 3105 } 3106 3107 static nokprobe_inline void do_signext(unsigned long *valp, int size) 3108 { 3109 switch (size) { 3110 case 2: 3111 *valp = (signed short) *valp; 3112 break; 3113 case 4: 3114 *valp = (signed int) *valp; 3115 break; 3116 } 3117 } 3118 3119 static nokprobe_inline void do_byterev(unsigned long *valp, int size) 3120 { 3121 switch (size) { 3122 case 2: 3123 *valp = byterev_2(*valp); 3124 break; 3125 case 4: 3126 *valp = byterev_4(*valp); 3127 break; 3128 #ifdef __powerpc64__ 3129 case 8: 3130 *valp = byterev_8(*valp); 3131 break; 3132 #endif 3133 } 3134 } 3135 3136 /* 3137 * Emulate an instruction that can be executed just by updating 3138 * fields in *regs. 3139 */ 3140 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op) 3141 { 3142 unsigned long next_pc; 3143 3144 next_pc = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op->type)); 3145 switch (GETTYPE(op->type)) { 3146 case COMPUTE: 3147 if (op->type & SETREG) 3148 regs->gpr[op->reg] = op->val; 3149 if (op->type & SETCC) 3150 regs->ccr = op->ccval; 3151 if (op->type & SETXER) 3152 regs->xer = op->xerval; 3153 break; 3154 3155 case BRANCH: 3156 if (op->type & SETLK) 3157 regs->link = next_pc; 3158 if (op->type & BRTAKEN) 3159 next_pc = op->val; 3160 if (op->type & DECCTR) 3161 --regs->ctr; 3162 break; 3163 3164 case BARRIER: 3165 switch (op->type & BARRIER_MASK) { 3166 case BARRIER_SYNC: 3167 mb(); 3168 break; 3169 case BARRIER_ISYNC: 3170 isync(); 3171 break; 3172 case BARRIER_EIEIO: 3173 eieio(); 3174 break; 3175 case BARRIER_LWSYNC: 3176 asm volatile("lwsync" : : : "memory"); 3177 break; 3178 case BARRIER_PTESYNC: 3179 asm volatile("ptesync" : : : "memory"); 3180 break; 3181 } 3182 break; 3183 3184 case MFSPR: 3185 switch (op->spr) { 3186 case SPRN_XER: 3187 regs->gpr[op->reg] = regs->xer & 0xffffffffUL; 3188 break; 3189 case SPRN_LR: 3190 regs->gpr[op->reg] = regs->link; 3191 break; 3192 case SPRN_CTR: 3193 regs->gpr[op->reg] = regs->ctr; 3194 break; 3195 default: 3196 WARN_ON_ONCE(1); 3197 } 3198 break; 3199 3200 case MTSPR: 3201 switch (op->spr) { 3202 case SPRN_XER: 3203 regs->xer = op->val & 0xffffffffUL; 3204 break; 3205 case SPRN_LR: 3206 regs->link = op->val; 3207 break; 3208 case SPRN_CTR: 3209 regs->ctr = op->val; 3210 break; 3211 default: 3212 WARN_ON_ONCE(1); 3213 } 3214 break; 3215 3216 default: 3217 WARN_ON_ONCE(1); 3218 } 3219 regs->nip = next_pc; 3220 } 3221 NOKPROBE_SYMBOL(emulate_update_regs); 3222 3223 /* 3224 * Emulate a previously-analysed load or store instruction. 3225 * Return values are: 3226 * 0 = instruction emulated successfully 3227 * -EFAULT = address out of range or access faulted (regs->dar 3228 * contains the faulting address) 3229 * -EACCES = misaligned access, instruction requires alignment 3230 * -EINVAL = unknown operation in *op 3231 */ 3232 int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op) 3233 { 3234 int err, size, type; 3235 int i, rd, nb; 3236 unsigned int cr; 3237 unsigned long val; 3238 unsigned long ea; 3239 bool cross_endian; 3240 3241 err = 0; 3242 size = GETSIZE(op->type); 3243 type = GETTYPE(op->type); 3244 cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE); 3245 ea = truncate_if_32bit(regs->msr, op->ea); 3246 3247 switch (type) { 3248 case LARX: 3249 if (ea & (size - 1)) 3250 return -EACCES; /* can't handle misaligned */ 3251 if (!address_ok(regs, ea, size)) 3252 return -EFAULT; 3253 err = 0; 3254 val = 0; 3255 switch (size) { 3256 #ifdef __powerpc64__ 3257 case 1: 3258 __get_user_asmx(val, ea, err, "lbarx"); 3259 break; 3260 case 2: 3261 __get_user_asmx(val, ea, err, "lharx"); 3262 break; 3263 #endif 3264 case 4: 3265 __get_user_asmx(val, ea, err, "lwarx"); 3266 break; 3267 #ifdef __powerpc64__ 3268 case 8: 3269 __get_user_asmx(val, ea, err, "ldarx"); 3270 break; 3271 case 16: 3272 err = do_lqarx(ea, ®s->gpr[op->reg]); 3273 break; 3274 #endif 3275 default: 3276 return -EINVAL; 3277 } 3278 if (err) { 3279 regs->dar = ea; 3280 break; 3281 } 3282 if (size < 16) 3283 regs->gpr[op->reg] = val; 3284 break; 3285 3286 case STCX: 3287 if (ea & (size - 1)) 3288 return -EACCES; /* can't handle misaligned */ 3289 if (!address_ok(regs, ea, size)) 3290 return -EFAULT; 3291 err = 0; 3292 switch (size) { 3293 #ifdef __powerpc64__ 3294 case 1: 3295 __put_user_asmx(op->val, ea, err, "stbcx.", cr); 3296 break; 3297 case 2: 3298 __put_user_asmx(op->val, ea, err, "stbcx.", cr); 3299 break; 3300 #endif 3301 case 4: 3302 __put_user_asmx(op->val, ea, err, "stwcx.", cr); 3303 break; 3304 #ifdef __powerpc64__ 3305 case 8: 3306 __put_user_asmx(op->val, ea, err, "stdcx.", cr); 3307 break; 3308 case 16: 3309 err = do_stqcx(ea, regs->gpr[op->reg], 3310 regs->gpr[op->reg + 1], &cr); 3311 break; 3312 #endif 3313 default: 3314 return -EINVAL; 3315 } 3316 if (!err) 3317 regs->ccr = (regs->ccr & 0x0fffffff) | 3318 (cr & 0xe0000000) | 3319 ((regs->xer >> 3) & 0x10000000); 3320 else 3321 regs->dar = ea; 3322 break; 3323 3324 case LOAD: 3325 #ifdef __powerpc64__ 3326 if (size == 16) { 3327 err = emulate_lq(regs, ea, op->reg, cross_endian); 3328 break; 3329 } 3330 #endif 3331 err = read_mem(®s->gpr[op->reg], ea, size, regs); 3332 if (!err) { 3333 if (op->type & SIGNEXT) 3334 do_signext(®s->gpr[op->reg], size); 3335 if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV)) 3336 do_byterev(®s->gpr[op->reg], size); 3337 } 3338 break; 3339 3340 #ifdef CONFIG_PPC_FPU 3341 case LOAD_FP: 3342 /* 3343 * If the instruction is in userspace, we can emulate it even 3344 * if the VMX state is not live, because we have the state 3345 * stored in the thread_struct. If the instruction is in 3346 * the kernel, we must not touch the state in the thread_struct. 3347 */ 3348 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP)) 3349 return 0; 3350 err = do_fp_load(op, ea, regs, cross_endian); 3351 break; 3352 #endif 3353 #ifdef CONFIG_ALTIVEC 3354 case LOAD_VMX: 3355 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC)) 3356 return 0; 3357 err = do_vec_load(op->reg, ea, size, regs, cross_endian); 3358 break; 3359 #endif 3360 #ifdef CONFIG_VSX 3361 case LOAD_VSX: { 3362 unsigned long msrbit = MSR_VSX; 3363 3364 /* 3365 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX 3366 * when the target of the instruction is a vector register. 3367 */ 3368 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC)) 3369 msrbit = MSR_VEC; 3370 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit)) 3371 return 0; 3372 err = do_vsx_load(op, ea, regs, cross_endian); 3373 break; 3374 } 3375 #endif 3376 case LOAD_MULTI: 3377 if (!address_ok(regs, ea, size)) 3378 return -EFAULT; 3379 rd = op->reg; 3380 for (i = 0; i < size; i += 4) { 3381 unsigned int v32 = 0; 3382 3383 nb = size - i; 3384 if (nb > 4) 3385 nb = 4; 3386 err = copy_mem_in((u8 *) &v32, ea, nb, regs); 3387 if (err) 3388 break; 3389 if (unlikely(cross_endian)) 3390 v32 = byterev_4(v32); 3391 regs->gpr[rd] = v32; 3392 ea += 4; 3393 /* reg number wraps from 31 to 0 for lsw[ix] */ 3394 rd = (rd + 1) & 0x1f; 3395 } 3396 break; 3397 3398 case STORE: 3399 #ifdef __powerpc64__ 3400 if (size == 16) { 3401 err = emulate_stq(regs, ea, op->reg, cross_endian); 3402 break; 3403 } 3404 #endif 3405 if ((op->type & UPDATE) && size == sizeof(long) && 3406 op->reg == 1 && op->update_reg == 1 && 3407 !(regs->msr & MSR_PR) && 3408 ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) { 3409 err = handle_stack_update(ea, regs); 3410 break; 3411 } 3412 if (unlikely(cross_endian)) 3413 do_byterev(&op->val, size); 3414 err = write_mem(op->val, ea, size, regs); 3415 break; 3416 3417 #ifdef CONFIG_PPC_FPU 3418 case STORE_FP: 3419 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP)) 3420 return 0; 3421 err = do_fp_store(op, ea, regs, cross_endian); 3422 break; 3423 #endif 3424 #ifdef CONFIG_ALTIVEC 3425 case STORE_VMX: 3426 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC)) 3427 return 0; 3428 err = do_vec_store(op->reg, ea, size, regs, cross_endian); 3429 break; 3430 #endif 3431 #ifdef CONFIG_VSX 3432 case STORE_VSX: { 3433 unsigned long msrbit = MSR_VSX; 3434 3435 /* 3436 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX 3437 * when the target of the instruction is a vector register. 3438 */ 3439 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC)) 3440 msrbit = MSR_VEC; 3441 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit)) 3442 return 0; 3443 err = do_vsx_store(op, ea, regs, cross_endian); 3444 break; 3445 } 3446 #endif 3447 case STORE_MULTI: 3448 if (!address_ok(regs, ea, size)) 3449 return -EFAULT; 3450 rd = op->reg; 3451 for (i = 0; i < size; i += 4) { 3452 unsigned int v32 = regs->gpr[rd]; 3453 3454 nb = size - i; 3455 if (nb > 4) 3456 nb = 4; 3457 if (unlikely(cross_endian)) 3458 v32 = byterev_4(v32); 3459 err = copy_mem_out((u8 *) &v32, ea, nb, regs); 3460 if (err) 3461 break; 3462 ea += 4; 3463 /* reg number wraps from 31 to 0 for stsw[ix] */ 3464 rd = (rd + 1) & 0x1f; 3465 } 3466 break; 3467 3468 default: 3469 return -EINVAL; 3470 } 3471 3472 if (err) 3473 return err; 3474 3475 if (op->type & UPDATE) 3476 regs->gpr[op->update_reg] = op->ea; 3477 3478 return 0; 3479 } 3480 NOKPROBE_SYMBOL(emulate_loadstore); 3481 3482 /* 3483 * Emulate instructions that cause a transfer of control, 3484 * loads and stores, and a few other instructions. 3485 * Returns 1 if the step was emulated, 0 if not, 3486 * or -1 if the instruction is one that should not be stepped, 3487 * such as an rfid, or a mtmsrd that would clear MSR_RI. 3488 */ 3489 int emulate_step(struct pt_regs *regs, struct ppc_inst instr) 3490 { 3491 struct instruction_op op; 3492 int r, err, type; 3493 unsigned long val; 3494 unsigned long ea; 3495 3496 r = analyse_instr(&op, regs, instr); 3497 if (r < 0) 3498 return r; 3499 if (r > 0) { 3500 emulate_update_regs(regs, &op); 3501 return 1; 3502 } 3503 3504 err = 0; 3505 type = GETTYPE(op.type); 3506 3507 if (OP_IS_LOAD_STORE(type)) { 3508 err = emulate_loadstore(regs, &op); 3509 if (err) 3510 return 0; 3511 goto instr_done; 3512 } 3513 3514 switch (type) { 3515 case CACHEOP: 3516 ea = truncate_if_32bit(regs->msr, op.ea); 3517 if (!address_ok(regs, ea, 8)) 3518 return 0; 3519 switch (op.type & CACHEOP_MASK) { 3520 case DCBST: 3521 __cacheop_user_asmx(ea, err, "dcbst"); 3522 break; 3523 case DCBF: 3524 __cacheop_user_asmx(ea, err, "dcbf"); 3525 break; 3526 case DCBTST: 3527 if (op.reg == 0) 3528 prefetchw((void *) ea); 3529 break; 3530 case DCBT: 3531 if (op.reg == 0) 3532 prefetch((void *) ea); 3533 break; 3534 case ICBI: 3535 __cacheop_user_asmx(ea, err, "icbi"); 3536 break; 3537 case DCBZ: 3538 err = emulate_dcbz(ea, regs); 3539 break; 3540 } 3541 if (err) { 3542 regs->dar = ea; 3543 return 0; 3544 } 3545 goto instr_done; 3546 3547 case MFMSR: 3548 regs->gpr[op.reg] = regs->msr & MSR_MASK; 3549 goto instr_done; 3550 3551 case MTMSR: 3552 val = regs->gpr[op.reg]; 3553 if ((val & MSR_RI) == 0) 3554 /* can't step mtmsr[d] that would clear MSR_RI */ 3555 return -1; 3556 /* here op.val is the mask of bits to change */ 3557 regs->msr = (regs->msr & ~op.val) | (val & op.val); 3558 goto instr_done; 3559 3560 #ifdef CONFIG_PPC64 3561 case SYSCALL: /* sc */ 3562 /* 3563 * N.B. this uses knowledge about how the syscall 3564 * entry code works. If that is changed, this will 3565 * need to be changed also. 3566 */ 3567 if (IS_ENABLED(CONFIG_PPC_FAST_ENDIAN_SWITCH) && 3568 cpu_has_feature(CPU_FTR_REAL_LE) && 3569 regs->gpr[0] == 0x1ebe) { 3570 regs->msr ^= MSR_LE; 3571 goto instr_done; 3572 } 3573 regs->gpr[9] = regs->gpr[13]; 3574 regs->gpr[10] = MSR_KERNEL; 3575 regs->gpr[11] = regs->nip + 4; 3576 regs->gpr[12] = regs->msr & MSR_MASK; 3577 regs->gpr[13] = (unsigned long) get_paca(); 3578 regs->nip = (unsigned long) &system_call_common; 3579 regs->msr = MSR_KERNEL; 3580 return 1; 3581 3582 #ifdef CONFIG_PPC_BOOK3S_64 3583 case SYSCALL_VECTORED_0: /* scv 0 */ 3584 regs->gpr[9] = regs->gpr[13]; 3585 regs->gpr[10] = MSR_KERNEL; 3586 regs->gpr[11] = regs->nip + 4; 3587 regs->gpr[12] = regs->msr & MSR_MASK; 3588 regs->gpr[13] = (unsigned long) get_paca(); 3589 regs->nip = (unsigned long) &system_call_vectored_emulate; 3590 regs->msr = MSR_KERNEL; 3591 return 1; 3592 #endif 3593 3594 case RFI: 3595 return -1; 3596 #endif 3597 } 3598 return 0; 3599 3600 instr_done: 3601 regs->nip = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op.type)); 3602 return 1; 3603 } 3604 NOKPROBE_SYMBOL(emulate_step); 3605