1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Single-step support. 4 * 5 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM 6 */ 7 #include <linux/kernel.h> 8 #include <linux/kprobes.h> 9 #include <linux/ptrace.h> 10 #include <linux/prefetch.h> 11 #include <asm/sstep.h> 12 #include <asm/processor.h> 13 #include <linux/uaccess.h> 14 #include <asm/cpu_has_feature.h> 15 #include <asm/cputable.h> 16 #include <asm/disassemble.h> 17 18 extern char system_call_common[]; 19 extern char system_call_vectored_emulate[]; 20 21 #ifdef CONFIG_PPC64 22 /* Bits in SRR1 that are copied from MSR */ 23 #define MSR_MASK 0xffffffff87c0ffffUL 24 #else 25 #define MSR_MASK 0x87c0ffff 26 #endif 27 28 /* Bits in XER */ 29 #define XER_SO 0x80000000U 30 #define XER_OV 0x40000000U 31 #define XER_CA 0x20000000U 32 #define XER_OV32 0x00080000U 33 #define XER_CA32 0x00040000U 34 35 #ifdef CONFIG_PPC_FPU 36 /* 37 * Functions in ldstfp.S 38 */ 39 extern void get_fpr(int rn, double *p); 40 extern void put_fpr(int rn, const double *p); 41 extern void get_vr(int rn, __vector128 *p); 42 extern void put_vr(int rn, __vector128 *p); 43 extern void load_vsrn(int vsr, const void *p); 44 extern void store_vsrn(int vsr, void *p); 45 extern void conv_sp_to_dp(const float *sp, double *dp); 46 extern void conv_dp_to_sp(const double *dp, float *sp); 47 #endif 48 49 #ifdef __powerpc64__ 50 /* 51 * Functions in quad.S 52 */ 53 extern int do_lq(unsigned long ea, unsigned long *regs); 54 extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1); 55 extern int do_lqarx(unsigned long ea, unsigned long *regs); 56 extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1, 57 unsigned int *crp); 58 #endif 59 60 #ifdef __LITTLE_ENDIAN__ 61 #define IS_LE 1 62 #define IS_BE 0 63 #else 64 #define IS_LE 0 65 #define IS_BE 1 66 #endif 67 68 /* 69 * Emulate the truncation of 64 bit values in 32-bit mode. 70 */ 71 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr, 72 unsigned long val) 73 { 74 #ifdef __powerpc64__ 75 if ((msr & MSR_64BIT) == 0) 76 val &= 0xffffffffUL; 77 #endif 78 return val; 79 } 80 81 /* 82 * Determine whether a conditional branch instruction would branch. 83 */ 84 static nokprobe_inline int branch_taken(unsigned int instr, 85 const struct pt_regs *regs, 86 struct instruction_op *op) 87 { 88 unsigned int bo = (instr >> 21) & 0x1f; 89 unsigned int bi; 90 91 if ((bo & 4) == 0) { 92 /* decrement counter */ 93 op->type |= DECCTR; 94 if (((bo >> 1) & 1) ^ (regs->ctr == 1)) 95 return 0; 96 } 97 if ((bo & 0x10) == 0) { 98 /* check bit from CR */ 99 bi = (instr >> 16) & 0x1f; 100 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1)) 101 return 0; 102 } 103 return 1; 104 } 105 106 static nokprobe_inline long address_ok(struct pt_regs *regs, 107 unsigned long ea, int nb) 108 { 109 if (!user_mode(regs)) 110 return 1; 111 if (__access_ok(ea, nb)) 112 return 1; 113 if (__access_ok(ea, 1)) 114 /* Access overlaps the end of the user region */ 115 regs->dar = TASK_SIZE_MAX - 1; 116 else 117 regs->dar = ea; 118 return 0; 119 } 120 121 /* 122 * Calculate effective address for a D-form instruction 123 */ 124 static nokprobe_inline unsigned long dform_ea(unsigned int instr, 125 const struct pt_regs *regs) 126 { 127 int ra; 128 unsigned long ea; 129 130 ra = (instr >> 16) & 0x1f; 131 ea = (signed short) instr; /* sign-extend */ 132 if (ra) 133 ea += regs->gpr[ra]; 134 135 return ea; 136 } 137 138 #ifdef __powerpc64__ 139 /* 140 * Calculate effective address for a DS-form instruction 141 */ 142 static nokprobe_inline unsigned long dsform_ea(unsigned int instr, 143 const struct pt_regs *regs) 144 { 145 int ra; 146 unsigned long ea; 147 148 ra = (instr >> 16) & 0x1f; 149 ea = (signed short) (instr & ~3); /* sign-extend */ 150 if (ra) 151 ea += regs->gpr[ra]; 152 153 return ea; 154 } 155 156 /* 157 * Calculate effective address for a DQ-form instruction 158 */ 159 static nokprobe_inline unsigned long dqform_ea(unsigned int instr, 160 const struct pt_regs *regs) 161 { 162 int ra; 163 unsigned long ea; 164 165 ra = (instr >> 16) & 0x1f; 166 ea = (signed short) (instr & ~0xf); /* sign-extend */ 167 if (ra) 168 ea += regs->gpr[ra]; 169 170 return ea; 171 } 172 #endif /* __powerpc64 */ 173 174 /* 175 * Calculate effective address for an X-form instruction 176 */ 177 static nokprobe_inline unsigned long xform_ea(unsigned int instr, 178 const struct pt_regs *regs) 179 { 180 int ra, rb; 181 unsigned long ea; 182 183 ra = (instr >> 16) & 0x1f; 184 rb = (instr >> 11) & 0x1f; 185 ea = regs->gpr[rb]; 186 if (ra) 187 ea += regs->gpr[ra]; 188 189 return ea; 190 } 191 192 /* 193 * Calculate effective address for a MLS:D-form / 8LS:D-form 194 * prefixed instruction 195 */ 196 static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned int instr, 197 unsigned int suffix, 198 const struct pt_regs *regs) 199 { 200 int ra, prefix_r; 201 unsigned int dd; 202 unsigned long ea, d0, d1, d; 203 204 prefix_r = GET_PREFIX_R(instr); 205 ra = GET_PREFIX_RA(suffix); 206 207 d0 = instr & 0x3ffff; 208 d1 = suffix & 0xffff; 209 d = (d0 << 16) | d1; 210 211 /* 212 * sign extend a 34 bit number 213 */ 214 dd = (unsigned int)(d >> 2); 215 ea = (signed int)dd; 216 ea = (ea << 2) | (d & 0x3); 217 218 if (!prefix_r && ra) 219 ea += regs->gpr[ra]; 220 else if (!prefix_r && !ra) 221 ; /* Leave ea as is */ 222 else if (prefix_r) 223 ea += regs->nip; 224 225 /* 226 * (prefix_r && ra) is an invalid form. Should already be 227 * checked for by caller! 228 */ 229 230 return ea; 231 } 232 233 /* 234 * Return the largest power of 2, not greater than sizeof(unsigned long), 235 * such that x is a multiple of it. 236 */ 237 static nokprobe_inline unsigned long max_align(unsigned long x) 238 { 239 x |= sizeof(unsigned long); 240 return x & -x; /* isolates rightmost bit */ 241 } 242 243 static nokprobe_inline unsigned long byterev_2(unsigned long x) 244 { 245 return ((x >> 8) & 0xff) | ((x & 0xff) << 8); 246 } 247 248 static nokprobe_inline unsigned long byterev_4(unsigned long x) 249 { 250 return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) | 251 ((x & 0xff00) << 8) | ((x & 0xff) << 24); 252 } 253 254 #ifdef __powerpc64__ 255 static nokprobe_inline unsigned long byterev_8(unsigned long x) 256 { 257 return (byterev_4(x) << 32) | byterev_4(x >> 32); 258 } 259 #endif 260 261 static nokprobe_inline void do_byte_reverse(void *ptr, int nb) 262 { 263 switch (nb) { 264 case 2: 265 *(u16 *)ptr = byterev_2(*(u16 *)ptr); 266 break; 267 case 4: 268 *(u32 *)ptr = byterev_4(*(u32 *)ptr); 269 break; 270 #ifdef __powerpc64__ 271 case 8: 272 *(unsigned long *)ptr = byterev_8(*(unsigned long *)ptr); 273 break; 274 case 16: { 275 unsigned long *up = (unsigned long *)ptr; 276 unsigned long tmp; 277 tmp = byterev_8(up[0]); 278 up[0] = byterev_8(up[1]); 279 up[1] = tmp; 280 break; 281 } 282 #endif 283 default: 284 WARN_ON_ONCE(1); 285 } 286 } 287 288 static nokprobe_inline int read_mem_aligned(unsigned long *dest, 289 unsigned long ea, int nb, 290 struct pt_regs *regs) 291 { 292 int err = 0; 293 unsigned long x = 0; 294 295 switch (nb) { 296 case 1: 297 err = __get_user(x, (unsigned char __user *) ea); 298 break; 299 case 2: 300 err = __get_user(x, (unsigned short __user *) ea); 301 break; 302 case 4: 303 err = __get_user(x, (unsigned int __user *) ea); 304 break; 305 #ifdef __powerpc64__ 306 case 8: 307 err = __get_user(x, (unsigned long __user *) ea); 308 break; 309 #endif 310 } 311 if (!err) 312 *dest = x; 313 else 314 regs->dar = ea; 315 return err; 316 } 317 318 /* 319 * Copy from userspace to a buffer, using the largest possible 320 * aligned accesses, up to sizeof(long). 321 */ 322 static nokprobe_inline int copy_mem_in(u8 *dest, unsigned long ea, int nb, 323 struct pt_regs *regs) 324 { 325 int err = 0; 326 int c; 327 328 for (; nb > 0; nb -= c) { 329 c = max_align(ea); 330 if (c > nb) 331 c = max_align(nb); 332 switch (c) { 333 case 1: 334 err = __get_user(*dest, (unsigned char __user *) ea); 335 break; 336 case 2: 337 err = __get_user(*(u16 *)dest, 338 (unsigned short __user *) ea); 339 break; 340 case 4: 341 err = __get_user(*(u32 *)dest, 342 (unsigned int __user *) ea); 343 break; 344 #ifdef __powerpc64__ 345 case 8: 346 err = __get_user(*(unsigned long *)dest, 347 (unsigned long __user *) ea); 348 break; 349 #endif 350 } 351 if (err) { 352 regs->dar = ea; 353 return err; 354 } 355 dest += c; 356 ea += c; 357 } 358 return 0; 359 } 360 361 static nokprobe_inline int read_mem_unaligned(unsigned long *dest, 362 unsigned long ea, int nb, 363 struct pt_regs *regs) 364 { 365 union { 366 unsigned long ul; 367 u8 b[sizeof(unsigned long)]; 368 } u; 369 int i; 370 int err; 371 372 u.ul = 0; 373 i = IS_BE ? sizeof(unsigned long) - nb : 0; 374 err = copy_mem_in(&u.b[i], ea, nb, regs); 375 if (!err) 376 *dest = u.ul; 377 return err; 378 } 379 380 /* 381 * Read memory at address ea for nb bytes, return 0 for success 382 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8. 383 * If nb < sizeof(long), the result is right-justified on BE systems. 384 */ 385 static int read_mem(unsigned long *dest, unsigned long ea, int nb, 386 struct pt_regs *regs) 387 { 388 if (!address_ok(regs, ea, nb)) 389 return -EFAULT; 390 if ((ea & (nb - 1)) == 0) 391 return read_mem_aligned(dest, ea, nb, regs); 392 return read_mem_unaligned(dest, ea, nb, regs); 393 } 394 NOKPROBE_SYMBOL(read_mem); 395 396 static nokprobe_inline int write_mem_aligned(unsigned long val, 397 unsigned long ea, int nb, 398 struct pt_regs *regs) 399 { 400 int err = 0; 401 402 switch (nb) { 403 case 1: 404 err = __put_user(val, (unsigned char __user *) ea); 405 break; 406 case 2: 407 err = __put_user(val, (unsigned short __user *) ea); 408 break; 409 case 4: 410 err = __put_user(val, (unsigned int __user *) ea); 411 break; 412 #ifdef __powerpc64__ 413 case 8: 414 err = __put_user(val, (unsigned long __user *) ea); 415 break; 416 #endif 417 } 418 if (err) 419 regs->dar = ea; 420 return err; 421 } 422 423 /* 424 * Copy from a buffer to userspace, using the largest possible 425 * aligned accesses, up to sizeof(long). 426 */ 427 static nokprobe_inline int copy_mem_out(u8 *dest, unsigned long ea, int nb, 428 struct pt_regs *regs) 429 { 430 int err = 0; 431 int c; 432 433 for (; nb > 0; nb -= c) { 434 c = max_align(ea); 435 if (c > nb) 436 c = max_align(nb); 437 switch (c) { 438 case 1: 439 err = __put_user(*dest, (unsigned char __user *) ea); 440 break; 441 case 2: 442 err = __put_user(*(u16 *)dest, 443 (unsigned short __user *) ea); 444 break; 445 case 4: 446 err = __put_user(*(u32 *)dest, 447 (unsigned int __user *) ea); 448 break; 449 #ifdef __powerpc64__ 450 case 8: 451 err = __put_user(*(unsigned long *)dest, 452 (unsigned long __user *) ea); 453 break; 454 #endif 455 } 456 if (err) { 457 regs->dar = ea; 458 return err; 459 } 460 dest += c; 461 ea += c; 462 } 463 return 0; 464 } 465 466 static nokprobe_inline int write_mem_unaligned(unsigned long val, 467 unsigned long ea, int nb, 468 struct pt_regs *regs) 469 { 470 union { 471 unsigned long ul; 472 u8 b[sizeof(unsigned long)]; 473 } u; 474 int i; 475 476 u.ul = val; 477 i = IS_BE ? sizeof(unsigned long) - nb : 0; 478 return copy_mem_out(&u.b[i], ea, nb, regs); 479 } 480 481 /* 482 * Write memory at address ea for nb bytes, return 0 for success 483 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8. 484 */ 485 static int write_mem(unsigned long val, unsigned long ea, int nb, 486 struct pt_regs *regs) 487 { 488 if (!address_ok(regs, ea, nb)) 489 return -EFAULT; 490 if ((ea & (nb - 1)) == 0) 491 return write_mem_aligned(val, ea, nb, regs); 492 return write_mem_unaligned(val, ea, nb, regs); 493 } 494 NOKPROBE_SYMBOL(write_mem); 495 496 #ifdef CONFIG_PPC_FPU 497 /* 498 * These access either the real FP register or the image in the 499 * thread_struct, depending on regs->msr & MSR_FP. 500 */ 501 static int do_fp_load(struct instruction_op *op, unsigned long ea, 502 struct pt_regs *regs, bool cross_endian) 503 { 504 int err, rn, nb; 505 union { 506 int i; 507 unsigned int u; 508 float f; 509 double d[2]; 510 unsigned long l[2]; 511 u8 b[2 * sizeof(double)]; 512 } u; 513 514 nb = GETSIZE(op->type); 515 if (!address_ok(regs, ea, nb)) 516 return -EFAULT; 517 rn = op->reg; 518 err = copy_mem_in(u.b, ea, nb, regs); 519 if (err) 520 return err; 521 if (unlikely(cross_endian)) { 522 do_byte_reverse(u.b, min(nb, 8)); 523 if (nb == 16) 524 do_byte_reverse(&u.b[8], 8); 525 } 526 preempt_disable(); 527 if (nb == 4) { 528 if (op->type & FPCONV) 529 conv_sp_to_dp(&u.f, &u.d[0]); 530 else if (op->type & SIGNEXT) 531 u.l[0] = u.i; 532 else 533 u.l[0] = u.u; 534 } 535 if (regs->msr & MSR_FP) 536 put_fpr(rn, &u.d[0]); 537 else 538 current->thread.TS_FPR(rn) = u.l[0]; 539 if (nb == 16) { 540 /* lfdp */ 541 rn |= 1; 542 if (regs->msr & MSR_FP) 543 put_fpr(rn, &u.d[1]); 544 else 545 current->thread.TS_FPR(rn) = u.l[1]; 546 } 547 preempt_enable(); 548 return 0; 549 } 550 NOKPROBE_SYMBOL(do_fp_load); 551 552 static int do_fp_store(struct instruction_op *op, unsigned long ea, 553 struct pt_regs *regs, bool cross_endian) 554 { 555 int rn, nb; 556 union { 557 unsigned int u; 558 float f; 559 double d[2]; 560 unsigned long l[2]; 561 u8 b[2 * sizeof(double)]; 562 } u; 563 564 nb = GETSIZE(op->type); 565 if (!address_ok(regs, ea, nb)) 566 return -EFAULT; 567 rn = op->reg; 568 preempt_disable(); 569 if (regs->msr & MSR_FP) 570 get_fpr(rn, &u.d[0]); 571 else 572 u.l[0] = current->thread.TS_FPR(rn); 573 if (nb == 4) { 574 if (op->type & FPCONV) 575 conv_dp_to_sp(&u.d[0], &u.f); 576 else 577 u.u = u.l[0]; 578 } 579 if (nb == 16) { 580 rn |= 1; 581 if (regs->msr & MSR_FP) 582 get_fpr(rn, &u.d[1]); 583 else 584 u.l[1] = current->thread.TS_FPR(rn); 585 } 586 preempt_enable(); 587 if (unlikely(cross_endian)) { 588 do_byte_reverse(u.b, min(nb, 8)); 589 if (nb == 16) 590 do_byte_reverse(&u.b[8], 8); 591 } 592 return copy_mem_out(u.b, ea, nb, regs); 593 } 594 NOKPROBE_SYMBOL(do_fp_store); 595 #endif 596 597 #ifdef CONFIG_ALTIVEC 598 /* For Altivec/VMX, no need to worry about alignment */ 599 static nokprobe_inline int do_vec_load(int rn, unsigned long ea, 600 int size, struct pt_regs *regs, 601 bool cross_endian) 602 { 603 int err; 604 union { 605 __vector128 v; 606 u8 b[sizeof(__vector128)]; 607 } u = {}; 608 609 if (!address_ok(regs, ea & ~0xfUL, 16)) 610 return -EFAULT; 611 /* align to multiple of size */ 612 ea &= ~(size - 1); 613 err = copy_mem_in(&u.b[ea & 0xf], ea, size, regs); 614 if (err) 615 return err; 616 if (unlikely(cross_endian)) 617 do_byte_reverse(&u.b[ea & 0xf], size); 618 preempt_disable(); 619 if (regs->msr & MSR_VEC) 620 put_vr(rn, &u.v); 621 else 622 current->thread.vr_state.vr[rn] = u.v; 623 preempt_enable(); 624 return 0; 625 } 626 627 static nokprobe_inline int do_vec_store(int rn, unsigned long ea, 628 int size, struct pt_regs *regs, 629 bool cross_endian) 630 { 631 union { 632 __vector128 v; 633 u8 b[sizeof(__vector128)]; 634 } u; 635 636 if (!address_ok(regs, ea & ~0xfUL, 16)) 637 return -EFAULT; 638 /* align to multiple of size */ 639 ea &= ~(size - 1); 640 641 preempt_disable(); 642 if (regs->msr & MSR_VEC) 643 get_vr(rn, &u.v); 644 else 645 u.v = current->thread.vr_state.vr[rn]; 646 preempt_enable(); 647 if (unlikely(cross_endian)) 648 do_byte_reverse(&u.b[ea & 0xf], size); 649 return copy_mem_out(&u.b[ea & 0xf], ea, size, regs); 650 } 651 #endif /* CONFIG_ALTIVEC */ 652 653 #ifdef __powerpc64__ 654 static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea, 655 int reg, bool cross_endian) 656 { 657 int err; 658 659 if (!address_ok(regs, ea, 16)) 660 return -EFAULT; 661 /* if aligned, should be atomic */ 662 if ((ea & 0xf) == 0) { 663 err = do_lq(ea, ®s->gpr[reg]); 664 } else { 665 err = read_mem(®s->gpr[reg + IS_LE], ea, 8, regs); 666 if (!err) 667 err = read_mem(®s->gpr[reg + IS_BE], ea + 8, 8, regs); 668 } 669 if (!err && unlikely(cross_endian)) 670 do_byte_reverse(®s->gpr[reg], 16); 671 return err; 672 } 673 674 static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea, 675 int reg, bool cross_endian) 676 { 677 int err; 678 unsigned long vals[2]; 679 680 if (!address_ok(regs, ea, 16)) 681 return -EFAULT; 682 vals[0] = regs->gpr[reg]; 683 vals[1] = regs->gpr[reg + 1]; 684 if (unlikely(cross_endian)) 685 do_byte_reverse(vals, 16); 686 687 /* if aligned, should be atomic */ 688 if ((ea & 0xf) == 0) 689 return do_stq(ea, vals[0], vals[1]); 690 691 err = write_mem(vals[IS_LE], ea, 8, regs); 692 if (!err) 693 err = write_mem(vals[IS_BE], ea + 8, 8, regs); 694 return err; 695 } 696 #endif /* __powerpc64 */ 697 698 #ifdef CONFIG_VSX 699 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg, 700 const void *mem, bool rev) 701 { 702 int size, read_size; 703 int i, j; 704 const unsigned int *wp; 705 const unsigned short *hp; 706 const unsigned char *bp; 707 708 size = GETSIZE(op->type); 709 reg->d[0] = reg->d[1] = 0; 710 711 switch (op->element_size) { 712 case 16: 713 /* whole vector; lxv[x] or lxvl[l] */ 714 if (size == 0) 715 break; 716 memcpy(reg, mem, size); 717 if (IS_LE && (op->vsx_flags & VSX_LDLEFT)) 718 rev = !rev; 719 if (rev) 720 do_byte_reverse(reg, 16); 721 break; 722 case 8: 723 /* scalar loads, lxvd2x, lxvdsx */ 724 read_size = (size >= 8) ? 8 : size; 725 i = IS_LE ? 8 : 8 - read_size; 726 memcpy(®->b[i], mem, read_size); 727 if (rev) 728 do_byte_reverse(®->b[i], 8); 729 if (size < 8) { 730 if (op->type & SIGNEXT) { 731 /* size == 4 is the only case here */ 732 reg->d[IS_LE] = (signed int) reg->d[IS_LE]; 733 } else if (op->vsx_flags & VSX_FPCONV) { 734 preempt_disable(); 735 conv_sp_to_dp(®->fp[1 + IS_LE], 736 ®->dp[IS_LE]); 737 preempt_enable(); 738 } 739 } else { 740 if (size == 16) { 741 unsigned long v = *(unsigned long *)(mem + 8); 742 reg->d[IS_BE] = !rev ? v : byterev_8(v); 743 } else if (op->vsx_flags & VSX_SPLAT) 744 reg->d[IS_BE] = reg->d[IS_LE]; 745 } 746 break; 747 case 4: 748 /* lxvw4x, lxvwsx */ 749 wp = mem; 750 for (j = 0; j < size / 4; ++j) { 751 i = IS_LE ? 3 - j : j; 752 reg->w[i] = !rev ? *wp++ : byterev_4(*wp++); 753 } 754 if (op->vsx_flags & VSX_SPLAT) { 755 u32 val = reg->w[IS_LE ? 3 : 0]; 756 for (; j < 4; ++j) { 757 i = IS_LE ? 3 - j : j; 758 reg->w[i] = val; 759 } 760 } 761 break; 762 case 2: 763 /* lxvh8x */ 764 hp = mem; 765 for (j = 0; j < size / 2; ++j) { 766 i = IS_LE ? 7 - j : j; 767 reg->h[i] = !rev ? *hp++ : byterev_2(*hp++); 768 } 769 break; 770 case 1: 771 /* lxvb16x */ 772 bp = mem; 773 for (j = 0; j < size; ++j) { 774 i = IS_LE ? 15 - j : j; 775 reg->b[i] = *bp++; 776 } 777 break; 778 } 779 } 780 EXPORT_SYMBOL_GPL(emulate_vsx_load); 781 NOKPROBE_SYMBOL(emulate_vsx_load); 782 783 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg, 784 void *mem, bool rev) 785 { 786 int size, write_size; 787 int i, j; 788 union vsx_reg buf; 789 unsigned int *wp; 790 unsigned short *hp; 791 unsigned char *bp; 792 793 size = GETSIZE(op->type); 794 795 switch (op->element_size) { 796 case 16: 797 /* stxv, stxvx, stxvl, stxvll */ 798 if (size == 0) 799 break; 800 if (IS_LE && (op->vsx_flags & VSX_LDLEFT)) 801 rev = !rev; 802 if (rev) { 803 /* reverse 16 bytes */ 804 buf.d[0] = byterev_8(reg->d[1]); 805 buf.d[1] = byterev_8(reg->d[0]); 806 reg = &buf; 807 } 808 memcpy(mem, reg, size); 809 break; 810 case 8: 811 /* scalar stores, stxvd2x */ 812 write_size = (size >= 8) ? 8 : size; 813 i = IS_LE ? 8 : 8 - write_size; 814 if (size < 8 && op->vsx_flags & VSX_FPCONV) { 815 buf.d[0] = buf.d[1] = 0; 816 preempt_disable(); 817 conv_dp_to_sp(®->dp[IS_LE], &buf.fp[1 + IS_LE]); 818 preempt_enable(); 819 reg = &buf; 820 } 821 memcpy(mem, ®->b[i], write_size); 822 if (size == 16) 823 memcpy(mem + 8, ®->d[IS_BE], 8); 824 if (unlikely(rev)) { 825 do_byte_reverse(mem, write_size); 826 if (size == 16) 827 do_byte_reverse(mem + 8, 8); 828 } 829 break; 830 case 4: 831 /* stxvw4x */ 832 wp = mem; 833 for (j = 0; j < size / 4; ++j) { 834 i = IS_LE ? 3 - j : j; 835 *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]); 836 } 837 break; 838 case 2: 839 /* stxvh8x */ 840 hp = mem; 841 for (j = 0; j < size / 2; ++j) { 842 i = IS_LE ? 7 - j : j; 843 *hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]); 844 } 845 break; 846 case 1: 847 /* stvxb16x */ 848 bp = mem; 849 for (j = 0; j < size; ++j) { 850 i = IS_LE ? 15 - j : j; 851 *bp++ = reg->b[i]; 852 } 853 break; 854 } 855 } 856 EXPORT_SYMBOL_GPL(emulate_vsx_store); 857 NOKPROBE_SYMBOL(emulate_vsx_store); 858 859 static nokprobe_inline int do_vsx_load(struct instruction_op *op, 860 unsigned long ea, struct pt_regs *regs, 861 bool cross_endian) 862 { 863 int reg = op->reg; 864 u8 mem[16]; 865 union vsx_reg buf; 866 int size = GETSIZE(op->type); 867 868 if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs)) 869 return -EFAULT; 870 871 emulate_vsx_load(op, &buf, mem, cross_endian); 872 preempt_disable(); 873 if (reg < 32) { 874 /* FP regs + extensions */ 875 if (regs->msr & MSR_FP) { 876 load_vsrn(reg, &buf); 877 } else { 878 current->thread.fp_state.fpr[reg][0] = buf.d[0]; 879 current->thread.fp_state.fpr[reg][1] = buf.d[1]; 880 } 881 } else { 882 if (regs->msr & MSR_VEC) 883 load_vsrn(reg, &buf); 884 else 885 current->thread.vr_state.vr[reg - 32] = buf.v; 886 } 887 preempt_enable(); 888 return 0; 889 } 890 891 static nokprobe_inline int do_vsx_store(struct instruction_op *op, 892 unsigned long ea, struct pt_regs *regs, 893 bool cross_endian) 894 { 895 int reg = op->reg; 896 u8 mem[16]; 897 union vsx_reg buf; 898 int size = GETSIZE(op->type); 899 900 if (!address_ok(regs, ea, size)) 901 return -EFAULT; 902 903 preempt_disable(); 904 if (reg < 32) { 905 /* FP regs + extensions */ 906 if (regs->msr & MSR_FP) { 907 store_vsrn(reg, &buf); 908 } else { 909 buf.d[0] = current->thread.fp_state.fpr[reg][0]; 910 buf.d[1] = current->thread.fp_state.fpr[reg][1]; 911 } 912 } else { 913 if (regs->msr & MSR_VEC) 914 store_vsrn(reg, &buf); 915 else 916 buf.v = current->thread.vr_state.vr[reg - 32]; 917 } 918 preempt_enable(); 919 emulate_vsx_store(op, &buf, mem, cross_endian); 920 return copy_mem_out(mem, ea, size, regs); 921 } 922 #endif /* CONFIG_VSX */ 923 924 int emulate_dcbz(unsigned long ea, struct pt_regs *regs) 925 { 926 int err; 927 unsigned long i, size; 928 929 #ifdef __powerpc64__ 930 size = ppc64_caches.l1d.block_size; 931 if (!(regs->msr & MSR_64BIT)) 932 ea &= 0xffffffffUL; 933 #else 934 size = L1_CACHE_BYTES; 935 #endif 936 ea &= ~(size - 1); 937 if (!address_ok(regs, ea, size)) 938 return -EFAULT; 939 for (i = 0; i < size; i += sizeof(long)) { 940 err = __put_user(0, (unsigned long __user *) (ea + i)); 941 if (err) { 942 regs->dar = ea; 943 return err; 944 } 945 } 946 return 0; 947 } 948 NOKPROBE_SYMBOL(emulate_dcbz); 949 950 #define __put_user_asmx(x, addr, err, op, cr) \ 951 __asm__ __volatile__( \ 952 "1: " op " %2,0,%3\n" \ 953 " mfcr %1\n" \ 954 "2:\n" \ 955 ".section .fixup,\"ax\"\n" \ 956 "3: li %0,%4\n" \ 957 " b 2b\n" \ 958 ".previous\n" \ 959 EX_TABLE(1b, 3b) \ 960 : "=r" (err), "=r" (cr) \ 961 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err)) 962 963 #define __get_user_asmx(x, addr, err, op) \ 964 __asm__ __volatile__( \ 965 "1: "op" %1,0,%2\n" \ 966 "2:\n" \ 967 ".section .fixup,\"ax\"\n" \ 968 "3: li %0,%3\n" \ 969 " b 2b\n" \ 970 ".previous\n" \ 971 EX_TABLE(1b, 3b) \ 972 : "=r" (err), "=r" (x) \ 973 : "r" (addr), "i" (-EFAULT), "0" (err)) 974 975 #define __cacheop_user_asmx(addr, err, op) \ 976 __asm__ __volatile__( \ 977 "1: "op" 0,%1\n" \ 978 "2:\n" \ 979 ".section .fixup,\"ax\"\n" \ 980 "3: li %0,%3\n" \ 981 " b 2b\n" \ 982 ".previous\n" \ 983 EX_TABLE(1b, 3b) \ 984 : "=r" (err) \ 985 : "r" (addr), "i" (-EFAULT), "0" (err)) 986 987 static nokprobe_inline void set_cr0(const struct pt_regs *regs, 988 struct instruction_op *op) 989 { 990 long val = op->val; 991 992 op->type |= SETCC; 993 op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000); 994 #ifdef __powerpc64__ 995 if (!(regs->msr & MSR_64BIT)) 996 val = (int) val; 997 #endif 998 if (val < 0) 999 op->ccval |= 0x80000000; 1000 else if (val > 0) 1001 op->ccval |= 0x40000000; 1002 else 1003 op->ccval |= 0x20000000; 1004 } 1005 1006 static nokprobe_inline void set_ca32(struct instruction_op *op, bool val) 1007 { 1008 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 1009 if (val) 1010 op->xerval |= XER_CA32; 1011 else 1012 op->xerval &= ~XER_CA32; 1013 } 1014 } 1015 1016 static nokprobe_inline void add_with_carry(const struct pt_regs *regs, 1017 struct instruction_op *op, int rd, 1018 unsigned long val1, unsigned long val2, 1019 unsigned long carry_in) 1020 { 1021 unsigned long val = val1 + val2; 1022 1023 if (carry_in) 1024 ++val; 1025 op->type = COMPUTE + SETREG + SETXER; 1026 op->reg = rd; 1027 op->val = val; 1028 #ifdef __powerpc64__ 1029 if (!(regs->msr & MSR_64BIT)) { 1030 val = (unsigned int) val; 1031 val1 = (unsigned int) val1; 1032 } 1033 #endif 1034 op->xerval = regs->xer; 1035 if (val < val1 || (carry_in && val == val1)) 1036 op->xerval |= XER_CA; 1037 else 1038 op->xerval &= ~XER_CA; 1039 1040 set_ca32(op, (unsigned int)val < (unsigned int)val1 || 1041 (carry_in && (unsigned int)val == (unsigned int)val1)); 1042 } 1043 1044 static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs, 1045 struct instruction_op *op, 1046 long v1, long v2, int crfld) 1047 { 1048 unsigned int crval, shift; 1049 1050 op->type = COMPUTE + SETCC; 1051 crval = (regs->xer >> 31) & 1; /* get SO bit */ 1052 if (v1 < v2) 1053 crval |= 8; 1054 else if (v1 > v2) 1055 crval |= 4; 1056 else 1057 crval |= 2; 1058 shift = (7 - crfld) * 4; 1059 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift); 1060 } 1061 1062 static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs, 1063 struct instruction_op *op, 1064 unsigned long v1, 1065 unsigned long v2, int crfld) 1066 { 1067 unsigned int crval, shift; 1068 1069 op->type = COMPUTE + SETCC; 1070 crval = (regs->xer >> 31) & 1; /* get SO bit */ 1071 if (v1 < v2) 1072 crval |= 8; 1073 else if (v1 > v2) 1074 crval |= 4; 1075 else 1076 crval |= 2; 1077 shift = (7 - crfld) * 4; 1078 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift); 1079 } 1080 1081 static nokprobe_inline void do_cmpb(const struct pt_regs *regs, 1082 struct instruction_op *op, 1083 unsigned long v1, unsigned long v2) 1084 { 1085 unsigned long long out_val, mask; 1086 int i; 1087 1088 out_val = 0; 1089 for (i = 0; i < 8; i++) { 1090 mask = 0xffUL << (i * 8); 1091 if ((v1 & mask) == (v2 & mask)) 1092 out_val |= mask; 1093 } 1094 op->val = out_val; 1095 } 1096 1097 /* 1098 * The size parameter is used to adjust the equivalent popcnt instruction. 1099 * popcntb = 8, popcntw = 32, popcntd = 64 1100 */ 1101 static nokprobe_inline void do_popcnt(const struct pt_regs *regs, 1102 struct instruction_op *op, 1103 unsigned long v1, int size) 1104 { 1105 unsigned long long out = v1; 1106 1107 out -= (out >> 1) & 0x5555555555555555ULL; 1108 out = (0x3333333333333333ULL & out) + 1109 (0x3333333333333333ULL & (out >> 2)); 1110 out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0fULL; 1111 1112 if (size == 8) { /* popcntb */ 1113 op->val = out; 1114 return; 1115 } 1116 out += out >> 8; 1117 out += out >> 16; 1118 if (size == 32) { /* popcntw */ 1119 op->val = out & 0x0000003f0000003fULL; 1120 return; 1121 } 1122 1123 out = (out + (out >> 32)) & 0x7f; 1124 op->val = out; /* popcntd */ 1125 } 1126 1127 #ifdef CONFIG_PPC64 1128 static nokprobe_inline void do_bpermd(const struct pt_regs *regs, 1129 struct instruction_op *op, 1130 unsigned long v1, unsigned long v2) 1131 { 1132 unsigned char perm, idx; 1133 unsigned int i; 1134 1135 perm = 0; 1136 for (i = 0; i < 8; i++) { 1137 idx = (v1 >> (i * 8)) & 0xff; 1138 if (idx < 64) 1139 if (v2 & PPC_BIT(idx)) 1140 perm |= 1 << i; 1141 } 1142 op->val = perm; 1143 } 1144 #endif /* CONFIG_PPC64 */ 1145 /* 1146 * The size parameter adjusts the equivalent prty instruction. 1147 * prtyw = 32, prtyd = 64 1148 */ 1149 static nokprobe_inline void do_prty(const struct pt_regs *regs, 1150 struct instruction_op *op, 1151 unsigned long v, int size) 1152 { 1153 unsigned long long res = v ^ (v >> 8); 1154 1155 res ^= res >> 16; 1156 if (size == 32) { /* prtyw */ 1157 op->val = res & 0x0000000100000001ULL; 1158 return; 1159 } 1160 1161 res ^= res >> 32; 1162 op->val = res & 1; /*prtyd */ 1163 } 1164 1165 static nokprobe_inline int trap_compare(long v1, long v2) 1166 { 1167 int ret = 0; 1168 1169 if (v1 < v2) 1170 ret |= 0x10; 1171 else if (v1 > v2) 1172 ret |= 0x08; 1173 else 1174 ret |= 0x04; 1175 if ((unsigned long)v1 < (unsigned long)v2) 1176 ret |= 0x02; 1177 else if ((unsigned long)v1 > (unsigned long)v2) 1178 ret |= 0x01; 1179 return ret; 1180 } 1181 1182 /* 1183 * Elements of 32-bit rotate and mask instructions. 1184 */ 1185 #define MASK32(mb, me) ((0xffffffffUL >> (mb)) + \ 1186 ((signed long)-0x80000000L >> (me)) + ((me) >= (mb))) 1187 #ifdef __powerpc64__ 1188 #define MASK64_L(mb) (~0UL >> (mb)) 1189 #define MASK64_R(me) ((signed long)-0x8000000000000000L >> (me)) 1190 #define MASK64(mb, me) (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb))) 1191 #define DATA32(x) (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32)) 1192 #else 1193 #define DATA32(x) (x) 1194 #endif 1195 #define ROTATE(x, n) ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x)) 1196 1197 /* 1198 * Decode an instruction, and return information about it in *op 1199 * without changing *regs. 1200 * Integer arithmetic and logical instructions, branches, and barrier 1201 * instructions can be emulated just using the information in *op. 1202 * 1203 * Return value is 1 if the instruction can be emulated just by 1204 * updating *regs with the information in *op, -1 if we need the 1205 * GPRs but *regs doesn't contain the full register set, or 0 1206 * otherwise. 1207 */ 1208 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, 1209 struct ppc_inst instr) 1210 { 1211 #ifdef CONFIG_PPC64 1212 unsigned int suffixopcode, prefixtype, prefix_r; 1213 #endif 1214 unsigned int opcode, ra, rb, rc, rd, spr, u; 1215 unsigned long int imm; 1216 unsigned long int val, val2; 1217 unsigned int mb, me, sh; 1218 unsigned int word, suffix; 1219 long ival; 1220 1221 word = ppc_inst_val(instr); 1222 suffix = ppc_inst_suffix(instr); 1223 1224 op->type = COMPUTE; 1225 1226 opcode = ppc_inst_primary_opcode(instr); 1227 switch (opcode) { 1228 case 16: /* bc */ 1229 op->type = BRANCH; 1230 imm = (signed short)(word & 0xfffc); 1231 if ((word & 2) == 0) 1232 imm += regs->nip; 1233 op->val = truncate_if_32bit(regs->msr, imm); 1234 if (word & 1) 1235 op->type |= SETLK; 1236 if (branch_taken(word, regs, op)) 1237 op->type |= BRTAKEN; 1238 return 1; 1239 #ifdef CONFIG_PPC64 1240 case 17: /* sc */ 1241 if ((word & 0xfe2) == 2) 1242 op->type = SYSCALL; 1243 else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && 1244 (word & 0xfe3) == 1) 1245 op->type = SYSCALL_VECTORED_0; 1246 else 1247 op->type = UNKNOWN; 1248 return 0; 1249 #endif 1250 case 18: /* b */ 1251 op->type = BRANCH | BRTAKEN; 1252 imm = word & 0x03fffffc; 1253 if (imm & 0x02000000) 1254 imm -= 0x04000000; 1255 if ((word & 2) == 0) 1256 imm += regs->nip; 1257 op->val = truncate_if_32bit(regs->msr, imm); 1258 if (word & 1) 1259 op->type |= SETLK; 1260 return 1; 1261 case 19: 1262 switch ((word >> 1) & 0x3ff) { 1263 case 0: /* mcrf */ 1264 op->type = COMPUTE + SETCC; 1265 rd = 7 - ((word >> 23) & 0x7); 1266 ra = 7 - ((word >> 18) & 0x7); 1267 rd *= 4; 1268 ra *= 4; 1269 val = (regs->ccr >> ra) & 0xf; 1270 op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd); 1271 return 1; 1272 1273 case 16: /* bclr */ 1274 case 528: /* bcctr */ 1275 op->type = BRANCH; 1276 imm = (word & 0x400)? regs->ctr: regs->link; 1277 op->val = truncate_if_32bit(regs->msr, imm); 1278 if (word & 1) 1279 op->type |= SETLK; 1280 if (branch_taken(word, regs, op)) 1281 op->type |= BRTAKEN; 1282 return 1; 1283 1284 case 18: /* rfid, scary */ 1285 if (regs->msr & MSR_PR) 1286 goto priv; 1287 op->type = RFI; 1288 return 0; 1289 1290 case 150: /* isync */ 1291 op->type = BARRIER | BARRIER_ISYNC; 1292 return 1; 1293 1294 case 33: /* crnor */ 1295 case 129: /* crandc */ 1296 case 193: /* crxor */ 1297 case 225: /* crnand */ 1298 case 257: /* crand */ 1299 case 289: /* creqv */ 1300 case 417: /* crorc */ 1301 case 449: /* cror */ 1302 op->type = COMPUTE + SETCC; 1303 ra = (word >> 16) & 0x1f; 1304 rb = (word >> 11) & 0x1f; 1305 rd = (word >> 21) & 0x1f; 1306 ra = (regs->ccr >> (31 - ra)) & 1; 1307 rb = (regs->ccr >> (31 - rb)) & 1; 1308 val = (word >> (6 + ra * 2 + rb)) & 1; 1309 op->ccval = (regs->ccr & ~(1UL << (31 - rd))) | 1310 (val << (31 - rd)); 1311 return 1; 1312 } 1313 break; 1314 case 31: 1315 switch ((word >> 1) & 0x3ff) { 1316 case 598: /* sync */ 1317 op->type = BARRIER + BARRIER_SYNC; 1318 #ifdef __powerpc64__ 1319 switch ((word >> 21) & 3) { 1320 case 1: /* lwsync */ 1321 op->type = BARRIER + BARRIER_LWSYNC; 1322 break; 1323 case 2: /* ptesync */ 1324 op->type = BARRIER + BARRIER_PTESYNC; 1325 break; 1326 } 1327 #endif 1328 return 1; 1329 1330 case 854: /* eieio */ 1331 op->type = BARRIER + BARRIER_EIEIO; 1332 return 1; 1333 } 1334 break; 1335 } 1336 1337 /* Following cases refer to regs->gpr[], so we need all regs */ 1338 if (!FULL_REGS(regs)) 1339 return -1; 1340 1341 rd = (word >> 21) & 0x1f; 1342 ra = (word >> 16) & 0x1f; 1343 rb = (word >> 11) & 0x1f; 1344 rc = (word >> 6) & 0x1f; 1345 1346 switch (opcode) { 1347 #ifdef __powerpc64__ 1348 case 1: 1349 prefix_r = GET_PREFIX_R(word); 1350 ra = GET_PREFIX_RA(suffix); 1351 rd = (suffix >> 21) & 0x1f; 1352 op->reg = rd; 1353 op->val = regs->gpr[rd]; 1354 suffixopcode = get_op(suffix); 1355 prefixtype = (word >> 24) & 0x3; 1356 switch (prefixtype) { 1357 case 2: 1358 if (prefix_r && ra) 1359 return 0; 1360 switch (suffixopcode) { 1361 case 14: /* paddi */ 1362 op->type = COMPUTE | PREFIXED; 1363 op->val = mlsd_8lsd_ea(word, suffix, regs); 1364 goto compute_done; 1365 } 1366 } 1367 break; 1368 case 2: /* tdi */ 1369 if (rd & trap_compare(regs->gpr[ra], (short) word)) 1370 goto trap; 1371 return 1; 1372 #endif 1373 case 3: /* twi */ 1374 if (rd & trap_compare((int)regs->gpr[ra], (short) word)) 1375 goto trap; 1376 return 1; 1377 1378 #ifdef __powerpc64__ 1379 case 4: 1380 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1381 return -1; 1382 1383 switch (word & 0x3f) { 1384 case 48: /* maddhd */ 1385 asm volatile(PPC_MADDHD(%0, %1, %2, %3) : 1386 "=r" (op->val) : "r" (regs->gpr[ra]), 1387 "r" (regs->gpr[rb]), "r" (regs->gpr[rc])); 1388 goto compute_done; 1389 1390 case 49: /* maddhdu */ 1391 asm volatile(PPC_MADDHDU(%0, %1, %2, %3) : 1392 "=r" (op->val) : "r" (regs->gpr[ra]), 1393 "r" (regs->gpr[rb]), "r" (regs->gpr[rc])); 1394 goto compute_done; 1395 1396 case 51: /* maddld */ 1397 asm volatile(PPC_MADDLD(%0, %1, %2, %3) : 1398 "=r" (op->val) : "r" (regs->gpr[ra]), 1399 "r" (regs->gpr[rb]), "r" (regs->gpr[rc])); 1400 goto compute_done; 1401 } 1402 1403 /* 1404 * There are other instructions from ISA 3.0 with the same 1405 * primary opcode which do not have emulation support yet. 1406 */ 1407 return -1; 1408 #endif 1409 1410 case 7: /* mulli */ 1411 op->val = regs->gpr[ra] * (short) word; 1412 goto compute_done; 1413 1414 case 8: /* subfic */ 1415 imm = (short) word; 1416 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1); 1417 return 1; 1418 1419 case 10: /* cmpli */ 1420 imm = (unsigned short) word; 1421 val = regs->gpr[ra]; 1422 #ifdef __powerpc64__ 1423 if ((rd & 1) == 0) 1424 val = (unsigned int) val; 1425 #endif 1426 do_cmp_unsigned(regs, op, val, imm, rd >> 2); 1427 return 1; 1428 1429 case 11: /* cmpi */ 1430 imm = (short) word; 1431 val = regs->gpr[ra]; 1432 #ifdef __powerpc64__ 1433 if ((rd & 1) == 0) 1434 val = (int) val; 1435 #endif 1436 do_cmp_signed(regs, op, val, imm, rd >> 2); 1437 return 1; 1438 1439 case 12: /* addic */ 1440 imm = (short) word; 1441 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0); 1442 return 1; 1443 1444 case 13: /* addic. */ 1445 imm = (short) word; 1446 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0); 1447 set_cr0(regs, op); 1448 return 1; 1449 1450 case 14: /* addi */ 1451 imm = (short) word; 1452 if (ra) 1453 imm += regs->gpr[ra]; 1454 op->val = imm; 1455 goto compute_done; 1456 1457 case 15: /* addis */ 1458 imm = ((short) word) << 16; 1459 if (ra) 1460 imm += regs->gpr[ra]; 1461 op->val = imm; 1462 goto compute_done; 1463 1464 case 19: 1465 if (((word >> 1) & 0x1f) == 2) { 1466 /* addpcis */ 1467 imm = (short) (word & 0xffc1); /* d0 + d2 fields */ 1468 imm |= (word >> 15) & 0x3e; /* d1 field */ 1469 op->val = regs->nip + (imm << 16) + 4; 1470 goto compute_done; 1471 } 1472 op->type = UNKNOWN; 1473 return 0; 1474 1475 case 20: /* rlwimi */ 1476 mb = (word >> 6) & 0x1f; 1477 me = (word >> 1) & 0x1f; 1478 val = DATA32(regs->gpr[rd]); 1479 imm = MASK32(mb, me); 1480 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm); 1481 goto logical_done; 1482 1483 case 21: /* rlwinm */ 1484 mb = (word >> 6) & 0x1f; 1485 me = (word >> 1) & 0x1f; 1486 val = DATA32(regs->gpr[rd]); 1487 op->val = ROTATE(val, rb) & MASK32(mb, me); 1488 goto logical_done; 1489 1490 case 23: /* rlwnm */ 1491 mb = (word >> 6) & 0x1f; 1492 me = (word >> 1) & 0x1f; 1493 rb = regs->gpr[rb] & 0x1f; 1494 val = DATA32(regs->gpr[rd]); 1495 op->val = ROTATE(val, rb) & MASK32(mb, me); 1496 goto logical_done; 1497 1498 case 24: /* ori */ 1499 op->val = regs->gpr[rd] | (unsigned short) word; 1500 goto logical_done_nocc; 1501 1502 case 25: /* oris */ 1503 imm = (unsigned short) word; 1504 op->val = regs->gpr[rd] | (imm << 16); 1505 goto logical_done_nocc; 1506 1507 case 26: /* xori */ 1508 op->val = regs->gpr[rd] ^ (unsigned short) word; 1509 goto logical_done_nocc; 1510 1511 case 27: /* xoris */ 1512 imm = (unsigned short) word; 1513 op->val = regs->gpr[rd] ^ (imm << 16); 1514 goto logical_done_nocc; 1515 1516 case 28: /* andi. */ 1517 op->val = regs->gpr[rd] & (unsigned short) word; 1518 set_cr0(regs, op); 1519 goto logical_done_nocc; 1520 1521 case 29: /* andis. */ 1522 imm = (unsigned short) word; 1523 op->val = regs->gpr[rd] & (imm << 16); 1524 set_cr0(regs, op); 1525 goto logical_done_nocc; 1526 1527 #ifdef __powerpc64__ 1528 case 30: /* rld* */ 1529 mb = ((word >> 6) & 0x1f) | (word & 0x20); 1530 val = regs->gpr[rd]; 1531 if ((word & 0x10) == 0) { 1532 sh = rb | ((word & 2) << 4); 1533 val = ROTATE(val, sh); 1534 switch ((word >> 2) & 3) { 1535 case 0: /* rldicl */ 1536 val &= MASK64_L(mb); 1537 break; 1538 case 1: /* rldicr */ 1539 val &= MASK64_R(mb); 1540 break; 1541 case 2: /* rldic */ 1542 val &= MASK64(mb, 63 - sh); 1543 break; 1544 case 3: /* rldimi */ 1545 imm = MASK64(mb, 63 - sh); 1546 val = (regs->gpr[ra] & ~imm) | 1547 (val & imm); 1548 } 1549 op->val = val; 1550 goto logical_done; 1551 } else { 1552 sh = regs->gpr[rb] & 0x3f; 1553 val = ROTATE(val, sh); 1554 switch ((word >> 1) & 7) { 1555 case 0: /* rldcl */ 1556 op->val = val & MASK64_L(mb); 1557 goto logical_done; 1558 case 1: /* rldcr */ 1559 op->val = val & MASK64_R(mb); 1560 goto logical_done; 1561 } 1562 } 1563 #endif 1564 op->type = UNKNOWN; /* illegal instruction */ 1565 return 0; 1566 1567 case 31: 1568 /* isel occupies 32 minor opcodes */ 1569 if (((word >> 1) & 0x1f) == 15) { 1570 mb = (word >> 6) & 0x1f; /* bc field */ 1571 val = (regs->ccr >> (31 - mb)) & 1; 1572 val2 = (ra) ? regs->gpr[ra] : 0; 1573 1574 op->val = (val) ? val2 : regs->gpr[rb]; 1575 goto compute_done; 1576 } 1577 1578 switch ((word >> 1) & 0x3ff) { 1579 case 4: /* tw */ 1580 if (rd == 0x1f || 1581 (rd & trap_compare((int)regs->gpr[ra], 1582 (int)regs->gpr[rb]))) 1583 goto trap; 1584 return 1; 1585 #ifdef __powerpc64__ 1586 case 68: /* td */ 1587 if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb])) 1588 goto trap; 1589 return 1; 1590 #endif 1591 case 83: /* mfmsr */ 1592 if (regs->msr & MSR_PR) 1593 goto priv; 1594 op->type = MFMSR; 1595 op->reg = rd; 1596 return 0; 1597 case 146: /* mtmsr */ 1598 if (regs->msr & MSR_PR) 1599 goto priv; 1600 op->type = MTMSR; 1601 op->reg = rd; 1602 op->val = 0xffffffff & ~(MSR_ME | MSR_LE); 1603 return 0; 1604 #ifdef CONFIG_PPC64 1605 case 178: /* mtmsrd */ 1606 if (regs->msr & MSR_PR) 1607 goto priv; 1608 op->type = MTMSR; 1609 op->reg = rd; 1610 /* only MSR_EE and MSR_RI get changed if bit 15 set */ 1611 /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */ 1612 imm = (word & 0x10000)? 0x8002: 0xefffffffffffeffeUL; 1613 op->val = imm; 1614 return 0; 1615 #endif 1616 1617 case 19: /* mfcr */ 1618 imm = 0xffffffffUL; 1619 if ((word >> 20) & 1) { 1620 imm = 0xf0000000UL; 1621 for (sh = 0; sh < 8; ++sh) { 1622 if (word & (0x80000 >> sh)) 1623 break; 1624 imm >>= 4; 1625 } 1626 } 1627 op->val = regs->ccr & imm; 1628 goto compute_done; 1629 1630 case 144: /* mtcrf */ 1631 op->type = COMPUTE + SETCC; 1632 imm = 0xf0000000UL; 1633 val = regs->gpr[rd]; 1634 op->ccval = regs->ccr; 1635 for (sh = 0; sh < 8; ++sh) { 1636 if (word & (0x80000 >> sh)) 1637 op->ccval = (op->ccval & ~imm) | 1638 (val & imm); 1639 imm >>= 4; 1640 } 1641 return 1; 1642 1643 case 339: /* mfspr */ 1644 spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0); 1645 op->type = MFSPR; 1646 op->reg = rd; 1647 op->spr = spr; 1648 if (spr == SPRN_XER || spr == SPRN_LR || 1649 spr == SPRN_CTR) 1650 return 1; 1651 return 0; 1652 1653 case 467: /* mtspr */ 1654 spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0); 1655 op->type = MTSPR; 1656 op->val = regs->gpr[rd]; 1657 op->spr = spr; 1658 if (spr == SPRN_XER || spr == SPRN_LR || 1659 spr == SPRN_CTR) 1660 return 1; 1661 return 0; 1662 1663 /* 1664 * Compare instructions 1665 */ 1666 case 0: /* cmp */ 1667 val = regs->gpr[ra]; 1668 val2 = regs->gpr[rb]; 1669 #ifdef __powerpc64__ 1670 if ((rd & 1) == 0) { 1671 /* word (32-bit) compare */ 1672 val = (int) val; 1673 val2 = (int) val2; 1674 } 1675 #endif 1676 do_cmp_signed(regs, op, val, val2, rd >> 2); 1677 return 1; 1678 1679 case 32: /* cmpl */ 1680 val = regs->gpr[ra]; 1681 val2 = regs->gpr[rb]; 1682 #ifdef __powerpc64__ 1683 if ((rd & 1) == 0) { 1684 /* word (32-bit) compare */ 1685 val = (unsigned int) val; 1686 val2 = (unsigned int) val2; 1687 } 1688 #endif 1689 do_cmp_unsigned(regs, op, val, val2, rd >> 2); 1690 return 1; 1691 1692 case 508: /* cmpb */ 1693 do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]); 1694 goto logical_done_nocc; 1695 1696 /* 1697 * Arithmetic instructions 1698 */ 1699 case 8: /* subfc */ 1700 add_with_carry(regs, op, rd, ~regs->gpr[ra], 1701 regs->gpr[rb], 1); 1702 goto arith_done; 1703 #ifdef __powerpc64__ 1704 case 9: /* mulhdu */ 1705 asm("mulhdu %0,%1,%2" : "=r" (op->val) : 1706 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); 1707 goto arith_done; 1708 #endif 1709 case 10: /* addc */ 1710 add_with_carry(regs, op, rd, regs->gpr[ra], 1711 regs->gpr[rb], 0); 1712 goto arith_done; 1713 1714 case 11: /* mulhwu */ 1715 asm("mulhwu %0,%1,%2" : "=r" (op->val) : 1716 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); 1717 goto arith_done; 1718 1719 case 40: /* subf */ 1720 op->val = regs->gpr[rb] - regs->gpr[ra]; 1721 goto arith_done; 1722 #ifdef __powerpc64__ 1723 case 73: /* mulhd */ 1724 asm("mulhd %0,%1,%2" : "=r" (op->val) : 1725 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); 1726 goto arith_done; 1727 #endif 1728 case 75: /* mulhw */ 1729 asm("mulhw %0,%1,%2" : "=r" (op->val) : 1730 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); 1731 goto arith_done; 1732 1733 case 104: /* neg */ 1734 op->val = -regs->gpr[ra]; 1735 goto arith_done; 1736 1737 case 136: /* subfe */ 1738 add_with_carry(regs, op, rd, ~regs->gpr[ra], 1739 regs->gpr[rb], regs->xer & XER_CA); 1740 goto arith_done; 1741 1742 case 138: /* adde */ 1743 add_with_carry(regs, op, rd, regs->gpr[ra], 1744 regs->gpr[rb], regs->xer & XER_CA); 1745 goto arith_done; 1746 1747 case 200: /* subfze */ 1748 add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L, 1749 regs->xer & XER_CA); 1750 goto arith_done; 1751 1752 case 202: /* addze */ 1753 add_with_carry(regs, op, rd, regs->gpr[ra], 0L, 1754 regs->xer & XER_CA); 1755 goto arith_done; 1756 1757 case 232: /* subfme */ 1758 add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L, 1759 regs->xer & XER_CA); 1760 goto arith_done; 1761 #ifdef __powerpc64__ 1762 case 233: /* mulld */ 1763 op->val = regs->gpr[ra] * regs->gpr[rb]; 1764 goto arith_done; 1765 #endif 1766 case 234: /* addme */ 1767 add_with_carry(regs, op, rd, regs->gpr[ra], -1L, 1768 regs->xer & XER_CA); 1769 goto arith_done; 1770 1771 case 235: /* mullw */ 1772 op->val = (long)(int) regs->gpr[ra] * 1773 (int) regs->gpr[rb]; 1774 1775 goto arith_done; 1776 #ifdef __powerpc64__ 1777 case 265: /* modud */ 1778 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1779 return -1; 1780 op->val = regs->gpr[ra] % regs->gpr[rb]; 1781 goto compute_done; 1782 #endif 1783 case 266: /* add */ 1784 op->val = regs->gpr[ra] + regs->gpr[rb]; 1785 goto arith_done; 1786 1787 case 267: /* moduw */ 1788 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1789 return -1; 1790 op->val = (unsigned int) regs->gpr[ra] % 1791 (unsigned int) regs->gpr[rb]; 1792 goto compute_done; 1793 #ifdef __powerpc64__ 1794 case 457: /* divdu */ 1795 op->val = regs->gpr[ra] / regs->gpr[rb]; 1796 goto arith_done; 1797 #endif 1798 case 459: /* divwu */ 1799 op->val = (unsigned int) regs->gpr[ra] / 1800 (unsigned int) regs->gpr[rb]; 1801 goto arith_done; 1802 #ifdef __powerpc64__ 1803 case 489: /* divd */ 1804 op->val = (long int) regs->gpr[ra] / 1805 (long int) regs->gpr[rb]; 1806 goto arith_done; 1807 #endif 1808 case 491: /* divw */ 1809 op->val = (int) regs->gpr[ra] / 1810 (int) regs->gpr[rb]; 1811 goto arith_done; 1812 #ifdef __powerpc64__ 1813 case 425: /* divde[.] */ 1814 asm volatile(PPC_DIVDE(%0, %1, %2) : 1815 "=r" (op->val) : "r" (regs->gpr[ra]), 1816 "r" (regs->gpr[rb])); 1817 goto arith_done; 1818 case 393: /* divdeu[.] */ 1819 asm volatile(PPC_DIVDEU(%0, %1, %2) : 1820 "=r" (op->val) : "r" (regs->gpr[ra]), 1821 "r" (regs->gpr[rb])); 1822 goto arith_done; 1823 #endif 1824 case 755: /* darn */ 1825 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1826 return -1; 1827 switch (ra & 0x3) { 1828 case 0: 1829 /* 32-bit conditioned */ 1830 asm volatile(PPC_DARN(%0, 0) : "=r" (op->val)); 1831 goto compute_done; 1832 1833 case 1: 1834 /* 64-bit conditioned */ 1835 asm volatile(PPC_DARN(%0, 1) : "=r" (op->val)); 1836 goto compute_done; 1837 1838 case 2: 1839 /* 64-bit raw */ 1840 asm volatile(PPC_DARN(%0, 2) : "=r" (op->val)); 1841 goto compute_done; 1842 } 1843 1844 return -1; 1845 #ifdef __powerpc64__ 1846 case 777: /* modsd */ 1847 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1848 return -1; 1849 op->val = (long int) regs->gpr[ra] % 1850 (long int) regs->gpr[rb]; 1851 goto compute_done; 1852 #endif 1853 case 779: /* modsw */ 1854 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1855 return -1; 1856 op->val = (int) regs->gpr[ra] % 1857 (int) regs->gpr[rb]; 1858 goto compute_done; 1859 1860 1861 /* 1862 * Logical instructions 1863 */ 1864 case 26: /* cntlzw */ 1865 val = (unsigned int) regs->gpr[rd]; 1866 op->val = ( val ? __builtin_clz(val) : 32 ); 1867 goto logical_done; 1868 #ifdef __powerpc64__ 1869 case 58: /* cntlzd */ 1870 val = regs->gpr[rd]; 1871 op->val = ( val ? __builtin_clzl(val) : 64 ); 1872 goto logical_done; 1873 #endif 1874 case 28: /* and */ 1875 op->val = regs->gpr[rd] & regs->gpr[rb]; 1876 goto logical_done; 1877 1878 case 60: /* andc */ 1879 op->val = regs->gpr[rd] & ~regs->gpr[rb]; 1880 goto logical_done; 1881 1882 case 122: /* popcntb */ 1883 do_popcnt(regs, op, regs->gpr[rd], 8); 1884 goto logical_done_nocc; 1885 1886 case 124: /* nor */ 1887 op->val = ~(regs->gpr[rd] | regs->gpr[rb]); 1888 goto logical_done; 1889 1890 case 154: /* prtyw */ 1891 do_prty(regs, op, regs->gpr[rd], 32); 1892 goto logical_done_nocc; 1893 1894 case 186: /* prtyd */ 1895 do_prty(regs, op, regs->gpr[rd], 64); 1896 goto logical_done_nocc; 1897 #ifdef CONFIG_PPC64 1898 case 252: /* bpermd */ 1899 do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]); 1900 goto logical_done_nocc; 1901 #endif 1902 case 284: /* xor */ 1903 op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]); 1904 goto logical_done; 1905 1906 case 316: /* xor */ 1907 op->val = regs->gpr[rd] ^ regs->gpr[rb]; 1908 goto logical_done; 1909 1910 case 378: /* popcntw */ 1911 do_popcnt(regs, op, regs->gpr[rd], 32); 1912 goto logical_done_nocc; 1913 1914 case 412: /* orc */ 1915 op->val = regs->gpr[rd] | ~regs->gpr[rb]; 1916 goto logical_done; 1917 1918 case 444: /* or */ 1919 op->val = regs->gpr[rd] | regs->gpr[rb]; 1920 goto logical_done; 1921 1922 case 476: /* nand */ 1923 op->val = ~(regs->gpr[rd] & regs->gpr[rb]); 1924 goto logical_done; 1925 #ifdef CONFIG_PPC64 1926 case 506: /* popcntd */ 1927 do_popcnt(regs, op, regs->gpr[rd], 64); 1928 goto logical_done_nocc; 1929 #endif 1930 case 538: /* cnttzw */ 1931 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1932 return -1; 1933 val = (unsigned int) regs->gpr[rd]; 1934 op->val = (val ? __builtin_ctz(val) : 32); 1935 goto logical_done; 1936 #ifdef __powerpc64__ 1937 case 570: /* cnttzd */ 1938 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1939 return -1; 1940 val = regs->gpr[rd]; 1941 op->val = (val ? __builtin_ctzl(val) : 64); 1942 goto logical_done; 1943 #endif 1944 case 922: /* extsh */ 1945 op->val = (signed short) regs->gpr[rd]; 1946 goto logical_done; 1947 1948 case 954: /* extsb */ 1949 op->val = (signed char) regs->gpr[rd]; 1950 goto logical_done; 1951 #ifdef __powerpc64__ 1952 case 986: /* extsw */ 1953 op->val = (signed int) regs->gpr[rd]; 1954 goto logical_done; 1955 #endif 1956 1957 /* 1958 * Shift instructions 1959 */ 1960 case 24: /* slw */ 1961 sh = regs->gpr[rb] & 0x3f; 1962 if (sh < 32) 1963 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL; 1964 else 1965 op->val = 0; 1966 goto logical_done; 1967 1968 case 536: /* srw */ 1969 sh = regs->gpr[rb] & 0x3f; 1970 if (sh < 32) 1971 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh; 1972 else 1973 op->val = 0; 1974 goto logical_done; 1975 1976 case 792: /* sraw */ 1977 op->type = COMPUTE + SETREG + SETXER; 1978 sh = regs->gpr[rb] & 0x3f; 1979 ival = (signed int) regs->gpr[rd]; 1980 op->val = ival >> (sh < 32 ? sh : 31); 1981 op->xerval = regs->xer; 1982 if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0)) 1983 op->xerval |= XER_CA; 1984 else 1985 op->xerval &= ~XER_CA; 1986 set_ca32(op, op->xerval & XER_CA); 1987 goto logical_done; 1988 1989 case 824: /* srawi */ 1990 op->type = COMPUTE + SETREG + SETXER; 1991 sh = rb; 1992 ival = (signed int) regs->gpr[rd]; 1993 op->val = ival >> sh; 1994 op->xerval = regs->xer; 1995 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0) 1996 op->xerval |= XER_CA; 1997 else 1998 op->xerval &= ~XER_CA; 1999 set_ca32(op, op->xerval & XER_CA); 2000 goto logical_done; 2001 2002 #ifdef __powerpc64__ 2003 case 27: /* sld */ 2004 sh = regs->gpr[rb] & 0x7f; 2005 if (sh < 64) 2006 op->val = regs->gpr[rd] << sh; 2007 else 2008 op->val = 0; 2009 goto logical_done; 2010 2011 case 539: /* srd */ 2012 sh = regs->gpr[rb] & 0x7f; 2013 if (sh < 64) 2014 op->val = regs->gpr[rd] >> sh; 2015 else 2016 op->val = 0; 2017 goto logical_done; 2018 2019 case 794: /* srad */ 2020 op->type = COMPUTE + SETREG + SETXER; 2021 sh = regs->gpr[rb] & 0x7f; 2022 ival = (signed long int) regs->gpr[rd]; 2023 op->val = ival >> (sh < 64 ? sh : 63); 2024 op->xerval = regs->xer; 2025 if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0)) 2026 op->xerval |= XER_CA; 2027 else 2028 op->xerval &= ~XER_CA; 2029 set_ca32(op, op->xerval & XER_CA); 2030 goto logical_done; 2031 2032 case 826: /* sradi with sh_5 = 0 */ 2033 case 827: /* sradi with sh_5 = 1 */ 2034 op->type = COMPUTE + SETREG + SETXER; 2035 sh = rb | ((word & 2) << 4); 2036 ival = (signed long int) regs->gpr[rd]; 2037 op->val = ival >> sh; 2038 op->xerval = regs->xer; 2039 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0) 2040 op->xerval |= XER_CA; 2041 else 2042 op->xerval &= ~XER_CA; 2043 set_ca32(op, op->xerval & XER_CA); 2044 goto logical_done; 2045 2046 case 890: /* extswsli with sh_5 = 0 */ 2047 case 891: /* extswsli with sh_5 = 1 */ 2048 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 2049 return -1; 2050 op->type = COMPUTE + SETREG; 2051 sh = rb | ((word & 2) << 4); 2052 val = (signed int) regs->gpr[rd]; 2053 if (sh) 2054 op->val = ROTATE(val, sh) & MASK64(0, 63 - sh); 2055 else 2056 op->val = val; 2057 goto logical_done; 2058 2059 #endif /* __powerpc64__ */ 2060 2061 /* 2062 * Cache instructions 2063 */ 2064 case 54: /* dcbst */ 2065 op->type = MKOP(CACHEOP, DCBST, 0); 2066 op->ea = xform_ea(word, regs); 2067 return 0; 2068 2069 case 86: /* dcbf */ 2070 op->type = MKOP(CACHEOP, DCBF, 0); 2071 op->ea = xform_ea(word, regs); 2072 return 0; 2073 2074 case 246: /* dcbtst */ 2075 op->type = MKOP(CACHEOP, DCBTST, 0); 2076 op->ea = xform_ea(word, regs); 2077 op->reg = rd; 2078 return 0; 2079 2080 case 278: /* dcbt */ 2081 op->type = MKOP(CACHEOP, DCBTST, 0); 2082 op->ea = xform_ea(word, regs); 2083 op->reg = rd; 2084 return 0; 2085 2086 case 982: /* icbi */ 2087 op->type = MKOP(CACHEOP, ICBI, 0); 2088 op->ea = xform_ea(word, regs); 2089 return 0; 2090 2091 case 1014: /* dcbz */ 2092 op->type = MKOP(CACHEOP, DCBZ, 0); 2093 op->ea = xform_ea(word, regs); 2094 return 0; 2095 } 2096 break; 2097 } 2098 2099 /* 2100 * Loads and stores. 2101 */ 2102 op->type = UNKNOWN; 2103 op->update_reg = ra; 2104 op->reg = rd; 2105 op->val = regs->gpr[rd]; 2106 u = (word >> 20) & UPDATE; 2107 op->vsx_flags = 0; 2108 2109 switch (opcode) { 2110 case 31: 2111 u = word & UPDATE; 2112 op->ea = xform_ea(word, regs); 2113 switch ((word >> 1) & 0x3ff) { 2114 case 20: /* lwarx */ 2115 op->type = MKOP(LARX, 0, 4); 2116 break; 2117 2118 case 150: /* stwcx. */ 2119 op->type = MKOP(STCX, 0, 4); 2120 break; 2121 2122 #ifdef __powerpc64__ 2123 case 84: /* ldarx */ 2124 op->type = MKOP(LARX, 0, 8); 2125 break; 2126 2127 case 214: /* stdcx. */ 2128 op->type = MKOP(STCX, 0, 8); 2129 break; 2130 2131 case 52: /* lbarx */ 2132 op->type = MKOP(LARX, 0, 1); 2133 break; 2134 2135 case 694: /* stbcx. */ 2136 op->type = MKOP(STCX, 0, 1); 2137 break; 2138 2139 case 116: /* lharx */ 2140 op->type = MKOP(LARX, 0, 2); 2141 break; 2142 2143 case 726: /* sthcx. */ 2144 op->type = MKOP(STCX, 0, 2); 2145 break; 2146 2147 case 276: /* lqarx */ 2148 if (!((rd & 1) || rd == ra || rd == rb)) 2149 op->type = MKOP(LARX, 0, 16); 2150 break; 2151 2152 case 182: /* stqcx. */ 2153 if (!(rd & 1)) 2154 op->type = MKOP(STCX, 0, 16); 2155 break; 2156 #endif 2157 2158 case 23: /* lwzx */ 2159 case 55: /* lwzux */ 2160 op->type = MKOP(LOAD, u, 4); 2161 break; 2162 2163 case 87: /* lbzx */ 2164 case 119: /* lbzux */ 2165 op->type = MKOP(LOAD, u, 1); 2166 break; 2167 2168 #ifdef CONFIG_ALTIVEC 2169 /* 2170 * Note: for the load/store vector element instructions, 2171 * bits of the EA say which field of the VMX register to use. 2172 */ 2173 case 7: /* lvebx */ 2174 op->type = MKOP(LOAD_VMX, 0, 1); 2175 op->element_size = 1; 2176 break; 2177 2178 case 39: /* lvehx */ 2179 op->type = MKOP(LOAD_VMX, 0, 2); 2180 op->element_size = 2; 2181 break; 2182 2183 case 71: /* lvewx */ 2184 op->type = MKOP(LOAD_VMX, 0, 4); 2185 op->element_size = 4; 2186 break; 2187 2188 case 103: /* lvx */ 2189 case 359: /* lvxl */ 2190 op->type = MKOP(LOAD_VMX, 0, 16); 2191 op->element_size = 16; 2192 break; 2193 2194 case 135: /* stvebx */ 2195 op->type = MKOP(STORE_VMX, 0, 1); 2196 op->element_size = 1; 2197 break; 2198 2199 case 167: /* stvehx */ 2200 op->type = MKOP(STORE_VMX, 0, 2); 2201 op->element_size = 2; 2202 break; 2203 2204 case 199: /* stvewx */ 2205 op->type = MKOP(STORE_VMX, 0, 4); 2206 op->element_size = 4; 2207 break; 2208 2209 case 231: /* stvx */ 2210 case 487: /* stvxl */ 2211 op->type = MKOP(STORE_VMX, 0, 16); 2212 break; 2213 #endif /* CONFIG_ALTIVEC */ 2214 2215 #ifdef __powerpc64__ 2216 case 21: /* ldx */ 2217 case 53: /* ldux */ 2218 op->type = MKOP(LOAD, u, 8); 2219 break; 2220 2221 case 149: /* stdx */ 2222 case 181: /* stdux */ 2223 op->type = MKOP(STORE, u, 8); 2224 break; 2225 #endif 2226 2227 case 151: /* stwx */ 2228 case 183: /* stwux */ 2229 op->type = MKOP(STORE, u, 4); 2230 break; 2231 2232 case 215: /* stbx */ 2233 case 247: /* stbux */ 2234 op->type = MKOP(STORE, u, 1); 2235 break; 2236 2237 case 279: /* lhzx */ 2238 case 311: /* lhzux */ 2239 op->type = MKOP(LOAD, u, 2); 2240 break; 2241 2242 #ifdef __powerpc64__ 2243 case 341: /* lwax */ 2244 case 373: /* lwaux */ 2245 op->type = MKOP(LOAD, SIGNEXT | u, 4); 2246 break; 2247 #endif 2248 2249 case 343: /* lhax */ 2250 case 375: /* lhaux */ 2251 op->type = MKOP(LOAD, SIGNEXT | u, 2); 2252 break; 2253 2254 case 407: /* sthx */ 2255 case 439: /* sthux */ 2256 op->type = MKOP(STORE, u, 2); 2257 break; 2258 2259 #ifdef __powerpc64__ 2260 case 532: /* ldbrx */ 2261 op->type = MKOP(LOAD, BYTEREV, 8); 2262 break; 2263 2264 #endif 2265 case 533: /* lswx */ 2266 op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f); 2267 break; 2268 2269 case 534: /* lwbrx */ 2270 op->type = MKOP(LOAD, BYTEREV, 4); 2271 break; 2272 2273 case 597: /* lswi */ 2274 if (rb == 0) 2275 rb = 32; /* # bytes to load */ 2276 op->type = MKOP(LOAD_MULTI, 0, rb); 2277 op->ea = ra ? regs->gpr[ra] : 0; 2278 break; 2279 2280 #ifdef CONFIG_PPC_FPU 2281 case 535: /* lfsx */ 2282 case 567: /* lfsux */ 2283 op->type = MKOP(LOAD_FP, u | FPCONV, 4); 2284 break; 2285 2286 case 599: /* lfdx */ 2287 case 631: /* lfdux */ 2288 op->type = MKOP(LOAD_FP, u, 8); 2289 break; 2290 2291 case 663: /* stfsx */ 2292 case 695: /* stfsux */ 2293 op->type = MKOP(STORE_FP, u | FPCONV, 4); 2294 break; 2295 2296 case 727: /* stfdx */ 2297 case 759: /* stfdux */ 2298 op->type = MKOP(STORE_FP, u, 8); 2299 break; 2300 2301 #ifdef __powerpc64__ 2302 case 791: /* lfdpx */ 2303 op->type = MKOP(LOAD_FP, 0, 16); 2304 break; 2305 2306 case 855: /* lfiwax */ 2307 op->type = MKOP(LOAD_FP, SIGNEXT, 4); 2308 break; 2309 2310 case 887: /* lfiwzx */ 2311 op->type = MKOP(LOAD_FP, 0, 4); 2312 break; 2313 2314 case 919: /* stfdpx */ 2315 op->type = MKOP(STORE_FP, 0, 16); 2316 break; 2317 2318 case 983: /* stfiwx */ 2319 op->type = MKOP(STORE_FP, 0, 4); 2320 break; 2321 #endif /* __powerpc64 */ 2322 #endif /* CONFIG_PPC_FPU */ 2323 2324 #ifdef __powerpc64__ 2325 case 660: /* stdbrx */ 2326 op->type = MKOP(STORE, BYTEREV, 8); 2327 op->val = byterev_8(regs->gpr[rd]); 2328 break; 2329 2330 #endif 2331 case 661: /* stswx */ 2332 op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f); 2333 break; 2334 2335 case 662: /* stwbrx */ 2336 op->type = MKOP(STORE, BYTEREV, 4); 2337 op->val = byterev_4(regs->gpr[rd]); 2338 break; 2339 2340 case 725: /* stswi */ 2341 if (rb == 0) 2342 rb = 32; /* # bytes to store */ 2343 op->type = MKOP(STORE_MULTI, 0, rb); 2344 op->ea = ra ? regs->gpr[ra] : 0; 2345 break; 2346 2347 case 790: /* lhbrx */ 2348 op->type = MKOP(LOAD, BYTEREV, 2); 2349 break; 2350 2351 case 918: /* sthbrx */ 2352 op->type = MKOP(STORE, BYTEREV, 2); 2353 op->val = byterev_2(regs->gpr[rd]); 2354 break; 2355 2356 #ifdef CONFIG_VSX 2357 case 12: /* lxsiwzx */ 2358 op->reg = rd | ((word & 1) << 5); 2359 op->type = MKOP(LOAD_VSX, 0, 4); 2360 op->element_size = 8; 2361 break; 2362 2363 case 76: /* lxsiwax */ 2364 op->reg = rd | ((word & 1) << 5); 2365 op->type = MKOP(LOAD_VSX, SIGNEXT, 4); 2366 op->element_size = 8; 2367 break; 2368 2369 case 140: /* stxsiwx */ 2370 op->reg = rd | ((word & 1) << 5); 2371 op->type = MKOP(STORE_VSX, 0, 4); 2372 op->element_size = 8; 2373 break; 2374 2375 case 268: /* lxvx */ 2376 op->reg = rd | ((word & 1) << 5); 2377 op->type = MKOP(LOAD_VSX, 0, 16); 2378 op->element_size = 16; 2379 op->vsx_flags = VSX_CHECK_VEC; 2380 break; 2381 2382 case 269: /* lxvl */ 2383 case 301: { /* lxvll */ 2384 int nb; 2385 op->reg = rd | ((word & 1) << 5); 2386 op->ea = ra ? regs->gpr[ra] : 0; 2387 nb = regs->gpr[rb] & 0xff; 2388 if (nb > 16) 2389 nb = 16; 2390 op->type = MKOP(LOAD_VSX, 0, nb); 2391 op->element_size = 16; 2392 op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) | 2393 VSX_CHECK_VEC; 2394 break; 2395 } 2396 case 332: /* lxvdsx */ 2397 op->reg = rd | ((word & 1) << 5); 2398 op->type = MKOP(LOAD_VSX, 0, 8); 2399 op->element_size = 8; 2400 op->vsx_flags = VSX_SPLAT; 2401 break; 2402 2403 case 364: /* lxvwsx */ 2404 op->reg = rd | ((word & 1) << 5); 2405 op->type = MKOP(LOAD_VSX, 0, 4); 2406 op->element_size = 4; 2407 op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC; 2408 break; 2409 2410 case 396: /* stxvx */ 2411 op->reg = rd | ((word & 1) << 5); 2412 op->type = MKOP(STORE_VSX, 0, 16); 2413 op->element_size = 16; 2414 op->vsx_flags = VSX_CHECK_VEC; 2415 break; 2416 2417 case 397: /* stxvl */ 2418 case 429: { /* stxvll */ 2419 int nb; 2420 op->reg = rd | ((word & 1) << 5); 2421 op->ea = ra ? regs->gpr[ra] : 0; 2422 nb = regs->gpr[rb] & 0xff; 2423 if (nb > 16) 2424 nb = 16; 2425 op->type = MKOP(STORE_VSX, 0, nb); 2426 op->element_size = 16; 2427 op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) | 2428 VSX_CHECK_VEC; 2429 break; 2430 } 2431 case 524: /* lxsspx */ 2432 op->reg = rd | ((word & 1) << 5); 2433 op->type = MKOP(LOAD_VSX, 0, 4); 2434 op->element_size = 8; 2435 op->vsx_flags = VSX_FPCONV; 2436 break; 2437 2438 case 588: /* lxsdx */ 2439 op->reg = rd | ((word & 1) << 5); 2440 op->type = MKOP(LOAD_VSX, 0, 8); 2441 op->element_size = 8; 2442 break; 2443 2444 case 652: /* stxsspx */ 2445 op->reg = rd | ((word & 1) << 5); 2446 op->type = MKOP(STORE_VSX, 0, 4); 2447 op->element_size = 8; 2448 op->vsx_flags = VSX_FPCONV; 2449 break; 2450 2451 case 716: /* stxsdx */ 2452 op->reg = rd | ((word & 1) << 5); 2453 op->type = MKOP(STORE_VSX, 0, 8); 2454 op->element_size = 8; 2455 break; 2456 2457 case 780: /* lxvw4x */ 2458 op->reg = rd | ((word & 1) << 5); 2459 op->type = MKOP(LOAD_VSX, 0, 16); 2460 op->element_size = 4; 2461 break; 2462 2463 case 781: /* lxsibzx */ 2464 op->reg = rd | ((word & 1) << 5); 2465 op->type = MKOP(LOAD_VSX, 0, 1); 2466 op->element_size = 8; 2467 op->vsx_flags = VSX_CHECK_VEC; 2468 break; 2469 2470 case 812: /* lxvh8x */ 2471 op->reg = rd | ((word & 1) << 5); 2472 op->type = MKOP(LOAD_VSX, 0, 16); 2473 op->element_size = 2; 2474 op->vsx_flags = VSX_CHECK_VEC; 2475 break; 2476 2477 case 813: /* lxsihzx */ 2478 op->reg = rd | ((word & 1) << 5); 2479 op->type = MKOP(LOAD_VSX, 0, 2); 2480 op->element_size = 8; 2481 op->vsx_flags = VSX_CHECK_VEC; 2482 break; 2483 2484 case 844: /* lxvd2x */ 2485 op->reg = rd | ((word & 1) << 5); 2486 op->type = MKOP(LOAD_VSX, 0, 16); 2487 op->element_size = 8; 2488 break; 2489 2490 case 876: /* lxvb16x */ 2491 op->reg = rd | ((word & 1) << 5); 2492 op->type = MKOP(LOAD_VSX, 0, 16); 2493 op->element_size = 1; 2494 op->vsx_flags = VSX_CHECK_VEC; 2495 break; 2496 2497 case 908: /* stxvw4x */ 2498 op->reg = rd | ((word & 1) << 5); 2499 op->type = MKOP(STORE_VSX, 0, 16); 2500 op->element_size = 4; 2501 break; 2502 2503 case 909: /* stxsibx */ 2504 op->reg = rd | ((word & 1) << 5); 2505 op->type = MKOP(STORE_VSX, 0, 1); 2506 op->element_size = 8; 2507 op->vsx_flags = VSX_CHECK_VEC; 2508 break; 2509 2510 case 940: /* stxvh8x */ 2511 op->reg = rd | ((word & 1) << 5); 2512 op->type = MKOP(STORE_VSX, 0, 16); 2513 op->element_size = 2; 2514 op->vsx_flags = VSX_CHECK_VEC; 2515 break; 2516 2517 case 941: /* stxsihx */ 2518 op->reg = rd | ((word & 1) << 5); 2519 op->type = MKOP(STORE_VSX, 0, 2); 2520 op->element_size = 8; 2521 op->vsx_flags = VSX_CHECK_VEC; 2522 break; 2523 2524 case 972: /* stxvd2x */ 2525 op->reg = rd | ((word & 1) << 5); 2526 op->type = MKOP(STORE_VSX, 0, 16); 2527 op->element_size = 8; 2528 break; 2529 2530 case 1004: /* stxvb16x */ 2531 op->reg = rd | ((word & 1) << 5); 2532 op->type = MKOP(STORE_VSX, 0, 16); 2533 op->element_size = 1; 2534 op->vsx_flags = VSX_CHECK_VEC; 2535 break; 2536 2537 #endif /* CONFIG_VSX */ 2538 } 2539 break; 2540 2541 case 32: /* lwz */ 2542 case 33: /* lwzu */ 2543 op->type = MKOP(LOAD, u, 4); 2544 op->ea = dform_ea(word, regs); 2545 break; 2546 2547 case 34: /* lbz */ 2548 case 35: /* lbzu */ 2549 op->type = MKOP(LOAD, u, 1); 2550 op->ea = dform_ea(word, regs); 2551 break; 2552 2553 case 36: /* stw */ 2554 case 37: /* stwu */ 2555 op->type = MKOP(STORE, u, 4); 2556 op->ea = dform_ea(word, regs); 2557 break; 2558 2559 case 38: /* stb */ 2560 case 39: /* stbu */ 2561 op->type = MKOP(STORE, u, 1); 2562 op->ea = dform_ea(word, regs); 2563 break; 2564 2565 case 40: /* lhz */ 2566 case 41: /* lhzu */ 2567 op->type = MKOP(LOAD, u, 2); 2568 op->ea = dform_ea(word, regs); 2569 break; 2570 2571 case 42: /* lha */ 2572 case 43: /* lhau */ 2573 op->type = MKOP(LOAD, SIGNEXT | u, 2); 2574 op->ea = dform_ea(word, regs); 2575 break; 2576 2577 case 44: /* sth */ 2578 case 45: /* sthu */ 2579 op->type = MKOP(STORE, u, 2); 2580 op->ea = dform_ea(word, regs); 2581 break; 2582 2583 case 46: /* lmw */ 2584 if (ra >= rd) 2585 break; /* invalid form, ra in range to load */ 2586 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd)); 2587 op->ea = dform_ea(word, regs); 2588 break; 2589 2590 case 47: /* stmw */ 2591 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd)); 2592 op->ea = dform_ea(word, regs); 2593 break; 2594 2595 #ifdef CONFIG_PPC_FPU 2596 case 48: /* lfs */ 2597 case 49: /* lfsu */ 2598 op->type = MKOP(LOAD_FP, u | FPCONV, 4); 2599 op->ea = dform_ea(word, regs); 2600 break; 2601 2602 case 50: /* lfd */ 2603 case 51: /* lfdu */ 2604 op->type = MKOP(LOAD_FP, u, 8); 2605 op->ea = dform_ea(word, regs); 2606 break; 2607 2608 case 52: /* stfs */ 2609 case 53: /* stfsu */ 2610 op->type = MKOP(STORE_FP, u | FPCONV, 4); 2611 op->ea = dform_ea(word, regs); 2612 break; 2613 2614 case 54: /* stfd */ 2615 case 55: /* stfdu */ 2616 op->type = MKOP(STORE_FP, u, 8); 2617 op->ea = dform_ea(word, regs); 2618 break; 2619 #endif 2620 2621 #ifdef __powerpc64__ 2622 case 56: /* lq */ 2623 if (!((rd & 1) || (rd == ra))) 2624 op->type = MKOP(LOAD, 0, 16); 2625 op->ea = dqform_ea(word, regs); 2626 break; 2627 #endif 2628 2629 #ifdef CONFIG_VSX 2630 case 57: /* lfdp, lxsd, lxssp */ 2631 op->ea = dsform_ea(word, regs); 2632 switch (word & 3) { 2633 case 0: /* lfdp */ 2634 if (rd & 1) 2635 break; /* reg must be even */ 2636 op->type = MKOP(LOAD_FP, 0, 16); 2637 break; 2638 case 2: /* lxsd */ 2639 op->reg = rd + 32; 2640 op->type = MKOP(LOAD_VSX, 0, 8); 2641 op->element_size = 8; 2642 op->vsx_flags = VSX_CHECK_VEC; 2643 break; 2644 case 3: /* lxssp */ 2645 op->reg = rd + 32; 2646 op->type = MKOP(LOAD_VSX, 0, 4); 2647 op->element_size = 8; 2648 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC; 2649 break; 2650 } 2651 break; 2652 #endif /* CONFIG_VSX */ 2653 2654 #ifdef __powerpc64__ 2655 case 58: /* ld[u], lwa */ 2656 op->ea = dsform_ea(word, regs); 2657 switch (word & 3) { 2658 case 0: /* ld */ 2659 op->type = MKOP(LOAD, 0, 8); 2660 break; 2661 case 1: /* ldu */ 2662 op->type = MKOP(LOAD, UPDATE, 8); 2663 break; 2664 case 2: /* lwa */ 2665 op->type = MKOP(LOAD, SIGNEXT, 4); 2666 break; 2667 } 2668 break; 2669 #endif 2670 2671 #ifdef CONFIG_VSX 2672 case 61: /* stfdp, lxv, stxsd, stxssp, stxv */ 2673 switch (word & 7) { 2674 case 0: /* stfdp with LSB of DS field = 0 */ 2675 case 4: /* stfdp with LSB of DS field = 1 */ 2676 op->ea = dsform_ea(word, regs); 2677 op->type = MKOP(STORE_FP, 0, 16); 2678 break; 2679 2680 case 1: /* lxv */ 2681 op->ea = dqform_ea(word, regs); 2682 if (word & 8) 2683 op->reg = rd + 32; 2684 op->type = MKOP(LOAD_VSX, 0, 16); 2685 op->element_size = 16; 2686 op->vsx_flags = VSX_CHECK_VEC; 2687 break; 2688 2689 case 2: /* stxsd with LSB of DS field = 0 */ 2690 case 6: /* stxsd with LSB of DS field = 1 */ 2691 op->ea = dsform_ea(word, regs); 2692 op->reg = rd + 32; 2693 op->type = MKOP(STORE_VSX, 0, 8); 2694 op->element_size = 8; 2695 op->vsx_flags = VSX_CHECK_VEC; 2696 break; 2697 2698 case 3: /* stxssp with LSB of DS field = 0 */ 2699 case 7: /* stxssp with LSB of DS field = 1 */ 2700 op->ea = dsform_ea(word, regs); 2701 op->reg = rd + 32; 2702 op->type = MKOP(STORE_VSX, 0, 4); 2703 op->element_size = 8; 2704 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC; 2705 break; 2706 2707 case 5: /* stxv */ 2708 op->ea = dqform_ea(word, regs); 2709 if (word & 8) 2710 op->reg = rd + 32; 2711 op->type = MKOP(STORE_VSX, 0, 16); 2712 op->element_size = 16; 2713 op->vsx_flags = VSX_CHECK_VEC; 2714 break; 2715 } 2716 break; 2717 #endif /* CONFIG_VSX */ 2718 2719 #ifdef __powerpc64__ 2720 case 62: /* std[u] */ 2721 op->ea = dsform_ea(word, regs); 2722 switch (word & 3) { 2723 case 0: /* std */ 2724 op->type = MKOP(STORE, 0, 8); 2725 break; 2726 case 1: /* stdu */ 2727 op->type = MKOP(STORE, UPDATE, 8); 2728 break; 2729 case 2: /* stq */ 2730 if (!(rd & 1)) 2731 op->type = MKOP(STORE, 0, 16); 2732 break; 2733 } 2734 break; 2735 case 1: /* Prefixed instructions */ 2736 prefix_r = GET_PREFIX_R(word); 2737 ra = GET_PREFIX_RA(suffix); 2738 op->update_reg = ra; 2739 rd = (suffix >> 21) & 0x1f; 2740 op->reg = rd; 2741 op->val = regs->gpr[rd]; 2742 2743 suffixopcode = get_op(suffix); 2744 prefixtype = (word >> 24) & 0x3; 2745 switch (prefixtype) { 2746 case 0: /* Type 00 Eight-Byte Load/Store */ 2747 if (prefix_r && ra) 2748 break; 2749 op->ea = mlsd_8lsd_ea(word, suffix, regs); 2750 switch (suffixopcode) { 2751 case 41: /* plwa */ 2752 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4); 2753 break; 2754 case 42: /* plxsd */ 2755 op->reg = rd + 32; 2756 op->type = MKOP(LOAD_VSX, PREFIXED, 8); 2757 op->element_size = 8; 2758 op->vsx_flags = VSX_CHECK_VEC; 2759 break; 2760 case 43: /* plxssp */ 2761 op->reg = rd + 32; 2762 op->type = MKOP(LOAD_VSX, PREFIXED, 4); 2763 op->element_size = 8; 2764 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC; 2765 break; 2766 case 46: /* pstxsd */ 2767 op->reg = rd + 32; 2768 op->type = MKOP(STORE_VSX, PREFIXED, 8); 2769 op->element_size = 8; 2770 op->vsx_flags = VSX_CHECK_VEC; 2771 break; 2772 case 47: /* pstxssp */ 2773 op->reg = rd + 32; 2774 op->type = MKOP(STORE_VSX, PREFIXED, 4); 2775 op->element_size = 8; 2776 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC; 2777 break; 2778 case 51: /* plxv1 */ 2779 op->reg += 32; 2780 fallthrough; 2781 case 50: /* plxv0 */ 2782 op->type = MKOP(LOAD_VSX, PREFIXED, 16); 2783 op->element_size = 16; 2784 op->vsx_flags = VSX_CHECK_VEC; 2785 break; 2786 case 55: /* pstxv1 */ 2787 op->reg = rd + 32; 2788 fallthrough; 2789 case 54: /* pstxv0 */ 2790 op->type = MKOP(STORE_VSX, PREFIXED, 16); 2791 op->element_size = 16; 2792 op->vsx_flags = VSX_CHECK_VEC; 2793 break; 2794 case 56: /* plq */ 2795 op->type = MKOP(LOAD, PREFIXED, 16); 2796 break; 2797 case 57: /* pld */ 2798 op->type = MKOP(LOAD, PREFIXED, 8); 2799 break; 2800 case 60: /* stq */ 2801 op->type = MKOP(STORE, PREFIXED, 16); 2802 break; 2803 case 61: /* pstd */ 2804 op->type = MKOP(STORE, PREFIXED, 8); 2805 break; 2806 } 2807 break; 2808 case 1: /* Type 01 Eight-Byte Register-to-Register */ 2809 break; 2810 case 2: /* Type 10 Modified Load/Store */ 2811 if (prefix_r && ra) 2812 break; 2813 op->ea = mlsd_8lsd_ea(word, suffix, regs); 2814 switch (suffixopcode) { 2815 case 32: /* plwz */ 2816 op->type = MKOP(LOAD, PREFIXED, 4); 2817 break; 2818 case 34: /* plbz */ 2819 op->type = MKOP(LOAD, PREFIXED, 1); 2820 break; 2821 case 36: /* pstw */ 2822 op->type = MKOP(STORE, PREFIXED, 4); 2823 break; 2824 case 38: /* pstb */ 2825 op->type = MKOP(STORE, PREFIXED, 1); 2826 break; 2827 case 40: /* plhz */ 2828 op->type = MKOP(LOAD, PREFIXED, 2); 2829 break; 2830 case 42: /* plha */ 2831 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 2); 2832 break; 2833 case 44: /* psth */ 2834 op->type = MKOP(STORE, PREFIXED, 2); 2835 break; 2836 case 48: /* plfs */ 2837 op->type = MKOP(LOAD_FP, PREFIXED | FPCONV, 4); 2838 break; 2839 case 50: /* plfd */ 2840 op->type = MKOP(LOAD_FP, PREFIXED, 8); 2841 break; 2842 case 52: /* pstfs */ 2843 op->type = MKOP(STORE_FP, PREFIXED | FPCONV, 4); 2844 break; 2845 case 54: /* pstfd */ 2846 op->type = MKOP(STORE_FP, PREFIXED, 8); 2847 break; 2848 } 2849 break; 2850 case 3: /* Type 11 Modified Register-to-Register */ 2851 break; 2852 } 2853 #endif /* __powerpc64__ */ 2854 2855 } 2856 2857 #ifdef CONFIG_VSX 2858 if ((GETTYPE(op->type) == LOAD_VSX || 2859 GETTYPE(op->type) == STORE_VSX) && 2860 !cpu_has_feature(CPU_FTR_VSX)) { 2861 return -1; 2862 } 2863 #endif /* CONFIG_VSX */ 2864 2865 return 0; 2866 2867 logical_done: 2868 if (word & 1) 2869 set_cr0(regs, op); 2870 logical_done_nocc: 2871 op->reg = ra; 2872 op->type |= SETREG; 2873 return 1; 2874 2875 arith_done: 2876 if (word & 1) 2877 set_cr0(regs, op); 2878 compute_done: 2879 op->reg = rd; 2880 op->type |= SETREG; 2881 return 1; 2882 2883 priv: 2884 op->type = INTERRUPT | 0x700; 2885 op->val = SRR1_PROGPRIV; 2886 return 0; 2887 2888 trap: 2889 op->type = INTERRUPT | 0x700; 2890 op->val = SRR1_PROGTRAP; 2891 return 0; 2892 } 2893 EXPORT_SYMBOL_GPL(analyse_instr); 2894 NOKPROBE_SYMBOL(analyse_instr); 2895 2896 /* 2897 * For PPC32 we always use stwu with r1 to change the stack pointer. 2898 * So this emulated store may corrupt the exception frame, now we 2899 * have to provide the exception frame trampoline, which is pushed 2900 * below the kprobed function stack. So we only update gpr[1] but 2901 * don't emulate the real store operation. We will do real store 2902 * operation safely in exception return code by checking this flag. 2903 */ 2904 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs) 2905 { 2906 #ifdef CONFIG_PPC32 2907 /* 2908 * Check if we will touch kernel stack overflow 2909 */ 2910 if (ea - STACK_INT_FRAME_SIZE <= current->thread.ksp_limit) { 2911 printk(KERN_CRIT "Can't kprobe this since kernel stack would overflow.\n"); 2912 return -EINVAL; 2913 } 2914 #endif /* CONFIG_PPC32 */ 2915 /* 2916 * Check if we already set since that means we'll 2917 * lose the previous value. 2918 */ 2919 WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE)); 2920 set_thread_flag(TIF_EMULATE_STACK_STORE); 2921 return 0; 2922 } 2923 2924 static nokprobe_inline void do_signext(unsigned long *valp, int size) 2925 { 2926 switch (size) { 2927 case 2: 2928 *valp = (signed short) *valp; 2929 break; 2930 case 4: 2931 *valp = (signed int) *valp; 2932 break; 2933 } 2934 } 2935 2936 static nokprobe_inline void do_byterev(unsigned long *valp, int size) 2937 { 2938 switch (size) { 2939 case 2: 2940 *valp = byterev_2(*valp); 2941 break; 2942 case 4: 2943 *valp = byterev_4(*valp); 2944 break; 2945 #ifdef __powerpc64__ 2946 case 8: 2947 *valp = byterev_8(*valp); 2948 break; 2949 #endif 2950 } 2951 } 2952 2953 /* 2954 * Emulate an instruction that can be executed just by updating 2955 * fields in *regs. 2956 */ 2957 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op) 2958 { 2959 unsigned long next_pc; 2960 2961 next_pc = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op->type)); 2962 switch (GETTYPE(op->type)) { 2963 case COMPUTE: 2964 if (op->type & SETREG) 2965 regs->gpr[op->reg] = op->val; 2966 if (op->type & SETCC) 2967 regs->ccr = op->ccval; 2968 if (op->type & SETXER) 2969 regs->xer = op->xerval; 2970 break; 2971 2972 case BRANCH: 2973 if (op->type & SETLK) 2974 regs->link = next_pc; 2975 if (op->type & BRTAKEN) 2976 next_pc = op->val; 2977 if (op->type & DECCTR) 2978 --regs->ctr; 2979 break; 2980 2981 case BARRIER: 2982 switch (op->type & BARRIER_MASK) { 2983 case BARRIER_SYNC: 2984 mb(); 2985 break; 2986 case BARRIER_ISYNC: 2987 isync(); 2988 break; 2989 case BARRIER_EIEIO: 2990 eieio(); 2991 break; 2992 case BARRIER_LWSYNC: 2993 asm volatile("lwsync" : : : "memory"); 2994 break; 2995 case BARRIER_PTESYNC: 2996 asm volatile("ptesync" : : : "memory"); 2997 break; 2998 } 2999 break; 3000 3001 case MFSPR: 3002 switch (op->spr) { 3003 case SPRN_XER: 3004 regs->gpr[op->reg] = regs->xer & 0xffffffffUL; 3005 break; 3006 case SPRN_LR: 3007 regs->gpr[op->reg] = regs->link; 3008 break; 3009 case SPRN_CTR: 3010 regs->gpr[op->reg] = regs->ctr; 3011 break; 3012 default: 3013 WARN_ON_ONCE(1); 3014 } 3015 break; 3016 3017 case MTSPR: 3018 switch (op->spr) { 3019 case SPRN_XER: 3020 regs->xer = op->val & 0xffffffffUL; 3021 break; 3022 case SPRN_LR: 3023 regs->link = op->val; 3024 break; 3025 case SPRN_CTR: 3026 regs->ctr = op->val; 3027 break; 3028 default: 3029 WARN_ON_ONCE(1); 3030 } 3031 break; 3032 3033 default: 3034 WARN_ON_ONCE(1); 3035 } 3036 regs->nip = next_pc; 3037 } 3038 NOKPROBE_SYMBOL(emulate_update_regs); 3039 3040 /* 3041 * Emulate a previously-analysed load or store instruction. 3042 * Return values are: 3043 * 0 = instruction emulated successfully 3044 * -EFAULT = address out of range or access faulted (regs->dar 3045 * contains the faulting address) 3046 * -EACCES = misaligned access, instruction requires alignment 3047 * -EINVAL = unknown operation in *op 3048 */ 3049 int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op) 3050 { 3051 int err, size, type; 3052 int i, rd, nb; 3053 unsigned int cr; 3054 unsigned long val; 3055 unsigned long ea; 3056 bool cross_endian; 3057 3058 err = 0; 3059 size = GETSIZE(op->type); 3060 type = GETTYPE(op->type); 3061 cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE); 3062 ea = truncate_if_32bit(regs->msr, op->ea); 3063 3064 switch (type) { 3065 case LARX: 3066 if (ea & (size - 1)) 3067 return -EACCES; /* can't handle misaligned */ 3068 if (!address_ok(regs, ea, size)) 3069 return -EFAULT; 3070 err = 0; 3071 val = 0; 3072 switch (size) { 3073 #ifdef __powerpc64__ 3074 case 1: 3075 __get_user_asmx(val, ea, err, "lbarx"); 3076 break; 3077 case 2: 3078 __get_user_asmx(val, ea, err, "lharx"); 3079 break; 3080 #endif 3081 case 4: 3082 __get_user_asmx(val, ea, err, "lwarx"); 3083 break; 3084 #ifdef __powerpc64__ 3085 case 8: 3086 __get_user_asmx(val, ea, err, "ldarx"); 3087 break; 3088 case 16: 3089 err = do_lqarx(ea, ®s->gpr[op->reg]); 3090 break; 3091 #endif 3092 default: 3093 return -EINVAL; 3094 } 3095 if (err) { 3096 regs->dar = ea; 3097 break; 3098 } 3099 if (size < 16) 3100 regs->gpr[op->reg] = val; 3101 break; 3102 3103 case STCX: 3104 if (ea & (size - 1)) 3105 return -EACCES; /* can't handle misaligned */ 3106 if (!address_ok(regs, ea, size)) 3107 return -EFAULT; 3108 err = 0; 3109 switch (size) { 3110 #ifdef __powerpc64__ 3111 case 1: 3112 __put_user_asmx(op->val, ea, err, "stbcx.", cr); 3113 break; 3114 case 2: 3115 __put_user_asmx(op->val, ea, err, "stbcx.", cr); 3116 break; 3117 #endif 3118 case 4: 3119 __put_user_asmx(op->val, ea, err, "stwcx.", cr); 3120 break; 3121 #ifdef __powerpc64__ 3122 case 8: 3123 __put_user_asmx(op->val, ea, err, "stdcx.", cr); 3124 break; 3125 case 16: 3126 err = do_stqcx(ea, regs->gpr[op->reg], 3127 regs->gpr[op->reg + 1], &cr); 3128 break; 3129 #endif 3130 default: 3131 return -EINVAL; 3132 } 3133 if (!err) 3134 regs->ccr = (regs->ccr & 0x0fffffff) | 3135 (cr & 0xe0000000) | 3136 ((regs->xer >> 3) & 0x10000000); 3137 else 3138 regs->dar = ea; 3139 break; 3140 3141 case LOAD: 3142 #ifdef __powerpc64__ 3143 if (size == 16) { 3144 err = emulate_lq(regs, ea, op->reg, cross_endian); 3145 break; 3146 } 3147 #endif 3148 err = read_mem(®s->gpr[op->reg], ea, size, regs); 3149 if (!err) { 3150 if (op->type & SIGNEXT) 3151 do_signext(®s->gpr[op->reg], size); 3152 if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV)) 3153 do_byterev(®s->gpr[op->reg], size); 3154 } 3155 break; 3156 3157 #ifdef CONFIG_PPC_FPU 3158 case LOAD_FP: 3159 /* 3160 * If the instruction is in userspace, we can emulate it even 3161 * if the VMX state is not live, because we have the state 3162 * stored in the thread_struct. If the instruction is in 3163 * the kernel, we must not touch the state in the thread_struct. 3164 */ 3165 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP)) 3166 return 0; 3167 err = do_fp_load(op, ea, regs, cross_endian); 3168 break; 3169 #endif 3170 #ifdef CONFIG_ALTIVEC 3171 case LOAD_VMX: 3172 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC)) 3173 return 0; 3174 err = do_vec_load(op->reg, ea, size, regs, cross_endian); 3175 break; 3176 #endif 3177 #ifdef CONFIG_VSX 3178 case LOAD_VSX: { 3179 unsigned long msrbit = MSR_VSX; 3180 3181 /* 3182 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX 3183 * when the target of the instruction is a vector register. 3184 */ 3185 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC)) 3186 msrbit = MSR_VEC; 3187 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit)) 3188 return 0; 3189 err = do_vsx_load(op, ea, regs, cross_endian); 3190 break; 3191 } 3192 #endif 3193 case LOAD_MULTI: 3194 if (!address_ok(regs, ea, size)) 3195 return -EFAULT; 3196 rd = op->reg; 3197 for (i = 0; i < size; i += 4) { 3198 unsigned int v32 = 0; 3199 3200 nb = size - i; 3201 if (nb > 4) 3202 nb = 4; 3203 err = copy_mem_in((u8 *) &v32, ea, nb, regs); 3204 if (err) 3205 break; 3206 if (unlikely(cross_endian)) 3207 v32 = byterev_4(v32); 3208 regs->gpr[rd] = v32; 3209 ea += 4; 3210 /* reg number wraps from 31 to 0 for lsw[ix] */ 3211 rd = (rd + 1) & 0x1f; 3212 } 3213 break; 3214 3215 case STORE: 3216 #ifdef __powerpc64__ 3217 if (size == 16) { 3218 err = emulate_stq(regs, ea, op->reg, cross_endian); 3219 break; 3220 } 3221 #endif 3222 if ((op->type & UPDATE) && size == sizeof(long) && 3223 op->reg == 1 && op->update_reg == 1 && 3224 !(regs->msr & MSR_PR) && 3225 ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) { 3226 err = handle_stack_update(ea, regs); 3227 break; 3228 } 3229 if (unlikely(cross_endian)) 3230 do_byterev(&op->val, size); 3231 err = write_mem(op->val, ea, size, regs); 3232 break; 3233 3234 #ifdef CONFIG_PPC_FPU 3235 case STORE_FP: 3236 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP)) 3237 return 0; 3238 err = do_fp_store(op, ea, regs, cross_endian); 3239 break; 3240 #endif 3241 #ifdef CONFIG_ALTIVEC 3242 case STORE_VMX: 3243 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC)) 3244 return 0; 3245 err = do_vec_store(op->reg, ea, size, regs, cross_endian); 3246 break; 3247 #endif 3248 #ifdef CONFIG_VSX 3249 case STORE_VSX: { 3250 unsigned long msrbit = MSR_VSX; 3251 3252 /* 3253 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX 3254 * when the target of the instruction is a vector register. 3255 */ 3256 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC)) 3257 msrbit = MSR_VEC; 3258 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit)) 3259 return 0; 3260 err = do_vsx_store(op, ea, regs, cross_endian); 3261 break; 3262 } 3263 #endif 3264 case STORE_MULTI: 3265 if (!address_ok(regs, ea, size)) 3266 return -EFAULT; 3267 rd = op->reg; 3268 for (i = 0; i < size; i += 4) { 3269 unsigned int v32 = regs->gpr[rd]; 3270 3271 nb = size - i; 3272 if (nb > 4) 3273 nb = 4; 3274 if (unlikely(cross_endian)) 3275 v32 = byterev_4(v32); 3276 err = copy_mem_out((u8 *) &v32, ea, nb, regs); 3277 if (err) 3278 break; 3279 ea += 4; 3280 /* reg number wraps from 31 to 0 for stsw[ix] */ 3281 rd = (rd + 1) & 0x1f; 3282 } 3283 break; 3284 3285 default: 3286 return -EINVAL; 3287 } 3288 3289 if (err) 3290 return err; 3291 3292 if (op->type & UPDATE) 3293 regs->gpr[op->update_reg] = op->ea; 3294 3295 return 0; 3296 } 3297 NOKPROBE_SYMBOL(emulate_loadstore); 3298 3299 /* 3300 * Emulate instructions that cause a transfer of control, 3301 * loads and stores, and a few other instructions. 3302 * Returns 1 if the step was emulated, 0 if not, 3303 * or -1 if the instruction is one that should not be stepped, 3304 * such as an rfid, or a mtmsrd that would clear MSR_RI. 3305 */ 3306 int emulate_step(struct pt_regs *regs, struct ppc_inst instr) 3307 { 3308 struct instruction_op op; 3309 int r, err, type; 3310 unsigned long val; 3311 unsigned long ea; 3312 3313 r = analyse_instr(&op, regs, instr); 3314 if (r < 0) 3315 return r; 3316 if (r > 0) { 3317 emulate_update_regs(regs, &op); 3318 return 1; 3319 } 3320 3321 err = 0; 3322 type = GETTYPE(op.type); 3323 3324 if (OP_IS_LOAD_STORE(type)) { 3325 err = emulate_loadstore(regs, &op); 3326 if (err) 3327 return 0; 3328 goto instr_done; 3329 } 3330 3331 switch (type) { 3332 case CACHEOP: 3333 ea = truncate_if_32bit(regs->msr, op.ea); 3334 if (!address_ok(regs, ea, 8)) 3335 return 0; 3336 switch (op.type & CACHEOP_MASK) { 3337 case DCBST: 3338 __cacheop_user_asmx(ea, err, "dcbst"); 3339 break; 3340 case DCBF: 3341 __cacheop_user_asmx(ea, err, "dcbf"); 3342 break; 3343 case DCBTST: 3344 if (op.reg == 0) 3345 prefetchw((void *) ea); 3346 break; 3347 case DCBT: 3348 if (op.reg == 0) 3349 prefetch((void *) ea); 3350 break; 3351 case ICBI: 3352 __cacheop_user_asmx(ea, err, "icbi"); 3353 break; 3354 case DCBZ: 3355 err = emulate_dcbz(ea, regs); 3356 break; 3357 } 3358 if (err) { 3359 regs->dar = ea; 3360 return 0; 3361 } 3362 goto instr_done; 3363 3364 case MFMSR: 3365 regs->gpr[op.reg] = regs->msr & MSR_MASK; 3366 goto instr_done; 3367 3368 case MTMSR: 3369 val = regs->gpr[op.reg]; 3370 if ((val & MSR_RI) == 0) 3371 /* can't step mtmsr[d] that would clear MSR_RI */ 3372 return -1; 3373 /* here op.val is the mask of bits to change */ 3374 regs->msr = (regs->msr & ~op.val) | (val & op.val); 3375 goto instr_done; 3376 3377 #ifdef CONFIG_PPC64 3378 case SYSCALL: /* sc */ 3379 /* 3380 * N.B. this uses knowledge about how the syscall 3381 * entry code works. If that is changed, this will 3382 * need to be changed also. 3383 */ 3384 if (IS_ENABLED(CONFIG_PPC_FAST_ENDIAN_SWITCH) && 3385 cpu_has_feature(CPU_FTR_REAL_LE) && 3386 regs->gpr[0] == 0x1ebe) { 3387 regs->msr ^= MSR_LE; 3388 goto instr_done; 3389 } 3390 regs->gpr[9] = regs->gpr[13]; 3391 regs->gpr[10] = MSR_KERNEL; 3392 regs->gpr[11] = regs->nip + 4; 3393 regs->gpr[12] = regs->msr & MSR_MASK; 3394 regs->gpr[13] = (unsigned long) get_paca(); 3395 regs->nip = (unsigned long) &system_call_common; 3396 regs->msr = MSR_KERNEL; 3397 return 1; 3398 3399 #ifdef CONFIG_PPC_BOOK3S_64 3400 case SYSCALL_VECTORED_0: /* scv 0 */ 3401 regs->gpr[9] = regs->gpr[13]; 3402 regs->gpr[10] = MSR_KERNEL; 3403 regs->gpr[11] = regs->nip + 4; 3404 regs->gpr[12] = regs->msr & MSR_MASK; 3405 regs->gpr[13] = (unsigned long) get_paca(); 3406 regs->nip = (unsigned long) &system_call_vectored_emulate; 3407 regs->msr = MSR_KERNEL; 3408 return 1; 3409 #endif 3410 3411 case RFI: 3412 return -1; 3413 #endif 3414 } 3415 return 0; 3416 3417 instr_done: 3418 regs->nip = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op.type)); 3419 return 1; 3420 } 3421 NOKPROBE_SYMBOL(emulate_step); 3422