1 /* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License, version 2, as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, write to the Free Software 13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 14 * 15 * Copyright IBM Corp. 2007 16 * Copyright 2011 Freescale Semiconductor, Inc. 17 * 18 * Authors: Hollis Blanchard <hollisb@us.ibm.com> 19 */ 20 21 #include <linux/jiffies.h> 22 #include <linux/hrtimer.h> 23 #include <linux/types.h> 24 #include <linux/string.h> 25 #include <linux/kvm_host.h> 26 #include <linux/clockchips.h> 27 28 #include <asm/reg.h> 29 #include <asm/time.h> 30 #include <asm/byteorder.h> 31 #include <asm/kvm_ppc.h> 32 #include <asm/disassemble.h> 33 #include "timing.h" 34 #include "trace.h" 35 36 #define OP_TRAP 3 37 #define OP_TRAP_64 2 38 39 #define OP_31_XOP_TRAP 4 40 #define OP_31_XOP_LWZX 23 41 #define OP_31_XOP_TRAP_64 68 42 #define OP_31_XOP_DCBF 86 43 #define OP_31_XOP_LBZX 87 44 #define OP_31_XOP_STWX 151 45 #define OP_31_XOP_STBX 215 46 #define OP_31_XOP_LBZUX 119 47 #define OP_31_XOP_STBUX 247 48 #define OP_31_XOP_LHZX 279 49 #define OP_31_XOP_LHZUX 311 50 #define OP_31_XOP_MFSPR 339 51 #define OP_31_XOP_LHAX 343 52 #define OP_31_XOP_STHX 407 53 #define OP_31_XOP_STHUX 439 54 #define OP_31_XOP_MTSPR 467 55 #define OP_31_XOP_DCBI 470 56 #define OP_31_XOP_LWBRX 534 57 #define OP_31_XOP_TLBSYNC 566 58 #define OP_31_XOP_STWBRX 662 59 #define OP_31_XOP_LHBRX 790 60 #define OP_31_XOP_STHBRX 918 61 62 #define OP_LWZ 32 63 #define OP_LD 58 64 #define OP_LWZU 33 65 #define OP_LBZ 34 66 #define OP_LBZU 35 67 #define OP_STW 36 68 #define OP_STWU 37 69 #define OP_STD 62 70 #define OP_STB 38 71 #define OP_STBU 39 72 #define OP_LHZ 40 73 #define OP_LHZU 41 74 #define OP_LHA 42 75 #define OP_LHAU 43 76 #define OP_STH 44 77 #define OP_STHU 45 78 79 void kvmppc_emulate_dec(struct kvm_vcpu *vcpu) 80 { 81 unsigned long dec_nsec; 82 unsigned long long dec_time; 83 84 pr_debug("mtDEC: %x\n", vcpu->arch.dec); 85 hrtimer_try_to_cancel(&vcpu->arch.dec_timer); 86 87 #ifdef CONFIG_PPC_BOOK3S 88 /* mtdec lowers the interrupt line when positive. */ 89 kvmppc_core_dequeue_dec(vcpu); 90 91 /* POWER4+ triggers a dec interrupt if the value is < 0 */ 92 if (vcpu->arch.dec & 0x80000000) { 93 kvmppc_core_queue_dec(vcpu); 94 return; 95 } 96 #endif 97 98 #ifdef CONFIG_BOOKE 99 /* On BOOKE, DEC = 0 is as good as decrementer not enabled */ 100 if (vcpu->arch.dec == 0) 101 return; 102 #endif 103 104 /* 105 * The decrementer ticks at the same rate as the timebase, so 106 * that's how we convert the guest DEC value to the number of 107 * host ticks. 108 */ 109 110 dec_time = vcpu->arch.dec; 111 /* 112 * Guest timebase ticks at the same frequency as host decrementer. 113 * So use the host decrementer calculations for decrementer emulation. 114 */ 115 dec_time = dec_time << decrementer_clockevent.shift; 116 do_div(dec_time, decrementer_clockevent.mult); 117 dec_nsec = do_div(dec_time, NSEC_PER_SEC); 118 hrtimer_start(&vcpu->arch.dec_timer, 119 ktime_set(dec_time, dec_nsec), HRTIMER_MODE_REL); 120 vcpu->arch.dec_jiffies = get_tb(); 121 } 122 123 u32 kvmppc_get_dec(struct kvm_vcpu *vcpu, u64 tb) 124 { 125 u64 jd = tb - vcpu->arch.dec_jiffies; 126 127 #ifdef CONFIG_BOOKE 128 if (vcpu->arch.dec < jd) 129 return 0; 130 #endif 131 132 return vcpu->arch.dec - jd; 133 } 134 135 static int kvmppc_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, int rs) 136 { 137 enum emulation_result emulated = EMULATE_DONE; 138 ulong spr_val = kvmppc_get_gpr(vcpu, rs); 139 140 switch (sprn) { 141 case SPRN_SRR0: 142 vcpu->arch.shared->srr0 = spr_val; 143 break; 144 case SPRN_SRR1: 145 vcpu->arch.shared->srr1 = spr_val; 146 break; 147 148 /* XXX We need to context-switch the timebase for 149 * watchdog and FIT. */ 150 case SPRN_TBWL: break; 151 case SPRN_TBWU: break; 152 153 case SPRN_MSSSR0: break; 154 155 case SPRN_DEC: 156 vcpu->arch.dec = spr_val; 157 kvmppc_emulate_dec(vcpu); 158 break; 159 160 case SPRN_SPRG0: 161 vcpu->arch.shared->sprg0 = spr_val; 162 break; 163 case SPRN_SPRG1: 164 vcpu->arch.shared->sprg1 = spr_val; 165 break; 166 case SPRN_SPRG2: 167 vcpu->arch.shared->sprg2 = spr_val; 168 break; 169 case SPRN_SPRG3: 170 vcpu->arch.shared->sprg3 = spr_val; 171 break; 172 173 default: 174 emulated = kvmppc_core_emulate_mtspr(vcpu, sprn, 175 spr_val); 176 if (emulated == EMULATE_FAIL) 177 printk(KERN_INFO "mtspr: unknown spr " 178 "0x%x\n", sprn); 179 break; 180 } 181 182 kvmppc_set_exit_type(vcpu, EMULATED_MTSPR_EXITS); 183 184 return emulated; 185 } 186 187 static int kvmppc_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt) 188 { 189 enum emulation_result emulated = EMULATE_DONE; 190 ulong spr_val = 0; 191 192 switch (sprn) { 193 case SPRN_SRR0: 194 spr_val = vcpu->arch.shared->srr0; 195 break; 196 case SPRN_SRR1: 197 spr_val = vcpu->arch.shared->srr1; 198 break; 199 case SPRN_PVR: 200 spr_val = vcpu->arch.pvr; 201 break; 202 case SPRN_PIR: 203 spr_val = vcpu->vcpu_id; 204 break; 205 case SPRN_MSSSR0: 206 spr_val = 0; 207 break; 208 209 /* Note: mftb and TBRL/TBWL are user-accessible, so 210 * the guest can always access the real TB anyways. 211 * In fact, we probably will never see these traps. */ 212 case SPRN_TBWL: 213 spr_val = get_tb() >> 32; 214 break; 215 case SPRN_TBWU: 216 spr_val = get_tb(); 217 break; 218 219 case SPRN_SPRG0: 220 spr_val = vcpu->arch.shared->sprg0; 221 break; 222 case SPRN_SPRG1: 223 spr_val = vcpu->arch.shared->sprg1; 224 break; 225 case SPRN_SPRG2: 226 spr_val = vcpu->arch.shared->sprg2; 227 break; 228 case SPRN_SPRG3: 229 spr_val = vcpu->arch.shared->sprg3; 230 break; 231 /* Note: SPRG4-7 are user-readable, so we don't get 232 * a trap. */ 233 234 case SPRN_DEC: 235 spr_val = kvmppc_get_dec(vcpu, get_tb()); 236 break; 237 default: 238 emulated = kvmppc_core_emulate_mfspr(vcpu, sprn, 239 &spr_val); 240 if (unlikely(emulated == EMULATE_FAIL)) { 241 printk(KERN_INFO "mfspr: unknown spr " 242 "0x%x\n", sprn); 243 } 244 break; 245 } 246 247 if (emulated == EMULATE_DONE) 248 kvmppc_set_gpr(vcpu, rt, spr_val); 249 kvmppc_set_exit_type(vcpu, EMULATED_MFSPR_EXITS); 250 251 return emulated; 252 } 253 254 /* XXX to do: 255 * lhax 256 * lhaux 257 * lswx 258 * lswi 259 * stswx 260 * stswi 261 * lha 262 * lhau 263 * lmw 264 * stmw 265 * 266 * XXX is_bigendian should depend on MMU mapping or MSR[LE] 267 */ 268 /* XXX Should probably auto-generate instruction decoding for a particular core 269 * from opcode tables in the future. */ 270 int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu) 271 { 272 u32 inst = kvmppc_get_last_inst(vcpu); 273 int ra = get_ra(inst); 274 int rs = get_rs(inst); 275 int rt = get_rt(inst); 276 int sprn = get_sprn(inst); 277 enum emulation_result emulated = EMULATE_DONE; 278 int advance = 1; 279 280 /* this default type might be overwritten by subcategories */ 281 kvmppc_set_exit_type(vcpu, EMULATED_INST_EXITS); 282 283 pr_debug("Emulating opcode %d / %d\n", get_op(inst), get_xop(inst)); 284 285 switch (get_op(inst)) { 286 case OP_TRAP: 287 #ifdef CONFIG_PPC_BOOK3S 288 case OP_TRAP_64: 289 kvmppc_core_queue_program(vcpu, SRR1_PROGTRAP); 290 #else 291 kvmppc_core_queue_program(vcpu, 292 vcpu->arch.shared->esr | ESR_PTR); 293 #endif 294 advance = 0; 295 break; 296 297 case 31: 298 switch (get_xop(inst)) { 299 300 case OP_31_XOP_TRAP: 301 #ifdef CONFIG_64BIT 302 case OP_31_XOP_TRAP_64: 303 #endif 304 #ifdef CONFIG_PPC_BOOK3S 305 kvmppc_core_queue_program(vcpu, SRR1_PROGTRAP); 306 #else 307 kvmppc_core_queue_program(vcpu, 308 vcpu->arch.shared->esr | ESR_PTR); 309 #endif 310 advance = 0; 311 break; 312 case OP_31_XOP_LWZX: 313 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1); 314 break; 315 316 case OP_31_XOP_LBZX: 317 emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1); 318 break; 319 320 case OP_31_XOP_LBZUX: 321 emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1); 322 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 323 break; 324 325 case OP_31_XOP_STWX: 326 emulated = kvmppc_handle_store(run, vcpu, 327 kvmppc_get_gpr(vcpu, rs), 328 4, 1); 329 break; 330 331 case OP_31_XOP_STBX: 332 emulated = kvmppc_handle_store(run, vcpu, 333 kvmppc_get_gpr(vcpu, rs), 334 1, 1); 335 break; 336 337 case OP_31_XOP_STBUX: 338 emulated = kvmppc_handle_store(run, vcpu, 339 kvmppc_get_gpr(vcpu, rs), 340 1, 1); 341 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 342 break; 343 344 case OP_31_XOP_LHAX: 345 emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1); 346 break; 347 348 case OP_31_XOP_LHZX: 349 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1); 350 break; 351 352 case OP_31_XOP_LHZUX: 353 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1); 354 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 355 break; 356 357 case OP_31_XOP_MFSPR: 358 emulated = kvmppc_emulate_mfspr(vcpu, sprn, rt); 359 break; 360 361 case OP_31_XOP_STHX: 362 emulated = kvmppc_handle_store(run, vcpu, 363 kvmppc_get_gpr(vcpu, rs), 364 2, 1); 365 break; 366 367 case OP_31_XOP_STHUX: 368 emulated = kvmppc_handle_store(run, vcpu, 369 kvmppc_get_gpr(vcpu, rs), 370 2, 1); 371 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 372 break; 373 374 case OP_31_XOP_MTSPR: 375 emulated = kvmppc_emulate_mtspr(vcpu, sprn, rs); 376 break; 377 378 case OP_31_XOP_DCBF: 379 case OP_31_XOP_DCBI: 380 /* Do nothing. The guest is performing dcbi because 381 * hardware DMA is not snooped by the dcache, but 382 * emulated DMA either goes through the dcache as 383 * normal writes, or the host kernel has handled dcache 384 * coherence. */ 385 break; 386 387 case OP_31_XOP_LWBRX: 388 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 0); 389 break; 390 391 case OP_31_XOP_TLBSYNC: 392 break; 393 394 case OP_31_XOP_STWBRX: 395 emulated = kvmppc_handle_store(run, vcpu, 396 kvmppc_get_gpr(vcpu, rs), 397 4, 0); 398 break; 399 400 case OP_31_XOP_LHBRX: 401 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 0); 402 break; 403 404 case OP_31_XOP_STHBRX: 405 emulated = kvmppc_handle_store(run, vcpu, 406 kvmppc_get_gpr(vcpu, rs), 407 2, 0); 408 break; 409 410 default: 411 /* Attempt core-specific emulation below. */ 412 emulated = EMULATE_FAIL; 413 } 414 break; 415 416 case OP_LWZ: 417 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1); 418 break; 419 420 /* TBD: Add support for other 64 bit load variants like ldu, ldux, ldx etc. */ 421 case OP_LD: 422 rt = get_rt(inst); 423 emulated = kvmppc_handle_load(run, vcpu, rt, 8, 1); 424 break; 425 426 case OP_LWZU: 427 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1); 428 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 429 break; 430 431 case OP_LBZ: 432 emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1); 433 break; 434 435 case OP_LBZU: 436 emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1); 437 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 438 break; 439 440 case OP_STW: 441 emulated = kvmppc_handle_store(run, vcpu, 442 kvmppc_get_gpr(vcpu, rs), 443 4, 1); 444 break; 445 446 /* TBD: Add support for other 64 bit store variants like stdu, stdux, stdx etc. */ 447 case OP_STD: 448 rs = get_rs(inst); 449 emulated = kvmppc_handle_store(run, vcpu, 450 kvmppc_get_gpr(vcpu, rs), 451 8, 1); 452 break; 453 454 case OP_STWU: 455 emulated = kvmppc_handle_store(run, vcpu, 456 kvmppc_get_gpr(vcpu, rs), 457 4, 1); 458 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 459 break; 460 461 case OP_STB: 462 emulated = kvmppc_handle_store(run, vcpu, 463 kvmppc_get_gpr(vcpu, rs), 464 1, 1); 465 break; 466 467 case OP_STBU: 468 emulated = kvmppc_handle_store(run, vcpu, 469 kvmppc_get_gpr(vcpu, rs), 470 1, 1); 471 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 472 break; 473 474 case OP_LHZ: 475 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1); 476 break; 477 478 case OP_LHZU: 479 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1); 480 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 481 break; 482 483 case OP_LHA: 484 emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1); 485 break; 486 487 case OP_LHAU: 488 emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1); 489 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 490 break; 491 492 case OP_STH: 493 emulated = kvmppc_handle_store(run, vcpu, 494 kvmppc_get_gpr(vcpu, rs), 495 2, 1); 496 break; 497 498 case OP_STHU: 499 emulated = kvmppc_handle_store(run, vcpu, 500 kvmppc_get_gpr(vcpu, rs), 501 2, 1); 502 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 503 break; 504 505 default: 506 emulated = EMULATE_FAIL; 507 } 508 509 if (emulated == EMULATE_FAIL) { 510 emulated = kvmppc_core_emulate_op(run, vcpu, inst, &advance); 511 if (emulated == EMULATE_AGAIN) { 512 advance = 0; 513 } else if (emulated == EMULATE_FAIL) { 514 advance = 0; 515 printk(KERN_ERR "Couldn't emulate instruction 0x%08x " 516 "(op %d xop %d)\n", inst, get_op(inst), get_xop(inst)); 517 kvmppc_core_queue_program(vcpu, 0); 518 } 519 } 520 521 trace_kvm_ppc_instr(inst, kvmppc_get_pc(vcpu), emulated); 522 523 /* Advance past emulated instruction. */ 524 if (advance) 525 kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + 4); 526 527 return emulated; 528 } 529