1 /* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License, version 2, as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, write to the Free Software 13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 14 * 15 * Copyright IBM Corp. 2007 16 * Copyright 2011 Freescale Semiconductor, Inc. 17 * 18 * Authors: Hollis Blanchard <hollisb@us.ibm.com> 19 */ 20 21 #include <linux/jiffies.h> 22 #include <linux/hrtimer.h> 23 #include <linux/types.h> 24 #include <linux/string.h> 25 #include <linux/kvm_host.h> 26 #include <linux/clockchips.h> 27 28 #include <asm/reg.h> 29 #include <asm/time.h> 30 #include <asm/byteorder.h> 31 #include <asm/kvm_ppc.h> 32 #include <asm/disassemble.h> 33 #include "timing.h" 34 #include "trace.h" 35 36 #define OP_TRAP 3 37 #define OP_TRAP_64 2 38 39 #define OP_31_XOP_TRAP 4 40 #define OP_31_XOP_LWZX 23 41 #define OP_31_XOP_TRAP_64 68 42 #define OP_31_XOP_DCBF 86 43 #define OP_31_XOP_LBZX 87 44 #define OP_31_XOP_STWX 151 45 #define OP_31_XOP_STBX 215 46 #define OP_31_XOP_LBZUX 119 47 #define OP_31_XOP_STBUX 247 48 #define OP_31_XOP_LHZX 279 49 #define OP_31_XOP_LHZUX 311 50 #define OP_31_XOP_MFSPR 339 51 #define OP_31_XOP_LHAX 343 52 #define OP_31_XOP_STHX 407 53 #define OP_31_XOP_STHUX 439 54 #define OP_31_XOP_MTSPR 467 55 #define OP_31_XOP_DCBI 470 56 #define OP_31_XOP_LWBRX 534 57 #define OP_31_XOP_TLBSYNC 566 58 #define OP_31_XOP_STWBRX 662 59 #define OP_31_XOP_LHBRX 790 60 #define OP_31_XOP_STHBRX 918 61 62 #define OP_LWZ 32 63 #define OP_LD 58 64 #define OP_LWZU 33 65 #define OP_LBZ 34 66 #define OP_LBZU 35 67 #define OP_STW 36 68 #define OP_STWU 37 69 #define OP_STD 62 70 #define OP_STB 38 71 #define OP_STBU 39 72 #define OP_LHZ 40 73 #define OP_LHZU 41 74 #define OP_LHA 42 75 #define OP_LHAU 43 76 #define OP_STH 44 77 #define OP_STHU 45 78 79 void kvmppc_emulate_dec(struct kvm_vcpu *vcpu) 80 { 81 unsigned long dec_nsec; 82 unsigned long long dec_time; 83 84 pr_debug("mtDEC: %x\n", vcpu->arch.dec); 85 hrtimer_try_to_cancel(&vcpu->arch.dec_timer); 86 87 #ifdef CONFIG_PPC_BOOK3S 88 /* mtdec lowers the interrupt line when positive. */ 89 kvmppc_core_dequeue_dec(vcpu); 90 91 /* POWER4+ triggers a dec interrupt if the value is < 0 */ 92 if (vcpu->arch.dec & 0x80000000) { 93 kvmppc_core_queue_dec(vcpu); 94 return; 95 } 96 #endif 97 98 #ifdef CONFIG_BOOKE 99 /* On BOOKE, DEC = 0 is as good as decrementer not enabled */ 100 if (vcpu->arch.dec == 0) 101 return; 102 #endif 103 104 /* 105 * The decrementer ticks at the same rate as the timebase, so 106 * that's how we convert the guest DEC value to the number of 107 * host ticks. 108 */ 109 110 dec_time = vcpu->arch.dec; 111 /* 112 * Guest timebase ticks at the same frequency as host decrementer. 113 * So use the host decrementer calculations for decrementer emulation. 114 */ 115 dec_time = dec_time << decrementer_clockevent.shift; 116 do_div(dec_time, decrementer_clockevent.mult); 117 dec_nsec = do_div(dec_time, NSEC_PER_SEC); 118 hrtimer_start(&vcpu->arch.dec_timer, 119 ktime_set(dec_time, dec_nsec), HRTIMER_MODE_REL); 120 vcpu->arch.dec_jiffies = get_tb(); 121 } 122 123 u32 kvmppc_get_dec(struct kvm_vcpu *vcpu, u64 tb) 124 { 125 u64 jd = tb - vcpu->arch.dec_jiffies; 126 127 #ifdef CONFIG_BOOKE 128 if (vcpu->arch.dec < jd) 129 return 0; 130 #endif 131 132 return vcpu->arch.dec - jd; 133 } 134 135 static int kvmppc_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, int rs) 136 { 137 enum emulation_result emulated = EMULATE_DONE; 138 ulong spr_val = kvmppc_get_gpr(vcpu, rs); 139 140 switch (sprn) { 141 case SPRN_SRR0: 142 vcpu->arch.shared->srr0 = spr_val; 143 break; 144 case SPRN_SRR1: 145 vcpu->arch.shared->srr1 = spr_val; 146 break; 147 148 /* XXX We need to context-switch the timebase for 149 * watchdog and FIT. */ 150 case SPRN_TBWL: break; 151 case SPRN_TBWU: break; 152 153 case SPRN_DEC: 154 vcpu->arch.dec = spr_val; 155 kvmppc_emulate_dec(vcpu); 156 break; 157 158 case SPRN_SPRG0: 159 vcpu->arch.shared->sprg0 = spr_val; 160 break; 161 case SPRN_SPRG1: 162 vcpu->arch.shared->sprg1 = spr_val; 163 break; 164 case SPRN_SPRG2: 165 vcpu->arch.shared->sprg2 = spr_val; 166 break; 167 case SPRN_SPRG3: 168 vcpu->arch.shared->sprg3 = spr_val; 169 break; 170 171 default: 172 emulated = kvmppc_core_emulate_mtspr(vcpu, sprn, 173 spr_val); 174 if (emulated == EMULATE_FAIL) 175 printk(KERN_INFO "mtspr: unknown spr " 176 "0x%x\n", sprn); 177 break; 178 } 179 180 kvmppc_set_exit_type(vcpu, EMULATED_MTSPR_EXITS); 181 182 return emulated; 183 } 184 185 static int kvmppc_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt) 186 { 187 enum emulation_result emulated = EMULATE_DONE; 188 ulong spr_val = 0; 189 190 switch (sprn) { 191 case SPRN_SRR0: 192 spr_val = vcpu->arch.shared->srr0; 193 break; 194 case SPRN_SRR1: 195 spr_val = vcpu->arch.shared->srr1; 196 break; 197 case SPRN_PVR: 198 spr_val = vcpu->arch.pvr; 199 break; 200 case SPRN_PIR: 201 spr_val = vcpu->vcpu_id; 202 break; 203 204 /* Note: mftb and TBRL/TBWL are user-accessible, so 205 * the guest can always access the real TB anyways. 206 * In fact, we probably will never see these traps. */ 207 case SPRN_TBWL: 208 spr_val = get_tb() >> 32; 209 break; 210 case SPRN_TBWU: 211 spr_val = get_tb(); 212 break; 213 214 case SPRN_SPRG0: 215 spr_val = vcpu->arch.shared->sprg0; 216 break; 217 case SPRN_SPRG1: 218 spr_val = vcpu->arch.shared->sprg1; 219 break; 220 case SPRN_SPRG2: 221 spr_val = vcpu->arch.shared->sprg2; 222 break; 223 case SPRN_SPRG3: 224 spr_val = vcpu->arch.shared->sprg3; 225 break; 226 /* Note: SPRG4-7 are user-readable, so we don't get 227 * a trap. */ 228 229 case SPRN_DEC: 230 spr_val = kvmppc_get_dec(vcpu, get_tb()); 231 break; 232 default: 233 emulated = kvmppc_core_emulate_mfspr(vcpu, sprn, 234 &spr_val); 235 if (unlikely(emulated == EMULATE_FAIL)) { 236 printk(KERN_INFO "mfspr: unknown spr " 237 "0x%x\n", sprn); 238 } 239 break; 240 } 241 242 if (emulated == EMULATE_DONE) 243 kvmppc_set_gpr(vcpu, rt, spr_val); 244 kvmppc_set_exit_type(vcpu, EMULATED_MFSPR_EXITS); 245 246 return emulated; 247 } 248 249 /* XXX to do: 250 * lhax 251 * lhaux 252 * lswx 253 * lswi 254 * stswx 255 * stswi 256 * lha 257 * lhau 258 * lmw 259 * stmw 260 * 261 * XXX is_bigendian should depend on MMU mapping or MSR[LE] 262 */ 263 /* XXX Should probably auto-generate instruction decoding for a particular core 264 * from opcode tables in the future. */ 265 int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu) 266 { 267 u32 inst = kvmppc_get_last_inst(vcpu); 268 int ra = get_ra(inst); 269 int rs = get_rs(inst); 270 int rt = get_rt(inst); 271 int sprn = get_sprn(inst); 272 enum emulation_result emulated = EMULATE_DONE; 273 int advance = 1; 274 275 /* this default type might be overwritten by subcategories */ 276 kvmppc_set_exit_type(vcpu, EMULATED_INST_EXITS); 277 278 pr_debug("Emulating opcode %d / %d\n", get_op(inst), get_xop(inst)); 279 280 switch (get_op(inst)) { 281 case OP_TRAP: 282 #ifdef CONFIG_PPC_BOOK3S 283 case OP_TRAP_64: 284 kvmppc_core_queue_program(vcpu, SRR1_PROGTRAP); 285 #else 286 kvmppc_core_queue_program(vcpu, 287 vcpu->arch.shared->esr | ESR_PTR); 288 #endif 289 advance = 0; 290 break; 291 292 case 31: 293 switch (get_xop(inst)) { 294 295 case OP_31_XOP_TRAP: 296 #ifdef CONFIG_64BIT 297 case OP_31_XOP_TRAP_64: 298 #endif 299 #ifdef CONFIG_PPC_BOOK3S 300 kvmppc_core_queue_program(vcpu, SRR1_PROGTRAP); 301 #else 302 kvmppc_core_queue_program(vcpu, 303 vcpu->arch.shared->esr | ESR_PTR); 304 #endif 305 advance = 0; 306 break; 307 case OP_31_XOP_LWZX: 308 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1); 309 break; 310 311 case OP_31_XOP_LBZX: 312 emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1); 313 break; 314 315 case OP_31_XOP_LBZUX: 316 emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1); 317 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 318 break; 319 320 case OP_31_XOP_STWX: 321 emulated = kvmppc_handle_store(run, vcpu, 322 kvmppc_get_gpr(vcpu, rs), 323 4, 1); 324 break; 325 326 case OP_31_XOP_STBX: 327 emulated = kvmppc_handle_store(run, vcpu, 328 kvmppc_get_gpr(vcpu, rs), 329 1, 1); 330 break; 331 332 case OP_31_XOP_STBUX: 333 emulated = kvmppc_handle_store(run, vcpu, 334 kvmppc_get_gpr(vcpu, rs), 335 1, 1); 336 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 337 break; 338 339 case OP_31_XOP_LHAX: 340 emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1); 341 break; 342 343 case OP_31_XOP_LHZX: 344 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1); 345 break; 346 347 case OP_31_XOP_LHZUX: 348 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1); 349 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 350 break; 351 352 case OP_31_XOP_MFSPR: 353 emulated = kvmppc_emulate_mfspr(vcpu, sprn, rt); 354 break; 355 356 case OP_31_XOP_STHX: 357 emulated = kvmppc_handle_store(run, vcpu, 358 kvmppc_get_gpr(vcpu, rs), 359 2, 1); 360 break; 361 362 case OP_31_XOP_STHUX: 363 emulated = kvmppc_handle_store(run, vcpu, 364 kvmppc_get_gpr(vcpu, rs), 365 2, 1); 366 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 367 break; 368 369 case OP_31_XOP_MTSPR: 370 emulated = kvmppc_emulate_mtspr(vcpu, sprn, rs); 371 break; 372 373 case OP_31_XOP_DCBF: 374 case OP_31_XOP_DCBI: 375 /* Do nothing. The guest is performing dcbi because 376 * hardware DMA is not snooped by the dcache, but 377 * emulated DMA either goes through the dcache as 378 * normal writes, or the host kernel has handled dcache 379 * coherence. */ 380 break; 381 382 case OP_31_XOP_LWBRX: 383 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 0); 384 break; 385 386 case OP_31_XOP_TLBSYNC: 387 break; 388 389 case OP_31_XOP_STWBRX: 390 emulated = kvmppc_handle_store(run, vcpu, 391 kvmppc_get_gpr(vcpu, rs), 392 4, 0); 393 break; 394 395 case OP_31_XOP_LHBRX: 396 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 0); 397 break; 398 399 case OP_31_XOP_STHBRX: 400 emulated = kvmppc_handle_store(run, vcpu, 401 kvmppc_get_gpr(vcpu, rs), 402 2, 0); 403 break; 404 405 default: 406 /* Attempt core-specific emulation below. */ 407 emulated = EMULATE_FAIL; 408 } 409 break; 410 411 case OP_LWZ: 412 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1); 413 break; 414 415 /* TBD: Add support for other 64 bit load variants like ldu, ldux, ldx etc. */ 416 case OP_LD: 417 rt = get_rt(inst); 418 emulated = kvmppc_handle_load(run, vcpu, rt, 8, 1); 419 break; 420 421 case OP_LWZU: 422 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1); 423 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 424 break; 425 426 case OP_LBZ: 427 emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1); 428 break; 429 430 case OP_LBZU: 431 emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1); 432 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 433 break; 434 435 case OP_STW: 436 emulated = kvmppc_handle_store(run, vcpu, 437 kvmppc_get_gpr(vcpu, rs), 438 4, 1); 439 break; 440 441 /* TBD: Add support for other 64 bit store variants like stdu, stdux, stdx etc. */ 442 case OP_STD: 443 rs = get_rs(inst); 444 emulated = kvmppc_handle_store(run, vcpu, 445 kvmppc_get_gpr(vcpu, rs), 446 8, 1); 447 break; 448 449 case OP_STWU: 450 emulated = kvmppc_handle_store(run, vcpu, 451 kvmppc_get_gpr(vcpu, rs), 452 4, 1); 453 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 454 break; 455 456 case OP_STB: 457 emulated = kvmppc_handle_store(run, vcpu, 458 kvmppc_get_gpr(vcpu, rs), 459 1, 1); 460 break; 461 462 case OP_STBU: 463 emulated = kvmppc_handle_store(run, vcpu, 464 kvmppc_get_gpr(vcpu, rs), 465 1, 1); 466 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 467 break; 468 469 case OP_LHZ: 470 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1); 471 break; 472 473 case OP_LHZU: 474 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1); 475 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 476 break; 477 478 case OP_LHA: 479 emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1); 480 break; 481 482 case OP_LHAU: 483 emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1); 484 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 485 break; 486 487 case OP_STH: 488 emulated = kvmppc_handle_store(run, vcpu, 489 kvmppc_get_gpr(vcpu, rs), 490 2, 1); 491 break; 492 493 case OP_STHU: 494 emulated = kvmppc_handle_store(run, vcpu, 495 kvmppc_get_gpr(vcpu, rs), 496 2, 1); 497 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed); 498 break; 499 500 default: 501 emulated = EMULATE_FAIL; 502 } 503 504 if (emulated == EMULATE_FAIL) { 505 emulated = kvmppc_core_emulate_op(run, vcpu, inst, &advance); 506 if (emulated == EMULATE_AGAIN) { 507 advance = 0; 508 } else if (emulated == EMULATE_FAIL) { 509 advance = 0; 510 printk(KERN_ERR "Couldn't emulate instruction 0x%08x " 511 "(op %d xop %d)\n", inst, get_op(inst), get_xop(inst)); 512 kvmppc_core_queue_program(vcpu, 0); 513 } 514 } 515 516 trace_kvm_ppc_instr(inst, kvmppc_get_pc(vcpu), emulated); 517 518 /* Advance past emulated instruction. */ 519 if (advance) 520 kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + 4); 521 522 return emulated; 523 } 524