1 /* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License, version 2, as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, write to the Free Software 13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 14 * 15 * Copyright IBM Corp. 2007 16 * 17 * Authors: Hollis Blanchard <hollisb@us.ibm.com> 18 */ 19 20 #include <linux/jiffies.h> 21 #include <linux/timer.h> 22 #include <linux/types.h> 23 #include <linux/string.h> 24 #include <linux/kvm_host.h> 25 26 #include <asm/dcr.h> 27 #include <asm/dcr-regs.h> 28 #include <asm/time.h> 29 #include <asm/byteorder.h> 30 #include <asm/kvm_ppc.h> 31 32 #include "44x_tlb.h" 33 34 /* Instruction decoding */ 35 static inline unsigned int get_op(u32 inst) 36 { 37 return inst >> 26; 38 } 39 40 static inline unsigned int get_xop(u32 inst) 41 { 42 return (inst >> 1) & 0x3ff; 43 } 44 45 static inline unsigned int get_sprn(u32 inst) 46 { 47 return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0); 48 } 49 50 static inline unsigned int get_dcrn(u32 inst) 51 { 52 return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0); 53 } 54 55 static inline unsigned int get_rt(u32 inst) 56 { 57 return (inst >> 21) & 0x1f; 58 } 59 60 static inline unsigned int get_rs(u32 inst) 61 { 62 return (inst >> 21) & 0x1f; 63 } 64 65 static inline unsigned int get_ra(u32 inst) 66 { 67 return (inst >> 16) & 0x1f; 68 } 69 70 static inline unsigned int get_rb(u32 inst) 71 { 72 return (inst >> 11) & 0x1f; 73 } 74 75 static inline unsigned int get_rc(u32 inst) 76 { 77 return inst & 0x1; 78 } 79 80 static inline unsigned int get_ws(u32 inst) 81 { 82 return (inst >> 11) & 0x1f; 83 } 84 85 static inline unsigned int get_d(u32 inst) 86 { 87 return inst & 0xffff; 88 } 89 90 static int tlbe_is_host_safe(const struct kvm_vcpu *vcpu, 91 const struct tlbe *tlbe) 92 { 93 gpa_t gpa; 94 95 if (!get_tlb_v(tlbe)) 96 return 0; 97 98 /* Does it match current guest AS? */ 99 /* XXX what about IS != DS? */ 100 if (get_tlb_ts(tlbe) != !!(vcpu->arch.msr & MSR_IS)) 101 return 0; 102 103 gpa = get_tlb_raddr(tlbe); 104 if (!gfn_to_memslot(vcpu->kvm, gpa >> PAGE_SHIFT)) 105 /* Mapping is not for RAM. */ 106 return 0; 107 108 return 1; 109 } 110 111 static int kvmppc_emul_tlbwe(struct kvm_vcpu *vcpu, u32 inst) 112 { 113 u64 eaddr; 114 u64 raddr; 115 u64 asid; 116 u32 flags; 117 struct tlbe *tlbe; 118 unsigned int ra; 119 unsigned int rs; 120 unsigned int ws; 121 unsigned int index; 122 123 ra = get_ra(inst); 124 rs = get_rs(inst); 125 ws = get_ws(inst); 126 127 index = vcpu->arch.gpr[ra]; 128 if (index > PPC44x_TLB_SIZE) { 129 printk("%s: index %d\n", __func__, index); 130 kvmppc_dump_vcpu(vcpu); 131 return EMULATE_FAIL; 132 } 133 134 tlbe = &vcpu->arch.guest_tlb[index]; 135 136 /* Invalidate shadow mappings for the about-to-be-clobbered TLBE. */ 137 if (tlbe->word0 & PPC44x_TLB_VALID) { 138 eaddr = get_tlb_eaddr(tlbe); 139 asid = (tlbe->word0 & PPC44x_TLB_TS) | tlbe->tid; 140 kvmppc_mmu_invalidate(vcpu, eaddr, get_tlb_end(tlbe), asid); 141 } 142 143 switch (ws) { 144 case PPC44x_TLB_PAGEID: 145 tlbe->tid = vcpu->arch.mmucr & 0xff; 146 tlbe->word0 = vcpu->arch.gpr[rs]; 147 break; 148 149 case PPC44x_TLB_XLAT: 150 tlbe->word1 = vcpu->arch.gpr[rs]; 151 break; 152 153 case PPC44x_TLB_ATTRIB: 154 tlbe->word2 = vcpu->arch.gpr[rs]; 155 break; 156 157 default: 158 return EMULATE_FAIL; 159 } 160 161 if (tlbe_is_host_safe(vcpu, tlbe)) { 162 eaddr = get_tlb_eaddr(tlbe); 163 raddr = get_tlb_raddr(tlbe); 164 asid = (tlbe->word0 & PPC44x_TLB_TS) | tlbe->tid; 165 flags = tlbe->word2 & 0xffff; 166 167 /* Create a 4KB mapping on the host. If the guest wanted a 168 * large page, only the first 4KB is mapped here and the rest 169 * are mapped on the fly. */ 170 kvmppc_mmu_map(vcpu, eaddr, raddr >> PAGE_SHIFT, asid, flags); 171 } 172 173 return EMULATE_DONE; 174 } 175 176 static void kvmppc_emulate_dec(struct kvm_vcpu *vcpu) 177 { 178 if (vcpu->arch.tcr & TCR_DIE) { 179 /* The decrementer ticks at the same rate as the timebase, so 180 * that's how we convert the guest DEC value to the number of 181 * host ticks. */ 182 unsigned long nr_jiffies; 183 184 nr_jiffies = vcpu->arch.dec / tb_ticks_per_jiffy; 185 mod_timer(&vcpu->arch.dec_timer, 186 get_jiffies_64() + nr_jiffies); 187 } else { 188 del_timer(&vcpu->arch.dec_timer); 189 } 190 } 191 192 static void kvmppc_emul_rfi(struct kvm_vcpu *vcpu) 193 { 194 vcpu->arch.pc = vcpu->arch.srr0; 195 kvmppc_set_msr(vcpu, vcpu->arch.srr1); 196 } 197 198 /* XXX to do: 199 * lhax 200 * lhaux 201 * lswx 202 * lswi 203 * stswx 204 * stswi 205 * lha 206 * lhau 207 * lmw 208 * stmw 209 * 210 * XXX is_bigendian should depend on MMU mapping or MSR[LE] 211 */ 212 int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu) 213 { 214 u32 inst = vcpu->arch.last_inst; 215 u32 ea; 216 int ra; 217 int rb; 218 int rc; 219 int rs; 220 int rt; 221 int sprn; 222 int dcrn; 223 enum emulation_result emulated = EMULATE_DONE; 224 int advance = 1; 225 226 switch (get_op(inst)) { 227 case 3: /* trap */ 228 printk("trap!\n"); 229 kvmppc_queue_exception(vcpu, BOOKE_INTERRUPT_PROGRAM); 230 advance = 0; 231 break; 232 233 case 19: 234 switch (get_xop(inst)) { 235 case 50: /* rfi */ 236 kvmppc_emul_rfi(vcpu); 237 advance = 0; 238 break; 239 240 default: 241 emulated = EMULATE_FAIL; 242 break; 243 } 244 break; 245 246 case 31: 247 switch (get_xop(inst)) { 248 249 case 23: /* lwzx */ 250 rt = get_rt(inst); 251 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1); 252 break; 253 254 case 83: /* mfmsr */ 255 rt = get_rt(inst); 256 vcpu->arch.gpr[rt] = vcpu->arch.msr; 257 break; 258 259 case 87: /* lbzx */ 260 rt = get_rt(inst); 261 emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1); 262 break; 263 264 case 131: /* wrtee */ 265 rs = get_rs(inst); 266 vcpu->arch.msr = (vcpu->arch.msr & ~MSR_EE) 267 | (vcpu->arch.gpr[rs] & MSR_EE); 268 break; 269 270 case 146: /* mtmsr */ 271 rs = get_rs(inst); 272 kvmppc_set_msr(vcpu, vcpu->arch.gpr[rs]); 273 break; 274 275 case 151: /* stwx */ 276 rs = get_rs(inst); 277 emulated = kvmppc_handle_store(run, vcpu, 278 vcpu->arch.gpr[rs], 279 4, 1); 280 break; 281 282 case 163: /* wrteei */ 283 vcpu->arch.msr = (vcpu->arch.msr & ~MSR_EE) 284 | (inst & MSR_EE); 285 break; 286 287 case 215: /* stbx */ 288 rs = get_rs(inst); 289 emulated = kvmppc_handle_store(run, vcpu, 290 vcpu->arch.gpr[rs], 291 1, 1); 292 break; 293 294 case 247: /* stbux */ 295 rs = get_rs(inst); 296 ra = get_ra(inst); 297 rb = get_rb(inst); 298 299 ea = vcpu->arch.gpr[rb]; 300 if (ra) 301 ea += vcpu->arch.gpr[ra]; 302 303 emulated = kvmppc_handle_store(run, vcpu, 304 vcpu->arch.gpr[rs], 305 1, 1); 306 vcpu->arch.gpr[rs] = ea; 307 break; 308 309 case 279: /* lhzx */ 310 rt = get_rt(inst); 311 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1); 312 break; 313 314 case 311: /* lhzux */ 315 rt = get_rt(inst); 316 ra = get_ra(inst); 317 rb = get_rb(inst); 318 319 ea = vcpu->arch.gpr[rb]; 320 if (ra) 321 ea += vcpu->arch.gpr[ra]; 322 323 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1); 324 vcpu->arch.gpr[ra] = ea; 325 break; 326 327 case 323: /* mfdcr */ 328 dcrn = get_dcrn(inst); 329 rt = get_rt(inst); 330 331 /* The guest may access CPR0 registers to determine the timebase 332 * frequency, and it must know the real host frequency because it 333 * can directly access the timebase registers. 334 * 335 * It would be possible to emulate those accesses in userspace, 336 * but userspace can really only figure out the end frequency. 337 * We could decompose that into the factors that compute it, but 338 * that's tricky math, and it's easier to just report the real 339 * CPR0 values. 340 */ 341 switch (dcrn) { 342 case DCRN_CPR0_CONFIG_ADDR: 343 vcpu->arch.gpr[rt] = vcpu->arch.cpr0_cfgaddr; 344 break; 345 case DCRN_CPR0_CONFIG_DATA: 346 local_irq_disable(); 347 mtdcr(DCRN_CPR0_CONFIG_ADDR, 348 vcpu->arch.cpr0_cfgaddr); 349 vcpu->arch.gpr[rt] = mfdcr(DCRN_CPR0_CONFIG_DATA); 350 local_irq_enable(); 351 break; 352 default: 353 run->dcr.dcrn = dcrn; 354 run->dcr.data = 0; 355 run->dcr.is_write = 0; 356 vcpu->arch.io_gpr = rt; 357 vcpu->arch.dcr_needed = 1; 358 emulated = EMULATE_DO_DCR; 359 } 360 361 break; 362 363 case 339: /* mfspr */ 364 sprn = get_sprn(inst); 365 rt = get_rt(inst); 366 367 switch (sprn) { 368 case SPRN_SRR0: 369 vcpu->arch.gpr[rt] = vcpu->arch.srr0; break; 370 case SPRN_SRR1: 371 vcpu->arch.gpr[rt] = vcpu->arch.srr1; break; 372 case SPRN_MMUCR: 373 vcpu->arch.gpr[rt] = vcpu->arch.mmucr; break; 374 case SPRN_PID: 375 vcpu->arch.gpr[rt] = vcpu->arch.pid; break; 376 case SPRN_IVPR: 377 vcpu->arch.gpr[rt] = vcpu->arch.ivpr; break; 378 case SPRN_CCR0: 379 vcpu->arch.gpr[rt] = vcpu->arch.ccr0; break; 380 case SPRN_CCR1: 381 vcpu->arch.gpr[rt] = vcpu->arch.ccr1; break; 382 case SPRN_PVR: 383 vcpu->arch.gpr[rt] = vcpu->arch.pvr; break; 384 case SPRN_DEAR: 385 vcpu->arch.gpr[rt] = vcpu->arch.dear; break; 386 case SPRN_ESR: 387 vcpu->arch.gpr[rt] = vcpu->arch.esr; break; 388 case SPRN_DBCR0: 389 vcpu->arch.gpr[rt] = vcpu->arch.dbcr0; break; 390 case SPRN_DBCR1: 391 vcpu->arch.gpr[rt] = vcpu->arch.dbcr1; break; 392 393 /* Note: mftb and TBRL/TBWL are user-accessible, so 394 * the guest can always access the real TB anyways. 395 * In fact, we probably will never see these traps. */ 396 case SPRN_TBWL: 397 vcpu->arch.gpr[rt] = mftbl(); break; 398 case SPRN_TBWU: 399 vcpu->arch.gpr[rt] = mftbu(); break; 400 401 case SPRN_SPRG0: 402 vcpu->arch.gpr[rt] = vcpu->arch.sprg0; break; 403 case SPRN_SPRG1: 404 vcpu->arch.gpr[rt] = vcpu->arch.sprg1; break; 405 case SPRN_SPRG2: 406 vcpu->arch.gpr[rt] = vcpu->arch.sprg2; break; 407 case SPRN_SPRG3: 408 vcpu->arch.gpr[rt] = vcpu->arch.sprg3; break; 409 /* Note: SPRG4-7 are user-readable, so we don't get 410 * a trap. */ 411 412 case SPRN_IVOR0: 413 vcpu->arch.gpr[rt] = vcpu->arch.ivor[0]; break; 414 case SPRN_IVOR1: 415 vcpu->arch.gpr[rt] = vcpu->arch.ivor[1]; break; 416 case SPRN_IVOR2: 417 vcpu->arch.gpr[rt] = vcpu->arch.ivor[2]; break; 418 case SPRN_IVOR3: 419 vcpu->arch.gpr[rt] = vcpu->arch.ivor[3]; break; 420 case SPRN_IVOR4: 421 vcpu->arch.gpr[rt] = vcpu->arch.ivor[4]; break; 422 case SPRN_IVOR5: 423 vcpu->arch.gpr[rt] = vcpu->arch.ivor[5]; break; 424 case SPRN_IVOR6: 425 vcpu->arch.gpr[rt] = vcpu->arch.ivor[6]; break; 426 case SPRN_IVOR7: 427 vcpu->arch.gpr[rt] = vcpu->arch.ivor[7]; break; 428 case SPRN_IVOR8: 429 vcpu->arch.gpr[rt] = vcpu->arch.ivor[8]; break; 430 case SPRN_IVOR9: 431 vcpu->arch.gpr[rt] = vcpu->arch.ivor[9]; break; 432 case SPRN_IVOR10: 433 vcpu->arch.gpr[rt] = vcpu->arch.ivor[10]; break; 434 case SPRN_IVOR11: 435 vcpu->arch.gpr[rt] = vcpu->arch.ivor[11]; break; 436 case SPRN_IVOR12: 437 vcpu->arch.gpr[rt] = vcpu->arch.ivor[12]; break; 438 case SPRN_IVOR13: 439 vcpu->arch.gpr[rt] = vcpu->arch.ivor[13]; break; 440 case SPRN_IVOR14: 441 vcpu->arch.gpr[rt] = vcpu->arch.ivor[14]; break; 442 case SPRN_IVOR15: 443 vcpu->arch.gpr[rt] = vcpu->arch.ivor[15]; break; 444 445 default: 446 printk("mfspr: unknown spr %x\n", sprn); 447 vcpu->arch.gpr[rt] = 0; 448 break; 449 } 450 break; 451 452 case 407: /* sthx */ 453 rs = get_rs(inst); 454 ra = get_ra(inst); 455 rb = get_rb(inst); 456 457 emulated = kvmppc_handle_store(run, vcpu, 458 vcpu->arch.gpr[rs], 459 2, 1); 460 break; 461 462 case 439: /* sthux */ 463 rs = get_rs(inst); 464 ra = get_ra(inst); 465 rb = get_rb(inst); 466 467 ea = vcpu->arch.gpr[rb]; 468 if (ra) 469 ea += vcpu->arch.gpr[ra]; 470 471 emulated = kvmppc_handle_store(run, vcpu, 472 vcpu->arch.gpr[rs], 473 2, 1); 474 vcpu->arch.gpr[ra] = ea; 475 break; 476 477 case 451: /* mtdcr */ 478 dcrn = get_dcrn(inst); 479 rs = get_rs(inst); 480 481 /* emulate some access in kernel */ 482 switch (dcrn) { 483 case DCRN_CPR0_CONFIG_ADDR: 484 vcpu->arch.cpr0_cfgaddr = vcpu->arch.gpr[rs]; 485 break; 486 default: 487 run->dcr.dcrn = dcrn; 488 run->dcr.data = vcpu->arch.gpr[rs]; 489 run->dcr.is_write = 1; 490 vcpu->arch.dcr_needed = 1; 491 emulated = EMULATE_DO_DCR; 492 } 493 494 break; 495 496 case 467: /* mtspr */ 497 sprn = get_sprn(inst); 498 rs = get_rs(inst); 499 switch (sprn) { 500 case SPRN_SRR0: 501 vcpu->arch.srr0 = vcpu->arch.gpr[rs]; break; 502 case SPRN_SRR1: 503 vcpu->arch.srr1 = vcpu->arch.gpr[rs]; break; 504 case SPRN_MMUCR: 505 vcpu->arch.mmucr = vcpu->arch.gpr[rs]; break; 506 case SPRN_PID: 507 vcpu->arch.pid = vcpu->arch.gpr[rs]; break; 508 case SPRN_CCR0: 509 vcpu->arch.ccr0 = vcpu->arch.gpr[rs]; break; 510 case SPRN_CCR1: 511 vcpu->arch.ccr1 = vcpu->arch.gpr[rs]; break; 512 case SPRN_DEAR: 513 vcpu->arch.dear = vcpu->arch.gpr[rs]; break; 514 case SPRN_ESR: 515 vcpu->arch.esr = vcpu->arch.gpr[rs]; break; 516 case SPRN_DBCR0: 517 vcpu->arch.dbcr0 = vcpu->arch.gpr[rs]; break; 518 case SPRN_DBCR1: 519 vcpu->arch.dbcr1 = vcpu->arch.gpr[rs]; break; 520 521 /* XXX We need to context-switch the timebase for 522 * watchdog and FIT. */ 523 case SPRN_TBWL: break; 524 case SPRN_TBWU: break; 525 526 case SPRN_DEC: 527 vcpu->arch.dec = vcpu->arch.gpr[rs]; 528 kvmppc_emulate_dec(vcpu); 529 break; 530 531 case SPRN_TSR: 532 vcpu->arch.tsr &= ~vcpu->arch.gpr[rs]; break; 533 534 case SPRN_TCR: 535 vcpu->arch.tcr = vcpu->arch.gpr[rs]; 536 kvmppc_emulate_dec(vcpu); 537 break; 538 539 case SPRN_SPRG0: 540 vcpu->arch.sprg0 = vcpu->arch.gpr[rs]; break; 541 case SPRN_SPRG1: 542 vcpu->arch.sprg1 = vcpu->arch.gpr[rs]; break; 543 case SPRN_SPRG2: 544 vcpu->arch.sprg2 = vcpu->arch.gpr[rs]; break; 545 case SPRN_SPRG3: 546 vcpu->arch.sprg3 = vcpu->arch.gpr[rs]; break; 547 548 /* Note: SPRG4-7 are user-readable. These values are 549 * loaded into the real SPRGs when resuming the 550 * guest. */ 551 case SPRN_SPRG4: 552 vcpu->arch.sprg4 = vcpu->arch.gpr[rs]; break; 553 case SPRN_SPRG5: 554 vcpu->arch.sprg5 = vcpu->arch.gpr[rs]; break; 555 case SPRN_SPRG6: 556 vcpu->arch.sprg6 = vcpu->arch.gpr[rs]; break; 557 case SPRN_SPRG7: 558 vcpu->arch.sprg7 = vcpu->arch.gpr[rs]; break; 559 560 case SPRN_IVPR: 561 vcpu->arch.ivpr = vcpu->arch.gpr[rs]; break; 562 case SPRN_IVOR0: 563 vcpu->arch.ivor[0] = vcpu->arch.gpr[rs]; break; 564 case SPRN_IVOR1: 565 vcpu->arch.ivor[1] = vcpu->arch.gpr[rs]; break; 566 case SPRN_IVOR2: 567 vcpu->arch.ivor[2] = vcpu->arch.gpr[rs]; break; 568 case SPRN_IVOR3: 569 vcpu->arch.ivor[3] = vcpu->arch.gpr[rs]; break; 570 case SPRN_IVOR4: 571 vcpu->arch.ivor[4] = vcpu->arch.gpr[rs]; break; 572 case SPRN_IVOR5: 573 vcpu->arch.ivor[5] = vcpu->arch.gpr[rs]; break; 574 case SPRN_IVOR6: 575 vcpu->arch.ivor[6] = vcpu->arch.gpr[rs]; break; 576 case SPRN_IVOR7: 577 vcpu->arch.ivor[7] = vcpu->arch.gpr[rs]; break; 578 case SPRN_IVOR8: 579 vcpu->arch.ivor[8] = vcpu->arch.gpr[rs]; break; 580 case SPRN_IVOR9: 581 vcpu->arch.ivor[9] = vcpu->arch.gpr[rs]; break; 582 case SPRN_IVOR10: 583 vcpu->arch.ivor[10] = vcpu->arch.gpr[rs]; break; 584 case SPRN_IVOR11: 585 vcpu->arch.ivor[11] = vcpu->arch.gpr[rs]; break; 586 case SPRN_IVOR12: 587 vcpu->arch.ivor[12] = vcpu->arch.gpr[rs]; break; 588 case SPRN_IVOR13: 589 vcpu->arch.ivor[13] = vcpu->arch.gpr[rs]; break; 590 case SPRN_IVOR14: 591 vcpu->arch.ivor[14] = vcpu->arch.gpr[rs]; break; 592 case SPRN_IVOR15: 593 vcpu->arch.ivor[15] = vcpu->arch.gpr[rs]; break; 594 595 default: 596 printk("mtspr: unknown spr %x\n", sprn); 597 emulated = EMULATE_FAIL; 598 break; 599 } 600 break; 601 602 case 470: /* dcbi */ 603 /* Do nothing. The guest is performing dcbi because 604 * hardware DMA is not snooped by the dcache, but 605 * emulated DMA either goes through the dcache as 606 * normal writes, or the host kernel has handled dcache 607 * coherence. */ 608 break; 609 610 case 534: /* lwbrx */ 611 rt = get_rt(inst); 612 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 0); 613 break; 614 615 case 566: /* tlbsync */ 616 break; 617 618 case 662: /* stwbrx */ 619 rs = get_rs(inst); 620 ra = get_ra(inst); 621 rb = get_rb(inst); 622 623 emulated = kvmppc_handle_store(run, vcpu, 624 vcpu->arch.gpr[rs], 625 4, 0); 626 break; 627 628 case 978: /* tlbwe */ 629 emulated = kvmppc_emul_tlbwe(vcpu, inst); 630 break; 631 632 case 914: { /* tlbsx */ 633 int index; 634 unsigned int as = get_mmucr_sts(vcpu); 635 unsigned int pid = get_mmucr_stid(vcpu); 636 637 rt = get_rt(inst); 638 ra = get_ra(inst); 639 rb = get_rb(inst); 640 rc = get_rc(inst); 641 642 ea = vcpu->arch.gpr[rb]; 643 if (ra) 644 ea += vcpu->arch.gpr[ra]; 645 646 index = kvmppc_44x_tlb_index(vcpu, ea, pid, as); 647 if (rc) { 648 if (index < 0) 649 vcpu->arch.cr &= ~0x20000000; 650 else 651 vcpu->arch.cr |= 0x20000000; 652 } 653 vcpu->arch.gpr[rt] = index; 654 655 } 656 break; 657 658 case 790: /* lhbrx */ 659 rt = get_rt(inst); 660 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 0); 661 break; 662 663 case 918: /* sthbrx */ 664 rs = get_rs(inst); 665 ra = get_ra(inst); 666 rb = get_rb(inst); 667 668 emulated = kvmppc_handle_store(run, vcpu, 669 vcpu->arch.gpr[rs], 670 2, 0); 671 break; 672 673 case 966: /* iccci */ 674 break; 675 676 default: 677 printk("unknown: op %d xop %d\n", get_op(inst), 678 get_xop(inst)); 679 emulated = EMULATE_FAIL; 680 break; 681 } 682 break; 683 684 case 32: /* lwz */ 685 rt = get_rt(inst); 686 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1); 687 break; 688 689 case 33: /* lwzu */ 690 ra = get_ra(inst); 691 rt = get_rt(inst); 692 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1); 693 vcpu->arch.gpr[ra] = vcpu->arch.paddr_accessed; 694 break; 695 696 case 34: /* lbz */ 697 rt = get_rt(inst); 698 emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1); 699 break; 700 701 case 35: /* lbzu */ 702 ra = get_ra(inst); 703 rt = get_rt(inst); 704 emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1); 705 vcpu->arch.gpr[ra] = vcpu->arch.paddr_accessed; 706 break; 707 708 case 36: /* stw */ 709 rs = get_rs(inst); 710 emulated = kvmppc_handle_store(run, vcpu, vcpu->arch.gpr[rs], 711 4, 1); 712 break; 713 714 case 37: /* stwu */ 715 ra = get_ra(inst); 716 rs = get_rs(inst); 717 emulated = kvmppc_handle_store(run, vcpu, vcpu->arch.gpr[rs], 718 4, 1); 719 vcpu->arch.gpr[ra] = vcpu->arch.paddr_accessed; 720 break; 721 722 case 38: /* stb */ 723 rs = get_rs(inst); 724 emulated = kvmppc_handle_store(run, vcpu, vcpu->arch.gpr[rs], 725 1, 1); 726 break; 727 728 case 39: /* stbu */ 729 ra = get_ra(inst); 730 rs = get_rs(inst); 731 emulated = kvmppc_handle_store(run, vcpu, vcpu->arch.gpr[rs], 732 1, 1); 733 vcpu->arch.gpr[ra] = vcpu->arch.paddr_accessed; 734 break; 735 736 case 40: /* lhz */ 737 rt = get_rt(inst); 738 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1); 739 break; 740 741 case 41: /* lhzu */ 742 ra = get_ra(inst); 743 rt = get_rt(inst); 744 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1); 745 vcpu->arch.gpr[ra] = vcpu->arch.paddr_accessed; 746 break; 747 748 case 44: /* sth */ 749 rs = get_rs(inst); 750 emulated = kvmppc_handle_store(run, vcpu, vcpu->arch.gpr[rs], 751 2, 1); 752 break; 753 754 case 45: /* sthu */ 755 ra = get_ra(inst); 756 rs = get_rs(inst); 757 emulated = kvmppc_handle_store(run, vcpu, vcpu->arch.gpr[rs], 758 2, 1); 759 vcpu->arch.gpr[ra] = vcpu->arch.paddr_accessed; 760 break; 761 762 default: 763 printk("unknown op %d\n", get_op(inst)); 764 emulated = EMULATE_FAIL; 765 break; 766 } 767 768 if (advance) 769 vcpu->arch.pc += 4; /* Advance past emulated instruction. */ 770 771 return emulated; 772 } 773