1 /* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License, version 2, as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, write to the Free Software 13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 14 * 15 * Copyright IBM Corp. 2007 16 * 17 * Authors: Hollis Blanchard <hollisb@us.ibm.com> 18 */ 19 20 #include <linux/jiffies.h> 21 #include <linux/hrtimer.h> 22 #include <linux/types.h> 23 #include <linux/string.h> 24 #include <linux/kvm_host.h> 25 26 #include <asm/reg.h> 27 #include <asm/time.h> 28 #include <asm/byteorder.h> 29 #include <asm/kvm_ppc.h> 30 #include <asm/disassemble.h> 31 #include "timing.h" 32 #include "trace.h" 33 34 #define OP_TRAP 3 35 #define OP_TRAP_64 2 36 37 #define OP_31_XOP_LWZX 23 38 #define OP_31_XOP_LBZX 87 39 #define OP_31_XOP_STWX 151 40 #define OP_31_XOP_STBX 215 41 #define OP_31_XOP_LBZUX 119 42 #define OP_31_XOP_STBUX 247 43 #define OP_31_XOP_LHZX 279 44 #define OP_31_XOP_LHZUX 311 45 #define OP_31_XOP_MFSPR 339 46 #define OP_31_XOP_LHAX 343 47 #define OP_31_XOP_STHX 407 48 #define OP_31_XOP_STHUX 439 49 #define OP_31_XOP_MTSPR 467 50 #define OP_31_XOP_DCBI 470 51 #define OP_31_XOP_LWBRX 534 52 #define OP_31_XOP_TLBSYNC 566 53 #define OP_31_XOP_STWBRX 662 54 #define OP_31_XOP_LHBRX 790 55 #define OP_31_XOP_STHBRX 918 56 57 #define OP_LWZ 32 58 #define OP_LWZU 33 59 #define OP_LBZ 34 60 #define OP_LBZU 35 61 #define OP_STW 36 62 #define OP_STWU 37 63 #define OP_STB 38 64 #define OP_STBU 39 65 #define OP_LHZ 40 66 #define OP_LHZU 41 67 #define OP_LHA 42 68 #define OP_LHAU 43 69 #define OP_STH 44 70 #define OP_STHU 45 71 72 #ifdef CONFIG_PPC_BOOK3S 73 static int kvmppc_dec_enabled(struct kvm_vcpu *vcpu) 74 { 75 return 1; 76 } 77 #else 78 static int kvmppc_dec_enabled(struct kvm_vcpu *vcpu) 79 { 80 return vcpu->arch.tcr & TCR_DIE; 81 } 82 #endif 83 84 void kvmppc_emulate_dec(struct kvm_vcpu *vcpu) 85 { 86 unsigned long dec_nsec; 87 88 pr_debug("mtDEC: %x\n", vcpu->arch.dec); 89 #ifdef CONFIG_PPC_BOOK3S 90 /* mtdec lowers the interrupt line when positive. */ 91 kvmppc_core_dequeue_dec(vcpu); 92 93 /* POWER4+ triggers a dec interrupt if the value is < 0 */ 94 if (vcpu->arch.dec & 0x80000000) { 95 hrtimer_try_to_cancel(&vcpu->arch.dec_timer); 96 kvmppc_core_queue_dec(vcpu); 97 return; 98 } 99 #endif 100 if (kvmppc_dec_enabled(vcpu)) { 101 /* The decrementer ticks at the same rate as the timebase, so 102 * that's how we convert the guest DEC value to the number of 103 * host ticks. */ 104 105 hrtimer_try_to_cancel(&vcpu->arch.dec_timer); 106 dec_nsec = vcpu->arch.dec; 107 dec_nsec *= 1000; 108 dec_nsec /= tb_ticks_per_usec; 109 hrtimer_start(&vcpu->arch.dec_timer, ktime_set(0, dec_nsec), 110 HRTIMER_MODE_REL); 111 vcpu->arch.dec_jiffies = get_tb(); 112 } else { 113 hrtimer_try_to_cancel(&vcpu->arch.dec_timer); 114 } 115 } 116 117 /* XXX to do: 118 * lhax 119 * lhaux 120 * lswx 121 * lswi 122 * stswx 123 * stswi 124 * lha 125 * lhau 126 * lmw 127 * stmw 128 * 129 * XXX is_bigendian should depend on MMU mapping or MSR[LE] 130 */ 131 /* XXX Should probably auto-generate instruction decoding for a particular core 132 * from opcode tables in the future. */ 133 int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu) 134 { 135 u32 inst = kvmppc_get_last_inst(vcpu); 136 u32 ea; 137 int ra; 138 int rb; 139 int rs; 140 int rt; 141 int sprn; 142 enum emulation_result emulated = EMULATE_DONE; 143 int advance = 1; 144 145 /* this default type might be overwritten by subcategories */ 146 kvmppc_set_exit_type(vcpu, EMULATED_INST_EXITS); 147 148 pr_debug(KERN_INFO "Emulating opcode %d / %d\n", get_op(inst), get_xop(inst)); 149 150 switch (get_op(inst)) { 151 case OP_TRAP: 152 #ifdef CONFIG_PPC_BOOK3S 153 case OP_TRAP_64: 154 kvmppc_core_queue_program(vcpu, SRR1_PROGTRAP); 155 #else 156 kvmppc_core_queue_program(vcpu, vcpu->arch.esr | ESR_PTR); 157 #endif 158 advance = 0; 159 break; 160 161 case 31: 162 switch (get_xop(inst)) { 163 164 case OP_31_XOP_LWZX: 165 rt = get_rt(inst); 166 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1); 167 break; 168 169 case OP_31_XOP_LBZX: 170 rt = get_rt(inst); 171 emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1); 172 break; 173 174 case OP_31_XOP_LBZUX: 175 rt = get_rt(inst); 176 ra = get_ra(inst); 177 rb = get_rb(inst); 178 179 ea = kvmppc_get_gpr(vcpu, rb); 180 if (ra) 181 ea += kvmppc_get_gpr(vcpu, ra); 182 183 emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1); 184 kvmppc_set_gpr(vcpu, ra, ea); 185 break; 186 187 case OP_31_XOP_STWX: 188 rs = get_rs(inst); 189 emulated = kvmppc_handle_store(run, vcpu, 190 kvmppc_get_gpr(vcpu, rs), 191 4, 1); 192 break; 193 194 case OP_31_XOP_STBX: 195 rs = get_rs(inst); 196 emulated = kvmppc_handle_store(run, vcpu, 197 kvmppc_get_gpr(vcpu, rs), 198 1, 1); 199 break; 200 201 case OP_31_XOP_STBUX: 202 rs = get_rs(inst); 203 ra = get_ra(inst); 204 rb = get_rb(inst); 205 206 ea = kvmppc_get_gpr(vcpu, rb); 207 if (ra) 208 ea += kvmppc_get_gpr(vcpu, ra); 209 210 emulated = kvmppc_handle_store(run, vcpu, 211 kvmppc_get_gpr(vcpu, rs), 212 1, 1); 213 kvmppc_set_gpr(vcpu, rs, ea); 214 break; 215 216 case OP_31_XOP_LHAX: 217 rt = get_rt(inst); 218 emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1); 219 break; 220 221 case OP_31_XOP_LHZX: 222 rt = get_rt(inst); 223 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1); 224 break; 225 226 case OP_31_XOP_LHZUX: 227 rt = get_rt(inst); 228 ra = get_ra(inst); 229 rb = get_rb(inst); 230 231 ea = kvmppc_get_gpr(vcpu, rb); 232 if (ra) 233 ea += kvmppc_get_gpr(vcpu, ra); 234 235 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1); 236 kvmppc_set_gpr(vcpu, ra, ea); 237 break; 238 239 case OP_31_XOP_MFSPR: 240 sprn = get_sprn(inst); 241 rt = get_rt(inst); 242 243 switch (sprn) { 244 case SPRN_SRR0: 245 kvmppc_set_gpr(vcpu, rt, vcpu->arch.srr0); break; 246 case SPRN_SRR1: 247 kvmppc_set_gpr(vcpu, rt, vcpu->arch.srr1); break; 248 case SPRN_PVR: 249 kvmppc_set_gpr(vcpu, rt, vcpu->arch.pvr); break; 250 case SPRN_PIR: 251 kvmppc_set_gpr(vcpu, rt, vcpu->vcpu_id); break; 252 case SPRN_MSSSR0: 253 kvmppc_set_gpr(vcpu, rt, 0); break; 254 255 /* Note: mftb and TBRL/TBWL are user-accessible, so 256 * the guest can always access the real TB anyways. 257 * In fact, we probably will never see these traps. */ 258 case SPRN_TBWL: 259 kvmppc_set_gpr(vcpu, rt, get_tb() >> 32); break; 260 case SPRN_TBWU: 261 kvmppc_set_gpr(vcpu, rt, get_tb()); break; 262 263 case SPRN_SPRG0: 264 kvmppc_set_gpr(vcpu, rt, vcpu->arch.sprg0); break; 265 case SPRN_SPRG1: 266 kvmppc_set_gpr(vcpu, rt, vcpu->arch.sprg1); break; 267 case SPRN_SPRG2: 268 kvmppc_set_gpr(vcpu, rt, vcpu->arch.sprg2); break; 269 case SPRN_SPRG3: 270 kvmppc_set_gpr(vcpu, rt, vcpu->arch.sprg3); break; 271 /* Note: SPRG4-7 are user-readable, so we don't get 272 * a trap. */ 273 274 case SPRN_DEC: 275 { 276 u64 jd = get_tb() - vcpu->arch.dec_jiffies; 277 kvmppc_set_gpr(vcpu, rt, vcpu->arch.dec - jd); 278 pr_debug(KERN_INFO "mfDEC: %x - %llx = %lx\n", 279 vcpu->arch.dec, jd, 280 kvmppc_get_gpr(vcpu, rt)); 281 break; 282 } 283 default: 284 emulated = kvmppc_core_emulate_mfspr(vcpu, sprn, rt); 285 if (emulated == EMULATE_FAIL) { 286 printk("mfspr: unknown spr %x\n", sprn); 287 kvmppc_set_gpr(vcpu, rt, 0); 288 } 289 break; 290 } 291 break; 292 293 case OP_31_XOP_STHX: 294 rs = get_rs(inst); 295 ra = get_ra(inst); 296 rb = get_rb(inst); 297 298 emulated = kvmppc_handle_store(run, vcpu, 299 kvmppc_get_gpr(vcpu, rs), 300 2, 1); 301 break; 302 303 case OP_31_XOP_STHUX: 304 rs = get_rs(inst); 305 ra = get_ra(inst); 306 rb = get_rb(inst); 307 308 ea = kvmppc_get_gpr(vcpu, rb); 309 if (ra) 310 ea += kvmppc_get_gpr(vcpu, ra); 311 312 emulated = kvmppc_handle_store(run, vcpu, 313 kvmppc_get_gpr(vcpu, rs), 314 2, 1); 315 kvmppc_set_gpr(vcpu, ra, ea); 316 break; 317 318 case OP_31_XOP_MTSPR: 319 sprn = get_sprn(inst); 320 rs = get_rs(inst); 321 switch (sprn) { 322 case SPRN_SRR0: 323 vcpu->arch.srr0 = kvmppc_get_gpr(vcpu, rs); break; 324 case SPRN_SRR1: 325 vcpu->arch.srr1 = kvmppc_get_gpr(vcpu, rs); break; 326 327 /* XXX We need to context-switch the timebase for 328 * watchdog and FIT. */ 329 case SPRN_TBWL: break; 330 case SPRN_TBWU: break; 331 332 case SPRN_MSSSR0: break; 333 334 case SPRN_DEC: 335 vcpu->arch.dec = kvmppc_get_gpr(vcpu, rs); 336 kvmppc_emulate_dec(vcpu); 337 break; 338 339 case SPRN_SPRG0: 340 vcpu->arch.sprg0 = kvmppc_get_gpr(vcpu, rs); break; 341 case SPRN_SPRG1: 342 vcpu->arch.sprg1 = kvmppc_get_gpr(vcpu, rs); break; 343 case SPRN_SPRG2: 344 vcpu->arch.sprg2 = kvmppc_get_gpr(vcpu, rs); break; 345 case SPRN_SPRG3: 346 vcpu->arch.sprg3 = kvmppc_get_gpr(vcpu, rs); break; 347 348 default: 349 emulated = kvmppc_core_emulate_mtspr(vcpu, sprn, rs); 350 if (emulated == EMULATE_FAIL) 351 printk("mtspr: unknown spr %x\n", sprn); 352 break; 353 } 354 break; 355 356 case OP_31_XOP_DCBI: 357 /* Do nothing. The guest is performing dcbi because 358 * hardware DMA is not snooped by the dcache, but 359 * emulated DMA either goes through the dcache as 360 * normal writes, or the host kernel has handled dcache 361 * coherence. */ 362 break; 363 364 case OP_31_XOP_LWBRX: 365 rt = get_rt(inst); 366 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 0); 367 break; 368 369 case OP_31_XOP_TLBSYNC: 370 break; 371 372 case OP_31_XOP_STWBRX: 373 rs = get_rs(inst); 374 ra = get_ra(inst); 375 rb = get_rb(inst); 376 377 emulated = kvmppc_handle_store(run, vcpu, 378 kvmppc_get_gpr(vcpu, rs), 379 4, 0); 380 break; 381 382 case OP_31_XOP_LHBRX: 383 rt = get_rt(inst); 384 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 0); 385 break; 386 387 case OP_31_XOP_STHBRX: 388 rs = get_rs(inst); 389 ra = get_ra(inst); 390 rb = get_rb(inst); 391 392 emulated = kvmppc_handle_store(run, vcpu, 393 kvmppc_get_gpr(vcpu, rs), 394 2, 0); 395 break; 396 397 default: 398 /* Attempt core-specific emulation below. */ 399 emulated = EMULATE_FAIL; 400 } 401 break; 402 403 case OP_LWZ: 404 rt = get_rt(inst); 405 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1); 406 break; 407 408 case OP_LWZU: 409 ra = get_ra(inst); 410 rt = get_rt(inst); 411 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1); 412 kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed); 413 break; 414 415 case OP_LBZ: 416 rt = get_rt(inst); 417 emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1); 418 break; 419 420 case OP_LBZU: 421 ra = get_ra(inst); 422 rt = get_rt(inst); 423 emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1); 424 kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed); 425 break; 426 427 case OP_STW: 428 rs = get_rs(inst); 429 emulated = kvmppc_handle_store(run, vcpu, 430 kvmppc_get_gpr(vcpu, rs), 431 4, 1); 432 break; 433 434 case OP_STWU: 435 ra = get_ra(inst); 436 rs = get_rs(inst); 437 emulated = kvmppc_handle_store(run, vcpu, 438 kvmppc_get_gpr(vcpu, rs), 439 4, 1); 440 kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed); 441 break; 442 443 case OP_STB: 444 rs = get_rs(inst); 445 emulated = kvmppc_handle_store(run, vcpu, 446 kvmppc_get_gpr(vcpu, rs), 447 1, 1); 448 break; 449 450 case OP_STBU: 451 ra = get_ra(inst); 452 rs = get_rs(inst); 453 emulated = kvmppc_handle_store(run, vcpu, 454 kvmppc_get_gpr(vcpu, rs), 455 1, 1); 456 kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed); 457 break; 458 459 case OP_LHZ: 460 rt = get_rt(inst); 461 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1); 462 break; 463 464 case OP_LHZU: 465 ra = get_ra(inst); 466 rt = get_rt(inst); 467 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1); 468 kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed); 469 break; 470 471 case OP_LHA: 472 rt = get_rt(inst); 473 emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1); 474 break; 475 476 case OP_LHAU: 477 ra = get_ra(inst); 478 rt = get_rt(inst); 479 emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1); 480 kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed); 481 break; 482 483 case OP_STH: 484 rs = get_rs(inst); 485 emulated = kvmppc_handle_store(run, vcpu, 486 kvmppc_get_gpr(vcpu, rs), 487 2, 1); 488 break; 489 490 case OP_STHU: 491 ra = get_ra(inst); 492 rs = get_rs(inst); 493 emulated = kvmppc_handle_store(run, vcpu, 494 kvmppc_get_gpr(vcpu, rs), 495 2, 1); 496 kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed); 497 break; 498 499 default: 500 emulated = EMULATE_FAIL; 501 } 502 503 if (emulated == EMULATE_FAIL) { 504 emulated = kvmppc_core_emulate_op(run, vcpu, inst, &advance); 505 if (emulated == EMULATE_AGAIN) { 506 advance = 0; 507 } else if (emulated == EMULATE_FAIL) { 508 advance = 0; 509 printk(KERN_ERR "Couldn't emulate instruction 0x%08x " 510 "(op %d xop %d)\n", inst, get_op(inst), get_xop(inst)); 511 kvmppc_core_queue_program(vcpu, 0); 512 } 513 } 514 515 trace_kvm_ppc_instr(inst, kvmppc_get_pc(vcpu), emulated); 516 517 /* Advance past emulated instruction. */ 518 if (advance) 519 kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + 4); 520 521 return emulated; 522 } 523