1/* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License, version 2, as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, write to the Free Software 13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 14 * 15 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 16 * 17 * Author: Varun Sethi <varun.sethi@freescale.com> 18 * Author: Scott Wood <scotwood@freescale.com> 19 * Author: Mihai Caraman <mihai.caraman@freescale.com> 20 * 21 * This file is derived from arch/powerpc/kvm/booke_interrupts.S 22 */ 23 24#include <asm/ppc_asm.h> 25#include <asm/kvm_asm.h> 26#include <asm/reg.h> 27#include <asm/mmu-44x.h> 28#include <asm/page.h> 29#include <asm/asm-compat.h> 30#include <asm/asm-offsets.h> 31#include <asm/bitsperlong.h> 32#include <asm/thread_info.h> 33 34#ifdef CONFIG_64BIT 35#include <asm/exception-64e.h> 36#include <asm/hw_irq.h> 37#include <asm/irqflags.h> 38#else 39#include "../kernel/head_booke.h" /* for THREAD_NORMSAVE() */ 40#endif 41 42#define LONGBYTES (BITS_PER_LONG / 8) 43 44#define VCPU_GUEST_SPRG(n) (VCPU_GUEST_SPRGS + (n * LONGBYTES)) 45 46/* The host stack layout: */ 47#define HOST_R1 0 /* Implied by stwu. */ 48#define HOST_CALLEE_LR PPC_LR_STKOFF 49#define HOST_RUN (HOST_CALLEE_LR + LONGBYTES) 50/* 51 * r2 is special: it holds 'current', and it made nonvolatile in the 52 * kernel with the -ffixed-r2 gcc option. 53 */ 54#define HOST_R2 (HOST_RUN + LONGBYTES) 55#define HOST_CR (HOST_R2 + LONGBYTES) 56#define HOST_NV_GPRS (HOST_CR + LONGBYTES) 57#define __HOST_NV_GPR(n) (HOST_NV_GPRS + ((n - 14) * LONGBYTES)) 58#define HOST_NV_GPR(n) __HOST_NV_GPR(__REG_##n) 59#define HOST_MIN_STACK_SIZE (HOST_NV_GPR(R31) + LONGBYTES) 60#define HOST_STACK_SIZE ((HOST_MIN_STACK_SIZE + 15) & ~15) /* Align. */ 61/* LR in caller stack frame. */ 62#define HOST_STACK_LR (HOST_STACK_SIZE + PPC_LR_STKOFF) 63 64#define NEED_EMU 0x00000001 /* emulation -- save nv regs */ 65#define NEED_DEAR 0x00000002 /* save faulting DEAR */ 66#define NEED_ESR 0x00000004 /* save faulting ESR */ 67 68/* 69 * On entry: 70 * r4 = vcpu, r5 = srr0, r6 = srr1 71 * saved in vcpu: cr, ctr, r3-r13 72 */ 73.macro kvm_handler_common intno, srr0, flags 74 /* Restore host stack pointer */ 75 PPC_STL r1, VCPU_GPR(R1)(r4) 76 PPC_STL r2, VCPU_GPR(R2)(r4) 77 PPC_LL r1, VCPU_HOST_STACK(r4) 78 PPC_LL r2, HOST_R2(r1) 79 80 mfspr r10, SPRN_PID 81 lwz r8, VCPU_HOST_PID(r4) 82 PPC_LL r11, VCPU_SHARED(r4) 83 PPC_STL r14, VCPU_GPR(R14)(r4) /* We need a non-volatile GPR. */ 84 li r14, \intno 85 86 stw r10, VCPU_GUEST_PID(r4) 87 mtspr SPRN_PID, r8 88 89#ifdef CONFIG_KVM_EXIT_TIMING 90 /* save exit time */ 911: mfspr r7, SPRN_TBRU 92 mfspr r8, SPRN_TBRL 93 mfspr r9, SPRN_TBRU 94 cmpw r9, r7 95 stw r8, VCPU_TIMING_EXIT_TBL(r4) 96 bne- 1b 97 stw r9, VCPU_TIMING_EXIT_TBU(r4) 98#endif 99 100 oris r8, r6, MSR_CE@h 101 PPC_STD(r6, VCPU_SHARED_MSR, r11) 102 ori r8, r8, MSR_ME | MSR_RI 103 PPC_STL r5, VCPU_PC(r4) 104 105 /* 106 * Make sure CE/ME/RI are set (if appropriate for exception type) 107 * whether or not the guest had it set. Since mfmsr/mtmsr are 108 * somewhat expensive, skip in the common case where the guest 109 * had all these bits set (and thus they're still set if 110 * appropriate for the exception type). 111 */ 112 cmpw r6, r8 113 beq 1f 114 mfmsr r7 115 .if \srr0 != SPRN_MCSRR0 && \srr0 != SPRN_CSRR0 116 oris r7, r7, MSR_CE@h 117 .endif 118 .if \srr0 != SPRN_MCSRR0 119 ori r7, r7, MSR_ME | MSR_RI 120 .endif 121 mtmsr r7 1221: 123 124 .if \flags & NEED_EMU 125 /* 126 * This assumes you have external PID support. 127 * To support a bookehv CPU without external PID, you'll 128 * need to look up the TLB entry and create a temporary mapping. 129 * 130 * FIXME: we don't currently handle if the lwepx faults. PR-mode 131 * booke doesn't handle it either. Since Linux doesn't use 132 * broadcast tlbivax anymore, the only way this should happen is 133 * if the guest maps its memory execute-but-not-read, or if we 134 * somehow take a TLB miss in the middle of this entry code and 135 * evict the relevant entry. On e500mc, all kernel lowmem is 136 * bolted into TLB1 large page mappings, and we don't use 137 * broadcast invalidates, so we should not take a TLB miss here. 138 * 139 * Later we'll need to deal with faults here. Disallowing guest 140 * mappings that are execute-but-not-read could be an option on 141 * e500mc, but not on chips with an LRAT if it is used. 142 */ 143 144 mfspr r3, SPRN_EPLC /* will already have correct ELPID and EGS */ 145 PPC_STL r15, VCPU_GPR(R15)(r4) 146 PPC_STL r16, VCPU_GPR(R16)(r4) 147 PPC_STL r17, VCPU_GPR(R17)(r4) 148 PPC_STL r18, VCPU_GPR(R18)(r4) 149 PPC_STL r19, VCPU_GPR(R19)(r4) 150 mr r8, r3 151 PPC_STL r20, VCPU_GPR(R20)(r4) 152 rlwimi r8, r6, EPC_EAS_SHIFT - MSR_IR_LG, EPC_EAS 153 PPC_STL r21, VCPU_GPR(R21)(r4) 154 rlwimi r8, r6, EPC_EPR_SHIFT - MSR_PR_LG, EPC_EPR 155 PPC_STL r22, VCPU_GPR(R22)(r4) 156 rlwimi r8, r10, EPC_EPID_SHIFT, EPC_EPID 157 PPC_STL r23, VCPU_GPR(R23)(r4) 158 PPC_STL r24, VCPU_GPR(R24)(r4) 159 PPC_STL r25, VCPU_GPR(R25)(r4) 160 PPC_STL r26, VCPU_GPR(R26)(r4) 161 PPC_STL r27, VCPU_GPR(R27)(r4) 162 PPC_STL r28, VCPU_GPR(R28)(r4) 163 PPC_STL r29, VCPU_GPR(R29)(r4) 164 PPC_STL r30, VCPU_GPR(R30)(r4) 165 PPC_STL r31, VCPU_GPR(R31)(r4) 166 mtspr SPRN_EPLC, r8 167 168 /* disable preemption, so we are sure we hit the fixup handler */ 169 CURRENT_THREAD_INFO(r8, r1) 170 li r7, 1 171 stw r7, TI_PREEMPT(r8) 172 173 isync 174 175 /* 176 * In case the read goes wrong, we catch it and write an invalid value 177 * in LAST_INST instead. 178 */ 1791: lwepx r9, 0, r5 1802: 181.section .fixup, "ax" 1823: li r9, KVM_INST_FETCH_FAILED 183 b 2b 184.previous 185.section __ex_table,"a" 186 PPC_LONG_ALIGN 187 PPC_LONG 1b,3b 188.previous 189 190 mtspr SPRN_EPLC, r3 191 li r7, 0 192 stw r7, TI_PREEMPT(r8) 193 stw r9, VCPU_LAST_INST(r4) 194 .endif 195 196 .if \flags & NEED_ESR 197 mfspr r8, SPRN_ESR 198 PPC_STL r8, VCPU_FAULT_ESR(r4) 199 .endif 200 201 .if \flags & NEED_DEAR 202 mfspr r9, SPRN_DEAR 203 PPC_STL r9, VCPU_FAULT_DEAR(r4) 204 .endif 205 206 b kvmppc_resume_host 207.endm 208 209#ifdef CONFIG_64BIT 210/* Exception types */ 211#define EX_GEN 1 212#define EX_GDBELL 2 213#define EX_DBG 3 214#define EX_MC 4 215#define EX_CRIT 5 216#define EX_TLB 6 217 218/* 219 * For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h 220 */ 221.macro kvm_handler intno type scratch, paca_ex, ex_r10, ex_r11, srr0, srr1, flags 222 _GLOBAL(kvmppc_handler_\intno\()_\srr1) 223 mr r11, r4 224 /* 225 * Get vcpu from Paca: paca->__current.thread->kvm_vcpu 226 */ 227 PPC_LL r4, PACACURRENT(r13) 228 PPC_LL r4, (THREAD + THREAD_KVM_VCPU)(r4) 229 stw r10, VCPU_CR(r4) 230 PPC_STL r11, VCPU_GPR(R4)(r4) 231 PPC_STL r5, VCPU_GPR(R5)(r4) 232 PPC_STL r6, VCPU_GPR(R6)(r4) 233 PPC_STL r8, VCPU_GPR(R8)(r4) 234 PPC_STL r9, VCPU_GPR(R9)(r4) 235 .if \type == EX_TLB 236 PPC_LL r5, EX_TLB_R13(r12) 237 PPC_LL r6, EX_TLB_R10(r12) 238 PPC_LL r8, EX_TLB_R11(r12) 239 mfspr r12, \scratch 240 .else 241 mfspr r5, \scratch 242 PPC_LL r6, (\paca_ex + \ex_r10)(r13) 243 PPC_LL r8, (\paca_ex + \ex_r11)(r13) 244 .endif 245 PPC_STL r5, VCPU_GPR(R13)(r4) 246 PPC_STL r3, VCPU_GPR(R3)(r4) 247 PPC_STL r7, VCPU_GPR(R7)(r4) 248 PPC_STL r12, VCPU_GPR(R12)(r4) 249 PPC_STL r6, VCPU_GPR(R10)(r4) 250 PPC_STL r8, VCPU_GPR(R11)(r4) 251 mfctr r5 252 PPC_STL r5, VCPU_CTR(r4) 253 mfspr r5, \srr0 254 mfspr r6, \srr1 255 kvm_handler_common \intno, \srr0, \flags 256.endm 257 258#define EX_PARAMS(type) \ 259 EX_##type, \ 260 SPRN_SPRG_##type##_SCRATCH, \ 261 PACA_EX##type, \ 262 EX_R10, \ 263 EX_R11 264 265#define EX_PARAMS_TLB \ 266 EX_TLB, \ 267 SPRN_SPRG_GEN_SCRATCH, \ 268 PACA_EXTLB, \ 269 EX_TLB_R10, \ 270 EX_TLB_R11 271 272kvm_handler BOOKE_INTERRUPT_CRITICAL, EX_PARAMS(CRIT), \ 273 SPRN_CSRR0, SPRN_CSRR1, 0 274kvm_handler BOOKE_INTERRUPT_MACHINE_CHECK, EX_PARAMS(MC), \ 275 SPRN_MCSRR0, SPRN_MCSRR1, 0 276kvm_handler BOOKE_INTERRUPT_DATA_STORAGE, EX_PARAMS(GEN), \ 277 SPRN_SRR0, SPRN_SRR1,(NEED_EMU | NEED_DEAR | NEED_ESR) 278kvm_handler BOOKE_INTERRUPT_INST_STORAGE, EX_PARAMS(GEN), \ 279 SPRN_SRR0, SPRN_SRR1, NEED_ESR 280kvm_handler BOOKE_INTERRUPT_EXTERNAL, EX_PARAMS(GEN), \ 281 SPRN_SRR0, SPRN_SRR1, 0 282kvm_handler BOOKE_INTERRUPT_ALIGNMENT, EX_PARAMS(GEN), \ 283 SPRN_SRR0, SPRN_SRR1,(NEED_DEAR | NEED_ESR) 284kvm_handler BOOKE_INTERRUPT_PROGRAM, EX_PARAMS(GEN), \ 285 SPRN_SRR0, SPRN_SRR1,NEED_ESR 286kvm_handler BOOKE_INTERRUPT_FP_UNAVAIL, EX_PARAMS(GEN), \ 287 SPRN_SRR0, SPRN_SRR1, 0 288kvm_handler BOOKE_INTERRUPT_AP_UNAVAIL, EX_PARAMS(GEN), \ 289 SPRN_SRR0, SPRN_SRR1, 0 290kvm_handler BOOKE_INTERRUPT_DECREMENTER, EX_PARAMS(GEN), \ 291 SPRN_SRR0, SPRN_SRR1, 0 292kvm_handler BOOKE_INTERRUPT_FIT, EX_PARAMS(GEN), \ 293 SPRN_SRR0, SPRN_SRR1, 0 294kvm_handler BOOKE_INTERRUPT_WATCHDOG, EX_PARAMS(CRIT),\ 295 SPRN_CSRR0, SPRN_CSRR1, 0 296/* 297 * Only bolted TLB miss exception handlers are supported for now 298 */ 299kvm_handler BOOKE_INTERRUPT_DTLB_MISS, EX_PARAMS_TLB, \ 300 SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR) 301kvm_handler BOOKE_INTERRUPT_ITLB_MISS, EX_PARAMS_TLB, \ 302 SPRN_SRR0, SPRN_SRR1, 0 303kvm_handler BOOKE_INTERRUPT_SPE_UNAVAIL, EX_PARAMS(GEN), \ 304 SPRN_SRR0, SPRN_SRR1, 0 305kvm_handler BOOKE_INTERRUPT_SPE_FP_DATA, EX_PARAMS(GEN), \ 306 SPRN_SRR0, SPRN_SRR1, 0 307kvm_handler BOOKE_INTERRUPT_SPE_FP_ROUND, EX_PARAMS(GEN), \ 308 SPRN_SRR0, SPRN_SRR1, 0 309kvm_handler BOOKE_INTERRUPT_PERFORMANCE_MONITOR, EX_PARAMS(GEN), \ 310 SPRN_SRR0, SPRN_SRR1, 0 311kvm_handler BOOKE_INTERRUPT_DOORBELL, EX_PARAMS(GEN), \ 312 SPRN_SRR0, SPRN_SRR1, 0 313kvm_handler BOOKE_INTERRUPT_DOORBELL_CRITICAL, EX_PARAMS(CRIT), \ 314 SPRN_CSRR0, SPRN_CSRR1, 0 315kvm_handler BOOKE_INTERRUPT_HV_PRIV, EX_PARAMS(GEN), \ 316 SPRN_SRR0, SPRN_SRR1, NEED_EMU 317kvm_handler BOOKE_INTERRUPT_HV_SYSCALL, EX_PARAMS(GEN), \ 318 SPRN_SRR0, SPRN_SRR1, 0 319kvm_handler BOOKE_INTERRUPT_GUEST_DBELL, EX_PARAMS(GDBELL), \ 320 SPRN_GSRR0, SPRN_GSRR1, 0 321kvm_handler BOOKE_INTERRUPT_GUEST_DBELL_CRIT, EX_PARAMS(CRIT), \ 322 SPRN_CSRR0, SPRN_CSRR1, 0 323kvm_handler BOOKE_INTERRUPT_DEBUG, EX_PARAMS(DBG), \ 324 SPRN_DSRR0, SPRN_DSRR1, 0 325kvm_handler BOOKE_INTERRUPT_DEBUG, EX_PARAMS(CRIT), \ 326 SPRN_CSRR0, SPRN_CSRR1, 0 327kvm_handler BOOKE_INTERRUPT_LRAT_ERROR, EX_PARAMS(GEN), \ 328 SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR) 329#else 330/* 331 * For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h 332 */ 333.macro kvm_handler intno srr0, srr1, flags 334_GLOBAL(kvmppc_handler_\intno\()_\srr1) 335 PPC_LL r11, THREAD_KVM_VCPU(r10) 336 PPC_STL r3, VCPU_GPR(R3)(r11) 337 mfspr r3, SPRN_SPRG_RSCRATCH0 338 PPC_STL r4, VCPU_GPR(R4)(r11) 339 PPC_LL r4, THREAD_NORMSAVE(0)(r10) 340 PPC_STL r5, VCPU_GPR(R5)(r11) 341 stw r13, VCPU_CR(r11) 342 mfspr r5, \srr0 343 PPC_STL r3, VCPU_GPR(R10)(r11) 344 PPC_LL r3, THREAD_NORMSAVE(2)(r10) 345 PPC_STL r6, VCPU_GPR(R6)(r11) 346 PPC_STL r4, VCPU_GPR(R11)(r11) 347 mfspr r6, \srr1 348 PPC_STL r7, VCPU_GPR(R7)(r11) 349 PPC_STL r8, VCPU_GPR(R8)(r11) 350 PPC_STL r9, VCPU_GPR(R9)(r11) 351 PPC_STL r3, VCPU_GPR(R13)(r11) 352 mfctr r7 353 PPC_STL r12, VCPU_GPR(R12)(r11) 354 PPC_STL r7, VCPU_CTR(r11) 355 mr r4, r11 356 kvm_handler_common \intno, \srr0, \flags 357.endm 358 359.macro kvm_lvl_handler intno scratch srr0, srr1, flags 360_GLOBAL(kvmppc_handler_\intno\()_\srr1) 361 mfspr r10, SPRN_SPRG_THREAD 362 PPC_LL r11, THREAD_KVM_VCPU(r10) 363 PPC_STL r3, VCPU_GPR(R3)(r11) 364 mfspr r3, \scratch 365 PPC_STL r4, VCPU_GPR(R4)(r11) 366 PPC_LL r4, GPR9(r8) 367 PPC_STL r5, VCPU_GPR(R5)(r11) 368 stw r9, VCPU_CR(r11) 369 mfspr r5, \srr0 370 PPC_STL r3, VCPU_GPR(R8)(r11) 371 PPC_LL r3, GPR10(r8) 372 PPC_STL r6, VCPU_GPR(R6)(r11) 373 PPC_STL r4, VCPU_GPR(R9)(r11) 374 mfspr r6, \srr1 375 PPC_LL r4, GPR11(r8) 376 PPC_STL r7, VCPU_GPR(R7)(r11) 377 PPC_STL r3, VCPU_GPR(R10)(r11) 378 mfctr r7 379 PPC_STL r12, VCPU_GPR(R12)(r11) 380 PPC_STL r13, VCPU_GPR(R13)(r11) 381 PPC_STL r4, VCPU_GPR(R11)(r11) 382 PPC_STL r7, VCPU_CTR(r11) 383 mr r4, r11 384 kvm_handler_common \intno, \srr0, \flags 385.endm 386 387kvm_lvl_handler BOOKE_INTERRUPT_CRITICAL, \ 388 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0 389kvm_lvl_handler BOOKE_INTERRUPT_MACHINE_CHECK, \ 390 SPRN_SPRG_RSCRATCH_MC, SPRN_MCSRR0, SPRN_MCSRR1, 0 391kvm_handler BOOKE_INTERRUPT_DATA_STORAGE, \ 392 SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR) 393kvm_handler BOOKE_INTERRUPT_INST_STORAGE, SPRN_SRR0, SPRN_SRR1, NEED_ESR 394kvm_handler BOOKE_INTERRUPT_EXTERNAL, SPRN_SRR0, SPRN_SRR1, 0 395kvm_handler BOOKE_INTERRUPT_ALIGNMENT, \ 396 SPRN_SRR0, SPRN_SRR1, (NEED_DEAR | NEED_ESR) 397kvm_handler BOOKE_INTERRUPT_PROGRAM, SPRN_SRR0, SPRN_SRR1, NEED_ESR 398kvm_handler BOOKE_INTERRUPT_FP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0 399kvm_handler BOOKE_INTERRUPT_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0 400kvm_handler BOOKE_INTERRUPT_AP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0 401kvm_handler BOOKE_INTERRUPT_DECREMENTER, SPRN_SRR0, SPRN_SRR1, 0 402kvm_handler BOOKE_INTERRUPT_FIT, SPRN_SRR0, SPRN_SRR1, 0 403kvm_lvl_handler BOOKE_INTERRUPT_WATCHDOG, \ 404 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0 405kvm_handler BOOKE_INTERRUPT_DTLB_MISS, \ 406 SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR) 407kvm_handler BOOKE_INTERRUPT_ITLB_MISS, SPRN_SRR0, SPRN_SRR1, 0 408kvm_handler BOOKE_INTERRUPT_SPE_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0 409kvm_handler BOOKE_INTERRUPT_SPE_FP_DATA, SPRN_SRR0, SPRN_SRR1, 0 410kvm_handler BOOKE_INTERRUPT_SPE_FP_ROUND, SPRN_SRR0, SPRN_SRR1, 0 411kvm_handler BOOKE_INTERRUPT_PERFORMANCE_MONITOR, SPRN_SRR0, SPRN_SRR1, 0 412kvm_handler BOOKE_INTERRUPT_DOORBELL, SPRN_SRR0, SPRN_SRR1, 0 413kvm_lvl_handler BOOKE_INTERRUPT_DOORBELL_CRITICAL, \ 414 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0 415kvm_handler BOOKE_INTERRUPT_HV_PRIV, SPRN_SRR0, SPRN_SRR1, NEED_EMU 416kvm_handler BOOKE_INTERRUPT_HV_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0 417kvm_handler BOOKE_INTERRUPT_GUEST_DBELL, SPRN_GSRR0, SPRN_GSRR1, 0 418kvm_lvl_handler BOOKE_INTERRUPT_GUEST_DBELL_CRIT, \ 419 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0 420kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \ 421 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0 422kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \ 423 SPRN_SPRG_RSCRATCH_DBG, SPRN_DSRR0, SPRN_DSRR1, 0 424#endif 425 426/* Registers: 427 * SPRG_SCRATCH0: guest r10 428 * r4: vcpu pointer 429 * r11: vcpu->arch.shared 430 * r14: KVM exit number 431 */ 432_GLOBAL(kvmppc_resume_host) 433 /* Save remaining volatile guest register state to vcpu. */ 434 mfspr r3, SPRN_VRSAVE 435 PPC_STL r0, VCPU_GPR(R0)(r4) 436 mflr r5 437 mfspr r6, SPRN_SPRG4 438 PPC_STL r5, VCPU_LR(r4) 439 mfspr r7, SPRN_SPRG5 440 stw r3, VCPU_VRSAVE(r4) 441#ifdef CONFIG_64BIT 442 PPC_LL r3, PACA_SPRG_VDSO(r13) 443#endif 444 PPC_STD(r6, VCPU_SHARED_SPRG4, r11) 445 mfspr r8, SPRN_SPRG6 446 PPC_STD(r7, VCPU_SHARED_SPRG5, r11) 447 mfspr r9, SPRN_SPRG7 448#ifdef CONFIG_64BIT 449 mtspr SPRN_SPRG_VDSO_WRITE, r3 450#endif 451 PPC_STD(r8, VCPU_SHARED_SPRG6, r11) 452 mfxer r3 453 PPC_STD(r9, VCPU_SHARED_SPRG7, r11) 454 455 /* save guest MAS registers and restore host mas4 & mas6 */ 456 mfspr r5, SPRN_MAS0 457 PPC_STL r3, VCPU_XER(r4) 458 mfspr r6, SPRN_MAS1 459 stw r5, VCPU_SHARED_MAS0(r11) 460 mfspr r7, SPRN_MAS2 461 stw r6, VCPU_SHARED_MAS1(r11) 462 PPC_STD(r7, VCPU_SHARED_MAS2, r11) 463 mfspr r5, SPRN_MAS3 464 mfspr r6, SPRN_MAS4 465 stw r5, VCPU_SHARED_MAS7_3+4(r11) 466 mfspr r7, SPRN_MAS6 467 stw r6, VCPU_SHARED_MAS4(r11) 468 mfspr r5, SPRN_MAS7 469 lwz r6, VCPU_HOST_MAS4(r4) 470 stw r7, VCPU_SHARED_MAS6(r11) 471 lwz r8, VCPU_HOST_MAS6(r4) 472 mtspr SPRN_MAS4, r6 473 stw r5, VCPU_SHARED_MAS7_3+0(r11) 474 mtspr SPRN_MAS6, r8 475 /* Enable MAS register updates via exception */ 476 mfspr r3, SPRN_EPCR 477 rlwinm r3, r3, 0, ~SPRN_EPCR_DMIUH 478 mtspr SPRN_EPCR, r3 479 isync 480 481#ifdef CONFIG_64BIT 482 /* 483 * We enter with interrupts disabled in hardware, but 484 * we need to call RECONCILE_IRQ_STATE to ensure 485 * that the software state is kept in sync. 486 */ 487 RECONCILE_IRQ_STATE(r3,r5) 488#endif 489 490 /* Switch to kernel stack and jump to handler. */ 491 PPC_LL r3, HOST_RUN(r1) 492 mr r5, r14 /* intno */ 493 mr r14, r4 /* Save vcpu pointer. */ 494 bl kvmppc_handle_exit 495 496 /* Restore vcpu pointer and the nonvolatiles we used. */ 497 mr r4, r14 498 PPC_LL r14, VCPU_GPR(R14)(r4) 499 500 andi. r5, r3, RESUME_FLAG_NV 501 beq skip_nv_load 502 PPC_LL r15, VCPU_GPR(R15)(r4) 503 PPC_LL r16, VCPU_GPR(R16)(r4) 504 PPC_LL r17, VCPU_GPR(R17)(r4) 505 PPC_LL r18, VCPU_GPR(R18)(r4) 506 PPC_LL r19, VCPU_GPR(R19)(r4) 507 PPC_LL r20, VCPU_GPR(R20)(r4) 508 PPC_LL r21, VCPU_GPR(R21)(r4) 509 PPC_LL r22, VCPU_GPR(R22)(r4) 510 PPC_LL r23, VCPU_GPR(R23)(r4) 511 PPC_LL r24, VCPU_GPR(R24)(r4) 512 PPC_LL r25, VCPU_GPR(R25)(r4) 513 PPC_LL r26, VCPU_GPR(R26)(r4) 514 PPC_LL r27, VCPU_GPR(R27)(r4) 515 PPC_LL r28, VCPU_GPR(R28)(r4) 516 PPC_LL r29, VCPU_GPR(R29)(r4) 517 PPC_LL r30, VCPU_GPR(R30)(r4) 518 PPC_LL r31, VCPU_GPR(R31)(r4) 519skip_nv_load: 520 /* Should we return to the guest? */ 521 andi. r5, r3, RESUME_FLAG_HOST 522 beq lightweight_exit 523 524 srawi r3, r3, 2 /* Shift -ERR back down. */ 525 526heavyweight_exit: 527 /* Not returning to guest. */ 528 PPC_LL r5, HOST_STACK_LR(r1) 529 lwz r6, HOST_CR(r1) 530 531 /* 532 * We already saved guest volatile register state; now save the 533 * non-volatiles. 534 */ 535 536 PPC_STL r15, VCPU_GPR(R15)(r4) 537 PPC_STL r16, VCPU_GPR(R16)(r4) 538 PPC_STL r17, VCPU_GPR(R17)(r4) 539 PPC_STL r18, VCPU_GPR(R18)(r4) 540 PPC_STL r19, VCPU_GPR(R19)(r4) 541 PPC_STL r20, VCPU_GPR(R20)(r4) 542 PPC_STL r21, VCPU_GPR(R21)(r4) 543 PPC_STL r22, VCPU_GPR(R22)(r4) 544 PPC_STL r23, VCPU_GPR(R23)(r4) 545 PPC_STL r24, VCPU_GPR(R24)(r4) 546 PPC_STL r25, VCPU_GPR(R25)(r4) 547 PPC_STL r26, VCPU_GPR(R26)(r4) 548 PPC_STL r27, VCPU_GPR(R27)(r4) 549 PPC_STL r28, VCPU_GPR(R28)(r4) 550 PPC_STL r29, VCPU_GPR(R29)(r4) 551 PPC_STL r30, VCPU_GPR(R30)(r4) 552 PPC_STL r31, VCPU_GPR(R31)(r4) 553 554 /* Load host non-volatile register state from host stack. */ 555 PPC_LL r14, HOST_NV_GPR(R14)(r1) 556 PPC_LL r15, HOST_NV_GPR(R15)(r1) 557 PPC_LL r16, HOST_NV_GPR(R16)(r1) 558 PPC_LL r17, HOST_NV_GPR(R17)(r1) 559 PPC_LL r18, HOST_NV_GPR(R18)(r1) 560 PPC_LL r19, HOST_NV_GPR(R19)(r1) 561 PPC_LL r20, HOST_NV_GPR(R20)(r1) 562 PPC_LL r21, HOST_NV_GPR(R21)(r1) 563 PPC_LL r22, HOST_NV_GPR(R22)(r1) 564 PPC_LL r23, HOST_NV_GPR(R23)(r1) 565 PPC_LL r24, HOST_NV_GPR(R24)(r1) 566 PPC_LL r25, HOST_NV_GPR(R25)(r1) 567 PPC_LL r26, HOST_NV_GPR(R26)(r1) 568 PPC_LL r27, HOST_NV_GPR(R27)(r1) 569 PPC_LL r28, HOST_NV_GPR(R28)(r1) 570 PPC_LL r29, HOST_NV_GPR(R29)(r1) 571 PPC_LL r30, HOST_NV_GPR(R30)(r1) 572 PPC_LL r31, HOST_NV_GPR(R31)(r1) 573 574 /* Return to kvm_vcpu_run(). */ 575 mtlr r5 576 mtcr r6 577 addi r1, r1, HOST_STACK_SIZE 578 /* r3 still contains the return code from kvmppc_handle_exit(). */ 579 blr 580 581/* Registers: 582 * r3: kvm_run pointer 583 * r4: vcpu pointer 584 */ 585_GLOBAL(__kvmppc_vcpu_run) 586 stwu r1, -HOST_STACK_SIZE(r1) 587 PPC_STL r1, VCPU_HOST_STACK(r4) /* Save stack pointer to vcpu. */ 588 589 /* Save host state to stack. */ 590 PPC_STL r3, HOST_RUN(r1) 591 mflr r3 592 mfcr r5 593 PPC_STL r3, HOST_STACK_LR(r1) 594 595 stw r5, HOST_CR(r1) 596 597 /* Save host non-volatile register state to stack. */ 598 PPC_STL r14, HOST_NV_GPR(R14)(r1) 599 PPC_STL r15, HOST_NV_GPR(R15)(r1) 600 PPC_STL r16, HOST_NV_GPR(R16)(r1) 601 PPC_STL r17, HOST_NV_GPR(R17)(r1) 602 PPC_STL r18, HOST_NV_GPR(R18)(r1) 603 PPC_STL r19, HOST_NV_GPR(R19)(r1) 604 PPC_STL r20, HOST_NV_GPR(R20)(r1) 605 PPC_STL r21, HOST_NV_GPR(R21)(r1) 606 PPC_STL r22, HOST_NV_GPR(R22)(r1) 607 PPC_STL r23, HOST_NV_GPR(R23)(r1) 608 PPC_STL r24, HOST_NV_GPR(R24)(r1) 609 PPC_STL r25, HOST_NV_GPR(R25)(r1) 610 PPC_STL r26, HOST_NV_GPR(R26)(r1) 611 PPC_STL r27, HOST_NV_GPR(R27)(r1) 612 PPC_STL r28, HOST_NV_GPR(R28)(r1) 613 PPC_STL r29, HOST_NV_GPR(R29)(r1) 614 PPC_STL r30, HOST_NV_GPR(R30)(r1) 615 PPC_STL r31, HOST_NV_GPR(R31)(r1) 616 617 /* Load guest non-volatiles. */ 618 PPC_LL r14, VCPU_GPR(R14)(r4) 619 PPC_LL r15, VCPU_GPR(R15)(r4) 620 PPC_LL r16, VCPU_GPR(R16)(r4) 621 PPC_LL r17, VCPU_GPR(R17)(r4) 622 PPC_LL r18, VCPU_GPR(R18)(r4) 623 PPC_LL r19, VCPU_GPR(R19)(r4) 624 PPC_LL r20, VCPU_GPR(R20)(r4) 625 PPC_LL r21, VCPU_GPR(R21)(r4) 626 PPC_LL r22, VCPU_GPR(R22)(r4) 627 PPC_LL r23, VCPU_GPR(R23)(r4) 628 PPC_LL r24, VCPU_GPR(R24)(r4) 629 PPC_LL r25, VCPU_GPR(R25)(r4) 630 PPC_LL r26, VCPU_GPR(R26)(r4) 631 PPC_LL r27, VCPU_GPR(R27)(r4) 632 PPC_LL r28, VCPU_GPR(R28)(r4) 633 PPC_LL r29, VCPU_GPR(R29)(r4) 634 PPC_LL r30, VCPU_GPR(R30)(r4) 635 PPC_LL r31, VCPU_GPR(R31)(r4) 636 637 638lightweight_exit: 639 PPC_STL r2, HOST_R2(r1) 640 641 mfspr r3, SPRN_PID 642 stw r3, VCPU_HOST_PID(r4) 643 lwz r3, VCPU_GUEST_PID(r4) 644 mtspr SPRN_PID, r3 645 646 PPC_LL r11, VCPU_SHARED(r4) 647 /* Disable MAS register updates via exception */ 648 mfspr r3, SPRN_EPCR 649 oris r3, r3, SPRN_EPCR_DMIUH@h 650 mtspr SPRN_EPCR, r3 651 isync 652 /* Save host mas4 and mas6 and load guest MAS registers */ 653 mfspr r3, SPRN_MAS4 654 stw r3, VCPU_HOST_MAS4(r4) 655 mfspr r3, SPRN_MAS6 656 stw r3, VCPU_HOST_MAS6(r4) 657 lwz r3, VCPU_SHARED_MAS0(r11) 658 lwz r5, VCPU_SHARED_MAS1(r11) 659 PPC_LD(r6, VCPU_SHARED_MAS2, r11) 660 lwz r7, VCPU_SHARED_MAS7_3+4(r11) 661 lwz r8, VCPU_SHARED_MAS4(r11) 662 mtspr SPRN_MAS0, r3 663 mtspr SPRN_MAS1, r5 664 mtspr SPRN_MAS2, r6 665 mtspr SPRN_MAS3, r7 666 mtspr SPRN_MAS4, r8 667 lwz r3, VCPU_SHARED_MAS6(r11) 668 lwz r5, VCPU_SHARED_MAS7_3+0(r11) 669 mtspr SPRN_MAS6, r3 670 mtspr SPRN_MAS7, r5 671 672 /* 673 * Host interrupt handlers may have clobbered these guest-readable 674 * SPRGs, so we need to reload them here with the guest's values. 675 */ 676 lwz r3, VCPU_VRSAVE(r4) 677 PPC_LD(r5, VCPU_SHARED_SPRG4, r11) 678 mtspr SPRN_VRSAVE, r3 679 PPC_LD(r6, VCPU_SHARED_SPRG5, r11) 680 mtspr SPRN_SPRG4W, r5 681 PPC_LD(r7, VCPU_SHARED_SPRG6, r11) 682 mtspr SPRN_SPRG5W, r6 683 PPC_LD(r8, VCPU_SHARED_SPRG7, r11) 684 mtspr SPRN_SPRG6W, r7 685 mtspr SPRN_SPRG7W, r8 686 687 /* Load some guest volatiles. */ 688 PPC_LL r3, VCPU_LR(r4) 689 PPC_LL r5, VCPU_XER(r4) 690 PPC_LL r6, VCPU_CTR(r4) 691 lwz r7, VCPU_CR(r4) 692 PPC_LL r8, VCPU_PC(r4) 693 PPC_LD(r9, VCPU_SHARED_MSR, r11) 694 PPC_LL r0, VCPU_GPR(R0)(r4) 695 PPC_LL r1, VCPU_GPR(R1)(r4) 696 PPC_LL r2, VCPU_GPR(R2)(r4) 697 PPC_LL r10, VCPU_GPR(R10)(r4) 698 PPC_LL r11, VCPU_GPR(R11)(r4) 699 PPC_LL r12, VCPU_GPR(R12)(r4) 700 PPC_LL r13, VCPU_GPR(R13)(r4) 701 mtlr r3 702 mtxer r5 703 mtctr r6 704 mtsrr0 r8 705 mtsrr1 r9 706 707#ifdef CONFIG_KVM_EXIT_TIMING 708 /* save enter time */ 7091: 710 mfspr r6, SPRN_TBRU 711 mfspr r9, SPRN_TBRL 712 mfspr r8, SPRN_TBRU 713 cmpw r8, r6 714 stw r9, VCPU_TIMING_LAST_ENTER_TBL(r4) 715 bne 1b 716 stw r8, VCPU_TIMING_LAST_ENTER_TBU(r4) 717#endif 718 719 /* 720 * Don't execute any instruction which can change CR after 721 * below instruction. 722 */ 723 mtcr r7 724 725 /* Finish loading guest volatiles and jump to guest. */ 726 PPC_LL r5, VCPU_GPR(R5)(r4) 727 PPC_LL r6, VCPU_GPR(R6)(r4) 728 PPC_LL r7, VCPU_GPR(R7)(r4) 729 PPC_LL r8, VCPU_GPR(R8)(r4) 730 PPC_LL r9, VCPU_GPR(R9)(r4) 731 732 PPC_LL r3, VCPU_GPR(R3)(r4) 733 PPC_LL r4, VCPU_GPR(R4)(r4) 734 rfi 735