1/* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License, version 2, as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, write to the Free Software 13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 14 * 15 * Copyright IBM Corp. 2007 16 * Copyright 2011 Freescale Semiconductor, Inc. 17 * 18 * Authors: Hollis Blanchard <hollisb@us.ibm.com> 19 */ 20 21#include <asm/ppc_asm.h> 22#include <asm/kvm_asm.h> 23#include <asm/reg.h> 24#include <asm/mmu-44x.h> 25#include <asm/page.h> 26#include <asm/asm-offsets.h> 27 28/* The host stack layout: */ 29#define HOST_R1 0 /* Implied by stwu. */ 30#define HOST_CALLEE_LR 4 31#define HOST_RUN 8 32/* r2 is special: it holds 'current', and it made nonvolatile in the 33 * kernel with the -ffixed-r2 gcc option. */ 34#define HOST_R2 12 35#define HOST_CR 16 36#define HOST_NV_GPRS 20 37#define __HOST_NV_GPR(n) (HOST_NV_GPRS + ((n - 14) * 4)) 38#define HOST_NV_GPR(n) __HOST_NV_GPR(__REG_##n) 39#define HOST_MIN_STACK_SIZE (HOST_NV_GPR(R31) + 4) 40#define HOST_STACK_SIZE (((HOST_MIN_STACK_SIZE + 15) / 16) * 16) /* Align. */ 41#define HOST_STACK_LR (HOST_STACK_SIZE + 4) /* In caller stack frame. */ 42 43#define NEED_INST_MASK ((1<<BOOKE_INTERRUPT_PROGRAM) | \ 44 (1<<BOOKE_INTERRUPT_DTLB_MISS) | \ 45 (1<<BOOKE_INTERRUPT_DEBUG)) 46 47#define NEED_DEAR_MASK ((1<<BOOKE_INTERRUPT_DATA_STORAGE) | \ 48 (1<<BOOKE_INTERRUPT_DTLB_MISS)) 49 50#define NEED_ESR_MASK ((1<<BOOKE_INTERRUPT_DATA_STORAGE) | \ 51 (1<<BOOKE_INTERRUPT_INST_STORAGE) | \ 52 (1<<BOOKE_INTERRUPT_PROGRAM) | \ 53 (1<<BOOKE_INTERRUPT_DTLB_MISS)) 54 55.macro KVM_HANDLER ivor_nr scratch srr0 56_GLOBAL(kvmppc_handler_\ivor_nr) 57 /* Get pointer to vcpu and record exit number. */ 58 mtspr \scratch , r4 59 mfspr r4, SPRN_SPRG_RVCPU 60 stw r3, VCPU_GPR(R3)(r4) 61 stw r5, VCPU_GPR(R5)(r4) 62 stw r6, VCPU_GPR(R6)(r4) 63 mfspr r3, \scratch 64 mfctr r5 65 stw r3, VCPU_GPR(R4)(r4) 66 stw r5, VCPU_CTR(r4) 67 mfspr r3, \srr0 68 lis r6, kvmppc_resume_host@h 69 stw r3, VCPU_PC(r4) 70 li r5, \ivor_nr 71 ori r6, r6, kvmppc_resume_host@l 72 mtctr r6 73 bctr 74.endm 75 76_GLOBAL(kvmppc_handlers_start) 77KVM_HANDLER BOOKE_INTERRUPT_CRITICAL SPRN_SPRG_RSCRATCH_CRIT SPRN_CSRR0 78KVM_HANDLER BOOKE_INTERRUPT_MACHINE_CHECK SPRN_SPRG_RSCRATCH_MC SPRN_MCSRR0 79KVM_HANDLER BOOKE_INTERRUPT_DATA_STORAGE SPRN_SPRG_RSCRATCH0 SPRN_SRR0 80KVM_HANDLER BOOKE_INTERRUPT_INST_STORAGE SPRN_SPRG_RSCRATCH0 SPRN_SRR0 81KVM_HANDLER BOOKE_INTERRUPT_EXTERNAL SPRN_SPRG_RSCRATCH0 SPRN_SRR0 82KVM_HANDLER BOOKE_INTERRUPT_ALIGNMENT SPRN_SPRG_RSCRATCH0 SPRN_SRR0 83KVM_HANDLER BOOKE_INTERRUPT_PROGRAM SPRN_SPRG_RSCRATCH0 SPRN_SRR0 84KVM_HANDLER BOOKE_INTERRUPT_FP_UNAVAIL SPRN_SPRG_RSCRATCH0 SPRN_SRR0 85KVM_HANDLER BOOKE_INTERRUPT_SYSCALL SPRN_SPRG_RSCRATCH0 SPRN_SRR0 86KVM_HANDLER BOOKE_INTERRUPT_AP_UNAVAIL SPRN_SPRG_RSCRATCH0 SPRN_SRR0 87KVM_HANDLER BOOKE_INTERRUPT_DECREMENTER SPRN_SPRG_RSCRATCH0 SPRN_SRR0 88KVM_HANDLER BOOKE_INTERRUPT_FIT SPRN_SPRG_RSCRATCH0 SPRN_SRR0 89KVM_HANDLER BOOKE_INTERRUPT_WATCHDOG SPRN_SPRG_RSCRATCH_CRIT SPRN_CSRR0 90KVM_HANDLER BOOKE_INTERRUPT_DTLB_MISS SPRN_SPRG_RSCRATCH0 SPRN_SRR0 91KVM_HANDLER BOOKE_INTERRUPT_ITLB_MISS SPRN_SPRG_RSCRATCH0 SPRN_SRR0 92KVM_HANDLER BOOKE_INTERRUPT_DEBUG SPRN_SPRG_RSCRATCH_CRIT SPRN_CSRR0 93KVM_HANDLER BOOKE_INTERRUPT_SPE_UNAVAIL SPRN_SPRG_RSCRATCH0 SPRN_SRR0 94KVM_HANDLER BOOKE_INTERRUPT_SPE_FP_DATA SPRN_SPRG_RSCRATCH0 SPRN_SRR0 95KVM_HANDLER BOOKE_INTERRUPT_SPE_FP_ROUND SPRN_SPRG_RSCRATCH0 SPRN_SRR0 96 97_GLOBAL(kvmppc_handler_len) 98 .long kvmppc_handler_1 - kvmppc_handler_0 99 100/* Registers: 101 * SPRG_SCRATCH0: guest r4 102 * r4: vcpu pointer 103 * r5: KVM exit number 104 */ 105_GLOBAL(kvmppc_resume_host) 106 mfcr r3 107 stw r3, VCPU_CR(r4) 108 stw r7, VCPU_GPR(R7)(r4) 109 stw r8, VCPU_GPR(R8)(r4) 110 stw r9, VCPU_GPR(R9)(r4) 111 112 li r6, 1 113 slw r6, r6, r5 114 115#ifdef CONFIG_KVM_EXIT_TIMING 116 /* save exit time */ 1171: 118 mfspr r7, SPRN_TBRU 119 mfspr r8, SPRN_TBRL 120 mfspr r9, SPRN_TBRU 121 cmpw r9, r7 122 bne 1b 123 stw r8, VCPU_TIMING_EXIT_TBL(r4) 124 stw r9, VCPU_TIMING_EXIT_TBU(r4) 125#endif 126 127 /* Save the faulting instruction and all GPRs for emulation. */ 128 andi. r7, r6, NEED_INST_MASK 129 beq ..skip_inst_copy 130 mfspr r9, SPRN_SRR0 131 mfmsr r8 132 ori r7, r8, MSR_DS 133 mtmsr r7 134 isync 135 lwz r9, 0(r9) 136 mtmsr r8 137 isync 138 stw r9, VCPU_LAST_INST(r4) 139 140 stw r15, VCPU_GPR(R15)(r4) 141 stw r16, VCPU_GPR(R16)(r4) 142 stw r17, VCPU_GPR(R17)(r4) 143 stw r18, VCPU_GPR(R18)(r4) 144 stw r19, VCPU_GPR(R19)(r4) 145 stw r20, VCPU_GPR(R20)(r4) 146 stw r21, VCPU_GPR(R21)(r4) 147 stw r22, VCPU_GPR(R22)(r4) 148 stw r23, VCPU_GPR(R23)(r4) 149 stw r24, VCPU_GPR(R24)(r4) 150 stw r25, VCPU_GPR(R25)(r4) 151 stw r26, VCPU_GPR(R26)(r4) 152 stw r27, VCPU_GPR(R27)(r4) 153 stw r28, VCPU_GPR(R28)(r4) 154 stw r29, VCPU_GPR(R29)(r4) 155 stw r30, VCPU_GPR(R30)(r4) 156 stw r31, VCPU_GPR(R31)(r4) 157..skip_inst_copy: 158 159 /* Also grab DEAR and ESR before the host can clobber them. */ 160 161 andi. r7, r6, NEED_DEAR_MASK 162 beq ..skip_dear 163 mfspr r9, SPRN_DEAR 164 stw r9, VCPU_FAULT_DEAR(r4) 165..skip_dear: 166 167 andi. r7, r6, NEED_ESR_MASK 168 beq ..skip_esr 169 mfspr r9, SPRN_ESR 170 stw r9, VCPU_FAULT_ESR(r4) 171..skip_esr: 172 173 /* Save remaining volatile guest register state to vcpu. */ 174 stw r0, VCPU_GPR(R0)(r4) 175 stw r1, VCPU_GPR(R1)(r4) 176 stw r2, VCPU_GPR(R2)(r4) 177 stw r10, VCPU_GPR(R10)(r4) 178 stw r11, VCPU_GPR(R11)(r4) 179 stw r12, VCPU_GPR(R12)(r4) 180 stw r13, VCPU_GPR(R13)(r4) 181 stw r14, VCPU_GPR(R14)(r4) /* We need a NV GPR below. */ 182 mflr r3 183 stw r3, VCPU_LR(r4) 184 mfxer r3 185 stw r3, VCPU_XER(r4) 186 187 /* Restore host stack pointer and PID before IVPR, since the host 188 * exception handlers use them. */ 189 lwz r1, VCPU_HOST_STACK(r4) 190 lwz r3, VCPU_HOST_PID(r4) 191 mtspr SPRN_PID, r3 192 193#ifdef CONFIG_FSL_BOOKE 194 /* we cheat and know that Linux doesn't use PID1 which is always 0 */ 195 lis r3, 0 196 mtspr SPRN_PID1, r3 197#endif 198 199 /* Restore host IVPR before re-enabling interrupts. We cheat and know 200 * that Linux IVPR is always 0xc0000000. */ 201 lis r3, 0xc000 202 mtspr SPRN_IVPR, r3 203 204 /* Switch to kernel stack and jump to handler. */ 205 LOAD_REG_ADDR(r3, kvmppc_handle_exit) 206 mtctr r3 207 lwz r3, HOST_RUN(r1) 208 lwz r2, HOST_R2(r1) 209 mr r14, r4 /* Save vcpu pointer. */ 210 211 bctrl /* kvmppc_handle_exit() */ 212 213 /* Restore vcpu pointer and the nonvolatiles we used. */ 214 mr r4, r14 215 lwz r14, VCPU_GPR(R14)(r4) 216 217 /* Sometimes instruction emulation must restore complete GPR state. */ 218 andi. r5, r3, RESUME_FLAG_NV 219 beq ..skip_nv_load 220 lwz r15, VCPU_GPR(R15)(r4) 221 lwz r16, VCPU_GPR(R16)(r4) 222 lwz r17, VCPU_GPR(R17)(r4) 223 lwz r18, VCPU_GPR(R18)(r4) 224 lwz r19, VCPU_GPR(R19)(r4) 225 lwz r20, VCPU_GPR(R20)(r4) 226 lwz r21, VCPU_GPR(R21)(r4) 227 lwz r22, VCPU_GPR(R22)(r4) 228 lwz r23, VCPU_GPR(R23)(r4) 229 lwz r24, VCPU_GPR(R24)(r4) 230 lwz r25, VCPU_GPR(R25)(r4) 231 lwz r26, VCPU_GPR(R26)(r4) 232 lwz r27, VCPU_GPR(R27)(r4) 233 lwz r28, VCPU_GPR(R28)(r4) 234 lwz r29, VCPU_GPR(R29)(r4) 235 lwz r30, VCPU_GPR(R30)(r4) 236 lwz r31, VCPU_GPR(R31)(r4) 237..skip_nv_load: 238 239 /* Should we return to the guest? */ 240 andi. r5, r3, RESUME_FLAG_HOST 241 beq lightweight_exit 242 243 srawi r3, r3, 2 /* Shift -ERR back down. */ 244 245heavyweight_exit: 246 /* Not returning to guest. */ 247 248#ifdef CONFIG_SPE 249 /* save guest SPEFSCR and load host SPEFSCR */ 250 mfspr r9, SPRN_SPEFSCR 251 stw r9, VCPU_SPEFSCR(r4) 252 lwz r9, VCPU_HOST_SPEFSCR(r4) 253 mtspr SPRN_SPEFSCR, r9 254#endif 255 256 /* We already saved guest volatile register state; now save the 257 * non-volatiles. */ 258 stw r15, VCPU_GPR(R15)(r4) 259 stw r16, VCPU_GPR(R16)(r4) 260 stw r17, VCPU_GPR(R17)(r4) 261 stw r18, VCPU_GPR(R18)(r4) 262 stw r19, VCPU_GPR(R19)(r4) 263 stw r20, VCPU_GPR(R20)(r4) 264 stw r21, VCPU_GPR(R21)(r4) 265 stw r22, VCPU_GPR(R22)(r4) 266 stw r23, VCPU_GPR(R23)(r4) 267 stw r24, VCPU_GPR(R24)(r4) 268 stw r25, VCPU_GPR(R25)(r4) 269 stw r26, VCPU_GPR(R26)(r4) 270 stw r27, VCPU_GPR(R27)(r4) 271 stw r28, VCPU_GPR(R28)(r4) 272 stw r29, VCPU_GPR(R29)(r4) 273 stw r30, VCPU_GPR(R30)(r4) 274 stw r31, VCPU_GPR(R31)(r4) 275 276 /* Load host non-volatile register state from host stack. */ 277 lwz r14, HOST_NV_GPR(R14)(r1) 278 lwz r15, HOST_NV_GPR(R15)(r1) 279 lwz r16, HOST_NV_GPR(R16)(r1) 280 lwz r17, HOST_NV_GPR(R17)(r1) 281 lwz r18, HOST_NV_GPR(R18)(r1) 282 lwz r19, HOST_NV_GPR(R19)(r1) 283 lwz r20, HOST_NV_GPR(R20)(r1) 284 lwz r21, HOST_NV_GPR(R21)(r1) 285 lwz r22, HOST_NV_GPR(R22)(r1) 286 lwz r23, HOST_NV_GPR(R23)(r1) 287 lwz r24, HOST_NV_GPR(R24)(r1) 288 lwz r25, HOST_NV_GPR(R25)(r1) 289 lwz r26, HOST_NV_GPR(R26)(r1) 290 lwz r27, HOST_NV_GPR(R27)(r1) 291 lwz r28, HOST_NV_GPR(R28)(r1) 292 lwz r29, HOST_NV_GPR(R29)(r1) 293 lwz r30, HOST_NV_GPR(R30)(r1) 294 lwz r31, HOST_NV_GPR(R31)(r1) 295 296 /* Return to kvm_vcpu_run(). */ 297 lwz r4, HOST_STACK_LR(r1) 298 lwz r5, HOST_CR(r1) 299 addi r1, r1, HOST_STACK_SIZE 300 mtlr r4 301 mtcr r5 302 /* r3 still contains the return code from kvmppc_handle_exit(). */ 303 blr 304 305 306/* Registers: 307 * r3: kvm_run pointer 308 * r4: vcpu pointer 309 */ 310_GLOBAL(__kvmppc_vcpu_run) 311 stwu r1, -HOST_STACK_SIZE(r1) 312 stw r1, VCPU_HOST_STACK(r4) /* Save stack pointer to vcpu. */ 313 314 /* Save host state to stack. */ 315 stw r3, HOST_RUN(r1) 316 mflr r3 317 stw r3, HOST_STACK_LR(r1) 318 mfcr r5 319 stw r5, HOST_CR(r1) 320 321 /* Save host non-volatile register state to stack. */ 322 stw r14, HOST_NV_GPR(R14)(r1) 323 stw r15, HOST_NV_GPR(R15)(r1) 324 stw r16, HOST_NV_GPR(R16)(r1) 325 stw r17, HOST_NV_GPR(R17)(r1) 326 stw r18, HOST_NV_GPR(R18)(r1) 327 stw r19, HOST_NV_GPR(R19)(r1) 328 stw r20, HOST_NV_GPR(R20)(r1) 329 stw r21, HOST_NV_GPR(R21)(r1) 330 stw r22, HOST_NV_GPR(R22)(r1) 331 stw r23, HOST_NV_GPR(R23)(r1) 332 stw r24, HOST_NV_GPR(R24)(r1) 333 stw r25, HOST_NV_GPR(R25)(r1) 334 stw r26, HOST_NV_GPR(R26)(r1) 335 stw r27, HOST_NV_GPR(R27)(r1) 336 stw r28, HOST_NV_GPR(R28)(r1) 337 stw r29, HOST_NV_GPR(R29)(r1) 338 stw r30, HOST_NV_GPR(R30)(r1) 339 stw r31, HOST_NV_GPR(R31)(r1) 340 341 /* Load guest non-volatiles. */ 342 lwz r14, VCPU_GPR(R14)(r4) 343 lwz r15, VCPU_GPR(R15)(r4) 344 lwz r16, VCPU_GPR(R16)(r4) 345 lwz r17, VCPU_GPR(R17)(r4) 346 lwz r18, VCPU_GPR(R18)(r4) 347 lwz r19, VCPU_GPR(R19)(r4) 348 lwz r20, VCPU_GPR(R20)(r4) 349 lwz r21, VCPU_GPR(R21)(r4) 350 lwz r22, VCPU_GPR(R22)(r4) 351 lwz r23, VCPU_GPR(R23)(r4) 352 lwz r24, VCPU_GPR(R24)(r4) 353 lwz r25, VCPU_GPR(R25)(r4) 354 lwz r26, VCPU_GPR(R26)(r4) 355 lwz r27, VCPU_GPR(R27)(r4) 356 lwz r28, VCPU_GPR(R28)(r4) 357 lwz r29, VCPU_GPR(R29)(r4) 358 lwz r30, VCPU_GPR(R30)(r4) 359 lwz r31, VCPU_GPR(R31)(r4) 360 361#ifdef CONFIG_SPE 362 /* save host SPEFSCR and load guest SPEFSCR */ 363 mfspr r3, SPRN_SPEFSCR 364 stw r3, VCPU_HOST_SPEFSCR(r4) 365 lwz r3, VCPU_SPEFSCR(r4) 366 mtspr SPRN_SPEFSCR, r3 367#endif 368 369lightweight_exit: 370 stw r2, HOST_R2(r1) 371 372 mfspr r3, SPRN_PID 373 stw r3, VCPU_HOST_PID(r4) 374 lwz r3, VCPU_SHADOW_PID(r4) 375 mtspr SPRN_PID, r3 376 377#ifdef CONFIG_FSL_BOOKE 378 lwz r3, VCPU_SHADOW_PID1(r4) 379 mtspr SPRN_PID1, r3 380#endif 381 382#ifdef CONFIG_44x 383 iccci 0, 0 /* XXX hack */ 384#endif 385 386 /* Load some guest volatiles. */ 387 lwz r0, VCPU_GPR(R0)(r4) 388 lwz r2, VCPU_GPR(R2)(r4) 389 lwz r9, VCPU_GPR(R9)(r4) 390 lwz r10, VCPU_GPR(R10)(r4) 391 lwz r11, VCPU_GPR(R11)(r4) 392 lwz r12, VCPU_GPR(R12)(r4) 393 lwz r13, VCPU_GPR(R13)(r4) 394 lwz r3, VCPU_LR(r4) 395 mtlr r3 396 lwz r3, VCPU_XER(r4) 397 mtxer r3 398 399 /* Switch the IVPR. XXX If we take a TLB miss after this we're screwed, 400 * so how do we make sure vcpu won't fault? */ 401 lis r8, kvmppc_booke_handlers@ha 402 lwz r8, kvmppc_booke_handlers@l(r8) 403 mtspr SPRN_IVPR, r8 404 405 /* Save vcpu pointer for the exception handlers. */ 406 mtspr SPRN_SPRG_WVCPU, r4 407 408 lwz r5, VCPU_SHARED(r4) 409 410 /* Can't switch the stack pointer until after IVPR is switched, 411 * because host interrupt handlers would get confused. */ 412 lwz r1, VCPU_GPR(R1)(r4) 413 414 /* 415 * Host interrupt handlers may have clobbered these 416 * guest-readable SPRGs, or the guest kernel may have 417 * written directly to the shared area, so we 418 * need to reload them here with the guest's values. 419 */ 420 PPC_LD(r3, VCPU_SHARED_SPRG4, r5) 421 mtspr SPRN_SPRG4W, r3 422 PPC_LD(r3, VCPU_SHARED_SPRG5, r5) 423 mtspr SPRN_SPRG5W, r3 424 PPC_LD(r3, VCPU_SHARED_SPRG6, r5) 425 mtspr SPRN_SPRG6W, r3 426 PPC_LD(r3, VCPU_SHARED_SPRG7, r5) 427 mtspr SPRN_SPRG7W, r3 428 429#ifdef CONFIG_KVM_EXIT_TIMING 430 /* save enter time */ 4311: 432 mfspr r6, SPRN_TBRU 433 mfspr r7, SPRN_TBRL 434 mfspr r8, SPRN_TBRU 435 cmpw r8, r6 436 bne 1b 437 stw r7, VCPU_TIMING_LAST_ENTER_TBL(r4) 438 stw r8, VCPU_TIMING_LAST_ENTER_TBU(r4) 439#endif 440 441 /* Finish loading guest volatiles and jump to guest. */ 442 lwz r3, VCPU_CTR(r4) 443 lwz r5, VCPU_CR(r4) 444 lwz r6, VCPU_PC(r4) 445 lwz r7, VCPU_SHADOW_MSR(r4) 446 mtctr r3 447 mtcr r5 448 mtsrr0 r6 449 mtsrr1 r7 450 lwz r5, VCPU_GPR(R5)(r4) 451 lwz r6, VCPU_GPR(R6)(r4) 452 lwz r7, VCPU_GPR(R7)(r4) 453 lwz r8, VCPU_GPR(R8)(r4) 454 455 /* Clear any debug events which occurred since we disabled MSR[DE]. 456 * XXX This gives us a 3-instruction window in which a breakpoint 457 * intended for guest context could fire in the host instead. */ 458 lis r3, 0xffff 459 ori r3, r3, 0xffff 460 mtspr SPRN_DBSR, r3 461 462 lwz r3, VCPU_GPR(R3)(r4) 463 lwz r4, VCPU_GPR(R4)(r4) 464 rfi 465 466#ifdef CONFIG_SPE 467_GLOBAL(kvmppc_save_guest_spe) 468 cmpi 0,r3,0 469 beqlr- 470 SAVE_32EVRS(0, r4, r3, VCPU_EVR) 471 evxor evr6, evr6, evr6 472 evmwumiaa evr6, evr6, evr6 473 li r4,VCPU_ACC 474 evstddx evr6, r4, r3 /* save acc */ 475 blr 476 477_GLOBAL(kvmppc_load_guest_spe) 478 cmpi 0,r3,0 479 beqlr- 480 li r4,VCPU_ACC 481 evlddx evr6,r4,r3 482 evmra evr6,evr6 /* load acc */ 483 REST_32EVRS(0, r4, r3, VCPU_EVR) 484 blr 485#endif 486