1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright IBM Corp. 2007 5 * Copyright 2010-2011 Freescale Semiconductor, Inc. 6 * 7 * Authors: Hollis Blanchard <hollisb@us.ibm.com> 8 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> 9 * Scott Wood <scottwood@freescale.com> 10 * Varun Sethi <varun.sethi@freescale.com> 11 */ 12 13 #include <linux/errno.h> 14 #include <linux/err.h> 15 #include <linux/kvm_host.h> 16 #include <linux/gfp.h> 17 #include <linux/module.h> 18 #include <linux/vmalloc.h> 19 #include <linux/fs.h> 20 21 #include <asm/cputable.h> 22 #include <linux/uaccess.h> 23 #include <asm/kvm_ppc.h> 24 #include <asm/cacheflush.h> 25 #include <asm/dbell.h> 26 #include <asm/hw_irq.h> 27 #include <asm/irq.h> 28 #include <asm/time.h> 29 30 #include "timing.h" 31 #include "booke.h" 32 33 #define CREATE_TRACE_POINTS 34 #include "trace_booke.h" 35 36 unsigned long kvmppc_booke_handlers; 37 38 struct kvm_stats_debugfs_item debugfs_entries[] = { 39 VCPU_STAT("mmio", mmio_exits), 40 VCPU_STAT("sig", signal_exits), 41 VCPU_STAT("itlb_r", itlb_real_miss_exits), 42 VCPU_STAT("itlb_v", itlb_virt_miss_exits), 43 VCPU_STAT("dtlb_r", dtlb_real_miss_exits), 44 VCPU_STAT("dtlb_v", dtlb_virt_miss_exits), 45 VCPU_STAT("sysc", syscall_exits), 46 VCPU_STAT("isi", isi_exits), 47 VCPU_STAT("dsi", dsi_exits), 48 VCPU_STAT("inst_emu", emulated_inst_exits), 49 VCPU_STAT("dec", dec_exits), 50 VCPU_STAT("ext_intr", ext_intr_exits), 51 VCPU_STAT("halt_successful_poll", halt_successful_poll), 52 VCPU_STAT("halt_attempted_poll", halt_attempted_poll), 53 VCPU_STAT("halt_poll_invalid", halt_poll_invalid), 54 VCPU_STAT("halt_wakeup", halt_wakeup), 55 VCPU_STAT("doorbell", dbell_exits), 56 VCPU_STAT("guest doorbell", gdbell_exits), 57 VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns), 58 VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns), 59 VM_STAT("remote_tlb_flush", remote_tlb_flush), 60 { NULL } 61 }; 62 63 /* TODO: use vcpu_printf() */ 64 void kvmppc_dump_vcpu(struct kvm_vcpu *vcpu) 65 { 66 int i; 67 68 printk("pc: %08lx msr: %08llx\n", vcpu->arch.regs.nip, 69 vcpu->arch.shared->msr); 70 printk("lr: %08lx ctr: %08lx\n", vcpu->arch.regs.link, 71 vcpu->arch.regs.ctr); 72 printk("srr0: %08llx srr1: %08llx\n", vcpu->arch.shared->srr0, 73 vcpu->arch.shared->srr1); 74 75 printk("exceptions: %08lx\n", vcpu->arch.pending_exceptions); 76 77 for (i = 0; i < 32; i += 4) { 78 printk("gpr%02d: %08lx %08lx %08lx %08lx\n", i, 79 kvmppc_get_gpr(vcpu, i), 80 kvmppc_get_gpr(vcpu, i+1), 81 kvmppc_get_gpr(vcpu, i+2), 82 kvmppc_get_gpr(vcpu, i+3)); 83 } 84 } 85 86 #ifdef CONFIG_SPE 87 void kvmppc_vcpu_disable_spe(struct kvm_vcpu *vcpu) 88 { 89 preempt_disable(); 90 enable_kernel_spe(); 91 kvmppc_save_guest_spe(vcpu); 92 disable_kernel_spe(); 93 vcpu->arch.shadow_msr &= ~MSR_SPE; 94 preempt_enable(); 95 } 96 97 static void kvmppc_vcpu_enable_spe(struct kvm_vcpu *vcpu) 98 { 99 preempt_disable(); 100 enable_kernel_spe(); 101 kvmppc_load_guest_spe(vcpu); 102 disable_kernel_spe(); 103 vcpu->arch.shadow_msr |= MSR_SPE; 104 preempt_enable(); 105 } 106 107 static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu) 108 { 109 if (vcpu->arch.shared->msr & MSR_SPE) { 110 if (!(vcpu->arch.shadow_msr & MSR_SPE)) 111 kvmppc_vcpu_enable_spe(vcpu); 112 } else if (vcpu->arch.shadow_msr & MSR_SPE) { 113 kvmppc_vcpu_disable_spe(vcpu); 114 } 115 } 116 #else 117 static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu) 118 { 119 } 120 #endif 121 122 /* 123 * Load up guest vcpu FP state if it's needed. 124 * It also set the MSR_FP in thread so that host know 125 * we're holding FPU, and then host can help to save 126 * guest vcpu FP state if other threads require to use FPU. 127 * This simulates an FP unavailable fault. 128 * 129 * It requires to be called with preemption disabled. 130 */ 131 static inline void kvmppc_load_guest_fp(struct kvm_vcpu *vcpu) 132 { 133 #ifdef CONFIG_PPC_FPU 134 if (!(current->thread.regs->msr & MSR_FP)) { 135 enable_kernel_fp(); 136 load_fp_state(&vcpu->arch.fp); 137 disable_kernel_fp(); 138 current->thread.fp_save_area = &vcpu->arch.fp; 139 current->thread.regs->msr |= MSR_FP; 140 } 141 #endif 142 } 143 144 /* 145 * Save guest vcpu FP state into thread. 146 * It requires to be called with preemption disabled. 147 */ 148 static inline void kvmppc_save_guest_fp(struct kvm_vcpu *vcpu) 149 { 150 #ifdef CONFIG_PPC_FPU 151 if (current->thread.regs->msr & MSR_FP) 152 giveup_fpu(current); 153 current->thread.fp_save_area = NULL; 154 #endif 155 } 156 157 static void kvmppc_vcpu_sync_fpu(struct kvm_vcpu *vcpu) 158 { 159 #if defined(CONFIG_PPC_FPU) && !defined(CONFIG_KVM_BOOKE_HV) 160 /* We always treat the FP bit as enabled from the host 161 perspective, so only need to adjust the shadow MSR */ 162 vcpu->arch.shadow_msr &= ~MSR_FP; 163 vcpu->arch.shadow_msr |= vcpu->arch.shared->msr & MSR_FP; 164 #endif 165 } 166 167 /* 168 * Simulate AltiVec unavailable fault to load guest state 169 * from thread to AltiVec unit. 170 * It requires to be called with preemption disabled. 171 */ 172 static inline void kvmppc_load_guest_altivec(struct kvm_vcpu *vcpu) 173 { 174 #ifdef CONFIG_ALTIVEC 175 if (cpu_has_feature(CPU_FTR_ALTIVEC)) { 176 if (!(current->thread.regs->msr & MSR_VEC)) { 177 enable_kernel_altivec(); 178 load_vr_state(&vcpu->arch.vr); 179 disable_kernel_altivec(); 180 current->thread.vr_save_area = &vcpu->arch.vr; 181 current->thread.regs->msr |= MSR_VEC; 182 } 183 } 184 #endif 185 } 186 187 /* 188 * Save guest vcpu AltiVec state into thread. 189 * It requires to be called with preemption disabled. 190 */ 191 static inline void kvmppc_save_guest_altivec(struct kvm_vcpu *vcpu) 192 { 193 #ifdef CONFIG_ALTIVEC 194 if (cpu_has_feature(CPU_FTR_ALTIVEC)) { 195 if (current->thread.regs->msr & MSR_VEC) 196 giveup_altivec(current); 197 current->thread.vr_save_area = NULL; 198 } 199 #endif 200 } 201 202 static void kvmppc_vcpu_sync_debug(struct kvm_vcpu *vcpu) 203 { 204 /* Synchronize guest's desire to get debug interrupts into shadow MSR */ 205 #ifndef CONFIG_KVM_BOOKE_HV 206 vcpu->arch.shadow_msr &= ~MSR_DE; 207 vcpu->arch.shadow_msr |= vcpu->arch.shared->msr & MSR_DE; 208 #endif 209 210 /* Force enable debug interrupts when user space wants to debug */ 211 if (vcpu->guest_debug) { 212 #ifdef CONFIG_KVM_BOOKE_HV 213 /* 214 * Since there is no shadow MSR, sync MSR_DE into the guest 215 * visible MSR. 216 */ 217 vcpu->arch.shared->msr |= MSR_DE; 218 #else 219 vcpu->arch.shadow_msr |= MSR_DE; 220 vcpu->arch.shared->msr &= ~MSR_DE; 221 #endif 222 } 223 } 224 225 /* 226 * Helper function for "full" MSR writes. No need to call this if only 227 * EE/CE/ME/DE/RI are changing. 228 */ 229 void kvmppc_set_msr(struct kvm_vcpu *vcpu, u32 new_msr) 230 { 231 u32 old_msr = vcpu->arch.shared->msr; 232 233 #ifdef CONFIG_KVM_BOOKE_HV 234 new_msr |= MSR_GS; 235 #endif 236 237 vcpu->arch.shared->msr = new_msr; 238 239 kvmppc_mmu_msr_notify(vcpu, old_msr); 240 kvmppc_vcpu_sync_spe(vcpu); 241 kvmppc_vcpu_sync_fpu(vcpu); 242 kvmppc_vcpu_sync_debug(vcpu); 243 } 244 245 static void kvmppc_booke_queue_irqprio(struct kvm_vcpu *vcpu, 246 unsigned int priority) 247 { 248 trace_kvm_booke_queue_irqprio(vcpu, priority); 249 set_bit(priority, &vcpu->arch.pending_exceptions); 250 } 251 252 void kvmppc_core_queue_dtlb_miss(struct kvm_vcpu *vcpu, 253 ulong dear_flags, ulong esr_flags) 254 { 255 vcpu->arch.queued_dear = dear_flags; 256 vcpu->arch.queued_esr = esr_flags; 257 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DTLB_MISS); 258 } 259 260 void kvmppc_core_queue_data_storage(struct kvm_vcpu *vcpu, 261 ulong dear_flags, ulong esr_flags) 262 { 263 vcpu->arch.queued_dear = dear_flags; 264 vcpu->arch.queued_esr = esr_flags; 265 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DATA_STORAGE); 266 } 267 268 void kvmppc_core_queue_itlb_miss(struct kvm_vcpu *vcpu) 269 { 270 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ITLB_MISS); 271 } 272 273 void kvmppc_core_queue_inst_storage(struct kvm_vcpu *vcpu, ulong esr_flags) 274 { 275 vcpu->arch.queued_esr = esr_flags; 276 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_INST_STORAGE); 277 } 278 279 static void kvmppc_core_queue_alignment(struct kvm_vcpu *vcpu, ulong dear_flags, 280 ulong esr_flags) 281 { 282 vcpu->arch.queued_dear = dear_flags; 283 vcpu->arch.queued_esr = esr_flags; 284 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALIGNMENT); 285 } 286 287 void kvmppc_core_queue_program(struct kvm_vcpu *vcpu, ulong esr_flags) 288 { 289 vcpu->arch.queued_esr = esr_flags; 290 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_PROGRAM); 291 } 292 293 void kvmppc_core_queue_fpunavail(struct kvm_vcpu *vcpu) 294 { 295 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_FP_UNAVAIL); 296 } 297 298 #ifdef CONFIG_ALTIVEC 299 void kvmppc_core_queue_vec_unavail(struct kvm_vcpu *vcpu) 300 { 301 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALTIVEC_UNAVAIL); 302 } 303 #endif 304 305 void kvmppc_core_queue_dec(struct kvm_vcpu *vcpu) 306 { 307 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DECREMENTER); 308 } 309 310 int kvmppc_core_pending_dec(struct kvm_vcpu *vcpu) 311 { 312 return test_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions); 313 } 314 315 void kvmppc_core_dequeue_dec(struct kvm_vcpu *vcpu) 316 { 317 clear_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions); 318 } 319 320 void kvmppc_core_queue_external(struct kvm_vcpu *vcpu, 321 struct kvm_interrupt *irq) 322 { 323 unsigned int prio = BOOKE_IRQPRIO_EXTERNAL; 324 325 if (irq->irq == KVM_INTERRUPT_SET_LEVEL) 326 prio = BOOKE_IRQPRIO_EXTERNAL_LEVEL; 327 328 kvmppc_booke_queue_irqprio(vcpu, prio); 329 } 330 331 void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu) 332 { 333 clear_bit(BOOKE_IRQPRIO_EXTERNAL, &vcpu->arch.pending_exceptions); 334 clear_bit(BOOKE_IRQPRIO_EXTERNAL_LEVEL, &vcpu->arch.pending_exceptions); 335 } 336 337 static void kvmppc_core_queue_watchdog(struct kvm_vcpu *vcpu) 338 { 339 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_WATCHDOG); 340 } 341 342 static void kvmppc_core_dequeue_watchdog(struct kvm_vcpu *vcpu) 343 { 344 clear_bit(BOOKE_IRQPRIO_WATCHDOG, &vcpu->arch.pending_exceptions); 345 } 346 347 void kvmppc_core_queue_debug(struct kvm_vcpu *vcpu) 348 { 349 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DEBUG); 350 } 351 352 void kvmppc_core_dequeue_debug(struct kvm_vcpu *vcpu) 353 { 354 clear_bit(BOOKE_IRQPRIO_DEBUG, &vcpu->arch.pending_exceptions); 355 } 356 357 static void set_guest_srr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1) 358 { 359 kvmppc_set_srr0(vcpu, srr0); 360 kvmppc_set_srr1(vcpu, srr1); 361 } 362 363 static void set_guest_csrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1) 364 { 365 vcpu->arch.csrr0 = srr0; 366 vcpu->arch.csrr1 = srr1; 367 } 368 369 static void set_guest_dsrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1) 370 { 371 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) { 372 vcpu->arch.dsrr0 = srr0; 373 vcpu->arch.dsrr1 = srr1; 374 } else { 375 set_guest_csrr(vcpu, srr0, srr1); 376 } 377 } 378 379 static void set_guest_mcsrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1) 380 { 381 vcpu->arch.mcsrr0 = srr0; 382 vcpu->arch.mcsrr1 = srr1; 383 } 384 385 /* Deliver the interrupt of the corresponding priority, if possible. */ 386 static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu, 387 unsigned int priority) 388 { 389 int allowed = 0; 390 ulong msr_mask = 0; 391 bool update_esr = false, update_dear = false, update_epr = false; 392 ulong crit_raw = vcpu->arch.shared->critical; 393 ulong crit_r1 = kvmppc_get_gpr(vcpu, 1); 394 bool crit; 395 bool keep_irq = false; 396 enum int_class int_class; 397 ulong new_msr = vcpu->arch.shared->msr; 398 399 /* Truncate crit indicators in 32 bit mode */ 400 if (!(vcpu->arch.shared->msr & MSR_SF)) { 401 crit_raw &= 0xffffffff; 402 crit_r1 &= 0xffffffff; 403 } 404 405 /* Critical section when crit == r1 */ 406 crit = (crit_raw == crit_r1); 407 /* ... and we're in supervisor mode */ 408 crit = crit && !(vcpu->arch.shared->msr & MSR_PR); 409 410 if (priority == BOOKE_IRQPRIO_EXTERNAL_LEVEL) { 411 priority = BOOKE_IRQPRIO_EXTERNAL; 412 keep_irq = true; 413 } 414 415 if ((priority == BOOKE_IRQPRIO_EXTERNAL) && vcpu->arch.epr_flags) 416 update_epr = true; 417 418 switch (priority) { 419 case BOOKE_IRQPRIO_DTLB_MISS: 420 case BOOKE_IRQPRIO_DATA_STORAGE: 421 case BOOKE_IRQPRIO_ALIGNMENT: 422 update_dear = true; 423 fallthrough; 424 case BOOKE_IRQPRIO_INST_STORAGE: 425 case BOOKE_IRQPRIO_PROGRAM: 426 update_esr = true; 427 fallthrough; 428 case BOOKE_IRQPRIO_ITLB_MISS: 429 case BOOKE_IRQPRIO_SYSCALL: 430 case BOOKE_IRQPRIO_FP_UNAVAIL: 431 #ifdef CONFIG_SPE_POSSIBLE 432 case BOOKE_IRQPRIO_SPE_UNAVAIL: 433 case BOOKE_IRQPRIO_SPE_FP_DATA: 434 case BOOKE_IRQPRIO_SPE_FP_ROUND: 435 #endif 436 #ifdef CONFIG_ALTIVEC 437 case BOOKE_IRQPRIO_ALTIVEC_UNAVAIL: 438 case BOOKE_IRQPRIO_ALTIVEC_ASSIST: 439 #endif 440 case BOOKE_IRQPRIO_AP_UNAVAIL: 441 allowed = 1; 442 msr_mask = MSR_CE | MSR_ME | MSR_DE; 443 int_class = INT_CLASS_NONCRIT; 444 break; 445 case BOOKE_IRQPRIO_WATCHDOG: 446 case BOOKE_IRQPRIO_CRITICAL: 447 case BOOKE_IRQPRIO_DBELL_CRIT: 448 allowed = vcpu->arch.shared->msr & MSR_CE; 449 allowed = allowed && !crit; 450 msr_mask = MSR_ME; 451 int_class = INT_CLASS_CRIT; 452 break; 453 case BOOKE_IRQPRIO_MACHINE_CHECK: 454 allowed = vcpu->arch.shared->msr & MSR_ME; 455 allowed = allowed && !crit; 456 int_class = INT_CLASS_MC; 457 break; 458 case BOOKE_IRQPRIO_DECREMENTER: 459 case BOOKE_IRQPRIO_FIT: 460 keep_irq = true; 461 fallthrough; 462 case BOOKE_IRQPRIO_EXTERNAL: 463 case BOOKE_IRQPRIO_DBELL: 464 allowed = vcpu->arch.shared->msr & MSR_EE; 465 allowed = allowed && !crit; 466 msr_mask = MSR_CE | MSR_ME | MSR_DE; 467 int_class = INT_CLASS_NONCRIT; 468 break; 469 case BOOKE_IRQPRIO_DEBUG: 470 allowed = vcpu->arch.shared->msr & MSR_DE; 471 allowed = allowed && !crit; 472 msr_mask = MSR_ME; 473 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) 474 int_class = INT_CLASS_DBG; 475 else 476 int_class = INT_CLASS_CRIT; 477 478 break; 479 } 480 481 if (allowed) { 482 switch (int_class) { 483 case INT_CLASS_NONCRIT: 484 set_guest_srr(vcpu, vcpu->arch.regs.nip, 485 vcpu->arch.shared->msr); 486 break; 487 case INT_CLASS_CRIT: 488 set_guest_csrr(vcpu, vcpu->arch.regs.nip, 489 vcpu->arch.shared->msr); 490 break; 491 case INT_CLASS_DBG: 492 set_guest_dsrr(vcpu, vcpu->arch.regs.nip, 493 vcpu->arch.shared->msr); 494 break; 495 case INT_CLASS_MC: 496 set_guest_mcsrr(vcpu, vcpu->arch.regs.nip, 497 vcpu->arch.shared->msr); 498 break; 499 } 500 501 vcpu->arch.regs.nip = vcpu->arch.ivpr | 502 vcpu->arch.ivor[priority]; 503 if (update_esr == true) 504 kvmppc_set_esr(vcpu, vcpu->arch.queued_esr); 505 if (update_dear == true) 506 kvmppc_set_dar(vcpu, vcpu->arch.queued_dear); 507 if (update_epr == true) { 508 if (vcpu->arch.epr_flags & KVMPPC_EPR_USER) 509 kvm_make_request(KVM_REQ_EPR_EXIT, vcpu); 510 else if (vcpu->arch.epr_flags & KVMPPC_EPR_KERNEL) { 511 BUG_ON(vcpu->arch.irq_type != KVMPPC_IRQ_MPIC); 512 kvmppc_mpic_set_epr(vcpu); 513 } 514 } 515 516 new_msr &= msr_mask; 517 #if defined(CONFIG_64BIT) 518 if (vcpu->arch.epcr & SPRN_EPCR_ICM) 519 new_msr |= MSR_CM; 520 #endif 521 kvmppc_set_msr(vcpu, new_msr); 522 523 if (!keep_irq) 524 clear_bit(priority, &vcpu->arch.pending_exceptions); 525 } 526 527 #ifdef CONFIG_KVM_BOOKE_HV 528 /* 529 * If an interrupt is pending but masked, raise a guest doorbell 530 * so that we are notified when the guest enables the relevant 531 * MSR bit. 532 */ 533 if (vcpu->arch.pending_exceptions & BOOKE_IRQMASK_EE) 534 kvmppc_set_pending_interrupt(vcpu, INT_CLASS_NONCRIT); 535 if (vcpu->arch.pending_exceptions & BOOKE_IRQMASK_CE) 536 kvmppc_set_pending_interrupt(vcpu, INT_CLASS_CRIT); 537 if (vcpu->arch.pending_exceptions & BOOKE_IRQPRIO_MACHINE_CHECK) 538 kvmppc_set_pending_interrupt(vcpu, INT_CLASS_MC); 539 #endif 540 541 return allowed; 542 } 543 544 /* 545 * Return the number of jiffies until the next timeout. If the timeout is 546 * longer than the NEXT_TIMER_MAX_DELTA, then return NEXT_TIMER_MAX_DELTA 547 * because the larger value can break the timer APIs. 548 */ 549 static unsigned long watchdog_next_timeout(struct kvm_vcpu *vcpu) 550 { 551 u64 tb, wdt_tb, wdt_ticks = 0; 552 u64 nr_jiffies = 0; 553 u32 period = TCR_GET_WP(vcpu->arch.tcr); 554 555 wdt_tb = 1ULL << (63 - period); 556 tb = get_tb(); 557 /* 558 * The watchdog timeout will hapeen when TB bit corresponding 559 * to watchdog will toggle from 0 to 1. 560 */ 561 if (tb & wdt_tb) 562 wdt_ticks = wdt_tb; 563 564 wdt_ticks += wdt_tb - (tb & (wdt_tb - 1)); 565 566 /* Convert timebase ticks to jiffies */ 567 nr_jiffies = wdt_ticks; 568 569 if (do_div(nr_jiffies, tb_ticks_per_jiffy)) 570 nr_jiffies++; 571 572 return min_t(unsigned long long, nr_jiffies, NEXT_TIMER_MAX_DELTA); 573 } 574 575 static void arm_next_watchdog(struct kvm_vcpu *vcpu) 576 { 577 unsigned long nr_jiffies; 578 unsigned long flags; 579 580 /* 581 * If TSR_ENW and TSR_WIS are not set then no need to exit to 582 * userspace, so clear the KVM_REQ_WATCHDOG request. 583 */ 584 if ((vcpu->arch.tsr & (TSR_ENW | TSR_WIS)) != (TSR_ENW | TSR_WIS)) 585 kvm_clear_request(KVM_REQ_WATCHDOG, vcpu); 586 587 spin_lock_irqsave(&vcpu->arch.wdt_lock, flags); 588 nr_jiffies = watchdog_next_timeout(vcpu); 589 /* 590 * If the number of jiffies of watchdog timer >= NEXT_TIMER_MAX_DELTA 591 * then do not run the watchdog timer as this can break timer APIs. 592 */ 593 if (nr_jiffies < NEXT_TIMER_MAX_DELTA) 594 mod_timer(&vcpu->arch.wdt_timer, jiffies + nr_jiffies); 595 else 596 del_timer(&vcpu->arch.wdt_timer); 597 spin_unlock_irqrestore(&vcpu->arch.wdt_lock, flags); 598 } 599 600 void kvmppc_watchdog_func(struct timer_list *t) 601 { 602 struct kvm_vcpu *vcpu = from_timer(vcpu, t, arch.wdt_timer); 603 u32 tsr, new_tsr; 604 int final; 605 606 do { 607 new_tsr = tsr = vcpu->arch.tsr; 608 final = 0; 609 610 /* Time out event */ 611 if (tsr & TSR_ENW) { 612 if (tsr & TSR_WIS) 613 final = 1; 614 else 615 new_tsr = tsr | TSR_WIS; 616 } else { 617 new_tsr = tsr | TSR_ENW; 618 } 619 } while (cmpxchg(&vcpu->arch.tsr, tsr, new_tsr) != tsr); 620 621 if (new_tsr & TSR_WIS) { 622 smp_wmb(); 623 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 624 kvm_vcpu_kick(vcpu); 625 } 626 627 /* 628 * If this is final watchdog expiry and some action is required 629 * then exit to userspace. 630 */ 631 if (final && (vcpu->arch.tcr & TCR_WRC_MASK) && 632 vcpu->arch.watchdog_enabled) { 633 smp_wmb(); 634 kvm_make_request(KVM_REQ_WATCHDOG, vcpu); 635 kvm_vcpu_kick(vcpu); 636 } 637 638 /* 639 * Stop running the watchdog timer after final expiration to 640 * prevent the host from being flooded with timers if the 641 * guest sets a short period. 642 * Timers will resume when TSR/TCR is updated next time. 643 */ 644 if (!final) 645 arm_next_watchdog(vcpu); 646 } 647 648 static void update_timer_ints(struct kvm_vcpu *vcpu) 649 { 650 if ((vcpu->arch.tcr & TCR_DIE) && (vcpu->arch.tsr & TSR_DIS)) 651 kvmppc_core_queue_dec(vcpu); 652 else 653 kvmppc_core_dequeue_dec(vcpu); 654 655 if ((vcpu->arch.tcr & TCR_WIE) && (vcpu->arch.tsr & TSR_WIS)) 656 kvmppc_core_queue_watchdog(vcpu); 657 else 658 kvmppc_core_dequeue_watchdog(vcpu); 659 } 660 661 static void kvmppc_core_check_exceptions(struct kvm_vcpu *vcpu) 662 { 663 unsigned long *pending = &vcpu->arch.pending_exceptions; 664 unsigned int priority; 665 666 priority = __ffs(*pending); 667 while (priority < BOOKE_IRQPRIO_MAX) { 668 if (kvmppc_booke_irqprio_deliver(vcpu, priority)) 669 break; 670 671 priority = find_next_bit(pending, 672 BITS_PER_BYTE * sizeof(*pending), 673 priority + 1); 674 } 675 676 /* Tell the guest about our interrupt status */ 677 vcpu->arch.shared->int_pending = !!*pending; 678 } 679 680 /* Check pending exceptions and deliver one, if possible. */ 681 int kvmppc_core_prepare_to_enter(struct kvm_vcpu *vcpu) 682 { 683 int r = 0; 684 WARN_ON_ONCE(!irqs_disabled()); 685 686 kvmppc_core_check_exceptions(vcpu); 687 688 if (kvm_request_pending(vcpu)) { 689 /* Exception delivery raised request; start over */ 690 return 1; 691 } 692 693 if (vcpu->arch.shared->msr & MSR_WE) { 694 local_irq_enable(); 695 kvm_vcpu_block(vcpu); 696 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 697 hard_irq_disable(); 698 699 kvmppc_set_exit_type(vcpu, EMULATED_MTMSRWE_EXITS); 700 r = 1; 701 }; 702 703 return r; 704 } 705 706 int kvmppc_core_check_requests(struct kvm_vcpu *vcpu) 707 { 708 int r = 1; /* Indicate we want to get back into the guest */ 709 710 if (kvm_check_request(KVM_REQ_PENDING_TIMER, vcpu)) 711 update_timer_ints(vcpu); 712 #if defined(CONFIG_KVM_E500V2) || defined(CONFIG_KVM_E500MC) 713 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 714 kvmppc_core_flush_tlb(vcpu); 715 #endif 716 717 if (kvm_check_request(KVM_REQ_WATCHDOG, vcpu)) { 718 vcpu->run->exit_reason = KVM_EXIT_WATCHDOG; 719 r = 0; 720 } 721 722 if (kvm_check_request(KVM_REQ_EPR_EXIT, vcpu)) { 723 vcpu->run->epr.epr = 0; 724 vcpu->arch.epr_needed = true; 725 vcpu->run->exit_reason = KVM_EXIT_EPR; 726 r = 0; 727 } 728 729 return r; 730 } 731 732 int kvmppc_vcpu_run(struct kvm_vcpu *vcpu) 733 { 734 struct kvm_run *run = vcpu->run; 735 int ret, s; 736 struct debug_reg debug; 737 738 if (!vcpu->arch.sane) { 739 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 740 return -EINVAL; 741 } 742 743 s = kvmppc_prepare_to_enter(vcpu); 744 if (s <= 0) { 745 ret = s; 746 goto out; 747 } 748 /* interrupts now hard-disabled */ 749 750 #ifdef CONFIG_PPC_FPU 751 /* Save userspace FPU state in stack */ 752 enable_kernel_fp(); 753 754 /* 755 * Since we can't trap on MSR_FP in GS-mode, we consider the guest 756 * as always using the FPU. 757 */ 758 kvmppc_load_guest_fp(vcpu); 759 #endif 760 761 #ifdef CONFIG_ALTIVEC 762 /* Save userspace AltiVec state in stack */ 763 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 764 enable_kernel_altivec(); 765 /* 766 * Since we can't trap on MSR_VEC in GS-mode, we consider the guest 767 * as always using the AltiVec. 768 */ 769 kvmppc_load_guest_altivec(vcpu); 770 #endif 771 772 /* Switch to guest debug context */ 773 debug = vcpu->arch.dbg_reg; 774 switch_booke_debug_regs(&debug); 775 debug = current->thread.debug; 776 current->thread.debug = vcpu->arch.dbg_reg; 777 778 vcpu->arch.pgdir = vcpu->kvm->mm->pgd; 779 kvmppc_fix_ee_before_entry(); 780 781 ret = __kvmppc_vcpu_run(run, vcpu); 782 783 /* No need for guest_exit. It's done in handle_exit. 784 We also get here with interrupts enabled. */ 785 786 /* Switch back to user space debug context */ 787 switch_booke_debug_regs(&debug); 788 current->thread.debug = debug; 789 790 #ifdef CONFIG_PPC_FPU 791 kvmppc_save_guest_fp(vcpu); 792 #endif 793 794 #ifdef CONFIG_ALTIVEC 795 kvmppc_save_guest_altivec(vcpu); 796 #endif 797 798 out: 799 vcpu->mode = OUTSIDE_GUEST_MODE; 800 return ret; 801 } 802 803 static int emulation_exit(struct kvm_vcpu *vcpu) 804 { 805 enum emulation_result er; 806 807 er = kvmppc_emulate_instruction(vcpu); 808 switch (er) { 809 case EMULATE_DONE: 810 /* don't overwrite subtypes, just account kvm_stats */ 811 kvmppc_account_exit_stat(vcpu, EMULATED_INST_EXITS); 812 /* Future optimization: only reload non-volatiles if 813 * they were actually modified by emulation. */ 814 return RESUME_GUEST_NV; 815 816 case EMULATE_AGAIN: 817 return RESUME_GUEST; 818 819 case EMULATE_FAIL: 820 printk(KERN_CRIT "%s: emulation at %lx failed (%08x)\n", 821 __func__, vcpu->arch.regs.nip, vcpu->arch.last_inst); 822 /* For debugging, encode the failing instruction and 823 * report it to userspace. */ 824 vcpu->run->hw.hardware_exit_reason = ~0ULL << 32; 825 vcpu->run->hw.hardware_exit_reason |= vcpu->arch.last_inst; 826 kvmppc_core_queue_program(vcpu, ESR_PIL); 827 return RESUME_HOST; 828 829 case EMULATE_EXIT_USER: 830 return RESUME_HOST; 831 832 default: 833 BUG(); 834 } 835 } 836 837 static int kvmppc_handle_debug(struct kvm_vcpu *vcpu) 838 { 839 struct kvm_run *run = vcpu->run; 840 struct debug_reg *dbg_reg = &(vcpu->arch.dbg_reg); 841 u32 dbsr = vcpu->arch.dbsr; 842 843 if (vcpu->guest_debug == 0) { 844 /* 845 * Debug resources belong to Guest. 846 * Imprecise debug event is not injected 847 */ 848 if (dbsr & DBSR_IDE) { 849 dbsr &= ~DBSR_IDE; 850 if (!dbsr) 851 return RESUME_GUEST; 852 } 853 854 if (dbsr && (vcpu->arch.shared->msr & MSR_DE) && 855 (vcpu->arch.dbg_reg.dbcr0 & DBCR0_IDM)) 856 kvmppc_core_queue_debug(vcpu); 857 858 /* Inject a program interrupt if trap debug is not allowed */ 859 if ((dbsr & DBSR_TIE) && !(vcpu->arch.shared->msr & MSR_DE)) 860 kvmppc_core_queue_program(vcpu, ESR_PTR); 861 862 return RESUME_GUEST; 863 } 864 865 /* 866 * Debug resource owned by userspace. 867 * Clear guest dbsr (vcpu->arch.dbsr) 868 */ 869 vcpu->arch.dbsr = 0; 870 run->debug.arch.status = 0; 871 run->debug.arch.address = vcpu->arch.regs.nip; 872 873 if (dbsr & (DBSR_IAC1 | DBSR_IAC2 | DBSR_IAC3 | DBSR_IAC4)) { 874 run->debug.arch.status |= KVMPPC_DEBUG_BREAKPOINT; 875 } else { 876 if (dbsr & (DBSR_DAC1W | DBSR_DAC2W)) 877 run->debug.arch.status |= KVMPPC_DEBUG_WATCH_WRITE; 878 else if (dbsr & (DBSR_DAC1R | DBSR_DAC2R)) 879 run->debug.arch.status |= KVMPPC_DEBUG_WATCH_READ; 880 if (dbsr & (DBSR_DAC1R | DBSR_DAC1W)) 881 run->debug.arch.address = dbg_reg->dac1; 882 else if (dbsr & (DBSR_DAC2R | DBSR_DAC2W)) 883 run->debug.arch.address = dbg_reg->dac2; 884 } 885 886 return RESUME_HOST; 887 } 888 889 static void kvmppc_fill_pt_regs(struct pt_regs *regs) 890 { 891 ulong r1, ip, msr, lr; 892 893 asm("mr %0, 1" : "=r"(r1)); 894 asm("mflr %0" : "=r"(lr)); 895 asm("mfmsr %0" : "=r"(msr)); 896 asm("bl 1f; 1: mflr %0" : "=r"(ip)); 897 898 memset(regs, 0, sizeof(*regs)); 899 regs->gpr[1] = r1; 900 regs->nip = ip; 901 regs->msr = msr; 902 regs->link = lr; 903 } 904 905 /* 906 * For interrupts needed to be handled by host interrupt handlers, 907 * corresponding host handler are called from here in similar way 908 * (but not exact) as they are called from low level handler 909 * (such as from arch/powerpc/kernel/head_fsl_booke.S). 910 */ 911 static void kvmppc_restart_interrupt(struct kvm_vcpu *vcpu, 912 unsigned int exit_nr) 913 { 914 struct pt_regs regs; 915 916 switch (exit_nr) { 917 case BOOKE_INTERRUPT_EXTERNAL: 918 kvmppc_fill_pt_regs(®s); 919 do_IRQ(®s); 920 break; 921 case BOOKE_INTERRUPT_DECREMENTER: 922 kvmppc_fill_pt_regs(®s); 923 timer_interrupt(®s); 924 break; 925 #if defined(CONFIG_PPC_DOORBELL) 926 case BOOKE_INTERRUPT_DOORBELL: 927 kvmppc_fill_pt_regs(®s); 928 doorbell_exception(®s); 929 break; 930 #endif 931 case BOOKE_INTERRUPT_MACHINE_CHECK: 932 /* FIXME */ 933 break; 934 case BOOKE_INTERRUPT_PERFORMANCE_MONITOR: 935 kvmppc_fill_pt_regs(®s); 936 performance_monitor_exception(®s); 937 break; 938 case BOOKE_INTERRUPT_WATCHDOG: 939 kvmppc_fill_pt_regs(®s); 940 #ifdef CONFIG_BOOKE_WDT 941 WatchdogException(®s); 942 #else 943 unknown_exception(®s); 944 #endif 945 break; 946 case BOOKE_INTERRUPT_CRITICAL: 947 kvmppc_fill_pt_regs(®s); 948 unknown_exception(®s); 949 break; 950 case BOOKE_INTERRUPT_DEBUG: 951 /* Save DBSR before preemption is enabled */ 952 vcpu->arch.dbsr = mfspr(SPRN_DBSR); 953 kvmppc_clear_dbsr(); 954 break; 955 } 956 } 957 958 static int kvmppc_resume_inst_load(struct kvm_vcpu *vcpu, 959 enum emulation_result emulated, u32 last_inst) 960 { 961 switch (emulated) { 962 case EMULATE_AGAIN: 963 return RESUME_GUEST; 964 965 case EMULATE_FAIL: 966 pr_debug("%s: load instruction from guest address %lx failed\n", 967 __func__, vcpu->arch.regs.nip); 968 /* For debugging, encode the failing instruction and 969 * report it to userspace. */ 970 vcpu->run->hw.hardware_exit_reason = ~0ULL << 32; 971 vcpu->run->hw.hardware_exit_reason |= last_inst; 972 kvmppc_core_queue_program(vcpu, ESR_PIL); 973 return RESUME_HOST; 974 975 default: 976 BUG(); 977 } 978 } 979 980 /** 981 * kvmppc_handle_exit 982 * 983 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV) 984 */ 985 int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, 986 unsigned int exit_nr) 987 { 988 int r = RESUME_HOST; 989 int s; 990 int idx; 991 u32 last_inst = KVM_INST_FETCH_FAILED; 992 enum emulation_result emulated = EMULATE_DONE; 993 994 /* update before a new last_exit_type is rewritten */ 995 kvmppc_update_timing_stats(vcpu); 996 997 /* restart interrupts if they were meant for the host */ 998 kvmppc_restart_interrupt(vcpu, exit_nr); 999 1000 /* 1001 * get last instruction before being preempted 1002 * TODO: for e6500 check also BOOKE_INTERRUPT_LRAT_ERROR & ESR_DATA 1003 */ 1004 switch (exit_nr) { 1005 case BOOKE_INTERRUPT_DATA_STORAGE: 1006 case BOOKE_INTERRUPT_DTLB_MISS: 1007 case BOOKE_INTERRUPT_HV_PRIV: 1008 emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst); 1009 break; 1010 case BOOKE_INTERRUPT_PROGRAM: 1011 /* SW breakpoints arrive as illegal instructions on HV */ 1012 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) 1013 emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst); 1014 break; 1015 default: 1016 break; 1017 } 1018 1019 trace_kvm_exit(exit_nr, vcpu); 1020 guest_exit_irqoff(); 1021 1022 local_irq_enable(); 1023 1024 run->exit_reason = KVM_EXIT_UNKNOWN; 1025 run->ready_for_interrupt_injection = 1; 1026 1027 if (emulated != EMULATE_DONE) { 1028 r = kvmppc_resume_inst_load(vcpu, emulated, last_inst); 1029 goto out; 1030 } 1031 1032 switch (exit_nr) { 1033 case BOOKE_INTERRUPT_MACHINE_CHECK: 1034 printk("MACHINE CHECK: %lx\n", mfspr(SPRN_MCSR)); 1035 kvmppc_dump_vcpu(vcpu); 1036 /* For debugging, send invalid exit reason to user space */ 1037 run->hw.hardware_exit_reason = ~1ULL << 32; 1038 run->hw.hardware_exit_reason |= mfspr(SPRN_MCSR); 1039 r = RESUME_HOST; 1040 break; 1041 1042 case BOOKE_INTERRUPT_EXTERNAL: 1043 kvmppc_account_exit(vcpu, EXT_INTR_EXITS); 1044 r = RESUME_GUEST; 1045 break; 1046 1047 case BOOKE_INTERRUPT_DECREMENTER: 1048 kvmppc_account_exit(vcpu, DEC_EXITS); 1049 r = RESUME_GUEST; 1050 break; 1051 1052 case BOOKE_INTERRUPT_WATCHDOG: 1053 r = RESUME_GUEST; 1054 break; 1055 1056 case BOOKE_INTERRUPT_DOORBELL: 1057 kvmppc_account_exit(vcpu, DBELL_EXITS); 1058 r = RESUME_GUEST; 1059 break; 1060 1061 case BOOKE_INTERRUPT_GUEST_DBELL_CRIT: 1062 kvmppc_account_exit(vcpu, GDBELL_EXITS); 1063 1064 /* 1065 * We are here because there is a pending guest interrupt 1066 * which could not be delivered as MSR_CE or MSR_ME was not 1067 * set. Once we break from here we will retry delivery. 1068 */ 1069 r = RESUME_GUEST; 1070 break; 1071 1072 case BOOKE_INTERRUPT_GUEST_DBELL: 1073 kvmppc_account_exit(vcpu, GDBELL_EXITS); 1074 1075 /* 1076 * We are here because there is a pending guest interrupt 1077 * which could not be delivered as MSR_EE was not set. Once 1078 * we break from here we will retry delivery. 1079 */ 1080 r = RESUME_GUEST; 1081 break; 1082 1083 case BOOKE_INTERRUPT_PERFORMANCE_MONITOR: 1084 r = RESUME_GUEST; 1085 break; 1086 1087 case BOOKE_INTERRUPT_HV_PRIV: 1088 r = emulation_exit(vcpu); 1089 break; 1090 1091 case BOOKE_INTERRUPT_PROGRAM: 1092 if ((vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) && 1093 (last_inst == KVMPPC_INST_SW_BREAKPOINT)) { 1094 /* 1095 * We are here because of an SW breakpoint instr, 1096 * so lets return to host to handle. 1097 */ 1098 r = kvmppc_handle_debug(vcpu); 1099 run->exit_reason = KVM_EXIT_DEBUG; 1100 kvmppc_account_exit(vcpu, DEBUG_EXITS); 1101 break; 1102 } 1103 1104 if (vcpu->arch.shared->msr & (MSR_PR | MSR_GS)) { 1105 /* 1106 * Program traps generated by user-level software must 1107 * be handled by the guest kernel. 1108 * 1109 * In GS mode, hypervisor privileged instructions trap 1110 * on BOOKE_INTERRUPT_HV_PRIV, not here, so these are 1111 * actual program interrupts, handled by the guest. 1112 */ 1113 kvmppc_core_queue_program(vcpu, vcpu->arch.fault_esr); 1114 r = RESUME_GUEST; 1115 kvmppc_account_exit(vcpu, USR_PR_INST); 1116 break; 1117 } 1118 1119 r = emulation_exit(vcpu); 1120 break; 1121 1122 case BOOKE_INTERRUPT_FP_UNAVAIL: 1123 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_FP_UNAVAIL); 1124 kvmppc_account_exit(vcpu, FP_UNAVAIL); 1125 r = RESUME_GUEST; 1126 break; 1127 1128 #ifdef CONFIG_SPE 1129 case BOOKE_INTERRUPT_SPE_UNAVAIL: { 1130 if (vcpu->arch.shared->msr & MSR_SPE) 1131 kvmppc_vcpu_enable_spe(vcpu); 1132 else 1133 kvmppc_booke_queue_irqprio(vcpu, 1134 BOOKE_IRQPRIO_SPE_UNAVAIL); 1135 r = RESUME_GUEST; 1136 break; 1137 } 1138 1139 case BOOKE_INTERRUPT_SPE_FP_DATA: 1140 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_DATA); 1141 r = RESUME_GUEST; 1142 break; 1143 1144 case BOOKE_INTERRUPT_SPE_FP_ROUND: 1145 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_ROUND); 1146 r = RESUME_GUEST; 1147 break; 1148 #elif defined(CONFIG_SPE_POSSIBLE) 1149 case BOOKE_INTERRUPT_SPE_UNAVAIL: 1150 /* 1151 * Guest wants SPE, but host kernel doesn't support it. Send 1152 * an "unimplemented operation" program check to the guest. 1153 */ 1154 kvmppc_core_queue_program(vcpu, ESR_PUO | ESR_SPV); 1155 r = RESUME_GUEST; 1156 break; 1157 1158 /* 1159 * These really should never happen without CONFIG_SPE, 1160 * as we should never enable the real MSR[SPE] in the guest. 1161 */ 1162 case BOOKE_INTERRUPT_SPE_FP_DATA: 1163 case BOOKE_INTERRUPT_SPE_FP_ROUND: 1164 printk(KERN_CRIT "%s: unexpected SPE interrupt %u at %08lx\n", 1165 __func__, exit_nr, vcpu->arch.regs.nip); 1166 run->hw.hardware_exit_reason = exit_nr; 1167 r = RESUME_HOST; 1168 break; 1169 #endif /* CONFIG_SPE_POSSIBLE */ 1170 1171 /* 1172 * On cores with Vector category, KVM is loaded only if CONFIG_ALTIVEC, 1173 * see kvmppc_core_check_processor_compat(). 1174 */ 1175 #ifdef CONFIG_ALTIVEC 1176 case BOOKE_INTERRUPT_ALTIVEC_UNAVAIL: 1177 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALTIVEC_UNAVAIL); 1178 r = RESUME_GUEST; 1179 break; 1180 1181 case BOOKE_INTERRUPT_ALTIVEC_ASSIST: 1182 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALTIVEC_ASSIST); 1183 r = RESUME_GUEST; 1184 break; 1185 #endif 1186 1187 case BOOKE_INTERRUPT_DATA_STORAGE: 1188 kvmppc_core_queue_data_storage(vcpu, vcpu->arch.fault_dear, 1189 vcpu->arch.fault_esr); 1190 kvmppc_account_exit(vcpu, DSI_EXITS); 1191 r = RESUME_GUEST; 1192 break; 1193 1194 case BOOKE_INTERRUPT_INST_STORAGE: 1195 kvmppc_core_queue_inst_storage(vcpu, vcpu->arch.fault_esr); 1196 kvmppc_account_exit(vcpu, ISI_EXITS); 1197 r = RESUME_GUEST; 1198 break; 1199 1200 case BOOKE_INTERRUPT_ALIGNMENT: 1201 kvmppc_core_queue_alignment(vcpu, vcpu->arch.fault_dear, 1202 vcpu->arch.fault_esr); 1203 r = RESUME_GUEST; 1204 break; 1205 1206 #ifdef CONFIG_KVM_BOOKE_HV 1207 case BOOKE_INTERRUPT_HV_SYSCALL: 1208 if (!(vcpu->arch.shared->msr & MSR_PR)) { 1209 kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu)); 1210 } else { 1211 /* 1212 * hcall from guest userspace -- send privileged 1213 * instruction program check. 1214 */ 1215 kvmppc_core_queue_program(vcpu, ESR_PPR); 1216 } 1217 1218 r = RESUME_GUEST; 1219 break; 1220 #else 1221 case BOOKE_INTERRUPT_SYSCALL: 1222 if (!(vcpu->arch.shared->msr & MSR_PR) && 1223 (((u32)kvmppc_get_gpr(vcpu, 0)) == KVM_SC_MAGIC_R0)) { 1224 /* KVM PV hypercalls */ 1225 kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu)); 1226 r = RESUME_GUEST; 1227 } else { 1228 /* Guest syscalls */ 1229 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SYSCALL); 1230 } 1231 kvmppc_account_exit(vcpu, SYSCALL_EXITS); 1232 r = RESUME_GUEST; 1233 break; 1234 #endif 1235 1236 case BOOKE_INTERRUPT_DTLB_MISS: { 1237 unsigned long eaddr = vcpu->arch.fault_dear; 1238 int gtlb_index; 1239 gpa_t gpaddr; 1240 gfn_t gfn; 1241 1242 #ifdef CONFIG_KVM_E500V2 1243 if (!(vcpu->arch.shared->msr & MSR_PR) && 1244 (eaddr & PAGE_MASK) == vcpu->arch.magic_page_ea) { 1245 kvmppc_map_magic(vcpu); 1246 kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS); 1247 r = RESUME_GUEST; 1248 1249 break; 1250 } 1251 #endif 1252 1253 /* Check the guest TLB. */ 1254 gtlb_index = kvmppc_mmu_dtlb_index(vcpu, eaddr); 1255 if (gtlb_index < 0) { 1256 /* The guest didn't have a mapping for it. */ 1257 kvmppc_core_queue_dtlb_miss(vcpu, 1258 vcpu->arch.fault_dear, 1259 vcpu->arch.fault_esr); 1260 kvmppc_mmu_dtlb_miss(vcpu); 1261 kvmppc_account_exit(vcpu, DTLB_REAL_MISS_EXITS); 1262 r = RESUME_GUEST; 1263 break; 1264 } 1265 1266 idx = srcu_read_lock(&vcpu->kvm->srcu); 1267 1268 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr); 1269 gfn = gpaddr >> PAGE_SHIFT; 1270 1271 if (kvm_is_visible_gfn(vcpu->kvm, gfn)) { 1272 /* The guest TLB had a mapping, but the shadow TLB 1273 * didn't, and it is RAM. This could be because: 1274 * a) the entry is mapping the host kernel, or 1275 * b) the guest used a large mapping which we're faking 1276 * Either way, we need to satisfy the fault without 1277 * invoking the guest. */ 1278 kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index); 1279 kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS); 1280 r = RESUME_GUEST; 1281 } else { 1282 /* Guest has mapped and accessed a page which is not 1283 * actually RAM. */ 1284 vcpu->arch.paddr_accessed = gpaddr; 1285 vcpu->arch.vaddr_accessed = eaddr; 1286 r = kvmppc_emulate_mmio(vcpu); 1287 kvmppc_account_exit(vcpu, MMIO_EXITS); 1288 } 1289 1290 srcu_read_unlock(&vcpu->kvm->srcu, idx); 1291 break; 1292 } 1293 1294 case BOOKE_INTERRUPT_ITLB_MISS: { 1295 unsigned long eaddr = vcpu->arch.regs.nip; 1296 gpa_t gpaddr; 1297 gfn_t gfn; 1298 int gtlb_index; 1299 1300 r = RESUME_GUEST; 1301 1302 /* Check the guest TLB. */ 1303 gtlb_index = kvmppc_mmu_itlb_index(vcpu, eaddr); 1304 if (gtlb_index < 0) { 1305 /* The guest didn't have a mapping for it. */ 1306 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ITLB_MISS); 1307 kvmppc_mmu_itlb_miss(vcpu); 1308 kvmppc_account_exit(vcpu, ITLB_REAL_MISS_EXITS); 1309 break; 1310 } 1311 1312 kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS); 1313 1314 idx = srcu_read_lock(&vcpu->kvm->srcu); 1315 1316 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr); 1317 gfn = gpaddr >> PAGE_SHIFT; 1318 1319 if (kvm_is_visible_gfn(vcpu->kvm, gfn)) { 1320 /* The guest TLB had a mapping, but the shadow TLB 1321 * didn't. This could be because: 1322 * a) the entry is mapping the host kernel, or 1323 * b) the guest used a large mapping which we're faking 1324 * Either way, we need to satisfy the fault without 1325 * invoking the guest. */ 1326 kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index); 1327 } else { 1328 /* Guest mapped and leaped at non-RAM! */ 1329 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_MACHINE_CHECK); 1330 } 1331 1332 srcu_read_unlock(&vcpu->kvm->srcu, idx); 1333 break; 1334 } 1335 1336 case BOOKE_INTERRUPT_DEBUG: { 1337 r = kvmppc_handle_debug(vcpu); 1338 if (r == RESUME_HOST) 1339 run->exit_reason = KVM_EXIT_DEBUG; 1340 kvmppc_account_exit(vcpu, DEBUG_EXITS); 1341 break; 1342 } 1343 1344 default: 1345 printk(KERN_EMERG "exit_nr %d\n", exit_nr); 1346 BUG(); 1347 } 1348 1349 out: 1350 /* 1351 * To avoid clobbering exit_reason, only check for signals if we 1352 * aren't already exiting to userspace for some other reason. 1353 */ 1354 if (!(r & RESUME_HOST)) { 1355 s = kvmppc_prepare_to_enter(vcpu); 1356 if (s <= 0) 1357 r = (s << 2) | RESUME_HOST | (r & RESUME_FLAG_NV); 1358 else { 1359 /* interrupts now hard-disabled */ 1360 kvmppc_fix_ee_before_entry(); 1361 kvmppc_load_guest_fp(vcpu); 1362 kvmppc_load_guest_altivec(vcpu); 1363 } 1364 } 1365 1366 return r; 1367 } 1368 1369 static void kvmppc_set_tsr(struct kvm_vcpu *vcpu, u32 new_tsr) 1370 { 1371 u32 old_tsr = vcpu->arch.tsr; 1372 1373 vcpu->arch.tsr = new_tsr; 1374 1375 if ((old_tsr ^ vcpu->arch.tsr) & (TSR_ENW | TSR_WIS)) 1376 arm_next_watchdog(vcpu); 1377 1378 update_timer_ints(vcpu); 1379 } 1380 1381 int kvmppc_subarch_vcpu_init(struct kvm_vcpu *vcpu) 1382 { 1383 /* setup watchdog timer once */ 1384 spin_lock_init(&vcpu->arch.wdt_lock); 1385 timer_setup(&vcpu->arch.wdt_timer, kvmppc_watchdog_func, 0); 1386 1387 /* 1388 * Clear DBSR.MRR to avoid guest debug interrupt as 1389 * this is of host interest 1390 */ 1391 mtspr(SPRN_DBSR, DBSR_MRR); 1392 return 0; 1393 } 1394 1395 void kvmppc_subarch_vcpu_uninit(struct kvm_vcpu *vcpu) 1396 { 1397 del_timer_sync(&vcpu->arch.wdt_timer); 1398 } 1399 1400 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 1401 { 1402 int i; 1403 1404 vcpu_load(vcpu); 1405 1406 regs->pc = vcpu->arch.regs.nip; 1407 regs->cr = kvmppc_get_cr(vcpu); 1408 regs->ctr = vcpu->arch.regs.ctr; 1409 regs->lr = vcpu->arch.regs.link; 1410 regs->xer = kvmppc_get_xer(vcpu); 1411 regs->msr = vcpu->arch.shared->msr; 1412 regs->srr0 = kvmppc_get_srr0(vcpu); 1413 regs->srr1 = kvmppc_get_srr1(vcpu); 1414 regs->pid = vcpu->arch.pid; 1415 regs->sprg0 = kvmppc_get_sprg0(vcpu); 1416 regs->sprg1 = kvmppc_get_sprg1(vcpu); 1417 regs->sprg2 = kvmppc_get_sprg2(vcpu); 1418 regs->sprg3 = kvmppc_get_sprg3(vcpu); 1419 regs->sprg4 = kvmppc_get_sprg4(vcpu); 1420 regs->sprg5 = kvmppc_get_sprg5(vcpu); 1421 regs->sprg6 = kvmppc_get_sprg6(vcpu); 1422 regs->sprg7 = kvmppc_get_sprg7(vcpu); 1423 1424 for (i = 0; i < ARRAY_SIZE(regs->gpr); i++) 1425 regs->gpr[i] = kvmppc_get_gpr(vcpu, i); 1426 1427 vcpu_put(vcpu); 1428 return 0; 1429 } 1430 1431 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 1432 { 1433 int i; 1434 1435 vcpu_load(vcpu); 1436 1437 vcpu->arch.regs.nip = regs->pc; 1438 kvmppc_set_cr(vcpu, regs->cr); 1439 vcpu->arch.regs.ctr = regs->ctr; 1440 vcpu->arch.regs.link = regs->lr; 1441 kvmppc_set_xer(vcpu, regs->xer); 1442 kvmppc_set_msr(vcpu, regs->msr); 1443 kvmppc_set_srr0(vcpu, regs->srr0); 1444 kvmppc_set_srr1(vcpu, regs->srr1); 1445 kvmppc_set_pid(vcpu, regs->pid); 1446 kvmppc_set_sprg0(vcpu, regs->sprg0); 1447 kvmppc_set_sprg1(vcpu, regs->sprg1); 1448 kvmppc_set_sprg2(vcpu, regs->sprg2); 1449 kvmppc_set_sprg3(vcpu, regs->sprg3); 1450 kvmppc_set_sprg4(vcpu, regs->sprg4); 1451 kvmppc_set_sprg5(vcpu, regs->sprg5); 1452 kvmppc_set_sprg6(vcpu, regs->sprg6); 1453 kvmppc_set_sprg7(vcpu, regs->sprg7); 1454 1455 for (i = 0; i < ARRAY_SIZE(regs->gpr); i++) 1456 kvmppc_set_gpr(vcpu, i, regs->gpr[i]); 1457 1458 vcpu_put(vcpu); 1459 return 0; 1460 } 1461 1462 static void get_sregs_base(struct kvm_vcpu *vcpu, 1463 struct kvm_sregs *sregs) 1464 { 1465 u64 tb = get_tb(); 1466 1467 sregs->u.e.features |= KVM_SREGS_E_BASE; 1468 1469 sregs->u.e.csrr0 = vcpu->arch.csrr0; 1470 sregs->u.e.csrr1 = vcpu->arch.csrr1; 1471 sregs->u.e.mcsr = vcpu->arch.mcsr; 1472 sregs->u.e.esr = kvmppc_get_esr(vcpu); 1473 sregs->u.e.dear = kvmppc_get_dar(vcpu); 1474 sregs->u.e.tsr = vcpu->arch.tsr; 1475 sregs->u.e.tcr = vcpu->arch.tcr; 1476 sregs->u.e.dec = kvmppc_get_dec(vcpu, tb); 1477 sregs->u.e.tb = tb; 1478 sregs->u.e.vrsave = vcpu->arch.vrsave; 1479 } 1480 1481 static int set_sregs_base(struct kvm_vcpu *vcpu, 1482 struct kvm_sregs *sregs) 1483 { 1484 if (!(sregs->u.e.features & KVM_SREGS_E_BASE)) 1485 return 0; 1486 1487 vcpu->arch.csrr0 = sregs->u.e.csrr0; 1488 vcpu->arch.csrr1 = sregs->u.e.csrr1; 1489 vcpu->arch.mcsr = sregs->u.e.mcsr; 1490 kvmppc_set_esr(vcpu, sregs->u.e.esr); 1491 kvmppc_set_dar(vcpu, sregs->u.e.dear); 1492 vcpu->arch.vrsave = sregs->u.e.vrsave; 1493 kvmppc_set_tcr(vcpu, sregs->u.e.tcr); 1494 1495 if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_DEC) { 1496 vcpu->arch.dec = sregs->u.e.dec; 1497 kvmppc_emulate_dec(vcpu); 1498 } 1499 1500 if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_TSR) 1501 kvmppc_set_tsr(vcpu, sregs->u.e.tsr); 1502 1503 return 0; 1504 } 1505 1506 static void get_sregs_arch206(struct kvm_vcpu *vcpu, 1507 struct kvm_sregs *sregs) 1508 { 1509 sregs->u.e.features |= KVM_SREGS_E_ARCH206; 1510 1511 sregs->u.e.pir = vcpu->vcpu_id; 1512 sregs->u.e.mcsrr0 = vcpu->arch.mcsrr0; 1513 sregs->u.e.mcsrr1 = vcpu->arch.mcsrr1; 1514 sregs->u.e.decar = vcpu->arch.decar; 1515 sregs->u.e.ivpr = vcpu->arch.ivpr; 1516 } 1517 1518 static int set_sregs_arch206(struct kvm_vcpu *vcpu, 1519 struct kvm_sregs *sregs) 1520 { 1521 if (!(sregs->u.e.features & KVM_SREGS_E_ARCH206)) 1522 return 0; 1523 1524 if (sregs->u.e.pir != vcpu->vcpu_id) 1525 return -EINVAL; 1526 1527 vcpu->arch.mcsrr0 = sregs->u.e.mcsrr0; 1528 vcpu->arch.mcsrr1 = sregs->u.e.mcsrr1; 1529 vcpu->arch.decar = sregs->u.e.decar; 1530 vcpu->arch.ivpr = sregs->u.e.ivpr; 1531 1532 return 0; 1533 } 1534 1535 int kvmppc_get_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 1536 { 1537 sregs->u.e.features |= KVM_SREGS_E_IVOR; 1538 1539 sregs->u.e.ivor_low[0] = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL]; 1540 sregs->u.e.ivor_low[1] = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK]; 1541 sregs->u.e.ivor_low[2] = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE]; 1542 sregs->u.e.ivor_low[3] = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE]; 1543 sregs->u.e.ivor_low[4] = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL]; 1544 sregs->u.e.ivor_low[5] = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT]; 1545 sregs->u.e.ivor_low[6] = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM]; 1546 sregs->u.e.ivor_low[7] = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL]; 1547 sregs->u.e.ivor_low[8] = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL]; 1548 sregs->u.e.ivor_low[9] = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL]; 1549 sregs->u.e.ivor_low[10] = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER]; 1550 sregs->u.e.ivor_low[11] = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT]; 1551 sregs->u.e.ivor_low[12] = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG]; 1552 sregs->u.e.ivor_low[13] = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS]; 1553 sregs->u.e.ivor_low[14] = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS]; 1554 sregs->u.e.ivor_low[15] = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG]; 1555 return 0; 1556 } 1557 1558 int kvmppc_set_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 1559 { 1560 if (!(sregs->u.e.features & KVM_SREGS_E_IVOR)) 1561 return 0; 1562 1563 vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = sregs->u.e.ivor_low[0]; 1564 vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = sregs->u.e.ivor_low[1]; 1565 vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = sregs->u.e.ivor_low[2]; 1566 vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = sregs->u.e.ivor_low[3]; 1567 vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = sregs->u.e.ivor_low[4]; 1568 vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = sregs->u.e.ivor_low[5]; 1569 vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = sregs->u.e.ivor_low[6]; 1570 vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = sregs->u.e.ivor_low[7]; 1571 vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = sregs->u.e.ivor_low[8]; 1572 vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = sregs->u.e.ivor_low[9]; 1573 vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = sregs->u.e.ivor_low[10]; 1574 vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = sregs->u.e.ivor_low[11]; 1575 vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = sregs->u.e.ivor_low[12]; 1576 vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = sregs->u.e.ivor_low[13]; 1577 vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = sregs->u.e.ivor_low[14]; 1578 vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = sregs->u.e.ivor_low[15]; 1579 1580 return 0; 1581 } 1582 1583 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 1584 struct kvm_sregs *sregs) 1585 { 1586 int ret; 1587 1588 vcpu_load(vcpu); 1589 1590 sregs->pvr = vcpu->arch.pvr; 1591 1592 get_sregs_base(vcpu, sregs); 1593 get_sregs_arch206(vcpu, sregs); 1594 ret = vcpu->kvm->arch.kvm_ops->get_sregs(vcpu, sregs); 1595 1596 vcpu_put(vcpu); 1597 return ret; 1598 } 1599 1600 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 1601 struct kvm_sregs *sregs) 1602 { 1603 int ret = -EINVAL; 1604 1605 vcpu_load(vcpu); 1606 if (vcpu->arch.pvr != sregs->pvr) 1607 goto out; 1608 1609 ret = set_sregs_base(vcpu, sregs); 1610 if (ret < 0) 1611 goto out; 1612 1613 ret = set_sregs_arch206(vcpu, sregs); 1614 if (ret < 0) 1615 goto out; 1616 1617 ret = vcpu->kvm->arch.kvm_ops->set_sregs(vcpu, sregs); 1618 1619 out: 1620 vcpu_put(vcpu); 1621 return ret; 1622 } 1623 1624 int kvmppc_get_one_reg(struct kvm_vcpu *vcpu, u64 id, 1625 union kvmppc_one_reg *val) 1626 { 1627 int r = 0; 1628 1629 switch (id) { 1630 case KVM_REG_PPC_IAC1: 1631 *val = get_reg_val(id, vcpu->arch.dbg_reg.iac1); 1632 break; 1633 case KVM_REG_PPC_IAC2: 1634 *val = get_reg_val(id, vcpu->arch.dbg_reg.iac2); 1635 break; 1636 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 1637 case KVM_REG_PPC_IAC3: 1638 *val = get_reg_val(id, vcpu->arch.dbg_reg.iac3); 1639 break; 1640 case KVM_REG_PPC_IAC4: 1641 *val = get_reg_val(id, vcpu->arch.dbg_reg.iac4); 1642 break; 1643 #endif 1644 case KVM_REG_PPC_DAC1: 1645 *val = get_reg_val(id, vcpu->arch.dbg_reg.dac1); 1646 break; 1647 case KVM_REG_PPC_DAC2: 1648 *val = get_reg_val(id, vcpu->arch.dbg_reg.dac2); 1649 break; 1650 case KVM_REG_PPC_EPR: { 1651 u32 epr = kvmppc_get_epr(vcpu); 1652 *val = get_reg_val(id, epr); 1653 break; 1654 } 1655 #if defined(CONFIG_64BIT) 1656 case KVM_REG_PPC_EPCR: 1657 *val = get_reg_val(id, vcpu->arch.epcr); 1658 break; 1659 #endif 1660 case KVM_REG_PPC_TCR: 1661 *val = get_reg_val(id, vcpu->arch.tcr); 1662 break; 1663 case KVM_REG_PPC_TSR: 1664 *val = get_reg_val(id, vcpu->arch.tsr); 1665 break; 1666 case KVM_REG_PPC_DEBUG_INST: 1667 *val = get_reg_val(id, KVMPPC_INST_SW_BREAKPOINT); 1668 break; 1669 case KVM_REG_PPC_VRSAVE: 1670 *val = get_reg_val(id, vcpu->arch.vrsave); 1671 break; 1672 default: 1673 r = vcpu->kvm->arch.kvm_ops->get_one_reg(vcpu, id, val); 1674 break; 1675 } 1676 1677 return r; 1678 } 1679 1680 int kvmppc_set_one_reg(struct kvm_vcpu *vcpu, u64 id, 1681 union kvmppc_one_reg *val) 1682 { 1683 int r = 0; 1684 1685 switch (id) { 1686 case KVM_REG_PPC_IAC1: 1687 vcpu->arch.dbg_reg.iac1 = set_reg_val(id, *val); 1688 break; 1689 case KVM_REG_PPC_IAC2: 1690 vcpu->arch.dbg_reg.iac2 = set_reg_val(id, *val); 1691 break; 1692 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 1693 case KVM_REG_PPC_IAC3: 1694 vcpu->arch.dbg_reg.iac3 = set_reg_val(id, *val); 1695 break; 1696 case KVM_REG_PPC_IAC4: 1697 vcpu->arch.dbg_reg.iac4 = set_reg_val(id, *val); 1698 break; 1699 #endif 1700 case KVM_REG_PPC_DAC1: 1701 vcpu->arch.dbg_reg.dac1 = set_reg_val(id, *val); 1702 break; 1703 case KVM_REG_PPC_DAC2: 1704 vcpu->arch.dbg_reg.dac2 = set_reg_val(id, *val); 1705 break; 1706 case KVM_REG_PPC_EPR: { 1707 u32 new_epr = set_reg_val(id, *val); 1708 kvmppc_set_epr(vcpu, new_epr); 1709 break; 1710 } 1711 #if defined(CONFIG_64BIT) 1712 case KVM_REG_PPC_EPCR: { 1713 u32 new_epcr = set_reg_val(id, *val); 1714 kvmppc_set_epcr(vcpu, new_epcr); 1715 break; 1716 } 1717 #endif 1718 case KVM_REG_PPC_OR_TSR: { 1719 u32 tsr_bits = set_reg_val(id, *val); 1720 kvmppc_set_tsr_bits(vcpu, tsr_bits); 1721 break; 1722 } 1723 case KVM_REG_PPC_CLEAR_TSR: { 1724 u32 tsr_bits = set_reg_val(id, *val); 1725 kvmppc_clr_tsr_bits(vcpu, tsr_bits); 1726 break; 1727 } 1728 case KVM_REG_PPC_TSR: { 1729 u32 tsr = set_reg_val(id, *val); 1730 kvmppc_set_tsr(vcpu, tsr); 1731 break; 1732 } 1733 case KVM_REG_PPC_TCR: { 1734 u32 tcr = set_reg_val(id, *val); 1735 kvmppc_set_tcr(vcpu, tcr); 1736 break; 1737 } 1738 case KVM_REG_PPC_VRSAVE: 1739 vcpu->arch.vrsave = set_reg_val(id, *val); 1740 break; 1741 default: 1742 r = vcpu->kvm->arch.kvm_ops->set_one_reg(vcpu, id, val); 1743 break; 1744 } 1745 1746 return r; 1747 } 1748 1749 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 1750 { 1751 return -ENOTSUPP; 1752 } 1753 1754 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 1755 { 1756 return -ENOTSUPP; 1757 } 1758 1759 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 1760 struct kvm_translation *tr) 1761 { 1762 int r; 1763 1764 vcpu_load(vcpu); 1765 r = kvmppc_core_vcpu_translate(vcpu, tr); 1766 vcpu_put(vcpu); 1767 return r; 1768 } 1769 1770 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) 1771 { 1772 1773 } 1774 1775 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 1776 { 1777 return -ENOTSUPP; 1778 } 1779 1780 void kvmppc_core_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) 1781 { 1782 } 1783 1784 int kvmppc_core_prepare_memory_region(struct kvm *kvm, 1785 struct kvm_memory_slot *memslot, 1786 const struct kvm_userspace_memory_region *mem, 1787 enum kvm_mr_change change) 1788 { 1789 return 0; 1790 } 1791 1792 void kvmppc_core_commit_memory_region(struct kvm *kvm, 1793 const struct kvm_userspace_memory_region *mem, 1794 const struct kvm_memory_slot *old, 1795 const struct kvm_memory_slot *new, 1796 enum kvm_mr_change change) 1797 { 1798 } 1799 1800 void kvmppc_core_flush_memslot(struct kvm *kvm, struct kvm_memory_slot *memslot) 1801 { 1802 } 1803 1804 void kvmppc_set_epcr(struct kvm_vcpu *vcpu, u32 new_epcr) 1805 { 1806 #if defined(CONFIG_64BIT) 1807 vcpu->arch.epcr = new_epcr; 1808 #ifdef CONFIG_KVM_BOOKE_HV 1809 vcpu->arch.shadow_epcr &= ~SPRN_EPCR_GICM; 1810 if (vcpu->arch.epcr & SPRN_EPCR_ICM) 1811 vcpu->arch.shadow_epcr |= SPRN_EPCR_GICM; 1812 #endif 1813 #endif 1814 } 1815 1816 void kvmppc_set_tcr(struct kvm_vcpu *vcpu, u32 new_tcr) 1817 { 1818 vcpu->arch.tcr = new_tcr; 1819 arm_next_watchdog(vcpu); 1820 update_timer_ints(vcpu); 1821 } 1822 1823 void kvmppc_set_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits) 1824 { 1825 set_bits(tsr_bits, &vcpu->arch.tsr); 1826 smp_wmb(); 1827 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1828 kvm_vcpu_kick(vcpu); 1829 } 1830 1831 void kvmppc_clr_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits) 1832 { 1833 clear_bits(tsr_bits, &vcpu->arch.tsr); 1834 1835 /* 1836 * We may have stopped the watchdog due to 1837 * being stuck on final expiration. 1838 */ 1839 if (tsr_bits & (TSR_ENW | TSR_WIS)) 1840 arm_next_watchdog(vcpu); 1841 1842 update_timer_ints(vcpu); 1843 } 1844 1845 void kvmppc_decrementer_func(struct kvm_vcpu *vcpu) 1846 { 1847 if (vcpu->arch.tcr & TCR_ARE) { 1848 vcpu->arch.dec = vcpu->arch.decar; 1849 kvmppc_emulate_dec(vcpu); 1850 } 1851 1852 kvmppc_set_tsr_bits(vcpu, TSR_DIS); 1853 } 1854 1855 static int kvmppc_booke_add_breakpoint(struct debug_reg *dbg_reg, 1856 uint64_t addr, int index) 1857 { 1858 switch (index) { 1859 case 0: 1860 dbg_reg->dbcr0 |= DBCR0_IAC1; 1861 dbg_reg->iac1 = addr; 1862 break; 1863 case 1: 1864 dbg_reg->dbcr0 |= DBCR0_IAC2; 1865 dbg_reg->iac2 = addr; 1866 break; 1867 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 1868 case 2: 1869 dbg_reg->dbcr0 |= DBCR0_IAC3; 1870 dbg_reg->iac3 = addr; 1871 break; 1872 case 3: 1873 dbg_reg->dbcr0 |= DBCR0_IAC4; 1874 dbg_reg->iac4 = addr; 1875 break; 1876 #endif 1877 default: 1878 return -EINVAL; 1879 } 1880 1881 dbg_reg->dbcr0 |= DBCR0_IDM; 1882 return 0; 1883 } 1884 1885 static int kvmppc_booke_add_watchpoint(struct debug_reg *dbg_reg, uint64_t addr, 1886 int type, int index) 1887 { 1888 switch (index) { 1889 case 0: 1890 if (type & KVMPPC_DEBUG_WATCH_READ) 1891 dbg_reg->dbcr0 |= DBCR0_DAC1R; 1892 if (type & KVMPPC_DEBUG_WATCH_WRITE) 1893 dbg_reg->dbcr0 |= DBCR0_DAC1W; 1894 dbg_reg->dac1 = addr; 1895 break; 1896 case 1: 1897 if (type & KVMPPC_DEBUG_WATCH_READ) 1898 dbg_reg->dbcr0 |= DBCR0_DAC2R; 1899 if (type & KVMPPC_DEBUG_WATCH_WRITE) 1900 dbg_reg->dbcr0 |= DBCR0_DAC2W; 1901 dbg_reg->dac2 = addr; 1902 break; 1903 default: 1904 return -EINVAL; 1905 } 1906 1907 dbg_reg->dbcr0 |= DBCR0_IDM; 1908 return 0; 1909 } 1910 void kvm_guest_protect_msr(struct kvm_vcpu *vcpu, ulong prot_bitmap, bool set) 1911 { 1912 /* XXX: Add similar MSR protection for BookE-PR */ 1913 #ifdef CONFIG_KVM_BOOKE_HV 1914 BUG_ON(prot_bitmap & ~(MSRP_UCLEP | MSRP_DEP | MSRP_PMMP)); 1915 if (set) { 1916 if (prot_bitmap & MSR_UCLE) 1917 vcpu->arch.shadow_msrp |= MSRP_UCLEP; 1918 if (prot_bitmap & MSR_DE) 1919 vcpu->arch.shadow_msrp |= MSRP_DEP; 1920 if (prot_bitmap & MSR_PMM) 1921 vcpu->arch.shadow_msrp |= MSRP_PMMP; 1922 } else { 1923 if (prot_bitmap & MSR_UCLE) 1924 vcpu->arch.shadow_msrp &= ~MSRP_UCLEP; 1925 if (prot_bitmap & MSR_DE) 1926 vcpu->arch.shadow_msrp &= ~MSRP_DEP; 1927 if (prot_bitmap & MSR_PMM) 1928 vcpu->arch.shadow_msrp &= ~MSRP_PMMP; 1929 } 1930 #endif 1931 } 1932 1933 int kvmppc_xlate(struct kvm_vcpu *vcpu, ulong eaddr, enum xlate_instdata xlid, 1934 enum xlate_readwrite xlrw, struct kvmppc_pte *pte) 1935 { 1936 int gtlb_index; 1937 gpa_t gpaddr; 1938 1939 #ifdef CONFIG_KVM_E500V2 1940 if (!(vcpu->arch.shared->msr & MSR_PR) && 1941 (eaddr & PAGE_MASK) == vcpu->arch.magic_page_ea) { 1942 pte->eaddr = eaddr; 1943 pte->raddr = (vcpu->arch.magic_page_pa & PAGE_MASK) | 1944 (eaddr & ~PAGE_MASK); 1945 pte->vpage = eaddr >> PAGE_SHIFT; 1946 pte->may_read = true; 1947 pte->may_write = true; 1948 pte->may_execute = true; 1949 1950 return 0; 1951 } 1952 #endif 1953 1954 /* Check the guest TLB. */ 1955 switch (xlid) { 1956 case XLATE_INST: 1957 gtlb_index = kvmppc_mmu_itlb_index(vcpu, eaddr); 1958 break; 1959 case XLATE_DATA: 1960 gtlb_index = kvmppc_mmu_dtlb_index(vcpu, eaddr); 1961 break; 1962 default: 1963 BUG(); 1964 } 1965 1966 /* Do we have a TLB entry at all? */ 1967 if (gtlb_index < 0) 1968 return -ENOENT; 1969 1970 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr); 1971 1972 pte->eaddr = eaddr; 1973 pte->raddr = (gpaddr & PAGE_MASK) | (eaddr & ~PAGE_MASK); 1974 pte->vpage = eaddr >> PAGE_SHIFT; 1975 1976 /* XXX read permissions from the guest TLB */ 1977 pte->may_read = true; 1978 pte->may_write = true; 1979 pte->may_execute = true; 1980 1981 return 0; 1982 } 1983 1984 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 1985 struct kvm_guest_debug *dbg) 1986 { 1987 struct debug_reg *dbg_reg; 1988 int n, b = 0, w = 0; 1989 int ret = 0; 1990 1991 vcpu_load(vcpu); 1992 1993 if (!(dbg->control & KVM_GUESTDBG_ENABLE)) { 1994 vcpu->arch.dbg_reg.dbcr0 = 0; 1995 vcpu->guest_debug = 0; 1996 kvm_guest_protect_msr(vcpu, MSR_DE, false); 1997 goto out; 1998 } 1999 2000 kvm_guest_protect_msr(vcpu, MSR_DE, true); 2001 vcpu->guest_debug = dbg->control; 2002 vcpu->arch.dbg_reg.dbcr0 = 0; 2003 2004 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 2005 vcpu->arch.dbg_reg.dbcr0 |= DBCR0_IDM | DBCR0_IC; 2006 2007 /* Code below handles only HW breakpoints */ 2008 dbg_reg = &(vcpu->arch.dbg_reg); 2009 2010 #ifdef CONFIG_KVM_BOOKE_HV 2011 /* 2012 * On BookE-HV (e500mc) the guest is always executed with MSR.GS=1 2013 * DBCR1 and DBCR2 are set to trigger debug events when MSR.PR is 0 2014 */ 2015 dbg_reg->dbcr1 = 0; 2016 dbg_reg->dbcr2 = 0; 2017 #else 2018 /* 2019 * On BookE-PR (e500v2) the guest is always executed with MSR.PR=1 2020 * We set DBCR1 and DBCR2 to only trigger debug events when MSR.PR 2021 * is set. 2022 */ 2023 dbg_reg->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | DBCR1_IAC3US | 2024 DBCR1_IAC4US; 2025 dbg_reg->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; 2026 #endif 2027 2028 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 2029 goto out; 2030 2031 ret = -EINVAL; 2032 for (n = 0; n < (KVMPPC_BOOKE_IAC_NUM + KVMPPC_BOOKE_DAC_NUM); n++) { 2033 uint64_t addr = dbg->arch.bp[n].addr; 2034 uint32_t type = dbg->arch.bp[n].type; 2035 2036 if (type == KVMPPC_DEBUG_NONE) 2037 continue; 2038 2039 if (type & ~(KVMPPC_DEBUG_WATCH_READ | 2040 KVMPPC_DEBUG_WATCH_WRITE | 2041 KVMPPC_DEBUG_BREAKPOINT)) 2042 goto out; 2043 2044 if (type & KVMPPC_DEBUG_BREAKPOINT) { 2045 /* Setting H/W breakpoint */ 2046 if (kvmppc_booke_add_breakpoint(dbg_reg, addr, b++)) 2047 goto out; 2048 } else { 2049 /* Setting H/W watchpoint */ 2050 if (kvmppc_booke_add_watchpoint(dbg_reg, addr, 2051 type, w++)) 2052 goto out; 2053 } 2054 } 2055 2056 ret = 0; 2057 out: 2058 vcpu_put(vcpu); 2059 return ret; 2060 } 2061 2062 void kvmppc_booke_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 2063 { 2064 vcpu->cpu = smp_processor_id(); 2065 current->thread.kvm_vcpu = vcpu; 2066 } 2067 2068 void kvmppc_booke_vcpu_put(struct kvm_vcpu *vcpu) 2069 { 2070 current->thread.kvm_vcpu = NULL; 2071 vcpu->cpu = -1; 2072 2073 /* Clear pending debug event in DBSR */ 2074 kvmppc_clear_dbsr(); 2075 } 2076 2077 int kvmppc_core_init_vm(struct kvm *kvm) 2078 { 2079 return kvm->arch.kvm_ops->init_vm(kvm); 2080 } 2081 2082 int kvmppc_core_vcpu_create(struct kvm_vcpu *vcpu) 2083 { 2084 int i; 2085 int r; 2086 2087 r = vcpu->kvm->arch.kvm_ops->vcpu_create(vcpu); 2088 if (r) 2089 return r; 2090 2091 /* Initial guest state: 16MB mapping 0 -> 0, PC = 0, MSR = 0, R1 = 16MB */ 2092 vcpu->arch.regs.nip = 0; 2093 vcpu->arch.shared->pir = vcpu->vcpu_id; 2094 kvmppc_set_gpr(vcpu, 1, (16<<20) - 8); /* -8 for the callee-save LR slot */ 2095 kvmppc_set_msr(vcpu, 0); 2096 2097 #ifndef CONFIG_KVM_BOOKE_HV 2098 vcpu->arch.shadow_msr = MSR_USER | MSR_IS | MSR_DS; 2099 vcpu->arch.shadow_pid = 1; 2100 vcpu->arch.shared->msr = 0; 2101 #endif 2102 2103 /* Eye-catching numbers so we know if the guest takes an interrupt 2104 * before it's programmed its own IVPR/IVORs. */ 2105 vcpu->arch.ivpr = 0x55550000; 2106 for (i = 0; i < BOOKE_IRQPRIO_MAX; i++) 2107 vcpu->arch.ivor[i] = 0x7700 | i * 4; 2108 2109 kvmppc_init_timing_stats(vcpu); 2110 2111 r = kvmppc_core_vcpu_setup(vcpu); 2112 if (r) 2113 vcpu->kvm->arch.kvm_ops->vcpu_free(vcpu); 2114 kvmppc_sanity_check(vcpu); 2115 return r; 2116 } 2117 2118 void kvmppc_core_vcpu_free(struct kvm_vcpu *vcpu) 2119 { 2120 vcpu->kvm->arch.kvm_ops->vcpu_free(vcpu); 2121 } 2122 2123 void kvmppc_core_destroy_vm(struct kvm *kvm) 2124 { 2125 kvm->arch.kvm_ops->destroy_vm(kvm); 2126 } 2127 2128 void kvmppc_core_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 2129 { 2130 vcpu->kvm->arch.kvm_ops->vcpu_load(vcpu, cpu); 2131 } 2132 2133 void kvmppc_core_vcpu_put(struct kvm_vcpu *vcpu) 2134 { 2135 vcpu->kvm->arch.kvm_ops->vcpu_put(vcpu); 2136 } 2137 2138 int __init kvmppc_booke_init(void) 2139 { 2140 #ifndef CONFIG_KVM_BOOKE_HV 2141 unsigned long ivor[16]; 2142 unsigned long *handler = kvmppc_booke_handler_addr; 2143 unsigned long max_ivor = 0; 2144 unsigned long handler_len; 2145 int i; 2146 2147 /* We install our own exception handlers by hijacking IVPR. IVPR must 2148 * be 16-bit aligned, so we need a 64KB allocation. */ 2149 kvmppc_booke_handlers = __get_free_pages(GFP_KERNEL | __GFP_ZERO, 2150 VCPU_SIZE_ORDER); 2151 if (!kvmppc_booke_handlers) 2152 return -ENOMEM; 2153 2154 /* XXX make sure our handlers are smaller than Linux's */ 2155 2156 /* Copy our interrupt handlers to match host IVORs. That way we don't 2157 * have to swap the IVORs on every guest/host transition. */ 2158 ivor[0] = mfspr(SPRN_IVOR0); 2159 ivor[1] = mfspr(SPRN_IVOR1); 2160 ivor[2] = mfspr(SPRN_IVOR2); 2161 ivor[3] = mfspr(SPRN_IVOR3); 2162 ivor[4] = mfspr(SPRN_IVOR4); 2163 ivor[5] = mfspr(SPRN_IVOR5); 2164 ivor[6] = mfspr(SPRN_IVOR6); 2165 ivor[7] = mfspr(SPRN_IVOR7); 2166 ivor[8] = mfspr(SPRN_IVOR8); 2167 ivor[9] = mfspr(SPRN_IVOR9); 2168 ivor[10] = mfspr(SPRN_IVOR10); 2169 ivor[11] = mfspr(SPRN_IVOR11); 2170 ivor[12] = mfspr(SPRN_IVOR12); 2171 ivor[13] = mfspr(SPRN_IVOR13); 2172 ivor[14] = mfspr(SPRN_IVOR14); 2173 ivor[15] = mfspr(SPRN_IVOR15); 2174 2175 for (i = 0; i < 16; i++) { 2176 if (ivor[i] > max_ivor) 2177 max_ivor = i; 2178 2179 handler_len = handler[i + 1] - handler[i]; 2180 memcpy((void *)kvmppc_booke_handlers + ivor[i], 2181 (void *)handler[i], handler_len); 2182 } 2183 2184 handler_len = handler[max_ivor + 1] - handler[max_ivor]; 2185 flush_icache_range(kvmppc_booke_handlers, kvmppc_booke_handlers + 2186 ivor[max_ivor] + handler_len); 2187 #endif /* !BOOKE_HV */ 2188 return 0; 2189 } 2190 2191 void __exit kvmppc_booke_exit(void) 2192 { 2193 free_pages(kvmppc_booke_handlers, VCPU_SIZE_ORDER); 2194 kvm_exit(); 2195 } 2196