1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2009. SUSE Linux Products GmbH. All rights reserved. 4 * 5 * Authors: 6 * Alexander Graf <agraf@suse.de> 7 * Kevin Wolf <mail@kevin-wolf.de> 8 * Paul Mackerras <paulus@samba.org> 9 * 10 * Description: 11 * Functions relating to running KVM on Book 3S processors where 12 * we don't have access to hypervisor mode, and we run the guest 13 * in problem state (user mode). 14 * 15 * This file is derived from arch/powerpc/kvm/44x.c, 16 * by Hollis Blanchard <hollisb@us.ibm.com>. 17 */ 18 19 #include <linux/kvm_host.h> 20 #include <linux/export.h> 21 #include <linux/err.h> 22 #include <linux/slab.h> 23 24 #include <asm/reg.h> 25 #include <asm/cputable.h> 26 #include <asm/cacheflush.h> 27 #include <linux/uaccess.h> 28 #include <asm/interrupt.h> 29 #include <asm/io.h> 30 #include <asm/kvm_ppc.h> 31 #include <asm/kvm_book3s.h> 32 #include <asm/mmu_context.h> 33 #include <asm/switch_to.h> 34 #include <asm/firmware.h> 35 #include <asm/setup.h> 36 #include <linux/gfp.h> 37 #include <linux/sched.h> 38 #include <linux/vmalloc.h> 39 #include <linux/highmem.h> 40 #include <linux/module.h> 41 #include <linux/miscdevice.h> 42 #include <asm/asm-prototypes.h> 43 #include <asm/tm.h> 44 45 #include "book3s.h" 46 47 #define CREATE_TRACE_POINTS 48 #include "trace_pr.h" 49 50 /* #define EXIT_DEBUG */ 51 /* #define DEBUG_EXT */ 52 53 static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr, 54 ulong msr); 55 #ifdef CONFIG_PPC_BOOK3S_64 56 static int kvmppc_handle_fac(struct kvm_vcpu *vcpu, ulong fac); 57 #endif 58 59 /* Some compatibility defines */ 60 #ifdef CONFIG_PPC_BOOK3S_32 61 #define MSR_USER32 MSR_USER 62 #define MSR_USER64 MSR_USER 63 #define HW_PAGE_SIZE PAGE_SIZE 64 #define HPTE_R_M _PAGE_COHERENT 65 #endif 66 67 static bool kvmppc_is_split_real(struct kvm_vcpu *vcpu) 68 { 69 ulong msr = kvmppc_get_msr(vcpu); 70 return (msr & (MSR_IR|MSR_DR)) == MSR_DR; 71 } 72 73 static void kvmppc_fixup_split_real(struct kvm_vcpu *vcpu) 74 { 75 ulong msr = kvmppc_get_msr(vcpu); 76 ulong pc = kvmppc_get_pc(vcpu); 77 78 /* We are in DR only split real mode */ 79 if ((msr & (MSR_IR|MSR_DR)) != MSR_DR) 80 return; 81 82 /* We have not fixed up the guest already */ 83 if (vcpu->arch.hflags & BOOK3S_HFLAG_SPLIT_HACK) 84 return; 85 86 /* The code is in fixupable address space */ 87 if (pc & SPLIT_HACK_MASK) 88 return; 89 90 vcpu->arch.hflags |= BOOK3S_HFLAG_SPLIT_HACK; 91 kvmppc_set_pc(vcpu, pc | SPLIT_HACK_OFFS); 92 } 93 94 static void kvmppc_unfixup_split_real(struct kvm_vcpu *vcpu) 95 { 96 if (vcpu->arch.hflags & BOOK3S_HFLAG_SPLIT_HACK) { 97 ulong pc = kvmppc_get_pc(vcpu); 98 ulong lr = kvmppc_get_lr(vcpu); 99 if ((pc & SPLIT_HACK_MASK) == SPLIT_HACK_OFFS) 100 kvmppc_set_pc(vcpu, pc & ~SPLIT_HACK_MASK); 101 if ((lr & SPLIT_HACK_MASK) == SPLIT_HACK_OFFS) 102 kvmppc_set_lr(vcpu, lr & ~SPLIT_HACK_MASK); 103 vcpu->arch.hflags &= ~BOOK3S_HFLAG_SPLIT_HACK; 104 } 105 } 106 107 static void kvmppc_inject_interrupt_pr(struct kvm_vcpu *vcpu, int vec, u64 srr1_flags) 108 { 109 unsigned long msr, pc, new_msr, new_pc; 110 111 kvmppc_unfixup_split_real(vcpu); 112 113 msr = kvmppc_get_msr(vcpu); 114 pc = kvmppc_get_pc(vcpu); 115 new_msr = vcpu->arch.intr_msr; 116 new_pc = to_book3s(vcpu)->hior + vec; 117 118 #ifdef CONFIG_PPC_BOOK3S_64 119 /* If transactional, change to suspend mode on IRQ delivery */ 120 if (MSR_TM_TRANSACTIONAL(msr)) 121 new_msr |= MSR_TS_S; 122 else 123 new_msr |= msr & MSR_TS_MASK; 124 #endif 125 126 kvmppc_set_srr0(vcpu, pc); 127 kvmppc_set_srr1(vcpu, (msr & SRR1_MSR_BITS) | srr1_flags); 128 kvmppc_set_pc(vcpu, new_pc); 129 kvmppc_set_msr(vcpu, new_msr); 130 } 131 132 static void kvmppc_core_vcpu_load_pr(struct kvm_vcpu *vcpu, int cpu) 133 { 134 #ifdef CONFIG_PPC_BOOK3S_64 135 struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu); 136 memcpy(svcpu->slb, to_book3s(vcpu)->slb_shadow, sizeof(svcpu->slb)); 137 svcpu->slb_max = to_book3s(vcpu)->slb_shadow_max; 138 svcpu->in_use = 0; 139 svcpu_put(svcpu); 140 141 /* Disable AIL if supported */ 142 if (cpu_has_feature(CPU_FTR_HVMODE)) { 143 if (cpu_has_feature(CPU_FTR_ARCH_207S)) 144 mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) & ~LPCR_AIL); 145 if (cpu_has_feature(CPU_FTR_ARCH_300) && (current->thread.fscr & FSCR_SCV)) 146 mtspr(SPRN_FSCR, mfspr(SPRN_FSCR) & ~FSCR_SCV); 147 } 148 #endif 149 150 vcpu->cpu = smp_processor_id(); 151 #ifdef CONFIG_PPC_BOOK3S_32 152 current->thread.kvm_shadow_vcpu = vcpu->arch.shadow_vcpu; 153 #endif 154 155 if (kvmppc_is_split_real(vcpu)) 156 kvmppc_fixup_split_real(vcpu); 157 158 kvmppc_restore_tm_pr(vcpu); 159 } 160 161 static void kvmppc_core_vcpu_put_pr(struct kvm_vcpu *vcpu) 162 { 163 #ifdef CONFIG_PPC_BOOK3S_64 164 struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu); 165 if (svcpu->in_use) { 166 kvmppc_copy_from_svcpu(vcpu); 167 } 168 memcpy(to_book3s(vcpu)->slb_shadow, svcpu->slb, sizeof(svcpu->slb)); 169 to_book3s(vcpu)->slb_shadow_max = svcpu->slb_max; 170 svcpu_put(svcpu); 171 172 /* Enable AIL if supported */ 173 if (cpu_has_feature(CPU_FTR_HVMODE)) { 174 if (cpu_has_feature(CPU_FTR_ARCH_207S)) 175 mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) | LPCR_AIL_3); 176 if (cpu_has_feature(CPU_FTR_ARCH_300) && (current->thread.fscr & FSCR_SCV)) 177 mtspr(SPRN_FSCR, mfspr(SPRN_FSCR) | FSCR_SCV); 178 } 179 #endif 180 181 if (kvmppc_is_split_real(vcpu)) 182 kvmppc_unfixup_split_real(vcpu); 183 184 kvmppc_giveup_ext(vcpu, MSR_FP | MSR_VEC | MSR_VSX); 185 kvmppc_giveup_fac(vcpu, FSCR_TAR_LG); 186 kvmppc_save_tm_pr(vcpu); 187 188 vcpu->cpu = -1; 189 } 190 191 /* Copy data needed by real-mode code from vcpu to shadow vcpu */ 192 void kvmppc_copy_to_svcpu(struct kvm_vcpu *vcpu) 193 { 194 struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu); 195 196 svcpu->gpr[0] = vcpu->arch.regs.gpr[0]; 197 svcpu->gpr[1] = vcpu->arch.regs.gpr[1]; 198 svcpu->gpr[2] = vcpu->arch.regs.gpr[2]; 199 svcpu->gpr[3] = vcpu->arch.regs.gpr[3]; 200 svcpu->gpr[4] = vcpu->arch.regs.gpr[4]; 201 svcpu->gpr[5] = vcpu->arch.regs.gpr[5]; 202 svcpu->gpr[6] = vcpu->arch.regs.gpr[6]; 203 svcpu->gpr[7] = vcpu->arch.regs.gpr[7]; 204 svcpu->gpr[8] = vcpu->arch.regs.gpr[8]; 205 svcpu->gpr[9] = vcpu->arch.regs.gpr[9]; 206 svcpu->gpr[10] = vcpu->arch.regs.gpr[10]; 207 svcpu->gpr[11] = vcpu->arch.regs.gpr[11]; 208 svcpu->gpr[12] = vcpu->arch.regs.gpr[12]; 209 svcpu->gpr[13] = vcpu->arch.regs.gpr[13]; 210 svcpu->cr = vcpu->arch.regs.ccr; 211 svcpu->xer = vcpu->arch.regs.xer; 212 svcpu->ctr = vcpu->arch.regs.ctr; 213 svcpu->lr = vcpu->arch.regs.link; 214 svcpu->pc = vcpu->arch.regs.nip; 215 #ifdef CONFIG_PPC_BOOK3S_64 216 svcpu->shadow_fscr = vcpu->arch.shadow_fscr; 217 #endif 218 /* 219 * Now also save the current time base value. We use this 220 * to find the guest purr and spurr value. 221 */ 222 vcpu->arch.entry_tb = get_tb(); 223 vcpu->arch.entry_vtb = get_vtb(); 224 if (cpu_has_feature(CPU_FTR_ARCH_207S)) 225 vcpu->arch.entry_ic = mfspr(SPRN_IC); 226 svcpu->in_use = true; 227 228 svcpu_put(svcpu); 229 } 230 231 static void kvmppc_recalc_shadow_msr(struct kvm_vcpu *vcpu) 232 { 233 ulong guest_msr = kvmppc_get_msr(vcpu); 234 ulong smsr = guest_msr; 235 236 /* Guest MSR values */ 237 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 238 smsr &= MSR_FE0 | MSR_FE1 | MSR_SF | MSR_SE | MSR_BE | MSR_LE | 239 MSR_TM | MSR_TS_MASK; 240 #else 241 smsr &= MSR_FE0 | MSR_FE1 | MSR_SF | MSR_SE | MSR_BE | MSR_LE; 242 #endif 243 /* Process MSR values */ 244 smsr |= MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_PR | MSR_EE; 245 /* External providers the guest reserved */ 246 smsr |= (guest_msr & vcpu->arch.guest_owned_ext); 247 /* 64-bit Process MSR values */ 248 #ifdef CONFIG_PPC_BOOK3S_64 249 smsr |= MSR_HV; 250 #endif 251 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 252 /* 253 * in guest privileged state, we want to fail all TM transactions. 254 * So disable MSR TM bit so that all tbegin. will be able to be 255 * trapped into host. 256 */ 257 if (!(guest_msr & MSR_PR)) 258 smsr &= ~MSR_TM; 259 #endif 260 vcpu->arch.shadow_msr = smsr; 261 } 262 263 /* Copy data touched by real-mode code from shadow vcpu back to vcpu */ 264 void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu) 265 { 266 struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu); 267 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 268 ulong old_msr; 269 #endif 270 271 /* 272 * Maybe we were already preempted and synced the svcpu from 273 * our preempt notifiers. Don't bother touching this svcpu then. 274 */ 275 if (!svcpu->in_use) 276 goto out; 277 278 vcpu->arch.regs.gpr[0] = svcpu->gpr[0]; 279 vcpu->arch.regs.gpr[1] = svcpu->gpr[1]; 280 vcpu->arch.regs.gpr[2] = svcpu->gpr[2]; 281 vcpu->arch.regs.gpr[3] = svcpu->gpr[3]; 282 vcpu->arch.regs.gpr[4] = svcpu->gpr[4]; 283 vcpu->arch.regs.gpr[5] = svcpu->gpr[5]; 284 vcpu->arch.regs.gpr[6] = svcpu->gpr[6]; 285 vcpu->arch.regs.gpr[7] = svcpu->gpr[7]; 286 vcpu->arch.regs.gpr[8] = svcpu->gpr[8]; 287 vcpu->arch.regs.gpr[9] = svcpu->gpr[9]; 288 vcpu->arch.regs.gpr[10] = svcpu->gpr[10]; 289 vcpu->arch.regs.gpr[11] = svcpu->gpr[11]; 290 vcpu->arch.regs.gpr[12] = svcpu->gpr[12]; 291 vcpu->arch.regs.gpr[13] = svcpu->gpr[13]; 292 vcpu->arch.regs.ccr = svcpu->cr; 293 vcpu->arch.regs.xer = svcpu->xer; 294 vcpu->arch.regs.ctr = svcpu->ctr; 295 vcpu->arch.regs.link = svcpu->lr; 296 vcpu->arch.regs.nip = svcpu->pc; 297 vcpu->arch.shadow_srr1 = svcpu->shadow_srr1; 298 vcpu->arch.fault_dar = svcpu->fault_dar; 299 vcpu->arch.fault_dsisr = svcpu->fault_dsisr; 300 vcpu->arch.last_inst = svcpu->last_inst; 301 #ifdef CONFIG_PPC_BOOK3S_64 302 vcpu->arch.shadow_fscr = svcpu->shadow_fscr; 303 #endif 304 /* 305 * Update purr and spurr using time base on exit. 306 */ 307 vcpu->arch.purr += get_tb() - vcpu->arch.entry_tb; 308 vcpu->arch.spurr += get_tb() - vcpu->arch.entry_tb; 309 to_book3s(vcpu)->vtb += get_vtb() - vcpu->arch.entry_vtb; 310 if (cpu_has_feature(CPU_FTR_ARCH_207S)) 311 vcpu->arch.ic += mfspr(SPRN_IC) - vcpu->arch.entry_ic; 312 313 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 314 /* 315 * Unlike other MSR bits, MSR[TS]bits can be changed at guest without 316 * notifying host: 317 * modified by unprivileged instructions like "tbegin"/"tend"/ 318 * "tresume"/"tsuspend" in PR KVM guest. 319 * 320 * It is necessary to sync here to calculate a correct shadow_msr. 321 * 322 * privileged guest's tbegin will be failed at present. So we 323 * only take care of problem state guest. 324 */ 325 old_msr = kvmppc_get_msr(vcpu); 326 if (unlikely((old_msr & MSR_PR) && 327 (vcpu->arch.shadow_srr1 & (MSR_TS_MASK)) != 328 (old_msr & (MSR_TS_MASK)))) { 329 old_msr &= ~(MSR_TS_MASK); 330 old_msr |= (vcpu->arch.shadow_srr1 & (MSR_TS_MASK)); 331 kvmppc_set_msr_fast(vcpu, old_msr); 332 kvmppc_recalc_shadow_msr(vcpu); 333 } 334 #endif 335 336 svcpu->in_use = false; 337 338 out: 339 svcpu_put(svcpu); 340 } 341 342 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 343 void kvmppc_save_tm_sprs(struct kvm_vcpu *vcpu) 344 { 345 tm_enable(); 346 vcpu->arch.tfhar = mfspr(SPRN_TFHAR); 347 vcpu->arch.texasr = mfspr(SPRN_TEXASR); 348 vcpu->arch.tfiar = mfspr(SPRN_TFIAR); 349 tm_disable(); 350 } 351 352 void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu) 353 { 354 tm_enable(); 355 mtspr(SPRN_TFHAR, vcpu->arch.tfhar); 356 mtspr(SPRN_TEXASR, vcpu->arch.texasr); 357 mtspr(SPRN_TFIAR, vcpu->arch.tfiar); 358 tm_disable(); 359 } 360 361 /* loadup math bits which is enabled at kvmppc_get_msr() but not enabled at 362 * hardware. 363 */ 364 static void kvmppc_handle_lost_math_exts(struct kvm_vcpu *vcpu) 365 { 366 ulong exit_nr; 367 ulong ext_diff = (kvmppc_get_msr(vcpu) & ~vcpu->arch.guest_owned_ext) & 368 (MSR_FP | MSR_VEC | MSR_VSX); 369 370 if (!ext_diff) 371 return; 372 373 if (ext_diff == MSR_FP) 374 exit_nr = BOOK3S_INTERRUPT_FP_UNAVAIL; 375 else if (ext_diff == MSR_VEC) 376 exit_nr = BOOK3S_INTERRUPT_ALTIVEC; 377 else 378 exit_nr = BOOK3S_INTERRUPT_VSX; 379 380 kvmppc_handle_ext(vcpu, exit_nr, ext_diff); 381 } 382 383 void kvmppc_save_tm_pr(struct kvm_vcpu *vcpu) 384 { 385 if (!(MSR_TM_ACTIVE(kvmppc_get_msr(vcpu)))) { 386 kvmppc_save_tm_sprs(vcpu); 387 return; 388 } 389 390 kvmppc_giveup_fac(vcpu, FSCR_TAR_LG); 391 kvmppc_giveup_ext(vcpu, MSR_VSX); 392 393 preempt_disable(); 394 _kvmppc_save_tm_pr(vcpu, mfmsr()); 395 preempt_enable(); 396 } 397 398 void kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu) 399 { 400 if (!MSR_TM_ACTIVE(kvmppc_get_msr(vcpu))) { 401 kvmppc_restore_tm_sprs(vcpu); 402 if (kvmppc_get_msr(vcpu) & MSR_TM) { 403 kvmppc_handle_lost_math_exts(vcpu); 404 if (vcpu->arch.fscr & FSCR_TAR) 405 kvmppc_handle_fac(vcpu, FSCR_TAR_LG); 406 } 407 return; 408 } 409 410 preempt_disable(); 411 _kvmppc_restore_tm_pr(vcpu, kvmppc_get_msr(vcpu)); 412 preempt_enable(); 413 414 if (kvmppc_get_msr(vcpu) & MSR_TM) { 415 kvmppc_handle_lost_math_exts(vcpu); 416 if (vcpu->arch.fscr & FSCR_TAR) 417 kvmppc_handle_fac(vcpu, FSCR_TAR_LG); 418 } 419 } 420 #endif 421 422 static int kvmppc_core_check_requests_pr(struct kvm_vcpu *vcpu) 423 { 424 int r = 1; /* Indicate we want to get back into the guest */ 425 426 /* We misuse TLB_FLUSH to indicate that we want to clear 427 all shadow cache entries */ 428 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 429 kvmppc_mmu_pte_flush(vcpu, 0, 0); 430 431 return r; 432 } 433 434 /************* MMU Notifiers *************/ 435 static bool do_kvm_unmap_gfn(struct kvm *kvm, struct kvm_gfn_range *range) 436 { 437 unsigned long i; 438 struct kvm_vcpu *vcpu; 439 440 kvm_for_each_vcpu(i, vcpu, kvm) 441 kvmppc_mmu_pte_pflush(vcpu, range->start << PAGE_SHIFT, 442 range->end << PAGE_SHIFT); 443 444 return false; 445 } 446 447 static bool kvm_unmap_gfn_range_pr(struct kvm *kvm, struct kvm_gfn_range *range) 448 { 449 return do_kvm_unmap_gfn(kvm, range); 450 } 451 452 static bool kvm_age_gfn_pr(struct kvm *kvm, struct kvm_gfn_range *range) 453 { 454 /* XXX could be more clever ;) */ 455 return false; 456 } 457 458 static bool kvm_test_age_gfn_pr(struct kvm *kvm, struct kvm_gfn_range *range) 459 { 460 /* XXX could be more clever ;) */ 461 return false; 462 } 463 464 static bool kvm_set_spte_gfn_pr(struct kvm *kvm, struct kvm_gfn_range *range) 465 { 466 /* The page will get remapped properly on its next fault */ 467 return do_kvm_unmap_gfn(kvm, range); 468 } 469 470 /*****************************************/ 471 472 static void kvmppc_set_msr_pr(struct kvm_vcpu *vcpu, u64 msr) 473 { 474 ulong old_msr; 475 476 /* For PAPR guest, make sure MSR reflects guest mode */ 477 if (vcpu->arch.papr_enabled) 478 msr = (msr & ~MSR_HV) | MSR_ME; 479 480 #ifdef EXIT_DEBUG 481 printk(KERN_INFO "KVM: Set MSR to 0x%llx\n", msr); 482 #endif 483 484 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 485 /* We should never target guest MSR to TS=10 && PR=0, 486 * since we always fail transaction for guest privilege 487 * state. 488 */ 489 if (!(msr & MSR_PR) && MSR_TM_TRANSACTIONAL(msr)) 490 kvmppc_emulate_tabort(vcpu, 491 TM_CAUSE_KVM_FAC_UNAV | TM_CAUSE_PERSISTENT); 492 #endif 493 494 old_msr = kvmppc_get_msr(vcpu); 495 msr &= to_book3s(vcpu)->msr_mask; 496 kvmppc_set_msr_fast(vcpu, msr); 497 kvmppc_recalc_shadow_msr(vcpu); 498 499 if (msr & MSR_POW) { 500 if (!vcpu->arch.pending_exceptions) { 501 kvm_vcpu_halt(vcpu); 502 vcpu->stat.generic.halt_wakeup++; 503 504 /* Unset POW bit after we woke up */ 505 msr &= ~MSR_POW; 506 kvmppc_set_msr_fast(vcpu, msr); 507 } 508 } 509 510 if (kvmppc_is_split_real(vcpu)) 511 kvmppc_fixup_split_real(vcpu); 512 else 513 kvmppc_unfixup_split_real(vcpu); 514 515 if ((kvmppc_get_msr(vcpu) & (MSR_PR|MSR_IR|MSR_DR)) != 516 (old_msr & (MSR_PR|MSR_IR|MSR_DR))) { 517 kvmppc_mmu_flush_segments(vcpu); 518 kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu)); 519 520 /* Preload magic page segment when in kernel mode */ 521 if (!(msr & MSR_PR) && vcpu->arch.magic_page_pa) { 522 struct kvm_vcpu_arch *a = &vcpu->arch; 523 524 if (msr & MSR_DR) 525 kvmppc_mmu_map_segment(vcpu, a->magic_page_ea); 526 else 527 kvmppc_mmu_map_segment(vcpu, a->magic_page_pa); 528 } 529 } 530 531 /* 532 * When switching from 32 to 64-bit, we may have a stale 32-bit 533 * magic page around, we need to flush it. Typically 32-bit magic 534 * page will be instantiated when calling into RTAS. Note: We 535 * assume that such transition only happens while in kernel mode, 536 * ie, we never transition from user 32-bit to kernel 64-bit with 537 * a 32-bit magic page around. 538 */ 539 if (vcpu->arch.magic_page_pa && 540 !(old_msr & MSR_PR) && !(old_msr & MSR_SF) && (msr & MSR_SF)) { 541 /* going from RTAS to normal kernel code */ 542 kvmppc_mmu_pte_flush(vcpu, (uint32_t)vcpu->arch.magic_page_pa, 543 ~0xFFFUL); 544 } 545 546 /* Preload FPU if it's enabled */ 547 if (kvmppc_get_msr(vcpu) & MSR_FP) 548 kvmppc_handle_ext(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL, MSR_FP); 549 550 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 551 if (kvmppc_get_msr(vcpu) & MSR_TM) 552 kvmppc_handle_lost_math_exts(vcpu); 553 #endif 554 } 555 556 static void kvmppc_set_pvr_pr(struct kvm_vcpu *vcpu, u32 pvr) 557 { 558 u32 host_pvr; 559 560 vcpu->arch.hflags &= ~BOOK3S_HFLAG_SLB; 561 vcpu->arch.pvr = pvr; 562 #ifdef CONFIG_PPC_BOOK3S_64 563 if ((pvr >= 0x330000) && (pvr < 0x70330000)) { 564 kvmppc_mmu_book3s_64_init(vcpu); 565 if (!to_book3s(vcpu)->hior_explicit) 566 to_book3s(vcpu)->hior = 0xfff00000; 567 to_book3s(vcpu)->msr_mask = 0xffffffffffffffffULL; 568 vcpu->arch.cpu_type = KVM_CPU_3S_64; 569 } else 570 #endif 571 { 572 kvmppc_mmu_book3s_32_init(vcpu); 573 if (!to_book3s(vcpu)->hior_explicit) 574 to_book3s(vcpu)->hior = 0; 575 to_book3s(vcpu)->msr_mask = 0xffffffffULL; 576 vcpu->arch.cpu_type = KVM_CPU_3S_32; 577 } 578 579 kvmppc_sanity_check(vcpu); 580 581 /* If we are in hypervisor level on 970, we can tell the CPU to 582 * treat DCBZ as 32 bytes store */ 583 vcpu->arch.hflags &= ~BOOK3S_HFLAG_DCBZ32; 584 if (vcpu->arch.mmu.is_dcbz32(vcpu) && (mfmsr() & MSR_HV) && 585 !strcmp(cur_cpu_spec->platform, "ppc970")) 586 vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32; 587 588 /* Cell performs badly if MSR_FEx are set. So let's hope nobody 589 really needs them in a VM on Cell and force disable them. */ 590 if (!strcmp(cur_cpu_spec->platform, "ppc-cell-be")) 591 to_book3s(vcpu)->msr_mask &= ~(MSR_FE0 | MSR_FE1); 592 593 /* 594 * If they're asking for POWER6 or later, set the flag 595 * indicating that we can do multiple large page sizes 596 * and 1TB segments. 597 * Also set the flag that indicates that tlbie has the large 598 * page bit in the RB operand instead of the instruction. 599 */ 600 switch (PVR_VER(pvr)) { 601 case PVR_POWER6: 602 case PVR_POWER7: 603 case PVR_POWER7p: 604 case PVR_POWER8: 605 case PVR_POWER8E: 606 case PVR_POWER8NVL: 607 case PVR_POWER9: 608 vcpu->arch.hflags |= BOOK3S_HFLAG_MULTI_PGSIZE | 609 BOOK3S_HFLAG_NEW_TLBIE; 610 break; 611 } 612 613 #ifdef CONFIG_PPC_BOOK3S_32 614 /* 32 bit Book3S always has 32 byte dcbz */ 615 vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32; 616 #endif 617 618 /* On some CPUs we can execute paired single operations natively */ 619 asm ( "mfpvr %0" : "=r"(host_pvr)); 620 switch (host_pvr) { 621 case 0x00080200: /* lonestar 2.0 */ 622 case 0x00088202: /* lonestar 2.2 */ 623 case 0x70000100: /* gekko 1.0 */ 624 case 0x00080100: /* gekko 2.0 */ 625 case 0x00083203: /* gekko 2.3a */ 626 case 0x00083213: /* gekko 2.3b */ 627 case 0x00083204: /* gekko 2.4 */ 628 case 0x00083214: /* gekko 2.4e (8SE) - retail HW2 */ 629 case 0x00087200: /* broadway */ 630 vcpu->arch.hflags |= BOOK3S_HFLAG_NATIVE_PS; 631 /* Enable HID2.PSE - in case we need it later */ 632 mtspr(SPRN_HID2_GEKKO, mfspr(SPRN_HID2_GEKKO) | (1 << 29)); 633 } 634 } 635 636 /* Book3s_32 CPUs always have 32 bytes cache line size, which Linux assumes. To 637 * make Book3s_32 Linux work on Book3s_64, we have to make sure we trap dcbz to 638 * emulate 32 bytes dcbz length. 639 * 640 * The Book3s_64 inventors also realized this case and implemented a special bit 641 * in the HID5 register, which is a hypervisor ressource. Thus we can't use it. 642 * 643 * My approach here is to patch the dcbz instruction on executing pages. 644 */ 645 static void kvmppc_patch_dcbz(struct kvm_vcpu *vcpu, struct kvmppc_pte *pte) 646 { 647 struct page *hpage; 648 u64 hpage_offset; 649 u32 *page; 650 int i; 651 652 hpage = gfn_to_page(vcpu->kvm, pte->raddr >> PAGE_SHIFT); 653 if (is_error_page(hpage)) 654 return; 655 656 hpage_offset = pte->raddr & ~PAGE_MASK; 657 hpage_offset &= ~0xFFFULL; 658 hpage_offset /= 4; 659 660 get_page(hpage); 661 page = kmap_atomic(hpage); 662 663 /* patch dcbz into reserved instruction, so we trap */ 664 for (i=hpage_offset; i < hpage_offset + (HW_PAGE_SIZE / 4); i++) 665 if ((be32_to_cpu(page[i]) & 0xff0007ff) == INS_DCBZ) 666 page[i] &= cpu_to_be32(0xfffffff7); 667 668 kunmap_atomic(page); 669 put_page(hpage); 670 } 671 672 static bool kvmppc_visible_gpa(struct kvm_vcpu *vcpu, gpa_t gpa) 673 { 674 ulong mp_pa = vcpu->arch.magic_page_pa; 675 676 if (!(kvmppc_get_msr(vcpu) & MSR_SF)) 677 mp_pa = (uint32_t)mp_pa; 678 679 gpa &= ~0xFFFULL; 680 if (unlikely(mp_pa) && unlikely((mp_pa & KVM_PAM) == (gpa & KVM_PAM))) { 681 return true; 682 } 683 684 return kvm_is_visible_gfn(vcpu->kvm, gpa >> PAGE_SHIFT); 685 } 686 687 static int kvmppc_handle_pagefault(struct kvm_vcpu *vcpu, 688 ulong eaddr, int vec) 689 { 690 bool data = (vec == BOOK3S_INTERRUPT_DATA_STORAGE); 691 bool iswrite = false; 692 int r = RESUME_GUEST; 693 int relocated; 694 int page_found = 0; 695 struct kvmppc_pte pte = { 0 }; 696 bool dr = (kvmppc_get_msr(vcpu) & MSR_DR) ? true : false; 697 bool ir = (kvmppc_get_msr(vcpu) & MSR_IR) ? true : false; 698 u64 vsid; 699 700 relocated = data ? dr : ir; 701 if (data && (vcpu->arch.fault_dsisr & DSISR_ISSTORE)) 702 iswrite = true; 703 704 /* Resolve real address if translation turned on */ 705 if (relocated) { 706 page_found = vcpu->arch.mmu.xlate(vcpu, eaddr, &pte, data, iswrite); 707 } else { 708 pte.may_execute = true; 709 pte.may_read = true; 710 pte.may_write = true; 711 pte.raddr = eaddr & KVM_PAM; 712 pte.eaddr = eaddr; 713 pte.vpage = eaddr >> 12; 714 pte.page_size = MMU_PAGE_64K; 715 pte.wimg = HPTE_R_M; 716 } 717 718 switch (kvmppc_get_msr(vcpu) & (MSR_DR|MSR_IR)) { 719 case 0: 720 pte.vpage |= ((u64)VSID_REAL << (SID_SHIFT - 12)); 721 break; 722 case MSR_DR: 723 if (!data && 724 (vcpu->arch.hflags & BOOK3S_HFLAG_SPLIT_HACK) && 725 ((pte.raddr & SPLIT_HACK_MASK) == SPLIT_HACK_OFFS)) 726 pte.raddr &= ~SPLIT_HACK_MASK; 727 fallthrough; 728 case MSR_IR: 729 vcpu->arch.mmu.esid_to_vsid(vcpu, eaddr >> SID_SHIFT, &vsid); 730 731 if ((kvmppc_get_msr(vcpu) & (MSR_DR|MSR_IR)) == MSR_DR) 732 pte.vpage |= ((u64)VSID_REAL_DR << (SID_SHIFT - 12)); 733 else 734 pte.vpage |= ((u64)VSID_REAL_IR << (SID_SHIFT - 12)); 735 pte.vpage |= vsid; 736 737 if (vsid == -1) 738 page_found = -EINVAL; 739 break; 740 } 741 742 if (vcpu->arch.mmu.is_dcbz32(vcpu) && 743 (!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) { 744 /* 745 * If we do the dcbz hack, we have to NX on every execution, 746 * so we can patch the executing code. This renders our guest 747 * NX-less. 748 */ 749 pte.may_execute = !data; 750 } 751 752 if (page_found == -ENOENT || page_found == -EPERM) { 753 /* Page not found in guest PTE entries, or protection fault */ 754 u64 flags; 755 756 if (page_found == -EPERM) 757 flags = DSISR_PROTFAULT; 758 else 759 flags = DSISR_NOHPTE; 760 if (data) { 761 flags |= vcpu->arch.fault_dsisr & DSISR_ISSTORE; 762 kvmppc_core_queue_data_storage(vcpu, 0, eaddr, flags); 763 } else { 764 kvmppc_core_queue_inst_storage(vcpu, flags); 765 } 766 } else if (page_found == -EINVAL) { 767 /* Page not found in guest SLB */ 768 kvmppc_set_dar(vcpu, kvmppc_get_fault_dar(vcpu)); 769 kvmppc_book3s_queue_irqprio(vcpu, vec + 0x80); 770 } else if (kvmppc_visible_gpa(vcpu, pte.raddr)) { 771 if (data && !(vcpu->arch.fault_dsisr & DSISR_NOHPTE)) { 772 /* 773 * There is already a host HPTE there, presumably 774 * a read-only one for a page the guest thinks 775 * is writable, so get rid of it first. 776 */ 777 kvmppc_mmu_unmap_page(vcpu, &pte); 778 } 779 /* The guest's PTE is not mapped yet. Map on the host */ 780 if (kvmppc_mmu_map_page(vcpu, &pte, iswrite) == -EIO) { 781 /* Exit KVM if mapping failed */ 782 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 783 return RESUME_HOST; 784 } 785 if (data) 786 vcpu->stat.sp_storage++; 787 else if (vcpu->arch.mmu.is_dcbz32(vcpu) && 788 (!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) 789 kvmppc_patch_dcbz(vcpu, &pte); 790 } else { 791 /* MMIO */ 792 vcpu->stat.mmio_exits++; 793 vcpu->arch.paddr_accessed = pte.raddr; 794 vcpu->arch.vaddr_accessed = pte.eaddr; 795 r = kvmppc_emulate_mmio(vcpu); 796 if ( r == RESUME_HOST_NV ) 797 r = RESUME_HOST; 798 } 799 800 return r; 801 } 802 803 /* Give up external provider (FPU, Altivec, VSX) */ 804 void kvmppc_giveup_ext(struct kvm_vcpu *vcpu, ulong msr) 805 { 806 struct thread_struct *t = ¤t->thread; 807 808 /* 809 * VSX instructions can access FP and vector registers, so if 810 * we are giving up VSX, make sure we give up FP and VMX as well. 811 */ 812 if (msr & MSR_VSX) 813 msr |= MSR_FP | MSR_VEC; 814 815 msr &= vcpu->arch.guest_owned_ext; 816 if (!msr) 817 return; 818 819 #ifdef DEBUG_EXT 820 printk(KERN_INFO "Giving up ext 0x%lx\n", msr); 821 #endif 822 823 if (msr & MSR_FP) { 824 /* 825 * Note that on CPUs with VSX, giveup_fpu stores 826 * both the traditional FP registers and the added VSX 827 * registers into thread.fp_state.fpr[]. 828 */ 829 if (t->regs->msr & MSR_FP) 830 giveup_fpu(current); 831 t->fp_save_area = NULL; 832 } 833 834 #ifdef CONFIG_ALTIVEC 835 if (msr & MSR_VEC) { 836 if (current->thread.regs->msr & MSR_VEC) 837 giveup_altivec(current); 838 t->vr_save_area = NULL; 839 } 840 #endif 841 842 vcpu->arch.guest_owned_ext &= ~(msr | MSR_VSX); 843 kvmppc_recalc_shadow_msr(vcpu); 844 } 845 846 /* Give up facility (TAR / EBB / DSCR) */ 847 void kvmppc_giveup_fac(struct kvm_vcpu *vcpu, ulong fac) 848 { 849 #ifdef CONFIG_PPC_BOOK3S_64 850 if (!(vcpu->arch.shadow_fscr & (1ULL << fac))) { 851 /* Facility not available to the guest, ignore giveup request*/ 852 return; 853 } 854 855 switch (fac) { 856 case FSCR_TAR_LG: 857 vcpu->arch.tar = mfspr(SPRN_TAR); 858 mtspr(SPRN_TAR, current->thread.tar); 859 vcpu->arch.shadow_fscr &= ~FSCR_TAR; 860 break; 861 } 862 #endif 863 } 864 865 /* Handle external providers (FPU, Altivec, VSX) */ 866 static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr, 867 ulong msr) 868 { 869 struct thread_struct *t = ¤t->thread; 870 871 /* When we have paired singles, we emulate in software */ 872 if (vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE) 873 return RESUME_GUEST; 874 875 if (!(kvmppc_get_msr(vcpu) & msr)) { 876 kvmppc_book3s_queue_irqprio(vcpu, exit_nr); 877 return RESUME_GUEST; 878 } 879 880 if (msr == MSR_VSX) { 881 /* No VSX? Give an illegal instruction interrupt */ 882 #ifdef CONFIG_VSX 883 if (!cpu_has_feature(CPU_FTR_VSX)) 884 #endif 885 { 886 kvmppc_core_queue_program(vcpu, SRR1_PROGILL); 887 return RESUME_GUEST; 888 } 889 890 /* 891 * We have to load up all the FP and VMX registers before 892 * we can let the guest use VSX instructions. 893 */ 894 msr = MSR_FP | MSR_VEC | MSR_VSX; 895 } 896 897 /* See if we already own all the ext(s) needed */ 898 msr &= ~vcpu->arch.guest_owned_ext; 899 if (!msr) 900 return RESUME_GUEST; 901 902 #ifdef DEBUG_EXT 903 printk(KERN_INFO "Loading up ext 0x%lx\n", msr); 904 #endif 905 906 if (msr & MSR_FP) { 907 preempt_disable(); 908 enable_kernel_fp(); 909 load_fp_state(&vcpu->arch.fp); 910 disable_kernel_fp(); 911 t->fp_save_area = &vcpu->arch.fp; 912 preempt_enable(); 913 } 914 915 if (msr & MSR_VEC) { 916 #ifdef CONFIG_ALTIVEC 917 preempt_disable(); 918 enable_kernel_altivec(); 919 load_vr_state(&vcpu->arch.vr); 920 disable_kernel_altivec(); 921 t->vr_save_area = &vcpu->arch.vr; 922 preempt_enable(); 923 #endif 924 } 925 926 t->regs->msr |= msr; 927 vcpu->arch.guest_owned_ext |= msr; 928 kvmppc_recalc_shadow_msr(vcpu); 929 930 return RESUME_GUEST; 931 } 932 933 /* 934 * Kernel code using FP or VMX could have flushed guest state to 935 * the thread_struct; if so, get it back now. 936 */ 937 static void kvmppc_handle_lost_ext(struct kvm_vcpu *vcpu) 938 { 939 unsigned long lost_ext; 940 941 lost_ext = vcpu->arch.guest_owned_ext & ~current->thread.regs->msr; 942 if (!lost_ext) 943 return; 944 945 if (lost_ext & MSR_FP) { 946 preempt_disable(); 947 enable_kernel_fp(); 948 load_fp_state(&vcpu->arch.fp); 949 disable_kernel_fp(); 950 preempt_enable(); 951 } 952 #ifdef CONFIG_ALTIVEC 953 if (lost_ext & MSR_VEC) { 954 preempt_disable(); 955 enable_kernel_altivec(); 956 load_vr_state(&vcpu->arch.vr); 957 disable_kernel_altivec(); 958 preempt_enable(); 959 } 960 #endif 961 current->thread.regs->msr |= lost_ext; 962 } 963 964 #ifdef CONFIG_PPC_BOOK3S_64 965 966 void kvmppc_trigger_fac_interrupt(struct kvm_vcpu *vcpu, ulong fac) 967 { 968 /* Inject the Interrupt Cause field and trigger a guest interrupt */ 969 vcpu->arch.fscr &= ~(0xffULL << 56); 970 vcpu->arch.fscr |= (fac << 56); 971 kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_FAC_UNAVAIL); 972 } 973 974 static void kvmppc_emulate_fac(struct kvm_vcpu *vcpu, ulong fac) 975 { 976 enum emulation_result er = EMULATE_FAIL; 977 978 if (!(kvmppc_get_msr(vcpu) & MSR_PR)) 979 er = kvmppc_emulate_instruction(vcpu); 980 981 if ((er != EMULATE_DONE) && (er != EMULATE_AGAIN)) { 982 /* Couldn't emulate, trigger interrupt in guest */ 983 kvmppc_trigger_fac_interrupt(vcpu, fac); 984 } 985 } 986 987 /* Enable facilities (TAR, EBB, DSCR) for the guest */ 988 static int kvmppc_handle_fac(struct kvm_vcpu *vcpu, ulong fac) 989 { 990 bool guest_fac_enabled; 991 BUG_ON(!cpu_has_feature(CPU_FTR_ARCH_207S)); 992 993 /* 994 * Not every facility is enabled by FSCR bits, check whether the 995 * guest has this facility enabled at all. 996 */ 997 switch (fac) { 998 case FSCR_TAR_LG: 999 case FSCR_EBB_LG: 1000 guest_fac_enabled = (vcpu->arch.fscr & (1ULL << fac)); 1001 break; 1002 case FSCR_TM_LG: 1003 guest_fac_enabled = kvmppc_get_msr(vcpu) & MSR_TM; 1004 break; 1005 default: 1006 guest_fac_enabled = false; 1007 break; 1008 } 1009 1010 if (!guest_fac_enabled) { 1011 /* Facility not enabled by the guest */ 1012 kvmppc_trigger_fac_interrupt(vcpu, fac); 1013 return RESUME_GUEST; 1014 } 1015 1016 switch (fac) { 1017 case FSCR_TAR_LG: 1018 /* TAR switching isn't lazy in Linux yet */ 1019 current->thread.tar = mfspr(SPRN_TAR); 1020 mtspr(SPRN_TAR, vcpu->arch.tar); 1021 vcpu->arch.shadow_fscr |= FSCR_TAR; 1022 break; 1023 default: 1024 kvmppc_emulate_fac(vcpu, fac); 1025 break; 1026 } 1027 1028 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1029 /* Since we disabled MSR_TM at privilege state, the mfspr instruction 1030 * for TM spr can trigger TM fac unavailable. In this case, the 1031 * emulation is handled by kvmppc_emulate_fac(), which invokes 1032 * kvmppc_emulate_mfspr() finally. But note the mfspr can include 1033 * RT for NV registers. So it need to restore those NV reg to reflect 1034 * the update. 1035 */ 1036 if ((fac == FSCR_TM_LG) && !(kvmppc_get_msr(vcpu) & MSR_PR)) 1037 return RESUME_GUEST_NV; 1038 #endif 1039 1040 return RESUME_GUEST; 1041 } 1042 1043 void kvmppc_set_fscr(struct kvm_vcpu *vcpu, u64 fscr) 1044 { 1045 if (fscr & FSCR_SCV) 1046 fscr &= ~FSCR_SCV; /* SCV must not be enabled */ 1047 /* Prohibit prefixed instructions for now */ 1048 fscr &= ~FSCR_PREFIX; 1049 if ((vcpu->arch.fscr & FSCR_TAR) && !(fscr & FSCR_TAR)) { 1050 /* TAR got dropped, drop it in shadow too */ 1051 kvmppc_giveup_fac(vcpu, FSCR_TAR_LG); 1052 } else if (!(vcpu->arch.fscr & FSCR_TAR) && (fscr & FSCR_TAR)) { 1053 vcpu->arch.fscr = fscr; 1054 kvmppc_handle_fac(vcpu, FSCR_TAR_LG); 1055 return; 1056 } 1057 1058 vcpu->arch.fscr = fscr; 1059 } 1060 #endif 1061 1062 static void kvmppc_setup_debug(struct kvm_vcpu *vcpu) 1063 { 1064 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 1065 u64 msr = kvmppc_get_msr(vcpu); 1066 1067 kvmppc_set_msr(vcpu, msr | MSR_SE); 1068 } 1069 } 1070 1071 static void kvmppc_clear_debug(struct kvm_vcpu *vcpu) 1072 { 1073 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 1074 u64 msr = kvmppc_get_msr(vcpu); 1075 1076 kvmppc_set_msr(vcpu, msr & ~MSR_SE); 1077 } 1078 } 1079 1080 static int kvmppc_exit_pr_progint(struct kvm_vcpu *vcpu, unsigned int exit_nr) 1081 { 1082 enum emulation_result er; 1083 ulong flags; 1084 ppc_inst_t last_inst; 1085 int emul, r; 1086 1087 /* 1088 * shadow_srr1 only contains valid flags if we came here via a program 1089 * exception. The other exceptions (emulation assist, FP unavailable, 1090 * etc.) do not provide flags in SRR1, so use an illegal-instruction 1091 * exception when injecting a program interrupt into the guest. 1092 */ 1093 if (exit_nr == BOOK3S_INTERRUPT_PROGRAM) 1094 flags = vcpu->arch.shadow_srr1 & 0x1f0000ull; 1095 else 1096 flags = SRR1_PROGILL; 1097 1098 emul = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst); 1099 if (emul != EMULATE_DONE) 1100 return RESUME_GUEST; 1101 1102 if (kvmppc_get_msr(vcpu) & MSR_PR) { 1103 #ifdef EXIT_DEBUG 1104 pr_info("Userspace triggered 0x700 exception at\n 0x%lx (0x%x)\n", 1105 kvmppc_get_pc(vcpu), ppc_inst_val(last_inst)); 1106 #endif 1107 if ((ppc_inst_val(last_inst) & 0xff0007ff) != (INS_DCBZ & 0xfffffff7)) { 1108 kvmppc_core_queue_program(vcpu, flags); 1109 return RESUME_GUEST; 1110 } 1111 } 1112 1113 vcpu->stat.emulated_inst_exits++; 1114 er = kvmppc_emulate_instruction(vcpu); 1115 switch (er) { 1116 case EMULATE_DONE: 1117 r = RESUME_GUEST_NV; 1118 break; 1119 case EMULATE_AGAIN: 1120 r = RESUME_GUEST; 1121 break; 1122 case EMULATE_FAIL: 1123 pr_crit("%s: emulation at %lx failed (%08x)\n", 1124 __func__, kvmppc_get_pc(vcpu), ppc_inst_val(last_inst)); 1125 kvmppc_core_queue_program(vcpu, flags); 1126 r = RESUME_GUEST; 1127 break; 1128 case EMULATE_DO_MMIO: 1129 vcpu->run->exit_reason = KVM_EXIT_MMIO; 1130 r = RESUME_HOST_NV; 1131 break; 1132 case EMULATE_EXIT_USER: 1133 r = RESUME_HOST_NV; 1134 break; 1135 default: 1136 BUG(); 1137 } 1138 1139 return r; 1140 } 1141 1142 int kvmppc_handle_exit_pr(struct kvm_vcpu *vcpu, unsigned int exit_nr) 1143 { 1144 struct kvm_run *run = vcpu->run; 1145 int r = RESUME_HOST; 1146 int s; 1147 1148 vcpu->stat.sum_exits++; 1149 1150 run->exit_reason = KVM_EXIT_UNKNOWN; 1151 run->ready_for_interrupt_injection = 1; 1152 1153 /* We get here with MSR.EE=1 */ 1154 1155 trace_kvm_exit(exit_nr, vcpu); 1156 guest_exit(); 1157 1158 switch (exit_nr) { 1159 case BOOK3S_INTERRUPT_INST_STORAGE: 1160 { 1161 ulong shadow_srr1 = vcpu->arch.shadow_srr1; 1162 vcpu->stat.pf_instruc++; 1163 1164 if (kvmppc_is_split_real(vcpu)) 1165 kvmppc_fixup_split_real(vcpu); 1166 1167 #ifdef CONFIG_PPC_BOOK3S_32 1168 /* We set segments as unused segments when invalidating them. So 1169 * treat the respective fault as segment fault. */ 1170 { 1171 struct kvmppc_book3s_shadow_vcpu *svcpu; 1172 u32 sr; 1173 1174 svcpu = svcpu_get(vcpu); 1175 sr = svcpu->sr[kvmppc_get_pc(vcpu) >> SID_SHIFT]; 1176 svcpu_put(svcpu); 1177 if (sr == SR_INVALID) { 1178 kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu)); 1179 r = RESUME_GUEST; 1180 break; 1181 } 1182 } 1183 #endif 1184 1185 /* only care about PTEG not found errors, but leave NX alone */ 1186 if (shadow_srr1 & 0x40000000) { 1187 int idx = srcu_read_lock(&vcpu->kvm->srcu); 1188 r = kvmppc_handle_pagefault(vcpu, kvmppc_get_pc(vcpu), exit_nr); 1189 srcu_read_unlock(&vcpu->kvm->srcu, idx); 1190 vcpu->stat.sp_instruc++; 1191 } else if (vcpu->arch.mmu.is_dcbz32(vcpu) && 1192 (!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) { 1193 /* 1194 * XXX If we do the dcbz hack we use the NX bit to flush&patch the page, 1195 * so we can't use the NX bit inside the guest. Let's cross our fingers, 1196 * that no guest that needs the dcbz hack does NX. 1197 */ 1198 kvmppc_mmu_pte_flush(vcpu, kvmppc_get_pc(vcpu), ~0xFFFUL); 1199 r = RESUME_GUEST; 1200 } else { 1201 kvmppc_core_queue_inst_storage(vcpu, 1202 shadow_srr1 & 0x58000000); 1203 r = RESUME_GUEST; 1204 } 1205 break; 1206 } 1207 case BOOK3S_INTERRUPT_DATA_STORAGE: 1208 { 1209 ulong dar = kvmppc_get_fault_dar(vcpu); 1210 u32 fault_dsisr = vcpu->arch.fault_dsisr; 1211 vcpu->stat.pf_storage++; 1212 1213 #ifdef CONFIG_PPC_BOOK3S_32 1214 /* We set segments as unused segments when invalidating them. So 1215 * treat the respective fault as segment fault. */ 1216 { 1217 struct kvmppc_book3s_shadow_vcpu *svcpu; 1218 u32 sr; 1219 1220 svcpu = svcpu_get(vcpu); 1221 sr = svcpu->sr[dar >> SID_SHIFT]; 1222 svcpu_put(svcpu); 1223 if (sr == SR_INVALID) { 1224 kvmppc_mmu_map_segment(vcpu, dar); 1225 r = RESUME_GUEST; 1226 break; 1227 } 1228 } 1229 #endif 1230 1231 /* 1232 * We need to handle missing shadow PTEs, and 1233 * protection faults due to us mapping a page read-only 1234 * when the guest thinks it is writable. 1235 */ 1236 if (fault_dsisr & (DSISR_NOHPTE | DSISR_PROTFAULT)) { 1237 int idx = srcu_read_lock(&vcpu->kvm->srcu); 1238 r = kvmppc_handle_pagefault(vcpu, dar, exit_nr); 1239 srcu_read_unlock(&vcpu->kvm->srcu, idx); 1240 } else { 1241 kvmppc_core_queue_data_storage(vcpu, 0, dar, fault_dsisr); 1242 r = RESUME_GUEST; 1243 } 1244 break; 1245 } 1246 case BOOK3S_INTERRUPT_DATA_SEGMENT: 1247 if (kvmppc_mmu_map_segment(vcpu, kvmppc_get_fault_dar(vcpu)) < 0) { 1248 kvmppc_set_dar(vcpu, kvmppc_get_fault_dar(vcpu)); 1249 kvmppc_book3s_queue_irqprio(vcpu, 1250 BOOK3S_INTERRUPT_DATA_SEGMENT); 1251 } 1252 r = RESUME_GUEST; 1253 break; 1254 case BOOK3S_INTERRUPT_INST_SEGMENT: 1255 if (kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu)) < 0) { 1256 kvmppc_book3s_queue_irqprio(vcpu, 1257 BOOK3S_INTERRUPT_INST_SEGMENT); 1258 } 1259 r = RESUME_GUEST; 1260 break; 1261 /* We're good on these - the host merely wanted to get our attention */ 1262 case BOOK3S_INTERRUPT_DECREMENTER: 1263 case BOOK3S_INTERRUPT_HV_DECREMENTER: 1264 case BOOK3S_INTERRUPT_DOORBELL: 1265 case BOOK3S_INTERRUPT_H_DOORBELL: 1266 vcpu->stat.dec_exits++; 1267 r = RESUME_GUEST; 1268 break; 1269 case BOOK3S_INTERRUPT_EXTERNAL: 1270 case BOOK3S_INTERRUPT_EXTERNAL_HV: 1271 case BOOK3S_INTERRUPT_H_VIRT: 1272 vcpu->stat.ext_intr_exits++; 1273 r = RESUME_GUEST; 1274 break; 1275 case BOOK3S_INTERRUPT_HMI: 1276 case BOOK3S_INTERRUPT_PERFMON: 1277 case BOOK3S_INTERRUPT_SYSTEM_RESET: 1278 r = RESUME_GUEST; 1279 break; 1280 case BOOK3S_INTERRUPT_PROGRAM: 1281 case BOOK3S_INTERRUPT_H_EMUL_ASSIST: 1282 r = kvmppc_exit_pr_progint(vcpu, exit_nr); 1283 break; 1284 case BOOK3S_INTERRUPT_SYSCALL: 1285 { 1286 ppc_inst_t last_sc; 1287 int emul; 1288 1289 /* Get last sc for papr */ 1290 if (vcpu->arch.papr_enabled) { 1291 /* The sc instruction points SRR0 to the next inst */ 1292 emul = kvmppc_get_last_inst(vcpu, INST_SC, &last_sc); 1293 if (emul != EMULATE_DONE) { 1294 kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) - 4); 1295 r = RESUME_GUEST; 1296 break; 1297 } 1298 } 1299 1300 if (vcpu->arch.papr_enabled && 1301 (ppc_inst_val(last_sc) == 0x44000022) && 1302 !(kvmppc_get_msr(vcpu) & MSR_PR)) { 1303 /* SC 1 papr hypercalls */ 1304 ulong cmd = kvmppc_get_gpr(vcpu, 3); 1305 int i; 1306 1307 #ifdef CONFIG_PPC_BOOK3S_64 1308 if (kvmppc_h_pr(vcpu, cmd) == EMULATE_DONE) { 1309 r = RESUME_GUEST; 1310 break; 1311 } 1312 #endif 1313 1314 run->papr_hcall.nr = cmd; 1315 for (i = 0; i < 9; ++i) { 1316 ulong gpr = kvmppc_get_gpr(vcpu, 4 + i); 1317 run->papr_hcall.args[i] = gpr; 1318 } 1319 run->exit_reason = KVM_EXIT_PAPR_HCALL; 1320 vcpu->arch.hcall_needed = 1; 1321 r = RESUME_HOST; 1322 } else if (vcpu->arch.osi_enabled && 1323 (((u32)kvmppc_get_gpr(vcpu, 3)) == OSI_SC_MAGIC_R3) && 1324 (((u32)kvmppc_get_gpr(vcpu, 4)) == OSI_SC_MAGIC_R4)) { 1325 /* MOL hypercalls */ 1326 u64 *gprs = run->osi.gprs; 1327 int i; 1328 1329 run->exit_reason = KVM_EXIT_OSI; 1330 for (i = 0; i < 32; i++) 1331 gprs[i] = kvmppc_get_gpr(vcpu, i); 1332 vcpu->arch.osi_needed = 1; 1333 r = RESUME_HOST_NV; 1334 } else if (!(kvmppc_get_msr(vcpu) & MSR_PR) && 1335 (((u32)kvmppc_get_gpr(vcpu, 0)) == KVM_SC_MAGIC_R0)) { 1336 /* KVM PV hypercalls */ 1337 kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu)); 1338 r = RESUME_GUEST; 1339 } else { 1340 /* Guest syscalls */ 1341 vcpu->stat.syscall_exits++; 1342 kvmppc_book3s_queue_irqprio(vcpu, exit_nr); 1343 r = RESUME_GUEST; 1344 } 1345 break; 1346 } 1347 case BOOK3S_INTERRUPT_FP_UNAVAIL: 1348 case BOOK3S_INTERRUPT_ALTIVEC: 1349 case BOOK3S_INTERRUPT_VSX: 1350 { 1351 int ext_msr = 0; 1352 int emul; 1353 ppc_inst_t last_inst; 1354 1355 if (vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE) { 1356 /* Do paired single instruction emulation */ 1357 emul = kvmppc_get_last_inst(vcpu, INST_GENERIC, 1358 &last_inst); 1359 if (emul == EMULATE_DONE) 1360 r = kvmppc_exit_pr_progint(vcpu, exit_nr); 1361 else 1362 r = RESUME_GUEST; 1363 1364 break; 1365 } 1366 1367 /* Enable external provider */ 1368 switch (exit_nr) { 1369 case BOOK3S_INTERRUPT_FP_UNAVAIL: 1370 ext_msr = MSR_FP; 1371 break; 1372 1373 case BOOK3S_INTERRUPT_ALTIVEC: 1374 ext_msr = MSR_VEC; 1375 break; 1376 1377 case BOOK3S_INTERRUPT_VSX: 1378 ext_msr = MSR_VSX; 1379 break; 1380 } 1381 1382 r = kvmppc_handle_ext(vcpu, exit_nr, ext_msr); 1383 break; 1384 } 1385 case BOOK3S_INTERRUPT_ALIGNMENT: 1386 { 1387 ppc_inst_t last_inst; 1388 int emul = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst); 1389 1390 if (emul == EMULATE_DONE) { 1391 u32 dsisr; 1392 u64 dar; 1393 1394 dsisr = kvmppc_alignment_dsisr(vcpu, ppc_inst_val(last_inst)); 1395 dar = kvmppc_alignment_dar(vcpu, ppc_inst_val(last_inst)); 1396 1397 kvmppc_set_dsisr(vcpu, dsisr); 1398 kvmppc_set_dar(vcpu, dar); 1399 1400 kvmppc_book3s_queue_irqprio(vcpu, exit_nr); 1401 } 1402 r = RESUME_GUEST; 1403 break; 1404 } 1405 #ifdef CONFIG_PPC_BOOK3S_64 1406 case BOOK3S_INTERRUPT_FAC_UNAVAIL: 1407 r = kvmppc_handle_fac(vcpu, vcpu->arch.shadow_fscr >> 56); 1408 break; 1409 #endif 1410 case BOOK3S_INTERRUPT_MACHINE_CHECK: 1411 kvmppc_book3s_queue_irqprio(vcpu, exit_nr); 1412 r = RESUME_GUEST; 1413 break; 1414 case BOOK3S_INTERRUPT_TRACE: 1415 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 1416 run->exit_reason = KVM_EXIT_DEBUG; 1417 r = RESUME_HOST; 1418 } else { 1419 kvmppc_book3s_queue_irqprio(vcpu, exit_nr); 1420 r = RESUME_GUEST; 1421 } 1422 break; 1423 default: 1424 { 1425 ulong shadow_srr1 = vcpu->arch.shadow_srr1; 1426 /* Ugh - bork here! What did we get? */ 1427 printk(KERN_EMERG "exit_nr=0x%x | pc=0x%lx | msr=0x%lx\n", 1428 exit_nr, kvmppc_get_pc(vcpu), shadow_srr1); 1429 r = RESUME_HOST; 1430 BUG(); 1431 break; 1432 } 1433 } 1434 1435 if (!(r & RESUME_HOST)) { 1436 /* To avoid clobbering exit_reason, only check for signals if 1437 * we aren't already exiting to userspace for some other 1438 * reason. */ 1439 1440 /* 1441 * Interrupts could be timers for the guest which we have to 1442 * inject again, so let's postpone them until we're in the guest 1443 * and if we really did time things so badly, then we just exit 1444 * again due to a host external interrupt. 1445 */ 1446 s = kvmppc_prepare_to_enter(vcpu); 1447 if (s <= 0) 1448 r = s; 1449 else { 1450 /* interrupts now hard-disabled */ 1451 kvmppc_fix_ee_before_entry(); 1452 } 1453 1454 kvmppc_handle_lost_ext(vcpu); 1455 } 1456 1457 trace_kvm_book3s_reenter(r, vcpu); 1458 1459 return r; 1460 } 1461 1462 static int kvm_arch_vcpu_ioctl_get_sregs_pr(struct kvm_vcpu *vcpu, 1463 struct kvm_sregs *sregs) 1464 { 1465 struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu); 1466 int i; 1467 1468 sregs->pvr = vcpu->arch.pvr; 1469 1470 sregs->u.s.sdr1 = to_book3s(vcpu)->sdr1; 1471 if (vcpu->arch.hflags & BOOK3S_HFLAG_SLB) { 1472 for (i = 0; i < 64; i++) { 1473 sregs->u.s.ppc64.slb[i].slbe = vcpu->arch.slb[i].orige | i; 1474 sregs->u.s.ppc64.slb[i].slbv = vcpu->arch.slb[i].origv; 1475 } 1476 } else { 1477 for (i = 0; i < 16; i++) 1478 sregs->u.s.ppc32.sr[i] = kvmppc_get_sr(vcpu, i); 1479 1480 for (i = 0; i < 8; i++) { 1481 sregs->u.s.ppc32.ibat[i] = vcpu3s->ibat[i].raw; 1482 sregs->u.s.ppc32.dbat[i] = vcpu3s->dbat[i].raw; 1483 } 1484 } 1485 1486 return 0; 1487 } 1488 1489 static int kvm_arch_vcpu_ioctl_set_sregs_pr(struct kvm_vcpu *vcpu, 1490 struct kvm_sregs *sregs) 1491 { 1492 struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu); 1493 int i; 1494 1495 kvmppc_set_pvr_pr(vcpu, sregs->pvr); 1496 1497 vcpu3s->sdr1 = sregs->u.s.sdr1; 1498 #ifdef CONFIG_PPC_BOOK3S_64 1499 if (vcpu->arch.hflags & BOOK3S_HFLAG_SLB) { 1500 /* Flush all SLB entries */ 1501 vcpu->arch.mmu.slbmte(vcpu, 0, 0); 1502 vcpu->arch.mmu.slbia(vcpu); 1503 1504 for (i = 0; i < 64; i++) { 1505 u64 rb = sregs->u.s.ppc64.slb[i].slbe; 1506 u64 rs = sregs->u.s.ppc64.slb[i].slbv; 1507 1508 if (rb & SLB_ESID_V) 1509 vcpu->arch.mmu.slbmte(vcpu, rs, rb); 1510 } 1511 } else 1512 #endif 1513 { 1514 for (i = 0; i < 16; i++) { 1515 vcpu->arch.mmu.mtsrin(vcpu, i, sregs->u.s.ppc32.sr[i]); 1516 } 1517 for (i = 0; i < 8; i++) { 1518 kvmppc_set_bat(vcpu, &(vcpu3s->ibat[i]), false, 1519 (u32)sregs->u.s.ppc32.ibat[i]); 1520 kvmppc_set_bat(vcpu, &(vcpu3s->ibat[i]), true, 1521 (u32)(sregs->u.s.ppc32.ibat[i] >> 32)); 1522 kvmppc_set_bat(vcpu, &(vcpu3s->dbat[i]), false, 1523 (u32)sregs->u.s.ppc32.dbat[i]); 1524 kvmppc_set_bat(vcpu, &(vcpu3s->dbat[i]), true, 1525 (u32)(sregs->u.s.ppc32.dbat[i] >> 32)); 1526 } 1527 } 1528 1529 /* Flush the MMU after messing with the segments */ 1530 kvmppc_mmu_pte_flush(vcpu, 0, 0); 1531 1532 return 0; 1533 } 1534 1535 static int kvmppc_get_one_reg_pr(struct kvm_vcpu *vcpu, u64 id, 1536 union kvmppc_one_reg *val) 1537 { 1538 int r = 0; 1539 1540 switch (id) { 1541 case KVM_REG_PPC_DEBUG_INST: 1542 *val = get_reg_val(id, KVMPPC_INST_SW_BREAKPOINT); 1543 break; 1544 case KVM_REG_PPC_HIOR: 1545 *val = get_reg_val(id, to_book3s(vcpu)->hior); 1546 break; 1547 case KVM_REG_PPC_VTB: 1548 *val = get_reg_val(id, to_book3s(vcpu)->vtb); 1549 break; 1550 case KVM_REG_PPC_LPCR: 1551 case KVM_REG_PPC_LPCR_64: 1552 /* 1553 * We are only interested in the LPCR_ILE bit 1554 */ 1555 if (vcpu->arch.intr_msr & MSR_LE) 1556 *val = get_reg_val(id, LPCR_ILE); 1557 else 1558 *val = get_reg_val(id, 0); 1559 break; 1560 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1561 case KVM_REG_PPC_TFHAR: 1562 *val = get_reg_val(id, vcpu->arch.tfhar); 1563 break; 1564 case KVM_REG_PPC_TFIAR: 1565 *val = get_reg_val(id, vcpu->arch.tfiar); 1566 break; 1567 case KVM_REG_PPC_TEXASR: 1568 *val = get_reg_val(id, vcpu->arch.texasr); 1569 break; 1570 case KVM_REG_PPC_TM_GPR0 ... KVM_REG_PPC_TM_GPR31: 1571 *val = get_reg_val(id, 1572 vcpu->arch.gpr_tm[id-KVM_REG_PPC_TM_GPR0]); 1573 break; 1574 case KVM_REG_PPC_TM_VSR0 ... KVM_REG_PPC_TM_VSR63: 1575 { 1576 int i, j; 1577 1578 i = id - KVM_REG_PPC_TM_VSR0; 1579 if (i < 32) 1580 for (j = 0; j < TS_FPRWIDTH; j++) 1581 val->vsxval[j] = vcpu->arch.fp_tm.fpr[i][j]; 1582 else { 1583 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 1584 val->vval = vcpu->arch.vr_tm.vr[i-32]; 1585 else 1586 r = -ENXIO; 1587 } 1588 break; 1589 } 1590 case KVM_REG_PPC_TM_CR: 1591 *val = get_reg_val(id, vcpu->arch.cr_tm); 1592 break; 1593 case KVM_REG_PPC_TM_XER: 1594 *val = get_reg_val(id, vcpu->arch.xer_tm); 1595 break; 1596 case KVM_REG_PPC_TM_LR: 1597 *val = get_reg_val(id, vcpu->arch.lr_tm); 1598 break; 1599 case KVM_REG_PPC_TM_CTR: 1600 *val = get_reg_val(id, vcpu->arch.ctr_tm); 1601 break; 1602 case KVM_REG_PPC_TM_FPSCR: 1603 *val = get_reg_val(id, vcpu->arch.fp_tm.fpscr); 1604 break; 1605 case KVM_REG_PPC_TM_AMR: 1606 *val = get_reg_val(id, vcpu->arch.amr_tm); 1607 break; 1608 case KVM_REG_PPC_TM_PPR: 1609 *val = get_reg_val(id, vcpu->arch.ppr_tm); 1610 break; 1611 case KVM_REG_PPC_TM_VRSAVE: 1612 *val = get_reg_val(id, vcpu->arch.vrsave_tm); 1613 break; 1614 case KVM_REG_PPC_TM_VSCR: 1615 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 1616 *val = get_reg_val(id, vcpu->arch.vr_tm.vscr.u[3]); 1617 else 1618 r = -ENXIO; 1619 break; 1620 case KVM_REG_PPC_TM_DSCR: 1621 *val = get_reg_val(id, vcpu->arch.dscr_tm); 1622 break; 1623 case KVM_REG_PPC_TM_TAR: 1624 *val = get_reg_val(id, vcpu->arch.tar_tm); 1625 break; 1626 #endif 1627 default: 1628 r = -EINVAL; 1629 break; 1630 } 1631 1632 return r; 1633 } 1634 1635 static void kvmppc_set_lpcr_pr(struct kvm_vcpu *vcpu, u64 new_lpcr) 1636 { 1637 if (new_lpcr & LPCR_ILE) 1638 vcpu->arch.intr_msr |= MSR_LE; 1639 else 1640 vcpu->arch.intr_msr &= ~MSR_LE; 1641 } 1642 1643 static int kvmppc_set_one_reg_pr(struct kvm_vcpu *vcpu, u64 id, 1644 union kvmppc_one_reg *val) 1645 { 1646 int r = 0; 1647 1648 switch (id) { 1649 case KVM_REG_PPC_HIOR: 1650 to_book3s(vcpu)->hior = set_reg_val(id, *val); 1651 to_book3s(vcpu)->hior_explicit = true; 1652 break; 1653 case KVM_REG_PPC_VTB: 1654 to_book3s(vcpu)->vtb = set_reg_val(id, *val); 1655 break; 1656 case KVM_REG_PPC_LPCR: 1657 case KVM_REG_PPC_LPCR_64: 1658 kvmppc_set_lpcr_pr(vcpu, set_reg_val(id, *val)); 1659 break; 1660 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1661 case KVM_REG_PPC_TFHAR: 1662 vcpu->arch.tfhar = set_reg_val(id, *val); 1663 break; 1664 case KVM_REG_PPC_TFIAR: 1665 vcpu->arch.tfiar = set_reg_val(id, *val); 1666 break; 1667 case KVM_REG_PPC_TEXASR: 1668 vcpu->arch.texasr = set_reg_val(id, *val); 1669 break; 1670 case KVM_REG_PPC_TM_GPR0 ... KVM_REG_PPC_TM_GPR31: 1671 vcpu->arch.gpr_tm[id - KVM_REG_PPC_TM_GPR0] = 1672 set_reg_val(id, *val); 1673 break; 1674 case KVM_REG_PPC_TM_VSR0 ... KVM_REG_PPC_TM_VSR63: 1675 { 1676 int i, j; 1677 1678 i = id - KVM_REG_PPC_TM_VSR0; 1679 if (i < 32) 1680 for (j = 0; j < TS_FPRWIDTH; j++) 1681 vcpu->arch.fp_tm.fpr[i][j] = val->vsxval[j]; 1682 else 1683 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 1684 vcpu->arch.vr_tm.vr[i-32] = val->vval; 1685 else 1686 r = -ENXIO; 1687 break; 1688 } 1689 case KVM_REG_PPC_TM_CR: 1690 vcpu->arch.cr_tm = set_reg_val(id, *val); 1691 break; 1692 case KVM_REG_PPC_TM_XER: 1693 vcpu->arch.xer_tm = set_reg_val(id, *val); 1694 break; 1695 case KVM_REG_PPC_TM_LR: 1696 vcpu->arch.lr_tm = set_reg_val(id, *val); 1697 break; 1698 case KVM_REG_PPC_TM_CTR: 1699 vcpu->arch.ctr_tm = set_reg_val(id, *val); 1700 break; 1701 case KVM_REG_PPC_TM_FPSCR: 1702 vcpu->arch.fp_tm.fpscr = set_reg_val(id, *val); 1703 break; 1704 case KVM_REG_PPC_TM_AMR: 1705 vcpu->arch.amr_tm = set_reg_val(id, *val); 1706 break; 1707 case KVM_REG_PPC_TM_PPR: 1708 vcpu->arch.ppr_tm = set_reg_val(id, *val); 1709 break; 1710 case KVM_REG_PPC_TM_VRSAVE: 1711 vcpu->arch.vrsave_tm = set_reg_val(id, *val); 1712 break; 1713 case KVM_REG_PPC_TM_VSCR: 1714 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 1715 vcpu->arch.vr.vscr.u[3] = set_reg_val(id, *val); 1716 else 1717 r = -ENXIO; 1718 break; 1719 case KVM_REG_PPC_TM_DSCR: 1720 vcpu->arch.dscr_tm = set_reg_val(id, *val); 1721 break; 1722 case KVM_REG_PPC_TM_TAR: 1723 vcpu->arch.tar_tm = set_reg_val(id, *val); 1724 break; 1725 #endif 1726 default: 1727 r = -EINVAL; 1728 break; 1729 } 1730 1731 return r; 1732 } 1733 1734 static int kvmppc_core_vcpu_create_pr(struct kvm_vcpu *vcpu) 1735 { 1736 struct kvmppc_vcpu_book3s *vcpu_book3s; 1737 unsigned long p; 1738 int err; 1739 1740 err = -ENOMEM; 1741 1742 vcpu_book3s = vzalloc(sizeof(struct kvmppc_vcpu_book3s)); 1743 if (!vcpu_book3s) 1744 goto out; 1745 vcpu->arch.book3s = vcpu_book3s; 1746 1747 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER 1748 vcpu->arch.shadow_vcpu = 1749 kzalloc(sizeof(*vcpu->arch.shadow_vcpu), GFP_KERNEL); 1750 if (!vcpu->arch.shadow_vcpu) 1751 goto free_vcpu3s; 1752 #endif 1753 1754 p = __get_free_page(GFP_KERNEL|__GFP_ZERO); 1755 if (!p) 1756 goto free_shadow_vcpu; 1757 vcpu->arch.shared = (void *)p; 1758 #ifdef CONFIG_PPC_BOOK3S_64 1759 /* Always start the shared struct in native endian mode */ 1760 #ifdef __BIG_ENDIAN__ 1761 vcpu->arch.shared_big_endian = true; 1762 #else 1763 vcpu->arch.shared_big_endian = false; 1764 #endif 1765 1766 /* 1767 * Default to the same as the host if we're on sufficiently 1768 * recent machine that we have 1TB segments; 1769 * otherwise default to PPC970FX. 1770 */ 1771 vcpu->arch.pvr = 0x3C0301; 1772 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 1773 vcpu->arch.pvr = mfspr(SPRN_PVR); 1774 vcpu->arch.intr_msr = MSR_SF; 1775 #else 1776 /* default to book3s_32 (750) */ 1777 vcpu->arch.pvr = 0x84202; 1778 vcpu->arch.intr_msr = 0; 1779 #endif 1780 kvmppc_set_pvr_pr(vcpu, vcpu->arch.pvr); 1781 vcpu->arch.slb_nr = 64; 1782 1783 vcpu->arch.shadow_msr = MSR_USER64 & ~MSR_LE; 1784 1785 err = kvmppc_mmu_init_pr(vcpu); 1786 if (err < 0) 1787 goto free_shared_page; 1788 1789 return 0; 1790 1791 free_shared_page: 1792 free_page((unsigned long)vcpu->arch.shared); 1793 free_shadow_vcpu: 1794 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER 1795 kfree(vcpu->arch.shadow_vcpu); 1796 free_vcpu3s: 1797 #endif 1798 vfree(vcpu_book3s); 1799 out: 1800 return err; 1801 } 1802 1803 static void kvmppc_core_vcpu_free_pr(struct kvm_vcpu *vcpu) 1804 { 1805 struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu); 1806 1807 kvmppc_mmu_destroy_pr(vcpu); 1808 free_page((unsigned long)vcpu->arch.shared & PAGE_MASK); 1809 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER 1810 kfree(vcpu->arch.shadow_vcpu); 1811 #endif 1812 vfree(vcpu_book3s); 1813 } 1814 1815 static int kvmppc_vcpu_run_pr(struct kvm_vcpu *vcpu) 1816 { 1817 int ret; 1818 1819 /* Check if we can run the vcpu at all */ 1820 if (!vcpu->arch.sane) { 1821 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 1822 ret = -EINVAL; 1823 goto out; 1824 } 1825 1826 kvmppc_setup_debug(vcpu); 1827 1828 /* 1829 * Interrupts could be timers for the guest which we have to inject 1830 * again, so let's postpone them until we're in the guest and if we 1831 * really did time things so badly, then we just exit again due to 1832 * a host external interrupt. 1833 */ 1834 ret = kvmppc_prepare_to_enter(vcpu); 1835 if (ret <= 0) 1836 goto out; 1837 /* interrupts now hard-disabled */ 1838 1839 /* Save FPU, Altivec and VSX state */ 1840 giveup_all(current); 1841 1842 /* Preload FPU if it's enabled */ 1843 if (kvmppc_get_msr(vcpu) & MSR_FP) 1844 kvmppc_handle_ext(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL, MSR_FP); 1845 1846 kvmppc_fix_ee_before_entry(); 1847 1848 ret = __kvmppc_vcpu_run(vcpu); 1849 1850 kvmppc_clear_debug(vcpu); 1851 1852 /* No need for guest_exit. It's done in handle_exit. 1853 We also get here with interrupts enabled. */ 1854 1855 /* Make sure we save the guest FPU/Altivec/VSX state */ 1856 kvmppc_giveup_ext(vcpu, MSR_FP | MSR_VEC | MSR_VSX); 1857 1858 /* Make sure we save the guest TAR/EBB/DSCR state */ 1859 kvmppc_giveup_fac(vcpu, FSCR_TAR_LG); 1860 1861 srr_regs_clobbered(); 1862 out: 1863 vcpu->mode = OUTSIDE_GUEST_MODE; 1864 return ret; 1865 } 1866 1867 /* 1868 * Get (and clear) the dirty memory log for a memory slot. 1869 */ 1870 static int kvm_vm_ioctl_get_dirty_log_pr(struct kvm *kvm, 1871 struct kvm_dirty_log *log) 1872 { 1873 struct kvm_memory_slot *memslot; 1874 struct kvm_vcpu *vcpu; 1875 ulong ga, ga_end; 1876 int is_dirty = 0; 1877 int r; 1878 unsigned long n; 1879 1880 mutex_lock(&kvm->slots_lock); 1881 1882 r = kvm_get_dirty_log(kvm, log, &is_dirty, &memslot); 1883 if (r) 1884 goto out; 1885 1886 /* If nothing is dirty, don't bother messing with page tables. */ 1887 if (is_dirty) { 1888 ga = memslot->base_gfn << PAGE_SHIFT; 1889 ga_end = ga + (memslot->npages << PAGE_SHIFT); 1890 1891 kvm_for_each_vcpu(n, vcpu, kvm) 1892 kvmppc_mmu_pte_pflush(vcpu, ga, ga_end); 1893 1894 n = kvm_dirty_bitmap_bytes(memslot); 1895 memset(memslot->dirty_bitmap, 0, n); 1896 } 1897 1898 r = 0; 1899 out: 1900 mutex_unlock(&kvm->slots_lock); 1901 return r; 1902 } 1903 1904 static void kvmppc_core_flush_memslot_pr(struct kvm *kvm, 1905 struct kvm_memory_slot *memslot) 1906 { 1907 return; 1908 } 1909 1910 static int kvmppc_core_prepare_memory_region_pr(struct kvm *kvm, 1911 const struct kvm_memory_slot *old, 1912 struct kvm_memory_slot *new, 1913 enum kvm_mr_change change) 1914 { 1915 return 0; 1916 } 1917 1918 static void kvmppc_core_commit_memory_region_pr(struct kvm *kvm, 1919 struct kvm_memory_slot *old, 1920 const struct kvm_memory_slot *new, 1921 enum kvm_mr_change change) 1922 { 1923 return; 1924 } 1925 1926 static void kvmppc_core_free_memslot_pr(struct kvm_memory_slot *slot) 1927 { 1928 return; 1929 } 1930 1931 #ifdef CONFIG_PPC64 1932 static int kvm_vm_ioctl_get_smmu_info_pr(struct kvm *kvm, 1933 struct kvm_ppc_smmu_info *info) 1934 { 1935 long int i; 1936 struct kvm_vcpu *vcpu; 1937 1938 info->flags = 0; 1939 1940 /* SLB is always 64 entries */ 1941 info->slb_size = 64; 1942 1943 /* Standard 4k base page size segment */ 1944 info->sps[0].page_shift = 12; 1945 info->sps[0].slb_enc = 0; 1946 info->sps[0].enc[0].page_shift = 12; 1947 info->sps[0].enc[0].pte_enc = 0; 1948 1949 /* 1950 * 64k large page size. 1951 * We only want to put this in if the CPUs we're emulating 1952 * support it, but unfortunately we don't have a vcpu easily 1953 * to hand here to test. Just pick the first vcpu, and if 1954 * that doesn't exist yet, report the minimum capability, 1955 * i.e., no 64k pages. 1956 * 1T segment support goes along with 64k pages. 1957 */ 1958 i = 1; 1959 vcpu = kvm_get_vcpu(kvm, 0); 1960 if (vcpu && (vcpu->arch.hflags & BOOK3S_HFLAG_MULTI_PGSIZE)) { 1961 info->flags = KVM_PPC_1T_SEGMENTS; 1962 info->sps[i].page_shift = 16; 1963 info->sps[i].slb_enc = SLB_VSID_L | SLB_VSID_LP_01; 1964 info->sps[i].enc[0].page_shift = 16; 1965 info->sps[i].enc[0].pte_enc = 1; 1966 ++i; 1967 } 1968 1969 /* Standard 16M large page size segment */ 1970 info->sps[i].page_shift = 24; 1971 info->sps[i].slb_enc = SLB_VSID_L; 1972 info->sps[i].enc[0].page_shift = 24; 1973 info->sps[i].enc[0].pte_enc = 0; 1974 1975 return 0; 1976 } 1977 1978 static int kvm_configure_mmu_pr(struct kvm *kvm, struct kvm_ppc_mmuv3_cfg *cfg) 1979 { 1980 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1981 return -ENODEV; 1982 /* Require flags and process table base and size to all be zero. */ 1983 if (cfg->flags || cfg->process_table) 1984 return -EINVAL; 1985 return 0; 1986 } 1987 1988 #else 1989 static int kvm_vm_ioctl_get_smmu_info_pr(struct kvm *kvm, 1990 struct kvm_ppc_smmu_info *info) 1991 { 1992 /* We should not get called */ 1993 BUG(); 1994 return 0; 1995 } 1996 #endif /* CONFIG_PPC64 */ 1997 1998 static unsigned int kvm_global_user_count = 0; 1999 static DEFINE_SPINLOCK(kvm_global_user_count_lock); 2000 2001 static int kvmppc_core_init_vm_pr(struct kvm *kvm) 2002 { 2003 mutex_init(&kvm->arch.hpt_mutex); 2004 2005 #ifdef CONFIG_PPC_BOOK3S_64 2006 /* Start out with the default set of hcalls enabled */ 2007 kvmppc_pr_init_default_hcalls(kvm); 2008 #endif 2009 2010 if (firmware_has_feature(FW_FEATURE_SET_MODE)) { 2011 spin_lock(&kvm_global_user_count_lock); 2012 if (++kvm_global_user_count == 1) 2013 pseries_disable_reloc_on_exc(); 2014 spin_unlock(&kvm_global_user_count_lock); 2015 } 2016 return 0; 2017 } 2018 2019 static void kvmppc_core_destroy_vm_pr(struct kvm *kvm) 2020 { 2021 #ifdef CONFIG_PPC64 2022 WARN_ON(!list_empty(&kvm->arch.spapr_tce_tables)); 2023 #endif 2024 2025 if (firmware_has_feature(FW_FEATURE_SET_MODE)) { 2026 spin_lock(&kvm_global_user_count_lock); 2027 BUG_ON(kvm_global_user_count == 0); 2028 if (--kvm_global_user_count == 0) 2029 pseries_enable_reloc_on_exc(); 2030 spin_unlock(&kvm_global_user_count_lock); 2031 } 2032 } 2033 2034 static int kvmppc_core_check_processor_compat_pr(void) 2035 { 2036 /* 2037 * PR KVM can work on POWER9 inside a guest partition 2038 * running in HPT mode. It can't work if we are using 2039 * radix translation (because radix provides no way for 2040 * a process to have unique translations in quadrant 3). 2041 */ 2042 if (cpu_has_feature(CPU_FTR_ARCH_300) && radix_enabled()) 2043 return -EIO; 2044 return 0; 2045 } 2046 2047 static int kvm_arch_vm_ioctl_pr(struct file *filp, 2048 unsigned int ioctl, unsigned long arg) 2049 { 2050 return -ENOTTY; 2051 } 2052 2053 static struct kvmppc_ops kvm_ops_pr = { 2054 .get_sregs = kvm_arch_vcpu_ioctl_get_sregs_pr, 2055 .set_sregs = kvm_arch_vcpu_ioctl_set_sregs_pr, 2056 .get_one_reg = kvmppc_get_one_reg_pr, 2057 .set_one_reg = kvmppc_set_one_reg_pr, 2058 .vcpu_load = kvmppc_core_vcpu_load_pr, 2059 .vcpu_put = kvmppc_core_vcpu_put_pr, 2060 .inject_interrupt = kvmppc_inject_interrupt_pr, 2061 .set_msr = kvmppc_set_msr_pr, 2062 .vcpu_run = kvmppc_vcpu_run_pr, 2063 .vcpu_create = kvmppc_core_vcpu_create_pr, 2064 .vcpu_free = kvmppc_core_vcpu_free_pr, 2065 .check_requests = kvmppc_core_check_requests_pr, 2066 .get_dirty_log = kvm_vm_ioctl_get_dirty_log_pr, 2067 .flush_memslot = kvmppc_core_flush_memslot_pr, 2068 .prepare_memory_region = kvmppc_core_prepare_memory_region_pr, 2069 .commit_memory_region = kvmppc_core_commit_memory_region_pr, 2070 .unmap_gfn_range = kvm_unmap_gfn_range_pr, 2071 .age_gfn = kvm_age_gfn_pr, 2072 .test_age_gfn = kvm_test_age_gfn_pr, 2073 .set_spte_gfn = kvm_set_spte_gfn_pr, 2074 .free_memslot = kvmppc_core_free_memslot_pr, 2075 .init_vm = kvmppc_core_init_vm_pr, 2076 .destroy_vm = kvmppc_core_destroy_vm_pr, 2077 .get_smmu_info = kvm_vm_ioctl_get_smmu_info_pr, 2078 .emulate_op = kvmppc_core_emulate_op_pr, 2079 .emulate_mtspr = kvmppc_core_emulate_mtspr_pr, 2080 .emulate_mfspr = kvmppc_core_emulate_mfspr_pr, 2081 .fast_vcpu_kick = kvm_vcpu_kick, 2082 .arch_vm_ioctl = kvm_arch_vm_ioctl_pr, 2083 #ifdef CONFIG_PPC_BOOK3S_64 2084 .hcall_implemented = kvmppc_hcall_impl_pr, 2085 .configure_mmu = kvm_configure_mmu_pr, 2086 #endif 2087 .giveup_ext = kvmppc_giveup_ext, 2088 }; 2089 2090 2091 int kvmppc_book3s_init_pr(void) 2092 { 2093 int r; 2094 2095 r = kvmppc_core_check_processor_compat_pr(); 2096 if (r < 0) 2097 return r; 2098 2099 kvm_ops_pr.owner = THIS_MODULE; 2100 kvmppc_pr_ops = &kvm_ops_pr; 2101 2102 r = kvmppc_mmu_hpte_sysinit(); 2103 return r; 2104 } 2105 2106 void kvmppc_book3s_exit_pr(void) 2107 { 2108 kvmppc_pr_ops = NULL; 2109 kvmppc_mmu_hpte_sysexit(); 2110 } 2111 2112 /* 2113 * We only support separate modules for book3s 64 2114 */ 2115 #ifdef CONFIG_PPC_BOOK3S_64 2116 2117 module_init(kvmppc_book3s_init_pr); 2118 module_exit(kvmppc_book3s_exit_pr); 2119 2120 MODULE_LICENSE("GPL"); 2121 MODULE_ALIAS_MISCDEV(KVM_MINOR); 2122 MODULE_ALIAS("devname:kvm"); 2123 #endif 2124