1 /* 2 * Copyright (C) 2009. SUSE Linux Products GmbH. All rights reserved. 3 * 4 * Authors: 5 * Alexander Graf <agraf@suse.de> 6 * Kevin Wolf <mail@kevin-wolf.de> 7 * Paul Mackerras <paulus@samba.org> 8 * 9 * Description: 10 * Functions relating to running KVM on Book 3S processors where 11 * we don't have access to hypervisor mode, and we run the guest 12 * in problem state (user mode). 13 * 14 * This file is derived from arch/powerpc/kvm/44x.c, 15 * by Hollis Blanchard <hollisb@us.ibm.com>. 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of the GNU General Public License, version 2, as 19 * published by the Free Software Foundation. 20 */ 21 22 #include <linux/kvm_host.h> 23 #include <linux/export.h> 24 #include <linux/err.h> 25 #include <linux/slab.h> 26 27 #include <asm/reg.h> 28 #include <asm/cputable.h> 29 #include <asm/cacheflush.h> 30 #include <asm/tlbflush.h> 31 #include <linux/uaccess.h> 32 #include <asm/io.h> 33 #include <asm/kvm_ppc.h> 34 #include <asm/kvm_book3s.h> 35 #include <asm/mmu_context.h> 36 #include <asm/switch_to.h> 37 #include <asm/firmware.h> 38 #include <asm/setup.h> 39 #include <linux/gfp.h> 40 #include <linux/sched.h> 41 #include <linux/vmalloc.h> 42 #include <linux/highmem.h> 43 #include <linux/module.h> 44 #include <linux/miscdevice.h> 45 #include <asm/asm-prototypes.h> 46 #include <asm/tm.h> 47 48 #include "book3s.h" 49 50 #define CREATE_TRACE_POINTS 51 #include "trace_pr.h" 52 53 /* #define EXIT_DEBUG */ 54 /* #define DEBUG_EXT */ 55 56 static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr, 57 ulong msr); 58 #ifdef CONFIG_PPC_BOOK3S_64 59 static int kvmppc_handle_fac(struct kvm_vcpu *vcpu, ulong fac); 60 #endif 61 62 /* Some compatibility defines */ 63 #ifdef CONFIG_PPC_BOOK3S_32 64 #define MSR_USER32 MSR_USER 65 #define MSR_USER64 MSR_USER 66 #define HW_PAGE_SIZE PAGE_SIZE 67 #define HPTE_R_M _PAGE_COHERENT 68 #endif 69 70 static bool kvmppc_is_split_real(struct kvm_vcpu *vcpu) 71 { 72 ulong msr = kvmppc_get_msr(vcpu); 73 return (msr & (MSR_IR|MSR_DR)) == MSR_DR; 74 } 75 76 static void kvmppc_fixup_split_real(struct kvm_vcpu *vcpu) 77 { 78 ulong msr = kvmppc_get_msr(vcpu); 79 ulong pc = kvmppc_get_pc(vcpu); 80 81 /* We are in DR only split real mode */ 82 if ((msr & (MSR_IR|MSR_DR)) != MSR_DR) 83 return; 84 85 /* We have not fixed up the guest already */ 86 if (vcpu->arch.hflags & BOOK3S_HFLAG_SPLIT_HACK) 87 return; 88 89 /* The code is in fixupable address space */ 90 if (pc & SPLIT_HACK_MASK) 91 return; 92 93 vcpu->arch.hflags |= BOOK3S_HFLAG_SPLIT_HACK; 94 kvmppc_set_pc(vcpu, pc | SPLIT_HACK_OFFS); 95 } 96 97 void kvmppc_unfixup_split_real(struct kvm_vcpu *vcpu); 98 99 static void kvmppc_core_vcpu_load_pr(struct kvm_vcpu *vcpu, int cpu) 100 { 101 #ifdef CONFIG_PPC_BOOK3S_64 102 struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu); 103 memcpy(svcpu->slb, to_book3s(vcpu)->slb_shadow, sizeof(svcpu->slb)); 104 svcpu->slb_max = to_book3s(vcpu)->slb_shadow_max; 105 svcpu->in_use = 0; 106 svcpu_put(svcpu); 107 #endif 108 109 /* Disable AIL if supported */ 110 if (cpu_has_feature(CPU_FTR_HVMODE) && 111 cpu_has_feature(CPU_FTR_ARCH_207S)) 112 mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) & ~LPCR_AIL); 113 114 vcpu->cpu = smp_processor_id(); 115 #ifdef CONFIG_PPC_BOOK3S_32 116 current->thread.kvm_shadow_vcpu = vcpu->arch.shadow_vcpu; 117 #endif 118 119 if (kvmppc_is_split_real(vcpu)) 120 kvmppc_fixup_split_real(vcpu); 121 122 kvmppc_restore_tm_pr(vcpu); 123 } 124 125 static void kvmppc_core_vcpu_put_pr(struct kvm_vcpu *vcpu) 126 { 127 #ifdef CONFIG_PPC_BOOK3S_64 128 struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu); 129 if (svcpu->in_use) { 130 kvmppc_copy_from_svcpu(vcpu); 131 } 132 memcpy(to_book3s(vcpu)->slb_shadow, svcpu->slb, sizeof(svcpu->slb)); 133 to_book3s(vcpu)->slb_shadow_max = svcpu->slb_max; 134 svcpu_put(svcpu); 135 #endif 136 137 if (kvmppc_is_split_real(vcpu)) 138 kvmppc_unfixup_split_real(vcpu); 139 140 kvmppc_giveup_ext(vcpu, MSR_FP | MSR_VEC | MSR_VSX); 141 kvmppc_giveup_fac(vcpu, FSCR_TAR_LG); 142 kvmppc_save_tm_pr(vcpu); 143 144 /* Enable AIL if supported */ 145 if (cpu_has_feature(CPU_FTR_HVMODE) && 146 cpu_has_feature(CPU_FTR_ARCH_207S)) 147 mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) | LPCR_AIL_3); 148 149 vcpu->cpu = -1; 150 } 151 152 /* Copy data needed by real-mode code from vcpu to shadow vcpu */ 153 void kvmppc_copy_to_svcpu(struct kvm_vcpu *vcpu) 154 { 155 struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu); 156 157 svcpu->gpr[0] = vcpu->arch.regs.gpr[0]; 158 svcpu->gpr[1] = vcpu->arch.regs.gpr[1]; 159 svcpu->gpr[2] = vcpu->arch.regs.gpr[2]; 160 svcpu->gpr[3] = vcpu->arch.regs.gpr[3]; 161 svcpu->gpr[4] = vcpu->arch.regs.gpr[4]; 162 svcpu->gpr[5] = vcpu->arch.regs.gpr[5]; 163 svcpu->gpr[6] = vcpu->arch.regs.gpr[6]; 164 svcpu->gpr[7] = vcpu->arch.regs.gpr[7]; 165 svcpu->gpr[8] = vcpu->arch.regs.gpr[8]; 166 svcpu->gpr[9] = vcpu->arch.regs.gpr[9]; 167 svcpu->gpr[10] = vcpu->arch.regs.gpr[10]; 168 svcpu->gpr[11] = vcpu->arch.regs.gpr[11]; 169 svcpu->gpr[12] = vcpu->arch.regs.gpr[12]; 170 svcpu->gpr[13] = vcpu->arch.regs.gpr[13]; 171 svcpu->cr = vcpu->arch.cr; 172 svcpu->xer = vcpu->arch.regs.xer; 173 svcpu->ctr = vcpu->arch.regs.ctr; 174 svcpu->lr = vcpu->arch.regs.link; 175 svcpu->pc = vcpu->arch.regs.nip; 176 #ifdef CONFIG_PPC_BOOK3S_64 177 svcpu->shadow_fscr = vcpu->arch.shadow_fscr; 178 #endif 179 /* 180 * Now also save the current time base value. We use this 181 * to find the guest purr and spurr value. 182 */ 183 vcpu->arch.entry_tb = get_tb(); 184 vcpu->arch.entry_vtb = get_vtb(); 185 if (cpu_has_feature(CPU_FTR_ARCH_207S)) 186 vcpu->arch.entry_ic = mfspr(SPRN_IC); 187 svcpu->in_use = true; 188 189 svcpu_put(svcpu); 190 } 191 192 static void kvmppc_recalc_shadow_msr(struct kvm_vcpu *vcpu) 193 { 194 ulong guest_msr = kvmppc_get_msr(vcpu); 195 ulong smsr = guest_msr; 196 197 /* Guest MSR values */ 198 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 199 smsr &= MSR_FE0 | MSR_FE1 | MSR_SF | MSR_SE | MSR_BE | MSR_LE | 200 MSR_TM | MSR_TS_MASK; 201 #else 202 smsr &= MSR_FE0 | MSR_FE1 | MSR_SF | MSR_SE | MSR_BE | MSR_LE; 203 #endif 204 /* Process MSR values */ 205 smsr |= MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_PR | MSR_EE; 206 /* External providers the guest reserved */ 207 smsr |= (guest_msr & vcpu->arch.guest_owned_ext); 208 /* 64-bit Process MSR values */ 209 #ifdef CONFIG_PPC_BOOK3S_64 210 smsr |= MSR_ISF | MSR_HV; 211 #endif 212 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 213 /* 214 * in guest privileged state, we want to fail all TM transactions. 215 * So disable MSR TM bit so that all tbegin. will be able to be 216 * trapped into host. 217 */ 218 if (!(guest_msr & MSR_PR)) 219 smsr &= ~MSR_TM; 220 #endif 221 vcpu->arch.shadow_msr = smsr; 222 } 223 224 /* Copy data touched by real-mode code from shadow vcpu back to vcpu */ 225 void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu) 226 { 227 struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu); 228 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 229 ulong old_msr; 230 #endif 231 232 /* 233 * Maybe we were already preempted and synced the svcpu from 234 * our preempt notifiers. Don't bother touching this svcpu then. 235 */ 236 if (!svcpu->in_use) 237 goto out; 238 239 vcpu->arch.regs.gpr[0] = svcpu->gpr[0]; 240 vcpu->arch.regs.gpr[1] = svcpu->gpr[1]; 241 vcpu->arch.regs.gpr[2] = svcpu->gpr[2]; 242 vcpu->arch.regs.gpr[3] = svcpu->gpr[3]; 243 vcpu->arch.regs.gpr[4] = svcpu->gpr[4]; 244 vcpu->arch.regs.gpr[5] = svcpu->gpr[5]; 245 vcpu->arch.regs.gpr[6] = svcpu->gpr[6]; 246 vcpu->arch.regs.gpr[7] = svcpu->gpr[7]; 247 vcpu->arch.regs.gpr[8] = svcpu->gpr[8]; 248 vcpu->arch.regs.gpr[9] = svcpu->gpr[9]; 249 vcpu->arch.regs.gpr[10] = svcpu->gpr[10]; 250 vcpu->arch.regs.gpr[11] = svcpu->gpr[11]; 251 vcpu->arch.regs.gpr[12] = svcpu->gpr[12]; 252 vcpu->arch.regs.gpr[13] = svcpu->gpr[13]; 253 vcpu->arch.cr = svcpu->cr; 254 vcpu->arch.regs.xer = svcpu->xer; 255 vcpu->arch.regs.ctr = svcpu->ctr; 256 vcpu->arch.regs.link = svcpu->lr; 257 vcpu->arch.regs.nip = svcpu->pc; 258 vcpu->arch.shadow_srr1 = svcpu->shadow_srr1; 259 vcpu->arch.fault_dar = svcpu->fault_dar; 260 vcpu->arch.fault_dsisr = svcpu->fault_dsisr; 261 vcpu->arch.last_inst = svcpu->last_inst; 262 #ifdef CONFIG_PPC_BOOK3S_64 263 vcpu->arch.shadow_fscr = svcpu->shadow_fscr; 264 #endif 265 /* 266 * Update purr and spurr using time base on exit. 267 */ 268 vcpu->arch.purr += get_tb() - vcpu->arch.entry_tb; 269 vcpu->arch.spurr += get_tb() - vcpu->arch.entry_tb; 270 to_book3s(vcpu)->vtb += get_vtb() - vcpu->arch.entry_vtb; 271 if (cpu_has_feature(CPU_FTR_ARCH_207S)) 272 vcpu->arch.ic += mfspr(SPRN_IC) - vcpu->arch.entry_ic; 273 274 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 275 /* 276 * Unlike other MSR bits, MSR[TS]bits can be changed at guest without 277 * notifying host: 278 * modified by unprivileged instructions like "tbegin"/"tend"/ 279 * "tresume"/"tsuspend" in PR KVM guest. 280 * 281 * It is necessary to sync here to calculate a correct shadow_msr. 282 * 283 * privileged guest's tbegin will be failed at present. So we 284 * only take care of problem state guest. 285 */ 286 old_msr = kvmppc_get_msr(vcpu); 287 if (unlikely((old_msr & MSR_PR) && 288 (vcpu->arch.shadow_srr1 & (MSR_TS_MASK)) != 289 (old_msr & (MSR_TS_MASK)))) { 290 old_msr &= ~(MSR_TS_MASK); 291 old_msr |= (vcpu->arch.shadow_srr1 & (MSR_TS_MASK)); 292 kvmppc_set_msr_fast(vcpu, old_msr); 293 kvmppc_recalc_shadow_msr(vcpu); 294 } 295 #endif 296 297 svcpu->in_use = false; 298 299 out: 300 svcpu_put(svcpu); 301 } 302 303 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 304 void kvmppc_save_tm_sprs(struct kvm_vcpu *vcpu) 305 { 306 tm_enable(); 307 vcpu->arch.tfhar = mfspr(SPRN_TFHAR); 308 vcpu->arch.texasr = mfspr(SPRN_TEXASR); 309 vcpu->arch.tfiar = mfspr(SPRN_TFIAR); 310 tm_disable(); 311 } 312 313 void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu) 314 { 315 tm_enable(); 316 mtspr(SPRN_TFHAR, vcpu->arch.tfhar); 317 mtspr(SPRN_TEXASR, vcpu->arch.texasr); 318 mtspr(SPRN_TFIAR, vcpu->arch.tfiar); 319 tm_disable(); 320 } 321 322 /* loadup math bits which is enabled at kvmppc_get_msr() but not enabled at 323 * hardware. 324 */ 325 static void kvmppc_handle_lost_math_exts(struct kvm_vcpu *vcpu) 326 { 327 ulong exit_nr; 328 ulong ext_diff = (kvmppc_get_msr(vcpu) & ~vcpu->arch.guest_owned_ext) & 329 (MSR_FP | MSR_VEC | MSR_VSX); 330 331 if (!ext_diff) 332 return; 333 334 if (ext_diff == MSR_FP) 335 exit_nr = BOOK3S_INTERRUPT_FP_UNAVAIL; 336 else if (ext_diff == MSR_VEC) 337 exit_nr = BOOK3S_INTERRUPT_ALTIVEC; 338 else 339 exit_nr = BOOK3S_INTERRUPT_VSX; 340 341 kvmppc_handle_ext(vcpu, exit_nr, ext_diff); 342 } 343 344 void kvmppc_save_tm_pr(struct kvm_vcpu *vcpu) 345 { 346 if (!(MSR_TM_ACTIVE(kvmppc_get_msr(vcpu)))) { 347 kvmppc_save_tm_sprs(vcpu); 348 return; 349 } 350 351 kvmppc_giveup_fac(vcpu, FSCR_TAR_LG); 352 kvmppc_giveup_ext(vcpu, MSR_VSX); 353 354 preempt_disable(); 355 _kvmppc_save_tm_pr(vcpu, mfmsr()); 356 preempt_enable(); 357 } 358 359 void kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu) 360 { 361 if (!MSR_TM_ACTIVE(kvmppc_get_msr(vcpu))) { 362 kvmppc_restore_tm_sprs(vcpu); 363 if (kvmppc_get_msr(vcpu) & MSR_TM) { 364 kvmppc_handle_lost_math_exts(vcpu); 365 if (vcpu->arch.fscr & FSCR_TAR) 366 kvmppc_handle_fac(vcpu, FSCR_TAR_LG); 367 } 368 return; 369 } 370 371 preempt_disable(); 372 _kvmppc_restore_tm_pr(vcpu, kvmppc_get_msr(vcpu)); 373 preempt_enable(); 374 375 if (kvmppc_get_msr(vcpu) & MSR_TM) { 376 kvmppc_handle_lost_math_exts(vcpu); 377 if (vcpu->arch.fscr & FSCR_TAR) 378 kvmppc_handle_fac(vcpu, FSCR_TAR_LG); 379 } 380 } 381 #endif 382 383 static int kvmppc_core_check_requests_pr(struct kvm_vcpu *vcpu) 384 { 385 int r = 1; /* Indicate we want to get back into the guest */ 386 387 /* We misuse TLB_FLUSH to indicate that we want to clear 388 all shadow cache entries */ 389 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 390 kvmppc_mmu_pte_flush(vcpu, 0, 0); 391 392 return r; 393 } 394 395 /************* MMU Notifiers *************/ 396 static void do_kvm_unmap_hva(struct kvm *kvm, unsigned long start, 397 unsigned long end) 398 { 399 long i; 400 struct kvm_vcpu *vcpu; 401 struct kvm_memslots *slots; 402 struct kvm_memory_slot *memslot; 403 404 slots = kvm_memslots(kvm); 405 kvm_for_each_memslot(memslot, slots) { 406 unsigned long hva_start, hva_end; 407 gfn_t gfn, gfn_end; 408 409 hva_start = max(start, memslot->userspace_addr); 410 hva_end = min(end, memslot->userspace_addr + 411 (memslot->npages << PAGE_SHIFT)); 412 if (hva_start >= hva_end) 413 continue; 414 /* 415 * {gfn(page) | page intersects with [hva_start, hva_end)} = 416 * {gfn, gfn+1, ..., gfn_end-1}. 417 */ 418 gfn = hva_to_gfn_memslot(hva_start, memslot); 419 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot); 420 kvm_for_each_vcpu(i, vcpu, kvm) 421 kvmppc_mmu_pte_pflush(vcpu, gfn << PAGE_SHIFT, 422 gfn_end << PAGE_SHIFT); 423 } 424 } 425 426 static int kvm_unmap_hva_range_pr(struct kvm *kvm, unsigned long start, 427 unsigned long end) 428 { 429 do_kvm_unmap_hva(kvm, start, end); 430 431 return 0; 432 } 433 434 static int kvm_age_hva_pr(struct kvm *kvm, unsigned long start, 435 unsigned long end) 436 { 437 /* XXX could be more clever ;) */ 438 return 0; 439 } 440 441 static int kvm_test_age_hva_pr(struct kvm *kvm, unsigned long hva) 442 { 443 /* XXX could be more clever ;) */ 444 return 0; 445 } 446 447 static void kvm_set_spte_hva_pr(struct kvm *kvm, unsigned long hva, pte_t pte) 448 { 449 /* The page will get remapped properly on its next fault */ 450 do_kvm_unmap_hva(kvm, hva, hva + PAGE_SIZE); 451 } 452 453 /*****************************************/ 454 455 static void kvmppc_set_msr_pr(struct kvm_vcpu *vcpu, u64 msr) 456 { 457 ulong old_msr; 458 459 /* For PAPR guest, make sure MSR reflects guest mode */ 460 if (vcpu->arch.papr_enabled) 461 msr = (msr & ~MSR_HV) | MSR_ME; 462 463 #ifdef EXIT_DEBUG 464 printk(KERN_INFO "KVM: Set MSR to 0x%llx\n", msr); 465 #endif 466 467 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 468 /* We should never target guest MSR to TS=10 && PR=0, 469 * since we always fail transaction for guest privilege 470 * state. 471 */ 472 if (!(msr & MSR_PR) && MSR_TM_TRANSACTIONAL(msr)) 473 kvmppc_emulate_tabort(vcpu, 474 TM_CAUSE_KVM_FAC_UNAV | TM_CAUSE_PERSISTENT); 475 #endif 476 477 old_msr = kvmppc_get_msr(vcpu); 478 msr &= to_book3s(vcpu)->msr_mask; 479 kvmppc_set_msr_fast(vcpu, msr); 480 kvmppc_recalc_shadow_msr(vcpu); 481 482 if (msr & MSR_POW) { 483 if (!vcpu->arch.pending_exceptions) { 484 kvm_vcpu_block(vcpu); 485 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 486 vcpu->stat.halt_wakeup++; 487 488 /* Unset POW bit after we woke up */ 489 msr &= ~MSR_POW; 490 kvmppc_set_msr_fast(vcpu, msr); 491 } 492 } 493 494 if (kvmppc_is_split_real(vcpu)) 495 kvmppc_fixup_split_real(vcpu); 496 else 497 kvmppc_unfixup_split_real(vcpu); 498 499 if ((kvmppc_get_msr(vcpu) & (MSR_PR|MSR_IR|MSR_DR)) != 500 (old_msr & (MSR_PR|MSR_IR|MSR_DR))) { 501 kvmppc_mmu_flush_segments(vcpu); 502 kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu)); 503 504 /* Preload magic page segment when in kernel mode */ 505 if (!(msr & MSR_PR) && vcpu->arch.magic_page_pa) { 506 struct kvm_vcpu_arch *a = &vcpu->arch; 507 508 if (msr & MSR_DR) 509 kvmppc_mmu_map_segment(vcpu, a->magic_page_ea); 510 else 511 kvmppc_mmu_map_segment(vcpu, a->magic_page_pa); 512 } 513 } 514 515 /* 516 * When switching from 32 to 64-bit, we may have a stale 32-bit 517 * magic page around, we need to flush it. Typically 32-bit magic 518 * page will be instanciated when calling into RTAS. Note: We 519 * assume that such transition only happens while in kernel mode, 520 * ie, we never transition from user 32-bit to kernel 64-bit with 521 * a 32-bit magic page around. 522 */ 523 if (vcpu->arch.magic_page_pa && 524 !(old_msr & MSR_PR) && !(old_msr & MSR_SF) && (msr & MSR_SF)) { 525 /* going from RTAS to normal kernel code */ 526 kvmppc_mmu_pte_flush(vcpu, (uint32_t)vcpu->arch.magic_page_pa, 527 ~0xFFFUL); 528 } 529 530 /* Preload FPU if it's enabled */ 531 if (kvmppc_get_msr(vcpu) & MSR_FP) 532 kvmppc_handle_ext(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL, MSR_FP); 533 534 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 535 if (kvmppc_get_msr(vcpu) & MSR_TM) 536 kvmppc_handle_lost_math_exts(vcpu); 537 #endif 538 } 539 540 void kvmppc_set_pvr_pr(struct kvm_vcpu *vcpu, u32 pvr) 541 { 542 u32 host_pvr; 543 544 vcpu->arch.hflags &= ~BOOK3S_HFLAG_SLB; 545 vcpu->arch.pvr = pvr; 546 #ifdef CONFIG_PPC_BOOK3S_64 547 if ((pvr >= 0x330000) && (pvr < 0x70330000)) { 548 kvmppc_mmu_book3s_64_init(vcpu); 549 if (!to_book3s(vcpu)->hior_explicit) 550 to_book3s(vcpu)->hior = 0xfff00000; 551 to_book3s(vcpu)->msr_mask = 0xffffffffffffffffULL; 552 vcpu->arch.cpu_type = KVM_CPU_3S_64; 553 } else 554 #endif 555 { 556 kvmppc_mmu_book3s_32_init(vcpu); 557 if (!to_book3s(vcpu)->hior_explicit) 558 to_book3s(vcpu)->hior = 0; 559 to_book3s(vcpu)->msr_mask = 0xffffffffULL; 560 vcpu->arch.cpu_type = KVM_CPU_3S_32; 561 } 562 563 kvmppc_sanity_check(vcpu); 564 565 /* If we are in hypervisor level on 970, we can tell the CPU to 566 * treat DCBZ as 32 bytes store */ 567 vcpu->arch.hflags &= ~BOOK3S_HFLAG_DCBZ32; 568 if (vcpu->arch.mmu.is_dcbz32(vcpu) && (mfmsr() & MSR_HV) && 569 !strcmp(cur_cpu_spec->platform, "ppc970")) 570 vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32; 571 572 /* Cell performs badly if MSR_FEx are set. So let's hope nobody 573 really needs them in a VM on Cell and force disable them. */ 574 if (!strcmp(cur_cpu_spec->platform, "ppc-cell-be")) 575 to_book3s(vcpu)->msr_mask &= ~(MSR_FE0 | MSR_FE1); 576 577 /* 578 * If they're asking for POWER6 or later, set the flag 579 * indicating that we can do multiple large page sizes 580 * and 1TB segments. 581 * Also set the flag that indicates that tlbie has the large 582 * page bit in the RB operand instead of the instruction. 583 */ 584 switch (PVR_VER(pvr)) { 585 case PVR_POWER6: 586 case PVR_POWER7: 587 case PVR_POWER7p: 588 case PVR_POWER8: 589 case PVR_POWER8E: 590 case PVR_POWER8NVL: 591 vcpu->arch.hflags |= BOOK3S_HFLAG_MULTI_PGSIZE | 592 BOOK3S_HFLAG_NEW_TLBIE; 593 break; 594 } 595 596 #ifdef CONFIG_PPC_BOOK3S_32 597 /* 32 bit Book3S always has 32 byte dcbz */ 598 vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32; 599 #endif 600 601 /* On some CPUs we can execute paired single operations natively */ 602 asm ( "mfpvr %0" : "=r"(host_pvr)); 603 switch (host_pvr) { 604 case 0x00080200: /* lonestar 2.0 */ 605 case 0x00088202: /* lonestar 2.2 */ 606 case 0x70000100: /* gekko 1.0 */ 607 case 0x00080100: /* gekko 2.0 */ 608 case 0x00083203: /* gekko 2.3a */ 609 case 0x00083213: /* gekko 2.3b */ 610 case 0x00083204: /* gekko 2.4 */ 611 case 0x00083214: /* gekko 2.4e (8SE) - retail HW2 */ 612 case 0x00087200: /* broadway */ 613 vcpu->arch.hflags |= BOOK3S_HFLAG_NATIVE_PS; 614 /* Enable HID2.PSE - in case we need it later */ 615 mtspr(SPRN_HID2_GEKKO, mfspr(SPRN_HID2_GEKKO) | (1 << 29)); 616 } 617 } 618 619 /* Book3s_32 CPUs always have 32 bytes cache line size, which Linux assumes. To 620 * make Book3s_32 Linux work on Book3s_64, we have to make sure we trap dcbz to 621 * emulate 32 bytes dcbz length. 622 * 623 * The Book3s_64 inventors also realized this case and implemented a special bit 624 * in the HID5 register, which is a hypervisor ressource. Thus we can't use it. 625 * 626 * My approach here is to patch the dcbz instruction on executing pages. 627 */ 628 static void kvmppc_patch_dcbz(struct kvm_vcpu *vcpu, struct kvmppc_pte *pte) 629 { 630 struct page *hpage; 631 u64 hpage_offset; 632 u32 *page; 633 int i; 634 635 hpage = gfn_to_page(vcpu->kvm, pte->raddr >> PAGE_SHIFT); 636 if (is_error_page(hpage)) 637 return; 638 639 hpage_offset = pte->raddr & ~PAGE_MASK; 640 hpage_offset &= ~0xFFFULL; 641 hpage_offset /= 4; 642 643 get_page(hpage); 644 page = kmap_atomic(hpage); 645 646 /* patch dcbz into reserved instruction, so we trap */ 647 for (i=hpage_offset; i < hpage_offset + (HW_PAGE_SIZE / 4); i++) 648 if ((be32_to_cpu(page[i]) & 0xff0007ff) == INS_DCBZ) 649 page[i] &= cpu_to_be32(0xfffffff7); 650 651 kunmap_atomic(page); 652 put_page(hpage); 653 } 654 655 static bool kvmppc_visible_gpa(struct kvm_vcpu *vcpu, gpa_t gpa) 656 { 657 ulong mp_pa = vcpu->arch.magic_page_pa; 658 659 if (!(kvmppc_get_msr(vcpu) & MSR_SF)) 660 mp_pa = (uint32_t)mp_pa; 661 662 gpa &= ~0xFFFULL; 663 if (unlikely(mp_pa) && unlikely((mp_pa & KVM_PAM) == (gpa & KVM_PAM))) { 664 return true; 665 } 666 667 return kvm_is_visible_gfn(vcpu->kvm, gpa >> PAGE_SHIFT); 668 } 669 670 int kvmppc_handle_pagefault(struct kvm_run *run, struct kvm_vcpu *vcpu, 671 ulong eaddr, int vec) 672 { 673 bool data = (vec == BOOK3S_INTERRUPT_DATA_STORAGE); 674 bool iswrite = false; 675 int r = RESUME_GUEST; 676 int relocated; 677 int page_found = 0; 678 struct kvmppc_pte pte = { 0 }; 679 bool dr = (kvmppc_get_msr(vcpu) & MSR_DR) ? true : false; 680 bool ir = (kvmppc_get_msr(vcpu) & MSR_IR) ? true : false; 681 u64 vsid; 682 683 relocated = data ? dr : ir; 684 if (data && (vcpu->arch.fault_dsisr & DSISR_ISSTORE)) 685 iswrite = true; 686 687 /* Resolve real address if translation turned on */ 688 if (relocated) { 689 page_found = vcpu->arch.mmu.xlate(vcpu, eaddr, &pte, data, iswrite); 690 } else { 691 pte.may_execute = true; 692 pte.may_read = true; 693 pte.may_write = true; 694 pte.raddr = eaddr & KVM_PAM; 695 pte.eaddr = eaddr; 696 pte.vpage = eaddr >> 12; 697 pte.page_size = MMU_PAGE_64K; 698 pte.wimg = HPTE_R_M; 699 } 700 701 switch (kvmppc_get_msr(vcpu) & (MSR_DR|MSR_IR)) { 702 case 0: 703 pte.vpage |= ((u64)VSID_REAL << (SID_SHIFT - 12)); 704 break; 705 case MSR_DR: 706 if (!data && 707 (vcpu->arch.hflags & BOOK3S_HFLAG_SPLIT_HACK) && 708 ((pte.raddr & SPLIT_HACK_MASK) == SPLIT_HACK_OFFS)) 709 pte.raddr &= ~SPLIT_HACK_MASK; 710 /* fall through */ 711 case MSR_IR: 712 vcpu->arch.mmu.esid_to_vsid(vcpu, eaddr >> SID_SHIFT, &vsid); 713 714 if ((kvmppc_get_msr(vcpu) & (MSR_DR|MSR_IR)) == MSR_DR) 715 pte.vpage |= ((u64)VSID_REAL_DR << (SID_SHIFT - 12)); 716 else 717 pte.vpage |= ((u64)VSID_REAL_IR << (SID_SHIFT - 12)); 718 pte.vpage |= vsid; 719 720 if (vsid == -1) 721 page_found = -EINVAL; 722 break; 723 } 724 725 if (vcpu->arch.mmu.is_dcbz32(vcpu) && 726 (!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) { 727 /* 728 * If we do the dcbz hack, we have to NX on every execution, 729 * so we can patch the executing code. This renders our guest 730 * NX-less. 731 */ 732 pte.may_execute = !data; 733 } 734 735 if (page_found == -ENOENT || page_found == -EPERM) { 736 /* Page not found in guest PTE entries, or protection fault */ 737 u64 flags; 738 739 if (page_found == -EPERM) 740 flags = DSISR_PROTFAULT; 741 else 742 flags = DSISR_NOHPTE; 743 if (data) { 744 flags |= vcpu->arch.fault_dsisr & DSISR_ISSTORE; 745 kvmppc_core_queue_data_storage(vcpu, eaddr, flags); 746 } else { 747 kvmppc_core_queue_inst_storage(vcpu, flags); 748 } 749 } else if (page_found == -EINVAL) { 750 /* Page not found in guest SLB */ 751 kvmppc_set_dar(vcpu, kvmppc_get_fault_dar(vcpu)); 752 kvmppc_book3s_queue_irqprio(vcpu, vec + 0x80); 753 } else if (kvmppc_visible_gpa(vcpu, pte.raddr)) { 754 if (data && !(vcpu->arch.fault_dsisr & DSISR_NOHPTE)) { 755 /* 756 * There is already a host HPTE there, presumably 757 * a read-only one for a page the guest thinks 758 * is writable, so get rid of it first. 759 */ 760 kvmppc_mmu_unmap_page(vcpu, &pte); 761 } 762 /* The guest's PTE is not mapped yet. Map on the host */ 763 if (kvmppc_mmu_map_page(vcpu, &pte, iswrite) == -EIO) { 764 /* Exit KVM if mapping failed */ 765 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 766 return RESUME_HOST; 767 } 768 if (data) 769 vcpu->stat.sp_storage++; 770 else if (vcpu->arch.mmu.is_dcbz32(vcpu) && 771 (!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) 772 kvmppc_patch_dcbz(vcpu, &pte); 773 } else { 774 /* MMIO */ 775 vcpu->stat.mmio_exits++; 776 vcpu->arch.paddr_accessed = pte.raddr; 777 vcpu->arch.vaddr_accessed = pte.eaddr; 778 r = kvmppc_emulate_mmio(run, vcpu); 779 if ( r == RESUME_HOST_NV ) 780 r = RESUME_HOST; 781 } 782 783 return r; 784 } 785 786 /* Give up external provider (FPU, Altivec, VSX) */ 787 void kvmppc_giveup_ext(struct kvm_vcpu *vcpu, ulong msr) 788 { 789 struct thread_struct *t = ¤t->thread; 790 791 /* 792 * VSX instructions can access FP and vector registers, so if 793 * we are giving up VSX, make sure we give up FP and VMX as well. 794 */ 795 if (msr & MSR_VSX) 796 msr |= MSR_FP | MSR_VEC; 797 798 msr &= vcpu->arch.guest_owned_ext; 799 if (!msr) 800 return; 801 802 #ifdef DEBUG_EXT 803 printk(KERN_INFO "Giving up ext 0x%lx\n", msr); 804 #endif 805 806 if (msr & MSR_FP) { 807 /* 808 * Note that on CPUs with VSX, giveup_fpu stores 809 * both the traditional FP registers and the added VSX 810 * registers into thread.fp_state.fpr[]. 811 */ 812 if (t->regs->msr & MSR_FP) 813 giveup_fpu(current); 814 t->fp_save_area = NULL; 815 } 816 817 #ifdef CONFIG_ALTIVEC 818 if (msr & MSR_VEC) { 819 if (current->thread.regs->msr & MSR_VEC) 820 giveup_altivec(current); 821 t->vr_save_area = NULL; 822 } 823 #endif 824 825 vcpu->arch.guest_owned_ext &= ~(msr | MSR_VSX); 826 kvmppc_recalc_shadow_msr(vcpu); 827 } 828 829 /* Give up facility (TAR / EBB / DSCR) */ 830 void kvmppc_giveup_fac(struct kvm_vcpu *vcpu, ulong fac) 831 { 832 #ifdef CONFIG_PPC_BOOK3S_64 833 if (!(vcpu->arch.shadow_fscr & (1ULL << fac))) { 834 /* Facility not available to the guest, ignore giveup request*/ 835 return; 836 } 837 838 switch (fac) { 839 case FSCR_TAR_LG: 840 vcpu->arch.tar = mfspr(SPRN_TAR); 841 mtspr(SPRN_TAR, current->thread.tar); 842 vcpu->arch.shadow_fscr &= ~FSCR_TAR; 843 break; 844 } 845 #endif 846 } 847 848 /* Handle external providers (FPU, Altivec, VSX) */ 849 static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr, 850 ulong msr) 851 { 852 struct thread_struct *t = ¤t->thread; 853 854 /* When we have paired singles, we emulate in software */ 855 if (vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE) 856 return RESUME_GUEST; 857 858 if (!(kvmppc_get_msr(vcpu) & msr)) { 859 kvmppc_book3s_queue_irqprio(vcpu, exit_nr); 860 return RESUME_GUEST; 861 } 862 863 if (msr == MSR_VSX) { 864 /* No VSX? Give an illegal instruction interrupt */ 865 #ifdef CONFIG_VSX 866 if (!cpu_has_feature(CPU_FTR_VSX)) 867 #endif 868 { 869 kvmppc_core_queue_program(vcpu, SRR1_PROGILL); 870 return RESUME_GUEST; 871 } 872 873 /* 874 * We have to load up all the FP and VMX registers before 875 * we can let the guest use VSX instructions. 876 */ 877 msr = MSR_FP | MSR_VEC | MSR_VSX; 878 } 879 880 /* See if we already own all the ext(s) needed */ 881 msr &= ~vcpu->arch.guest_owned_ext; 882 if (!msr) 883 return RESUME_GUEST; 884 885 #ifdef DEBUG_EXT 886 printk(KERN_INFO "Loading up ext 0x%lx\n", msr); 887 #endif 888 889 if (msr & MSR_FP) { 890 preempt_disable(); 891 enable_kernel_fp(); 892 load_fp_state(&vcpu->arch.fp); 893 disable_kernel_fp(); 894 t->fp_save_area = &vcpu->arch.fp; 895 preempt_enable(); 896 } 897 898 if (msr & MSR_VEC) { 899 #ifdef CONFIG_ALTIVEC 900 preempt_disable(); 901 enable_kernel_altivec(); 902 load_vr_state(&vcpu->arch.vr); 903 disable_kernel_altivec(); 904 t->vr_save_area = &vcpu->arch.vr; 905 preempt_enable(); 906 #endif 907 } 908 909 t->regs->msr |= msr; 910 vcpu->arch.guest_owned_ext |= msr; 911 kvmppc_recalc_shadow_msr(vcpu); 912 913 return RESUME_GUEST; 914 } 915 916 /* 917 * Kernel code using FP or VMX could have flushed guest state to 918 * the thread_struct; if so, get it back now. 919 */ 920 static void kvmppc_handle_lost_ext(struct kvm_vcpu *vcpu) 921 { 922 unsigned long lost_ext; 923 924 lost_ext = vcpu->arch.guest_owned_ext & ~current->thread.regs->msr; 925 if (!lost_ext) 926 return; 927 928 if (lost_ext & MSR_FP) { 929 preempt_disable(); 930 enable_kernel_fp(); 931 load_fp_state(&vcpu->arch.fp); 932 disable_kernel_fp(); 933 preempt_enable(); 934 } 935 #ifdef CONFIG_ALTIVEC 936 if (lost_ext & MSR_VEC) { 937 preempt_disable(); 938 enable_kernel_altivec(); 939 load_vr_state(&vcpu->arch.vr); 940 disable_kernel_altivec(); 941 preempt_enable(); 942 } 943 #endif 944 current->thread.regs->msr |= lost_ext; 945 } 946 947 #ifdef CONFIG_PPC_BOOK3S_64 948 949 void kvmppc_trigger_fac_interrupt(struct kvm_vcpu *vcpu, ulong fac) 950 { 951 /* Inject the Interrupt Cause field and trigger a guest interrupt */ 952 vcpu->arch.fscr &= ~(0xffULL << 56); 953 vcpu->arch.fscr |= (fac << 56); 954 kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_FAC_UNAVAIL); 955 } 956 957 static void kvmppc_emulate_fac(struct kvm_vcpu *vcpu, ulong fac) 958 { 959 enum emulation_result er = EMULATE_FAIL; 960 961 if (!(kvmppc_get_msr(vcpu) & MSR_PR)) 962 er = kvmppc_emulate_instruction(vcpu->run, vcpu); 963 964 if ((er != EMULATE_DONE) && (er != EMULATE_AGAIN)) { 965 /* Couldn't emulate, trigger interrupt in guest */ 966 kvmppc_trigger_fac_interrupt(vcpu, fac); 967 } 968 } 969 970 /* Enable facilities (TAR, EBB, DSCR) for the guest */ 971 static int kvmppc_handle_fac(struct kvm_vcpu *vcpu, ulong fac) 972 { 973 bool guest_fac_enabled; 974 BUG_ON(!cpu_has_feature(CPU_FTR_ARCH_207S)); 975 976 /* 977 * Not every facility is enabled by FSCR bits, check whether the 978 * guest has this facility enabled at all. 979 */ 980 switch (fac) { 981 case FSCR_TAR_LG: 982 case FSCR_EBB_LG: 983 guest_fac_enabled = (vcpu->arch.fscr & (1ULL << fac)); 984 break; 985 case FSCR_TM_LG: 986 guest_fac_enabled = kvmppc_get_msr(vcpu) & MSR_TM; 987 break; 988 default: 989 guest_fac_enabled = false; 990 break; 991 } 992 993 if (!guest_fac_enabled) { 994 /* Facility not enabled by the guest */ 995 kvmppc_trigger_fac_interrupt(vcpu, fac); 996 return RESUME_GUEST; 997 } 998 999 switch (fac) { 1000 case FSCR_TAR_LG: 1001 /* TAR switching isn't lazy in Linux yet */ 1002 current->thread.tar = mfspr(SPRN_TAR); 1003 mtspr(SPRN_TAR, vcpu->arch.tar); 1004 vcpu->arch.shadow_fscr |= FSCR_TAR; 1005 break; 1006 default: 1007 kvmppc_emulate_fac(vcpu, fac); 1008 break; 1009 } 1010 1011 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1012 /* Since we disabled MSR_TM at privilege state, the mfspr instruction 1013 * for TM spr can trigger TM fac unavailable. In this case, the 1014 * emulation is handled by kvmppc_emulate_fac(), which invokes 1015 * kvmppc_emulate_mfspr() finally. But note the mfspr can include 1016 * RT for NV registers. So it need to restore those NV reg to reflect 1017 * the update. 1018 */ 1019 if ((fac == FSCR_TM_LG) && !(kvmppc_get_msr(vcpu) & MSR_PR)) 1020 return RESUME_GUEST_NV; 1021 #endif 1022 1023 return RESUME_GUEST; 1024 } 1025 1026 void kvmppc_set_fscr(struct kvm_vcpu *vcpu, u64 fscr) 1027 { 1028 if ((vcpu->arch.fscr & FSCR_TAR) && !(fscr & FSCR_TAR)) { 1029 /* TAR got dropped, drop it in shadow too */ 1030 kvmppc_giveup_fac(vcpu, FSCR_TAR_LG); 1031 } else if (!(vcpu->arch.fscr & FSCR_TAR) && (fscr & FSCR_TAR)) { 1032 vcpu->arch.fscr = fscr; 1033 kvmppc_handle_fac(vcpu, FSCR_TAR_LG); 1034 return; 1035 } 1036 1037 vcpu->arch.fscr = fscr; 1038 } 1039 #endif 1040 1041 static void kvmppc_setup_debug(struct kvm_vcpu *vcpu) 1042 { 1043 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 1044 u64 msr = kvmppc_get_msr(vcpu); 1045 1046 kvmppc_set_msr(vcpu, msr | MSR_SE); 1047 } 1048 } 1049 1050 static void kvmppc_clear_debug(struct kvm_vcpu *vcpu) 1051 { 1052 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 1053 u64 msr = kvmppc_get_msr(vcpu); 1054 1055 kvmppc_set_msr(vcpu, msr & ~MSR_SE); 1056 } 1057 } 1058 1059 static int kvmppc_exit_pr_progint(struct kvm_run *run, struct kvm_vcpu *vcpu, 1060 unsigned int exit_nr) 1061 { 1062 enum emulation_result er; 1063 ulong flags; 1064 u32 last_inst; 1065 int emul, r; 1066 1067 /* 1068 * shadow_srr1 only contains valid flags if we came here via a program 1069 * exception. The other exceptions (emulation assist, FP unavailable, 1070 * etc.) do not provide flags in SRR1, so use an illegal-instruction 1071 * exception when injecting a program interrupt into the guest. 1072 */ 1073 if (exit_nr == BOOK3S_INTERRUPT_PROGRAM) 1074 flags = vcpu->arch.shadow_srr1 & 0x1f0000ull; 1075 else 1076 flags = SRR1_PROGILL; 1077 1078 emul = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst); 1079 if (emul != EMULATE_DONE) 1080 return RESUME_GUEST; 1081 1082 if (kvmppc_get_msr(vcpu) & MSR_PR) { 1083 #ifdef EXIT_DEBUG 1084 pr_info("Userspace triggered 0x700 exception at\n 0x%lx (0x%x)\n", 1085 kvmppc_get_pc(vcpu), last_inst); 1086 #endif 1087 if ((last_inst & 0xff0007ff) != (INS_DCBZ & 0xfffffff7)) { 1088 kvmppc_core_queue_program(vcpu, flags); 1089 return RESUME_GUEST; 1090 } 1091 } 1092 1093 vcpu->stat.emulated_inst_exits++; 1094 er = kvmppc_emulate_instruction(run, vcpu); 1095 switch (er) { 1096 case EMULATE_DONE: 1097 r = RESUME_GUEST_NV; 1098 break; 1099 case EMULATE_AGAIN: 1100 r = RESUME_GUEST; 1101 break; 1102 case EMULATE_FAIL: 1103 pr_crit("%s: emulation at %lx failed (%08x)\n", 1104 __func__, kvmppc_get_pc(vcpu), last_inst); 1105 kvmppc_core_queue_program(vcpu, flags); 1106 r = RESUME_GUEST; 1107 break; 1108 case EMULATE_DO_MMIO: 1109 run->exit_reason = KVM_EXIT_MMIO; 1110 r = RESUME_HOST_NV; 1111 break; 1112 case EMULATE_EXIT_USER: 1113 r = RESUME_HOST_NV; 1114 break; 1115 default: 1116 BUG(); 1117 } 1118 1119 return r; 1120 } 1121 1122 int kvmppc_handle_exit_pr(struct kvm_run *run, struct kvm_vcpu *vcpu, 1123 unsigned int exit_nr) 1124 { 1125 int r = RESUME_HOST; 1126 int s; 1127 1128 vcpu->stat.sum_exits++; 1129 1130 run->exit_reason = KVM_EXIT_UNKNOWN; 1131 run->ready_for_interrupt_injection = 1; 1132 1133 /* We get here with MSR.EE=1 */ 1134 1135 trace_kvm_exit(exit_nr, vcpu); 1136 guest_exit(); 1137 1138 switch (exit_nr) { 1139 case BOOK3S_INTERRUPT_INST_STORAGE: 1140 { 1141 ulong shadow_srr1 = vcpu->arch.shadow_srr1; 1142 vcpu->stat.pf_instruc++; 1143 1144 if (kvmppc_is_split_real(vcpu)) 1145 kvmppc_fixup_split_real(vcpu); 1146 1147 #ifdef CONFIG_PPC_BOOK3S_32 1148 /* We set segments as unused segments when invalidating them. So 1149 * treat the respective fault as segment fault. */ 1150 { 1151 struct kvmppc_book3s_shadow_vcpu *svcpu; 1152 u32 sr; 1153 1154 svcpu = svcpu_get(vcpu); 1155 sr = svcpu->sr[kvmppc_get_pc(vcpu) >> SID_SHIFT]; 1156 svcpu_put(svcpu); 1157 if (sr == SR_INVALID) { 1158 kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu)); 1159 r = RESUME_GUEST; 1160 break; 1161 } 1162 } 1163 #endif 1164 1165 /* only care about PTEG not found errors, but leave NX alone */ 1166 if (shadow_srr1 & 0x40000000) { 1167 int idx = srcu_read_lock(&vcpu->kvm->srcu); 1168 r = kvmppc_handle_pagefault(run, vcpu, kvmppc_get_pc(vcpu), exit_nr); 1169 srcu_read_unlock(&vcpu->kvm->srcu, idx); 1170 vcpu->stat.sp_instruc++; 1171 } else if (vcpu->arch.mmu.is_dcbz32(vcpu) && 1172 (!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) { 1173 /* 1174 * XXX If we do the dcbz hack we use the NX bit to flush&patch the page, 1175 * so we can't use the NX bit inside the guest. Let's cross our fingers, 1176 * that no guest that needs the dcbz hack does NX. 1177 */ 1178 kvmppc_mmu_pte_flush(vcpu, kvmppc_get_pc(vcpu), ~0xFFFUL); 1179 r = RESUME_GUEST; 1180 } else { 1181 kvmppc_core_queue_inst_storage(vcpu, 1182 shadow_srr1 & 0x58000000); 1183 r = RESUME_GUEST; 1184 } 1185 break; 1186 } 1187 case BOOK3S_INTERRUPT_DATA_STORAGE: 1188 { 1189 ulong dar = kvmppc_get_fault_dar(vcpu); 1190 u32 fault_dsisr = vcpu->arch.fault_dsisr; 1191 vcpu->stat.pf_storage++; 1192 1193 #ifdef CONFIG_PPC_BOOK3S_32 1194 /* We set segments as unused segments when invalidating them. So 1195 * treat the respective fault as segment fault. */ 1196 { 1197 struct kvmppc_book3s_shadow_vcpu *svcpu; 1198 u32 sr; 1199 1200 svcpu = svcpu_get(vcpu); 1201 sr = svcpu->sr[dar >> SID_SHIFT]; 1202 svcpu_put(svcpu); 1203 if (sr == SR_INVALID) { 1204 kvmppc_mmu_map_segment(vcpu, dar); 1205 r = RESUME_GUEST; 1206 break; 1207 } 1208 } 1209 #endif 1210 1211 /* 1212 * We need to handle missing shadow PTEs, and 1213 * protection faults due to us mapping a page read-only 1214 * when the guest thinks it is writable. 1215 */ 1216 if (fault_dsisr & (DSISR_NOHPTE | DSISR_PROTFAULT)) { 1217 int idx = srcu_read_lock(&vcpu->kvm->srcu); 1218 r = kvmppc_handle_pagefault(run, vcpu, dar, exit_nr); 1219 srcu_read_unlock(&vcpu->kvm->srcu, idx); 1220 } else { 1221 kvmppc_core_queue_data_storage(vcpu, dar, fault_dsisr); 1222 r = RESUME_GUEST; 1223 } 1224 break; 1225 } 1226 case BOOK3S_INTERRUPT_DATA_SEGMENT: 1227 if (kvmppc_mmu_map_segment(vcpu, kvmppc_get_fault_dar(vcpu)) < 0) { 1228 kvmppc_set_dar(vcpu, kvmppc_get_fault_dar(vcpu)); 1229 kvmppc_book3s_queue_irqprio(vcpu, 1230 BOOK3S_INTERRUPT_DATA_SEGMENT); 1231 } 1232 r = RESUME_GUEST; 1233 break; 1234 case BOOK3S_INTERRUPT_INST_SEGMENT: 1235 if (kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu)) < 0) { 1236 kvmppc_book3s_queue_irqprio(vcpu, 1237 BOOK3S_INTERRUPT_INST_SEGMENT); 1238 } 1239 r = RESUME_GUEST; 1240 break; 1241 /* We're good on these - the host merely wanted to get our attention */ 1242 case BOOK3S_INTERRUPT_DECREMENTER: 1243 case BOOK3S_INTERRUPT_HV_DECREMENTER: 1244 case BOOK3S_INTERRUPT_DOORBELL: 1245 case BOOK3S_INTERRUPT_H_DOORBELL: 1246 vcpu->stat.dec_exits++; 1247 r = RESUME_GUEST; 1248 break; 1249 case BOOK3S_INTERRUPT_EXTERNAL: 1250 case BOOK3S_INTERRUPT_EXTERNAL_LEVEL: 1251 case BOOK3S_INTERRUPT_EXTERNAL_HV: 1252 case BOOK3S_INTERRUPT_H_VIRT: 1253 vcpu->stat.ext_intr_exits++; 1254 r = RESUME_GUEST; 1255 break; 1256 case BOOK3S_INTERRUPT_HMI: 1257 case BOOK3S_INTERRUPT_PERFMON: 1258 case BOOK3S_INTERRUPT_SYSTEM_RESET: 1259 r = RESUME_GUEST; 1260 break; 1261 case BOOK3S_INTERRUPT_PROGRAM: 1262 case BOOK3S_INTERRUPT_H_EMUL_ASSIST: 1263 r = kvmppc_exit_pr_progint(run, vcpu, exit_nr); 1264 break; 1265 case BOOK3S_INTERRUPT_SYSCALL: 1266 { 1267 u32 last_sc; 1268 int emul; 1269 1270 /* Get last sc for papr */ 1271 if (vcpu->arch.papr_enabled) { 1272 /* The sc instuction points SRR0 to the next inst */ 1273 emul = kvmppc_get_last_inst(vcpu, INST_SC, &last_sc); 1274 if (emul != EMULATE_DONE) { 1275 kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) - 4); 1276 r = RESUME_GUEST; 1277 break; 1278 } 1279 } 1280 1281 if (vcpu->arch.papr_enabled && 1282 (last_sc == 0x44000022) && 1283 !(kvmppc_get_msr(vcpu) & MSR_PR)) { 1284 /* SC 1 papr hypercalls */ 1285 ulong cmd = kvmppc_get_gpr(vcpu, 3); 1286 int i; 1287 1288 #ifdef CONFIG_PPC_BOOK3S_64 1289 if (kvmppc_h_pr(vcpu, cmd) == EMULATE_DONE) { 1290 r = RESUME_GUEST; 1291 break; 1292 } 1293 #endif 1294 1295 run->papr_hcall.nr = cmd; 1296 for (i = 0; i < 9; ++i) { 1297 ulong gpr = kvmppc_get_gpr(vcpu, 4 + i); 1298 run->papr_hcall.args[i] = gpr; 1299 } 1300 run->exit_reason = KVM_EXIT_PAPR_HCALL; 1301 vcpu->arch.hcall_needed = 1; 1302 r = RESUME_HOST; 1303 } else if (vcpu->arch.osi_enabled && 1304 (((u32)kvmppc_get_gpr(vcpu, 3)) == OSI_SC_MAGIC_R3) && 1305 (((u32)kvmppc_get_gpr(vcpu, 4)) == OSI_SC_MAGIC_R4)) { 1306 /* MOL hypercalls */ 1307 u64 *gprs = run->osi.gprs; 1308 int i; 1309 1310 run->exit_reason = KVM_EXIT_OSI; 1311 for (i = 0; i < 32; i++) 1312 gprs[i] = kvmppc_get_gpr(vcpu, i); 1313 vcpu->arch.osi_needed = 1; 1314 r = RESUME_HOST_NV; 1315 } else if (!(kvmppc_get_msr(vcpu) & MSR_PR) && 1316 (((u32)kvmppc_get_gpr(vcpu, 0)) == KVM_SC_MAGIC_R0)) { 1317 /* KVM PV hypercalls */ 1318 kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu)); 1319 r = RESUME_GUEST; 1320 } else { 1321 /* Guest syscalls */ 1322 vcpu->stat.syscall_exits++; 1323 kvmppc_book3s_queue_irqprio(vcpu, exit_nr); 1324 r = RESUME_GUEST; 1325 } 1326 break; 1327 } 1328 case BOOK3S_INTERRUPT_FP_UNAVAIL: 1329 case BOOK3S_INTERRUPT_ALTIVEC: 1330 case BOOK3S_INTERRUPT_VSX: 1331 { 1332 int ext_msr = 0; 1333 int emul; 1334 u32 last_inst; 1335 1336 if (vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE) { 1337 /* Do paired single instruction emulation */ 1338 emul = kvmppc_get_last_inst(vcpu, INST_GENERIC, 1339 &last_inst); 1340 if (emul == EMULATE_DONE) 1341 r = kvmppc_exit_pr_progint(run, vcpu, exit_nr); 1342 else 1343 r = RESUME_GUEST; 1344 1345 break; 1346 } 1347 1348 /* Enable external provider */ 1349 switch (exit_nr) { 1350 case BOOK3S_INTERRUPT_FP_UNAVAIL: 1351 ext_msr = MSR_FP; 1352 break; 1353 1354 case BOOK3S_INTERRUPT_ALTIVEC: 1355 ext_msr = MSR_VEC; 1356 break; 1357 1358 case BOOK3S_INTERRUPT_VSX: 1359 ext_msr = MSR_VSX; 1360 break; 1361 } 1362 1363 r = kvmppc_handle_ext(vcpu, exit_nr, ext_msr); 1364 break; 1365 } 1366 case BOOK3S_INTERRUPT_ALIGNMENT: 1367 { 1368 u32 last_inst; 1369 int emul = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst); 1370 1371 if (emul == EMULATE_DONE) { 1372 u32 dsisr; 1373 u64 dar; 1374 1375 dsisr = kvmppc_alignment_dsisr(vcpu, last_inst); 1376 dar = kvmppc_alignment_dar(vcpu, last_inst); 1377 1378 kvmppc_set_dsisr(vcpu, dsisr); 1379 kvmppc_set_dar(vcpu, dar); 1380 1381 kvmppc_book3s_queue_irqprio(vcpu, exit_nr); 1382 } 1383 r = RESUME_GUEST; 1384 break; 1385 } 1386 #ifdef CONFIG_PPC_BOOK3S_64 1387 case BOOK3S_INTERRUPT_FAC_UNAVAIL: 1388 r = kvmppc_handle_fac(vcpu, vcpu->arch.shadow_fscr >> 56); 1389 break; 1390 #endif 1391 case BOOK3S_INTERRUPT_MACHINE_CHECK: 1392 kvmppc_book3s_queue_irqprio(vcpu, exit_nr); 1393 r = RESUME_GUEST; 1394 break; 1395 case BOOK3S_INTERRUPT_TRACE: 1396 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 1397 run->exit_reason = KVM_EXIT_DEBUG; 1398 r = RESUME_HOST; 1399 } else { 1400 kvmppc_book3s_queue_irqprio(vcpu, exit_nr); 1401 r = RESUME_GUEST; 1402 } 1403 break; 1404 default: 1405 { 1406 ulong shadow_srr1 = vcpu->arch.shadow_srr1; 1407 /* Ugh - bork here! What did we get? */ 1408 printk(KERN_EMERG "exit_nr=0x%x | pc=0x%lx | msr=0x%lx\n", 1409 exit_nr, kvmppc_get_pc(vcpu), shadow_srr1); 1410 r = RESUME_HOST; 1411 BUG(); 1412 break; 1413 } 1414 } 1415 1416 if (!(r & RESUME_HOST)) { 1417 /* To avoid clobbering exit_reason, only check for signals if 1418 * we aren't already exiting to userspace for some other 1419 * reason. */ 1420 1421 /* 1422 * Interrupts could be timers for the guest which we have to 1423 * inject again, so let's postpone them until we're in the guest 1424 * and if we really did time things so badly, then we just exit 1425 * again due to a host external interrupt. 1426 */ 1427 s = kvmppc_prepare_to_enter(vcpu); 1428 if (s <= 0) 1429 r = s; 1430 else { 1431 /* interrupts now hard-disabled */ 1432 kvmppc_fix_ee_before_entry(); 1433 } 1434 1435 kvmppc_handle_lost_ext(vcpu); 1436 } 1437 1438 trace_kvm_book3s_reenter(r, vcpu); 1439 1440 return r; 1441 } 1442 1443 static int kvm_arch_vcpu_ioctl_get_sregs_pr(struct kvm_vcpu *vcpu, 1444 struct kvm_sregs *sregs) 1445 { 1446 struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu); 1447 int i; 1448 1449 sregs->pvr = vcpu->arch.pvr; 1450 1451 sregs->u.s.sdr1 = to_book3s(vcpu)->sdr1; 1452 if (vcpu->arch.hflags & BOOK3S_HFLAG_SLB) { 1453 for (i = 0; i < 64; i++) { 1454 sregs->u.s.ppc64.slb[i].slbe = vcpu->arch.slb[i].orige | i; 1455 sregs->u.s.ppc64.slb[i].slbv = vcpu->arch.slb[i].origv; 1456 } 1457 } else { 1458 for (i = 0; i < 16; i++) 1459 sregs->u.s.ppc32.sr[i] = kvmppc_get_sr(vcpu, i); 1460 1461 for (i = 0; i < 8; i++) { 1462 sregs->u.s.ppc32.ibat[i] = vcpu3s->ibat[i].raw; 1463 sregs->u.s.ppc32.dbat[i] = vcpu3s->dbat[i].raw; 1464 } 1465 } 1466 1467 return 0; 1468 } 1469 1470 static int kvm_arch_vcpu_ioctl_set_sregs_pr(struct kvm_vcpu *vcpu, 1471 struct kvm_sregs *sregs) 1472 { 1473 struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu); 1474 int i; 1475 1476 kvmppc_set_pvr_pr(vcpu, sregs->pvr); 1477 1478 vcpu3s->sdr1 = sregs->u.s.sdr1; 1479 #ifdef CONFIG_PPC_BOOK3S_64 1480 if (vcpu->arch.hflags & BOOK3S_HFLAG_SLB) { 1481 /* Flush all SLB entries */ 1482 vcpu->arch.mmu.slbmte(vcpu, 0, 0); 1483 vcpu->arch.mmu.slbia(vcpu); 1484 1485 for (i = 0; i < 64; i++) { 1486 u64 rb = sregs->u.s.ppc64.slb[i].slbe; 1487 u64 rs = sregs->u.s.ppc64.slb[i].slbv; 1488 1489 if (rb & SLB_ESID_V) 1490 vcpu->arch.mmu.slbmte(vcpu, rs, rb); 1491 } 1492 } else 1493 #endif 1494 { 1495 for (i = 0; i < 16; i++) { 1496 vcpu->arch.mmu.mtsrin(vcpu, i, sregs->u.s.ppc32.sr[i]); 1497 } 1498 for (i = 0; i < 8; i++) { 1499 kvmppc_set_bat(vcpu, &(vcpu3s->ibat[i]), false, 1500 (u32)sregs->u.s.ppc32.ibat[i]); 1501 kvmppc_set_bat(vcpu, &(vcpu3s->ibat[i]), true, 1502 (u32)(sregs->u.s.ppc32.ibat[i] >> 32)); 1503 kvmppc_set_bat(vcpu, &(vcpu3s->dbat[i]), false, 1504 (u32)sregs->u.s.ppc32.dbat[i]); 1505 kvmppc_set_bat(vcpu, &(vcpu3s->dbat[i]), true, 1506 (u32)(sregs->u.s.ppc32.dbat[i] >> 32)); 1507 } 1508 } 1509 1510 /* Flush the MMU after messing with the segments */ 1511 kvmppc_mmu_pte_flush(vcpu, 0, 0); 1512 1513 return 0; 1514 } 1515 1516 static int kvmppc_get_one_reg_pr(struct kvm_vcpu *vcpu, u64 id, 1517 union kvmppc_one_reg *val) 1518 { 1519 int r = 0; 1520 1521 switch (id) { 1522 case KVM_REG_PPC_DEBUG_INST: 1523 *val = get_reg_val(id, KVMPPC_INST_SW_BREAKPOINT); 1524 break; 1525 case KVM_REG_PPC_HIOR: 1526 *val = get_reg_val(id, to_book3s(vcpu)->hior); 1527 break; 1528 case KVM_REG_PPC_VTB: 1529 *val = get_reg_val(id, to_book3s(vcpu)->vtb); 1530 break; 1531 case KVM_REG_PPC_LPCR: 1532 case KVM_REG_PPC_LPCR_64: 1533 /* 1534 * We are only interested in the LPCR_ILE bit 1535 */ 1536 if (vcpu->arch.intr_msr & MSR_LE) 1537 *val = get_reg_val(id, LPCR_ILE); 1538 else 1539 *val = get_reg_val(id, 0); 1540 break; 1541 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1542 case KVM_REG_PPC_TFHAR: 1543 *val = get_reg_val(id, vcpu->arch.tfhar); 1544 break; 1545 case KVM_REG_PPC_TFIAR: 1546 *val = get_reg_val(id, vcpu->arch.tfiar); 1547 break; 1548 case KVM_REG_PPC_TEXASR: 1549 *val = get_reg_val(id, vcpu->arch.texasr); 1550 break; 1551 case KVM_REG_PPC_TM_GPR0 ... KVM_REG_PPC_TM_GPR31: 1552 *val = get_reg_val(id, 1553 vcpu->arch.gpr_tm[id-KVM_REG_PPC_TM_GPR0]); 1554 break; 1555 case KVM_REG_PPC_TM_VSR0 ... KVM_REG_PPC_TM_VSR63: 1556 { 1557 int i, j; 1558 1559 i = id - KVM_REG_PPC_TM_VSR0; 1560 if (i < 32) 1561 for (j = 0; j < TS_FPRWIDTH; j++) 1562 val->vsxval[j] = vcpu->arch.fp_tm.fpr[i][j]; 1563 else { 1564 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 1565 val->vval = vcpu->arch.vr_tm.vr[i-32]; 1566 else 1567 r = -ENXIO; 1568 } 1569 break; 1570 } 1571 case KVM_REG_PPC_TM_CR: 1572 *val = get_reg_val(id, vcpu->arch.cr_tm); 1573 break; 1574 case KVM_REG_PPC_TM_XER: 1575 *val = get_reg_val(id, vcpu->arch.xer_tm); 1576 break; 1577 case KVM_REG_PPC_TM_LR: 1578 *val = get_reg_val(id, vcpu->arch.lr_tm); 1579 break; 1580 case KVM_REG_PPC_TM_CTR: 1581 *val = get_reg_val(id, vcpu->arch.ctr_tm); 1582 break; 1583 case KVM_REG_PPC_TM_FPSCR: 1584 *val = get_reg_val(id, vcpu->arch.fp_tm.fpscr); 1585 break; 1586 case KVM_REG_PPC_TM_AMR: 1587 *val = get_reg_val(id, vcpu->arch.amr_tm); 1588 break; 1589 case KVM_REG_PPC_TM_PPR: 1590 *val = get_reg_val(id, vcpu->arch.ppr_tm); 1591 break; 1592 case KVM_REG_PPC_TM_VRSAVE: 1593 *val = get_reg_val(id, vcpu->arch.vrsave_tm); 1594 break; 1595 case KVM_REG_PPC_TM_VSCR: 1596 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 1597 *val = get_reg_val(id, vcpu->arch.vr_tm.vscr.u[3]); 1598 else 1599 r = -ENXIO; 1600 break; 1601 case KVM_REG_PPC_TM_DSCR: 1602 *val = get_reg_val(id, vcpu->arch.dscr_tm); 1603 break; 1604 case KVM_REG_PPC_TM_TAR: 1605 *val = get_reg_val(id, vcpu->arch.tar_tm); 1606 break; 1607 #endif 1608 default: 1609 r = -EINVAL; 1610 break; 1611 } 1612 1613 return r; 1614 } 1615 1616 static void kvmppc_set_lpcr_pr(struct kvm_vcpu *vcpu, u64 new_lpcr) 1617 { 1618 if (new_lpcr & LPCR_ILE) 1619 vcpu->arch.intr_msr |= MSR_LE; 1620 else 1621 vcpu->arch.intr_msr &= ~MSR_LE; 1622 } 1623 1624 static int kvmppc_set_one_reg_pr(struct kvm_vcpu *vcpu, u64 id, 1625 union kvmppc_one_reg *val) 1626 { 1627 int r = 0; 1628 1629 switch (id) { 1630 case KVM_REG_PPC_HIOR: 1631 to_book3s(vcpu)->hior = set_reg_val(id, *val); 1632 to_book3s(vcpu)->hior_explicit = true; 1633 break; 1634 case KVM_REG_PPC_VTB: 1635 to_book3s(vcpu)->vtb = set_reg_val(id, *val); 1636 break; 1637 case KVM_REG_PPC_LPCR: 1638 case KVM_REG_PPC_LPCR_64: 1639 kvmppc_set_lpcr_pr(vcpu, set_reg_val(id, *val)); 1640 break; 1641 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1642 case KVM_REG_PPC_TFHAR: 1643 vcpu->arch.tfhar = set_reg_val(id, *val); 1644 break; 1645 case KVM_REG_PPC_TFIAR: 1646 vcpu->arch.tfiar = set_reg_val(id, *val); 1647 break; 1648 case KVM_REG_PPC_TEXASR: 1649 vcpu->arch.texasr = set_reg_val(id, *val); 1650 break; 1651 case KVM_REG_PPC_TM_GPR0 ... KVM_REG_PPC_TM_GPR31: 1652 vcpu->arch.gpr_tm[id - KVM_REG_PPC_TM_GPR0] = 1653 set_reg_val(id, *val); 1654 break; 1655 case KVM_REG_PPC_TM_VSR0 ... KVM_REG_PPC_TM_VSR63: 1656 { 1657 int i, j; 1658 1659 i = id - KVM_REG_PPC_TM_VSR0; 1660 if (i < 32) 1661 for (j = 0; j < TS_FPRWIDTH; j++) 1662 vcpu->arch.fp_tm.fpr[i][j] = val->vsxval[j]; 1663 else 1664 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 1665 vcpu->arch.vr_tm.vr[i-32] = val->vval; 1666 else 1667 r = -ENXIO; 1668 break; 1669 } 1670 case KVM_REG_PPC_TM_CR: 1671 vcpu->arch.cr_tm = set_reg_val(id, *val); 1672 break; 1673 case KVM_REG_PPC_TM_XER: 1674 vcpu->arch.xer_tm = set_reg_val(id, *val); 1675 break; 1676 case KVM_REG_PPC_TM_LR: 1677 vcpu->arch.lr_tm = set_reg_val(id, *val); 1678 break; 1679 case KVM_REG_PPC_TM_CTR: 1680 vcpu->arch.ctr_tm = set_reg_val(id, *val); 1681 break; 1682 case KVM_REG_PPC_TM_FPSCR: 1683 vcpu->arch.fp_tm.fpscr = set_reg_val(id, *val); 1684 break; 1685 case KVM_REG_PPC_TM_AMR: 1686 vcpu->arch.amr_tm = set_reg_val(id, *val); 1687 break; 1688 case KVM_REG_PPC_TM_PPR: 1689 vcpu->arch.ppr_tm = set_reg_val(id, *val); 1690 break; 1691 case KVM_REG_PPC_TM_VRSAVE: 1692 vcpu->arch.vrsave_tm = set_reg_val(id, *val); 1693 break; 1694 case KVM_REG_PPC_TM_VSCR: 1695 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 1696 vcpu->arch.vr.vscr.u[3] = set_reg_val(id, *val); 1697 else 1698 r = -ENXIO; 1699 break; 1700 case KVM_REG_PPC_TM_DSCR: 1701 vcpu->arch.dscr_tm = set_reg_val(id, *val); 1702 break; 1703 case KVM_REG_PPC_TM_TAR: 1704 vcpu->arch.tar_tm = set_reg_val(id, *val); 1705 break; 1706 #endif 1707 default: 1708 r = -EINVAL; 1709 break; 1710 } 1711 1712 return r; 1713 } 1714 1715 static struct kvm_vcpu *kvmppc_core_vcpu_create_pr(struct kvm *kvm, 1716 unsigned int id) 1717 { 1718 struct kvmppc_vcpu_book3s *vcpu_book3s; 1719 struct kvm_vcpu *vcpu; 1720 int err = -ENOMEM; 1721 unsigned long p; 1722 1723 vcpu = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); 1724 if (!vcpu) 1725 goto out; 1726 1727 vcpu_book3s = vzalloc(sizeof(struct kvmppc_vcpu_book3s)); 1728 if (!vcpu_book3s) 1729 goto free_vcpu; 1730 vcpu->arch.book3s = vcpu_book3s; 1731 1732 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER 1733 vcpu->arch.shadow_vcpu = 1734 kzalloc(sizeof(*vcpu->arch.shadow_vcpu), GFP_KERNEL); 1735 if (!vcpu->arch.shadow_vcpu) 1736 goto free_vcpu3s; 1737 #endif 1738 1739 err = kvm_vcpu_init(vcpu, kvm, id); 1740 if (err) 1741 goto free_shadow_vcpu; 1742 1743 err = -ENOMEM; 1744 p = __get_free_page(GFP_KERNEL|__GFP_ZERO); 1745 if (!p) 1746 goto uninit_vcpu; 1747 vcpu->arch.shared = (void *)p; 1748 #ifdef CONFIG_PPC_BOOK3S_64 1749 /* Always start the shared struct in native endian mode */ 1750 #ifdef __BIG_ENDIAN__ 1751 vcpu->arch.shared_big_endian = true; 1752 #else 1753 vcpu->arch.shared_big_endian = false; 1754 #endif 1755 1756 /* 1757 * Default to the same as the host if we're on sufficiently 1758 * recent machine that we have 1TB segments; 1759 * otherwise default to PPC970FX. 1760 */ 1761 vcpu->arch.pvr = 0x3C0301; 1762 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 1763 vcpu->arch.pvr = mfspr(SPRN_PVR); 1764 vcpu->arch.intr_msr = MSR_SF; 1765 #else 1766 /* default to book3s_32 (750) */ 1767 vcpu->arch.pvr = 0x84202; 1768 #endif 1769 kvmppc_set_pvr_pr(vcpu, vcpu->arch.pvr); 1770 vcpu->arch.slb_nr = 64; 1771 1772 vcpu->arch.shadow_msr = MSR_USER64 & ~MSR_LE; 1773 1774 err = kvmppc_mmu_init(vcpu); 1775 if (err < 0) 1776 goto uninit_vcpu; 1777 1778 return vcpu; 1779 1780 uninit_vcpu: 1781 kvm_vcpu_uninit(vcpu); 1782 free_shadow_vcpu: 1783 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER 1784 kfree(vcpu->arch.shadow_vcpu); 1785 free_vcpu3s: 1786 #endif 1787 vfree(vcpu_book3s); 1788 free_vcpu: 1789 kmem_cache_free(kvm_vcpu_cache, vcpu); 1790 out: 1791 return ERR_PTR(err); 1792 } 1793 1794 static void kvmppc_core_vcpu_free_pr(struct kvm_vcpu *vcpu) 1795 { 1796 struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu); 1797 1798 free_page((unsigned long)vcpu->arch.shared & PAGE_MASK); 1799 kvm_vcpu_uninit(vcpu); 1800 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER 1801 kfree(vcpu->arch.shadow_vcpu); 1802 #endif 1803 vfree(vcpu_book3s); 1804 kmem_cache_free(kvm_vcpu_cache, vcpu); 1805 } 1806 1807 static int kvmppc_vcpu_run_pr(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) 1808 { 1809 int ret; 1810 #ifdef CONFIG_ALTIVEC 1811 unsigned long uninitialized_var(vrsave); 1812 #endif 1813 1814 /* Check if we can run the vcpu at all */ 1815 if (!vcpu->arch.sane) { 1816 kvm_run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 1817 ret = -EINVAL; 1818 goto out; 1819 } 1820 1821 kvmppc_setup_debug(vcpu); 1822 1823 /* 1824 * Interrupts could be timers for the guest which we have to inject 1825 * again, so let's postpone them until we're in the guest and if we 1826 * really did time things so badly, then we just exit again due to 1827 * a host external interrupt. 1828 */ 1829 ret = kvmppc_prepare_to_enter(vcpu); 1830 if (ret <= 0) 1831 goto out; 1832 /* interrupts now hard-disabled */ 1833 1834 /* Save FPU, Altivec and VSX state */ 1835 giveup_all(current); 1836 1837 /* Preload FPU if it's enabled */ 1838 if (kvmppc_get_msr(vcpu) & MSR_FP) 1839 kvmppc_handle_ext(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL, MSR_FP); 1840 1841 kvmppc_fix_ee_before_entry(); 1842 1843 ret = __kvmppc_vcpu_run(kvm_run, vcpu); 1844 1845 kvmppc_clear_debug(vcpu); 1846 1847 /* No need for guest_exit. It's done in handle_exit. 1848 We also get here with interrupts enabled. */ 1849 1850 /* Make sure we save the guest FPU/Altivec/VSX state */ 1851 kvmppc_giveup_ext(vcpu, MSR_FP | MSR_VEC | MSR_VSX); 1852 1853 /* Make sure we save the guest TAR/EBB/DSCR state */ 1854 kvmppc_giveup_fac(vcpu, FSCR_TAR_LG); 1855 1856 out: 1857 vcpu->mode = OUTSIDE_GUEST_MODE; 1858 return ret; 1859 } 1860 1861 /* 1862 * Get (and clear) the dirty memory log for a memory slot. 1863 */ 1864 static int kvm_vm_ioctl_get_dirty_log_pr(struct kvm *kvm, 1865 struct kvm_dirty_log *log) 1866 { 1867 struct kvm_memslots *slots; 1868 struct kvm_memory_slot *memslot; 1869 struct kvm_vcpu *vcpu; 1870 ulong ga, ga_end; 1871 int is_dirty = 0; 1872 int r; 1873 unsigned long n; 1874 1875 mutex_lock(&kvm->slots_lock); 1876 1877 r = kvm_get_dirty_log(kvm, log, &is_dirty); 1878 if (r) 1879 goto out; 1880 1881 /* If nothing is dirty, don't bother messing with page tables. */ 1882 if (is_dirty) { 1883 slots = kvm_memslots(kvm); 1884 memslot = id_to_memslot(slots, log->slot); 1885 1886 ga = memslot->base_gfn << PAGE_SHIFT; 1887 ga_end = ga + (memslot->npages << PAGE_SHIFT); 1888 1889 kvm_for_each_vcpu(n, vcpu, kvm) 1890 kvmppc_mmu_pte_pflush(vcpu, ga, ga_end); 1891 1892 n = kvm_dirty_bitmap_bytes(memslot); 1893 memset(memslot->dirty_bitmap, 0, n); 1894 } 1895 1896 r = 0; 1897 out: 1898 mutex_unlock(&kvm->slots_lock); 1899 return r; 1900 } 1901 1902 static void kvmppc_core_flush_memslot_pr(struct kvm *kvm, 1903 struct kvm_memory_slot *memslot) 1904 { 1905 return; 1906 } 1907 1908 static int kvmppc_core_prepare_memory_region_pr(struct kvm *kvm, 1909 struct kvm_memory_slot *memslot, 1910 const struct kvm_userspace_memory_region *mem) 1911 { 1912 return 0; 1913 } 1914 1915 static void kvmppc_core_commit_memory_region_pr(struct kvm *kvm, 1916 const struct kvm_userspace_memory_region *mem, 1917 const struct kvm_memory_slot *old, 1918 const struct kvm_memory_slot *new) 1919 { 1920 return; 1921 } 1922 1923 static void kvmppc_core_free_memslot_pr(struct kvm_memory_slot *free, 1924 struct kvm_memory_slot *dont) 1925 { 1926 return; 1927 } 1928 1929 static int kvmppc_core_create_memslot_pr(struct kvm_memory_slot *slot, 1930 unsigned long npages) 1931 { 1932 return 0; 1933 } 1934 1935 1936 #ifdef CONFIG_PPC64 1937 static int kvm_vm_ioctl_get_smmu_info_pr(struct kvm *kvm, 1938 struct kvm_ppc_smmu_info *info) 1939 { 1940 long int i; 1941 struct kvm_vcpu *vcpu; 1942 1943 info->flags = 0; 1944 1945 /* SLB is always 64 entries */ 1946 info->slb_size = 64; 1947 1948 /* Standard 4k base page size segment */ 1949 info->sps[0].page_shift = 12; 1950 info->sps[0].slb_enc = 0; 1951 info->sps[0].enc[0].page_shift = 12; 1952 info->sps[0].enc[0].pte_enc = 0; 1953 1954 /* 1955 * 64k large page size. 1956 * We only want to put this in if the CPUs we're emulating 1957 * support it, but unfortunately we don't have a vcpu easily 1958 * to hand here to test. Just pick the first vcpu, and if 1959 * that doesn't exist yet, report the minimum capability, 1960 * i.e., no 64k pages. 1961 * 1T segment support goes along with 64k pages. 1962 */ 1963 i = 1; 1964 vcpu = kvm_get_vcpu(kvm, 0); 1965 if (vcpu && (vcpu->arch.hflags & BOOK3S_HFLAG_MULTI_PGSIZE)) { 1966 info->flags = KVM_PPC_1T_SEGMENTS; 1967 info->sps[i].page_shift = 16; 1968 info->sps[i].slb_enc = SLB_VSID_L | SLB_VSID_LP_01; 1969 info->sps[i].enc[0].page_shift = 16; 1970 info->sps[i].enc[0].pte_enc = 1; 1971 ++i; 1972 } 1973 1974 /* Standard 16M large page size segment */ 1975 info->sps[i].page_shift = 24; 1976 info->sps[i].slb_enc = SLB_VSID_L; 1977 info->sps[i].enc[0].page_shift = 24; 1978 info->sps[i].enc[0].pte_enc = 0; 1979 1980 return 0; 1981 } 1982 1983 static int kvm_configure_mmu_pr(struct kvm *kvm, struct kvm_ppc_mmuv3_cfg *cfg) 1984 { 1985 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1986 return -ENODEV; 1987 /* Require flags and process table base and size to all be zero. */ 1988 if (cfg->flags || cfg->process_table) 1989 return -EINVAL; 1990 return 0; 1991 } 1992 1993 #else 1994 static int kvm_vm_ioctl_get_smmu_info_pr(struct kvm *kvm, 1995 struct kvm_ppc_smmu_info *info) 1996 { 1997 /* We should not get called */ 1998 BUG(); 1999 } 2000 #endif /* CONFIG_PPC64 */ 2001 2002 static unsigned int kvm_global_user_count = 0; 2003 static DEFINE_SPINLOCK(kvm_global_user_count_lock); 2004 2005 static int kvmppc_core_init_vm_pr(struct kvm *kvm) 2006 { 2007 mutex_init(&kvm->arch.hpt_mutex); 2008 2009 #ifdef CONFIG_PPC_BOOK3S_64 2010 /* Start out with the default set of hcalls enabled */ 2011 kvmppc_pr_init_default_hcalls(kvm); 2012 #endif 2013 2014 if (firmware_has_feature(FW_FEATURE_SET_MODE)) { 2015 spin_lock(&kvm_global_user_count_lock); 2016 if (++kvm_global_user_count == 1) 2017 pseries_disable_reloc_on_exc(); 2018 spin_unlock(&kvm_global_user_count_lock); 2019 } 2020 return 0; 2021 } 2022 2023 static void kvmppc_core_destroy_vm_pr(struct kvm *kvm) 2024 { 2025 #ifdef CONFIG_PPC64 2026 WARN_ON(!list_empty(&kvm->arch.spapr_tce_tables)); 2027 #endif 2028 2029 if (firmware_has_feature(FW_FEATURE_SET_MODE)) { 2030 spin_lock(&kvm_global_user_count_lock); 2031 BUG_ON(kvm_global_user_count == 0); 2032 if (--kvm_global_user_count == 0) 2033 pseries_enable_reloc_on_exc(); 2034 spin_unlock(&kvm_global_user_count_lock); 2035 } 2036 } 2037 2038 static int kvmppc_core_check_processor_compat_pr(void) 2039 { 2040 /* 2041 * PR KVM can work on POWER9 inside a guest partition 2042 * running in HPT mode. It can't work if we are using 2043 * radix translation (because radix provides no way for 2044 * a process to have unique translations in quadrant 3). 2045 */ 2046 if (cpu_has_feature(CPU_FTR_ARCH_300) && radix_enabled()) 2047 return -EIO; 2048 return 0; 2049 } 2050 2051 static long kvm_arch_vm_ioctl_pr(struct file *filp, 2052 unsigned int ioctl, unsigned long arg) 2053 { 2054 return -ENOTTY; 2055 } 2056 2057 static struct kvmppc_ops kvm_ops_pr = { 2058 .get_sregs = kvm_arch_vcpu_ioctl_get_sregs_pr, 2059 .set_sregs = kvm_arch_vcpu_ioctl_set_sregs_pr, 2060 .get_one_reg = kvmppc_get_one_reg_pr, 2061 .set_one_reg = kvmppc_set_one_reg_pr, 2062 .vcpu_load = kvmppc_core_vcpu_load_pr, 2063 .vcpu_put = kvmppc_core_vcpu_put_pr, 2064 .set_msr = kvmppc_set_msr_pr, 2065 .vcpu_run = kvmppc_vcpu_run_pr, 2066 .vcpu_create = kvmppc_core_vcpu_create_pr, 2067 .vcpu_free = kvmppc_core_vcpu_free_pr, 2068 .check_requests = kvmppc_core_check_requests_pr, 2069 .get_dirty_log = kvm_vm_ioctl_get_dirty_log_pr, 2070 .flush_memslot = kvmppc_core_flush_memslot_pr, 2071 .prepare_memory_region = kvmppc_core_prepare_memory_region_pr, 2072 .commit_memory_region = kvmppc_core_commit_memory_region_pr, 2073 .unmap_hva_range = kvm_unmap_hva_range_pr, 2074 .age_hva = kvm_age_hva_pr, 2075 .test_age_hva = kvm_test_age_hva_pr, 2076 .set_spte_hva = kvm_set_spte_hva_pr, 2077 .mmu_destroy = kvmppc_mmu_destroy_pr, 2078 .free_memslot = kvmppc_core_free_memslot_pr, 2079 .create_memslot = kvmppc_core_create_memslot_pr, 2080 .init_vm = kvmppc_core_init_vm_pr, 2081 .destroy_vm = kvmppc_core_destroy_vm_pr, 2082 .get_smmu_info = kvm_vm_ioctl_get_smmu_info_pr, 2083 .emulate_op = kvmppc_core_emulate_op_pr, 2084 .emulate_mtspr = kvmppc_core_emulate_mtspr_pr, 2085 .emulate_mfspr = kvmppc_core_emulate_mfspr_pr, 2086 .fast_vcpu_kick = kvm_vcpu_kick, 2087 .arch_vm_ioctl = kvm_arch_vm_ioctl_pr, 2088 #ifdef CONFIG_PPC_BOOK3S_64 2089 .hcall_implemented = kvmppc_hcall_impl_pr, 2090 .configure_mmu = kvm_configure_mmu_pr, 2091 #endif 2092 .giveup_ext = kvmppc_giveup_ext, 2093 }; 2094 2095 2096 int kvmppc_book3s_init_pr(void) 2097 { 2098 int r; 2099 2100 r = kvmppc_core_check_processor_compat_pr(); 2101 if (r < 0) 2102 return r; 2103 2104 kvm_ops_pr.owner = THIS_MODULE; 2105 kvmppc_pr_ops = &kvm_ops_pr; 2106 2107 r = kvmppc_mmu_hpte_sysinit(); 2108 return r; 2109 } 2110 2111 void kvmppc_book3s_exit_pr(void) 2112 { 2113 kvmppc_pr_ops = NULL; 2114 kvmppc_mmu_hpte_sysexit(); 2115 } 2116 2117 /* 2118 * We only support separate modules for book3s 64 2119 */ 2120 #ifdef CONFIG_PPC_BOOK3S_64 2121 2122 module_init(kvmppc_book3s_init_pr); 2123 module_exit(kvmppc_book3s_exit_pr); 2124 2125 MODULE_LICENSE("GPL"); 2126 MODULE_ALIAS_MISCDEV(KVM_MINOR); 2127 MODULE_ALIAS("devname:kvm"); 2128 #endif 2129