1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
9 * GNU General Public License for more details.
10 *
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
12 *
13 * Derived from book3s_rmhandlers.S and other files, which are:
14 *
15 * Copyright SUSE Linux Products GmbH 2009
16 *
17 * Authors: Alexander Graf <agraf@suse.de>
18 */
19
20#include <asm/ppc_asm.h>
21#include <asm/kvm_asm.h>
22#include <asm/reg.h>
23#include <asm/mmu.h>
24#include <asm/page.h>
25#include <asm/ptrace.h>
26#include <asm/hvcall.h>
27#include <asm/asm-offsets.h>
28#include <asm/exception-64s.h>
29#include <asm/kvm_book3s_asm.h>
30
31/*****************************************************************************
32 *                                                                           *
33 *        Real Mode handlers that need to be in the linear mapping           *
34 *                                                                           *
35 ****************************************************************************/
36
37	.globl	kvmppc_skip_interrupt
38kvmppc_skip_interrupt:
39	mfspr	r13,SPRN_SRR0
40	addi	r13,r13,4
41	mtspr	SPRN_SRR0,r13
42	GET_SCRATCH0(r13)
43	rfid
44	b	.
45
46	.globl	kvmppc_skip_Hinterrupt
47kvmppc_skip_Hinterrupt:
48	mfspr	r13,SPRN_HSRR0
49	addi	r13,r13,4
50	mtspr	SPRN_HSRR0,r13
51	GET_SCRATCH0(r13)
52	hrfid
53	b	.
54
55/*
56 * Call kvmppc_hv_entry in real mode.
57 * Must be called with interrupts hard-disabled.
58 *
59 * Input Registers:
60 *
61 * LR = return address to continue at after eventually re-enabling MMU
62 */
63_GLOBAL(kvmppc_hv_entry_trampoline)
64	mfmsr	r10
65	LOAD_REG_ADDR(r5, kvmppc_hv_entry)
66	li	r0,MSR_RI
67	andc	r0,r10,r0
68	li	r6,MSR_IR | MSR_DR
69	andc	r6,r10,r6
70	mtmsrd	r0,1		/* clear RI in MSR */
71	mtsrr0	r5
72	mtsrr1	r6
73	RFI
74
75/******************************************************************************
76 *                                                                            *
77 *                               Entry code                                   *
78 *                                                                            *
79 *****************************************************************************/
80
81#define XICS_XIRR		4
82#define XICS_QIRR		0xc
83#define XICS_IPI		2	/* interrupt source # for IPIs */
84
85/*
86 * We come in here when wakened from nap mode on a secondary hw thread.
87 * Relocation is off and most register values are lost.
88 * r13 points to the PACA.
89 */
90	.globl	kvm_start_guest
91kvm_start_guest:
92	ld	r1,PACAEMERGSP(r13)
93	subi	r1,r1,STACK_FRAME_OVERHEAD
94	ld	r2,PACATOC(r13)
95
96	li	r0,KVM_HWTHREAD_IN_KVM
97	stb	r0,HSTATE_HWTHREAD_STATE(r13)
98
99	/* NV GPR values from power7_idle() will no longer be valid */
100	li	r0,1
101	stb	r0,PACA_NAPSTATELOST(r13)
102
103	/* get vcpu pointer, NULL if we have no vcpu to run */
104	ld	r4,HSTATE_KVM_VCPU(r13)
105	cmpdi	cr1,r4,0
106
107	/* Check the wake reason in SRR1 to see why we got here */
108	mfspr	r3,SPRN_SRR1
109	rlwinm	r3,r3,44-31,0x7		/* extract wake reason field */
110	cmpwi	r3,4			/* was it an external interrupt? */
111	bne	27f
112
113	/*
114	 * External interrupt - for now assume it is an IPI, since we
115	 * should never get any other interrupts sent to offline threads.
116	 * Only do this for secondary threads.
117	 */
118	beq	cr1,25f
119	lwz	r3,VCPU_PTID(r4)
120	cmpwi	r3,0
121	beq	27f
12225:	ld	r5,HSTATE_XICS_PHYS(r13)
123	li	r0,0xff
124	li	r6,XICS_QIRR
125	li	r7,XICS_XIRR
126	lwzcix	r8,r5,r7		/* get and ack the interrupt */
127	sync
128	clrldi.	r9,r8,40		/* get interrupt source ID. */
129	beq	27f			/* none there? */
130	cmpwi	r9,XICS_IPI
131	bne	26f
132	stbcix	r0,r5,r6		/* clear IPI */
13326:	stwcix	r8,r5,r7		/* EOI the interrupt */
134
13527:	/* XXX should handle hypervisor maintenance interrupts etc. here */
136
137	/* if we have no vcpu to run, go back to sleep */
138	beq	cr1,kvm_no_guest
139
140	/* were we napping due to cede? */
141	lbz	r0,HSTATE_NAPPING(r13)
142	cmpwi	r0,0
143	bne	kvm_end_cede
144
145.global kvmppc_hv_entry
146kvmppc_hv_entry:
147
148	/* Required state:
149	 *
150	 * R4 = vcpu pointer
151	 * MSR = ~IR|DR
152	 * R13 = PACA
153	 * R1 = host R1
154	 * all other volatile GPRS = free
155	 */
156	mflr	r0
157	std	r0, HSTATE_VMHANDLER(r13)
158
159	/* Set partition DABR */
160	/* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
161	li	r5,3
162	ld	r6,VCPU_DABR(r4)
163	mtspr	SPRN_DABRX,r5
164	mtspr	SPRN_DABR,r6
165BEGIN_FTR_SECTION
166	isync
167END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
168
169	/* Load guest PMU registers */
170	/* R4 is live here (vcpu pointer) */
171	li	r3, 1
172	sldi	r3, r3, 31		/* MMCR0_FC (freeze counters) bit */
173	mtspr	SPRN_MMCR0, r3		/* freeze all counters, disable ints */
174	isync
175	lwz	r3, VCPU_PMC(r4)	/* always load up guest PMU registers */
176	lwz	r5, VCPU_PMC + 4(r4)	/* to prevent information leak */
177	lwz	r6, VCPU_PMC + 8(r4)
178	lwz	r7, VCPU_PMC + 12(r4)
179	lwz	r8, VCPU_PMC + 16(r4)
180	lwz	r9, VCPU_PMC + 20(r4)
181BEGIN_FTR_SECTION
182	lwz	r10, VCPU_PMC + 24(r4)
183	lwz	r11, VCPU_PMC + 28(r4)
184END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
185	mtspr	SPRN_PMC1, r3
186	mtspr	SPRN_PMC2, r5
187	mtspr	SPRN_PMC3, r6
188	mtspr	SPRN_PMC4, r7
189	mtspr	SPRN_PMC5, r8
190	mtspr	SPRN_PMC6, r9
191BEGIN_FTR_SECTION
192	mtspr	SPRN_PMC7, r10
193	mtspr	SPRN_PMC8, r11
194END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
195	ld	r3, VCPU_MMCR(r4)
196	ld	r5, VCPU_MMCR + 8(r4)
197	ld	r6, VCPU_MMCR + 16(r4)
198	mtspr	SPRN_MMCR1, r5
199	mtspr	SPRN_MMCRA, r6
200	mtspr	SPRN_MMCR0, r3
201	isync
202
203	/* Load up FP, VMX and VSX registers */
204	bl	kvmppc_load_fp
205
206	ld	r14, VCPU_GPR(R14)(r4)
207	ld	r15, VCPU_GPR(R15)(r4)
208	ld	r16, VCPU_GPR(R16)(r4)
209	ld	r17, VCPU_GPR(R17)(r4)
210	ld	r18, VCPU_GPR(R18)(r4)
211	ld	r19, VCPU_GPR(R19)(r4)
212	ld	r20, VCPU_GPR(R20)(r4)
213	ld	r21, VCPU_GPR(R21)(r4)
214	ld	r22, VCPU_GPR(R22)(r4)
215	ld	r23, VCPU_GPR(R23)(r4)
216	ld	r24, VCPU_GPR(R24)(r4)
217	ld	r25, VCPU_GPR(R25)(r4)
218	ld	r26, VCPU_GPR(R26)(r4)
219	ld	r27, VCPU_GPR(R27)(r4)
220	ld	r28, VCPU_GPR(R28)(r4)
221	ld	r29, VCPU_GPR(R29)(r4)
222	ld	r30, VCPU_GPR(R30)(r4)
223	ld	r31, VCPU_GPR(R31)(r4)
224
225BEGIN_FTR_SECTION
226	/* Switch DSCR to guest value */
227	ld	r5, VCPU_DSCR(r4)
228	mtspr	SPRN_DSCR, r5
229END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
230
231	/*
232	 * Set the decrementer to the guest decrementer.
233	 */
234	ld	r8,VCPU_DEC_EXPIRES(r4)
235	mftb	r7
236	subf	r3,r7,r8
237	mtspr	SPRN_DEC,r3
238	stw	r3,VCPU_DEC(r4)
239
240	ld	r5, VCPU_SPRG0(r4)
241	ld	r6, VCPU_SPRG1(r4)
242	ld	r7, VCPU_SPRG2(r4)
243	ld	r8, VCPU_SPRG3(r4)
244	mtspr	SPRN_SPRG0, r5
245	mtspr	SPRN_SPRG1, r6
246	mtspr	SPRN_SPRG2, r7
247	mtspr	SPRN_SPRG3, r8
248
249	/* Save R1 in the PACA */
250	std	r1, HSTATE_HOST_R1(r13)
251
252	/* Increment yield count if they have a VPA */
253	ld	r3, VCPU_VPA(r4)
254	cmpdi	r3, 0
255	beq	25f
256	lwz	r5, LPPACA_YIELDCOUNT(r3)
257	addi	r5, r5, 1
258	stw	r5, LPPACA_YIELDCOUNT(r3)
25925:
260	/* Load up DAR and DSISR */
261	ld	r5, VCPU_DAR(r4)
262	lwz	r6, VCPU_DSISR(r4)
263	mtspr	SPRN_DAR, r5
264	mtspr	SPRN_DSISR, r6
265
266BEGIN_FTR_SECTION
267	/* Restore AMR and UAMOR, set AMOR to all 1s */
268	ld	r5,VCPU_AMR(r4)
269	ld	r6,VCPU_UAMOR(r4)
270	li	r7,-1
271	mtspr	SPRN_AMR,r5
272	mtspr	SPRN_UAMOR,r6
273	mtspr	SPRN_AMOR,r7
274END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
275
276	/* Clear out SLB */
277	li	r6,0
278	slbmte	r6,r6
279	slbia
280	ptesync
281
282BEGIN_FTR_SECTION
283	b	30f
284END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
285	/*
286	 * POWER7 host -> guest partition switch code.
287	 * We don't have to lock against concurrent tlbies,
288	 * but we do have to coordinate across hardware threads.
289	 */
290	/* Increment entry count iff exit count is zero. */
291	ld	r5,HSTATE_KVM_VCORE(r13)
292	addi	r9,r5,VCORE_ENTRY_EXIT
29321:	lwarx	r3,0,r9
294	cmpwi	r3,0x100		/* any threads starting to exit? */
295	bge	secondary_too_late	/* if so we're too late to the party */
296	addi	r3,r3,1
297	stwcx.	r3,0,r9
298	bne	21b
299
300	/* Primary thread switches to guest partition. */
301	ld	r9,VCPU_KVM(r4)		/* pointer to struct kvm */
302	lwz	r6,VCPU_PTID(r4)
303	cmpwi	r6,0
304	bne	20f
305	ld	r6,KVM_SDR1(r9)
306	lwz	r7,KVM_LPID(r9)
307	li	r0,LPID_RSVD		/* switch to reserved LPID */
308	mtspr	SPRN_LPID,r0
309	ptesync
310	mtspr	SPRN_SDR1,r6		/* switch to partition page table */
311	mtspr	SPRN_LPID,r7
312	isync
313	li	r0,1
314	stb	r0,VCORE_IN_GUEST(r5)	/* signal secondaries to continue */
315	b	10f
316
317	/* Secondary threads wait for primary to have done partition switch */
31820:	lbz	r0,VCORE_IN_GUEST(r5)
319	cmpwi	r0,0
320	beq	20b
321
322	/* Set LPCR and RMOR. */
32310:	ld	r8,KVM_LPCR(r9)
324	mtspr	SPRN_LPCR,r8
325	ld	r8,KVM_RMOR(r9)
326	mtspr	SPRN_RMOR,r8
327	isync
328
329	/* Check if HDEC expires soon */
330	mfspr	r3,SPRN_HDEC
331	cmpwi	r3,10
332	li	r12,BOOK3S_INTERRUPT_HV_DECREMENTER
333	mr	r9,r4
334	blt	hdec_soon
335
336	/*
337	 * Invalidate the TLB if we could possibly have stale TLB
338	 * entries for this partition on this core due to the use
339	 * of tlbiel.
340	 * XXX maybe only need this on primary thread?
341	 */
342	ld	r9,VCPU_KVM(r4)		/* pointer to struct kvm */
343	lwz	r5,VCPU_VCPUID(r4)
344	lhz	r6,PACAPACAINDEX(r13)
345	rldimi	r6,r5,0,62		/* XXX map as if threads 1:1 p:v */
346	lhz	r8,VCPU_LAST_CPU(r4)
347	sldi	r7,r6,1			/* see if this is the same vcpu */
348	add	r7,r7,r9		/* as last ran on this pcpu */
349	lhz	r0,KVM_LAST_VCPU(r7)
350	cmpw	r6,r8			/* on the same cpu core as last time? */
351	bne	3f
352	cmpw	r0,r5			/* same vcpu as this core last ran? */
353	beq	1f
3543:	sth	r6,VCPU_LAST_CPU(r4)	/* if not, invalidate partition TLB */
355	sth	r5,KVM_LAST_VCPU(r7)
356	li	r6,128
357	mtctr	r6
358	li	r7,0x800		/* IS field = 0b10 */
359	ptesync
3602:	tlbiel	r7
361	addi	r7,r7,0x1000
362	bdnz	2b
363	ptesync
3641:
365
366	/* Save purr/spurr */
367	mfspr	r5,SPRN_PURR
368	mfspr	r6,SPRN_SPURR
369	std	r5,HSTATE_PURR(r13)
370	std	r6,HSTATE_SPURR(r13)
371	ld	r7,VCPU_PURR(r4)
372	ld	r8,VCPU_SPURR(r4)
373	mtspr	SPRN_PURR,r7
374	mtspr	SPRN_SPURR,r8
375	b	31f
376
377	/*
378	 * PPC970 host -> guest partition switch code.
379	 * We have to lock against concurrent tlbies,
380	 * using native_tlbie_lock to lock against host tlbies
381	 * and kvm->arch.tlbie_lock to lock against guest tlbies.
382	 * We also have to invalidate the TLB since its
383	 * entries aren't tagged with the LPID.
384	 */
38530:	ld	r9,VCPU_KVM(r4)		/* pointer to struct kvm */
386
387	/* first take native_tlbie_lock */
388	.section ".toc","aw"
389toc_tlbie_lock:
390	.tc	native_tlbie_lock[TC],native_tlbie_lock
391	.previous
392	ld	r3,toc_tlbie_lock@toc(2)
393	lwz	r8,PACA_LOCK_TOKEN(r13)
39424:	lwarx	r0,0,r3
395	cmpwi	r0,0
396	bne	24b
397	stwcx.	r8,0,r3
398	bne	24b
399	isync
400
401	ld	r7,KVM_LPCR(r9)		/* use kvm->arch.lpcr to store HID4 */
402	li	r0,0x18f
403	rotldi	r0,r0,HID4_LPID5_SH	/* all lpid bits in HID4 = 1 */
404	or	r0,r7,r0
405	ptesync
406	sync
407	mtspr	SPRN_HID4,r0		/* switch to reserved LPID */
408	isync
409	li	r0,0
410	stw	r0,0(r3)		/* drop native_tlbie_lock */
411
412	/* invalidate the whole TLB */
413	li	r0,256
414	mtctr	r0
415	li	r6,0
41625:	tlbiel	r6
417	addi	r6,r6,0x1000
418	bdnz	25b
419	ptesync
420
421	/* Take the guest's tlbie_lock */
422	addi	r3,r9,KVM_TLBIE_LOCK
42324:	lwarx	r0,0,r3
424	cmpwi	r0,0
425	bne	24b
426	stwcx.	r8,0,r3
427	bne	24b
428	isync
429	ld	r6,KVM_SDR1(r9)
430	mtspr	SPRN_SDR1,r6		/* switch to partition page table */
431
432	/* Set up HID4 with the guest's LPID etc. */
433	sync
434	mtspr	SPRN_HID4,r7
435	isync
436
437	/* drop the guest's tlbie_lock */
438	li	r0,0
439	stw	r0,0(r3)
440
441	/* Check if HDEC expires soon */
442	mfspr	r3,SPRN_HDEC
443	cmpwi	r3,10
444	li	r12,BOOK3S_INTERRUPT_HV_DECREMENTER
445	mr	r9,r4
446	blt	hdec_soon
447
448	/* Enable HDEC interrupts */
449	mfspr	r0,SPRN_HID0
450	li	r3,1
451	rldimi	r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
452	sync
453	mtspr	SPRN_HID0,r0
454	mfspr	r0,SPRN_HID0
455	mfspr	r0,SPRN_HID0
456	mfspr	r0,SPRN_HID0
457	mfspr	r0,SPRN_HID0
458	mfspr	r0,SPRN_HID0
459	mfspr	r0,SPRN_HID0
460
461	/* Load up guest SLB entries */
46231:	lwz	r5,VCPU_SLB_MAX(r4)
463	cmpwi	r5,0
464	beq	9f
465	mtctr	r5
466	addi	r6,r4,VCPU_SLB
4671:	ld	r8,VCPU_SLB_E(r6)
468	ld	r9,VCPU_SLB_V(r6)
469	slbmte	r9,r8
470	addi	r6,r6,VCPU_SLB_SIZE
471	bdnz	1b
4729:
473
474	/* Restore state of CTRL run bit; assume 1 on entry */
475	lwz	r5,VCPU_CTRL(r4)
476	andi.	r5,r5,1
477	bne	4f
478	mfspr	r6,SPRN_CTRLF
479	clrrdi	r6,r6,1
480	mtspr	SPRN_CTRLT,r6
4814:
482	ld	r6, VCPU_CTR(r4)
483	lwz	r7, VCPU_XER(r4)
484
485	mtctr	r6
486	mtxer	r7
487
488kvmppc_cede_reentry:		/* r4 = vcpu, r13 = paca */
489	ld	r6, VCPU_SRR0(r4)
490	ld	r7, VCPU_SRR1(r4)
491	ld	r10, VCPU_PC(r4)
492	ld	r11, VCPU_MSR(r4)	/* r11 = vcpu->arch.msr & ~MSR_HV */
493
494	rldicl	r11, r11, 63 - MSR_HV_LG, 1
495	rotldi	r11, r11, 1 + MSR_HV_LG
496	ori	r11, r11, MSR_ME
497
498	/* Check if we can deliver an external or decrementer interrupt now */
499	ld	r0,VCPU_PENDING_EXC(r4)
500	li	r8,(1 << BOOK3S_IRQPRIO_EXTERNAL)
501	oris	r8,r8,(1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h
502	and	r0,r0,r8
503	cmpdi	cr1,r0,0
504	andi.	r0,r11,MSR_EE
505	beq	cr1,11f
506BEGIN_FTR_SECTION
507	mfspr	r8,SPRN_LPCR
508	ori	r8,r8,LPCR_MER
509	mtspr	SPRN_LPCR,r8
510	isync
511END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
512	beq	5f
513	li	r0,BOOK3S_INTERRUPT_EXTERNAL
51412:	mr	r6,r10
515	mr	r10,r0
516	mr	r7,r11
517	li	r11,(MSR_ME << 1) | 1	/* synthesize MSR_SF | MSR_ME */
518	rotldi	r11,r11,63
519	b	5f
52011:	beq	5f
521	mfspr	r0,SPRN_DEC
522	cmpwi	r0,0
523	li	r0,BOOK3S_INTERRUPT_DECREMENTER
524	blt	12b
525
526	/* Move SRR0 and SRR1 into the respective regs */
5275:	mtspr	SPRN_SRR0, r6
528	mtspr	SPRN_SRR1, r7
529	li	r0,0
530	stb	r0,VCPU_CEDED(r4)	/* cancel cede */
531
532fast_guest_return:
533	mtspr	SPRN_HSRR0,r10
534	mtspr	SPRN_HSRR1,r11
535
536	/* Activate guest mode, so faults get handled by KVM */
537	li	r9, KVM_GUEST_MODE_GUEST
538	stb	r9, HSTATE_IN_GUEST(r13)
539
540	/* Enter guest */
541
542	ld	r5, VCPU_LR(r4)
543	lwz	r6, VCPU_CR(r4)
544	mtlr	r5
545	mtcr	r6
546
547	ld	r0, VCPU_GPR(R0)(r4)
548	ld	r1, VCPU_GPR(R1)(r4)
549	ld	r2, VCPU_GPR(R2)(r4)
550	ld	r3, VCPU_GPR(R3)(r4)
551	ld	r5, VCPU_GPR(R5)(r4)
552	ld	r6, VCPU_GPR(R6)(r4)
553	ld	r7, VCPU_GPR(R7)(r4)
554	ld	r8, VCPU_GPR(R8)(r4)
555	ld	r9, VCPU_GPR(R9)(r4)
556	ld	r10, VCPU_GPR(R10)(r4)
557	ld	r11, VCPU_GPR(R11)(r4)
558	ld	r12, VCPU_GPR(R12)(r4)
559	ld	r13, VCPU_GPR(R13)(r4)
560
561	ld	r4, VCPU_GPR(R4)(r4)
562
563	hrfid
564	b	.
565
566/******************************************************************************
567 *                                                                            *
568 *                               Exit code                                    *
569 *                                                                            *
570 *****************************************************************************/
571
572/*
573 * We come here from the first-level interrupt handlers.
574 */
575	.globl	kvmppc_interrupt
576kvmppc_interrupt:
577	/*
578	 * Register contents:
579	 * R12		= interrupt vector
580	 * R13		= PACA
581	 * guest CR, R12 saved in shadow VCPU SCRATCH1/0
582	 * guest R13 saved in SPRN_SCRATCH0
583	 */
584	/* abuse host_r2 as third scratch area; we get r2 from PACATOC(r13) */
585	std	r9, HSTATE_HOST_R2(r13)
586	ld	r9, HSTATE_KVM_VCPU(r13)
587
588	/* Save registers */
589
590	std	r0, VCPU_GPR(R0)(r9)
591	std	r1, VCPU_GPR(R1)(r9)
592	std	r2, VCPU_GPR(R2)(r9)
593	std	r3, VCPU_GPR(R3)(r9)
594	std	r4, VCPU_GPR(R4)(r9)
595	std	r5, VCPU_GPR(R5)(r9)
596	std	r6, VCPU_GPR(R6)(r9)
597	std	r7, VCPU_GPR(R7)(r9)
598	std	r8, VCPU_GPR(R8)(r9)
599	ld	r0, HSTATE_HOST_R2(r13)
600	std	r0, VCPU_GPR(R9)(r9)
601	std	r10, VCPU_GPR(R10)(r9)
602	std	r11, VCPU_GPR(R11)(r9)
603	ld	r3, HSTATE_SCRATCH0(r13)
604	lwz	r4, HSTATE_SCRATCH1(r13)
605	std	r3, VCPU_GPR(R12)(r9)
606	stw	r4, VCPU_CR(r9)
607
608	/* Restore R1/R2 so we can handle faults */
609	ld	r1, HSTATE_HOST_R1(r13)
610	ld	r2, PACATOC(r13)
611
612	mfspr	r10, SPRN_SRR0
613	mfspr	r11, SPRN_SRR1
614	std	r10, VCPU_SRR0(r9)
615	std	r11, VCPU_SRR1(r9)
616	andi.	r0, r12, 2		/* need to read HSRR0/1? */
617	beq	1f
618	mfspr	r10, SPRN_HSRR0
619	mfspr	r11, SPRN_HSRR1
620	clrrdi	r12, r12, 2
6211:	std	r10, VCPU_PC(r9)
622	std	r11, VCPU_MSR(r9)
623
624	GET_SCRATCH0(r3)
625	mflr	r4
626	std	r3, VCPU_GPR(R13)(r9)
627	std	r4, VCPU_LR(r9)
628
629	/* Unset guest mode */
630	li	r0, KVM_GUEST_MODE_NONE
631	stb	r0, HSTATE_IN_GUEST(r13)
632
633	stw	r12,VCPU_TRAP(r9)
634
635	/* Save HEIR (HV emulation assist reg) in last_inst
636	   if this is an HEI (HV emulation interrupt, e40) */
637	li	r3,KVM_INST_FETCH_FAILED
638BEGIN_FTR_SECTION
639	cmpwi	r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
640	bne	11f
641	mfspr	r3,SPRN_HEIR
642END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
64311:	stw	r3,VCPU_LAST_INST(r9)
644
645	/* these are volatile across C function calls */
646	mfctr	r3
647	mfxer	r4
648	std	r3, VCPU_CTR(r9)
649	stw	r4, VCPU_XER(r9)
650
651BEGIN_FTR_SECTION
652	/* If this is a page table miss then see if it's theirs or ours */
653	cmpwi	r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
654	beq	kvmppc_hdsi
655	cmpwi	r12, BOOK3S_INTERRUPT_H_INST_STORAGE
656	beq	kvmppc_hisi
657END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
658
659	/* See if this is a leftover HDEC interrupt */
660	cmpwi	r12,BOOK3S_INTERRUPT_HV_DECREMENTER
661	bne	2f
662	mfspr	r3,SPRN_HDEC
663	cmpwi	r3,0
664	bge	ignore_hdec
6652:
666	/* See if this is an hcall we can handle in real mode */
667	cmpwi	r12,BOOK3S_INTERRUPT_SYSCALL
668	beq	hcall_try_real_mode
669
670	/* Check for mediated interrupts (could be done earlier really ...) */
671BEGIN_FTR_SECTION
672	cmpwi	r12,BOOK3S_INTERRUPT_EXTERNAL
673	bne+	1f
674	andi.	r0,r11,MSR_EE
675	beq	1f
676	mfspr	r5,SPRN_LPCR
677	andi.	r0,r5,LPCR_MER
678	bne	bounce_ext_interrupt
6791:
680END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
681
682nohpte_cont:
683hcall_real_cont:		/* r9 = vcpu, r12 = trap, r13 = paca */
684	/* Save DEC */
685	mfspr	r5,SPRN_DEC
686	mftb	r6
687	extsw	r5,r5
688	add	r5,r5,r6
689	std	r5,VCPU_DEC_EXPIRES(r9)
690
691	/* Save more register state  */
692	mfdar	r6
693	mfdsisr	r7
694	std	r6, VCPU_DAR(r9)
695	stw	r7, VCPU_DSISR(r9)
696BEGIN_FTR_SECTION
697	/* don't overwrite fault_dar/fault_dsisr if HDSI */
698	cmpwi	r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
699	beq	6f
700END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
701	std	r6, VCPU_FAULT_DAR(r9)
702	stw	r7, VCPU_FAULT_DSISR(r9)
703
704	/* Save guest CTRL register, set runlatch to 1 */
7056:	mfspr	r6,SPRN_CTRLF
706	stw	r6,VCPU_CTRL(r9)
707	andi.	r0,r6,1
708	bne	4f
709	ori	r6,r6,1
710	mtspr	SPRN_CTRLT,r6
7114:
712	/* Read the guest SLB and save it away */
713	lwz	r0,VCPU_SLB_NR(r9)	/* number of entries in SLB */
714	mtctr	r0
715	li	r6,0
716	addi	r7,r9,VCPU_SLB
717	li	r5,0
7181:	slbmfee	r8,r6
719	andis.	r0,r8,SLB_ESID_V@h
720	beq	2f
721	add	r8,r8,r6		/* put index in */
722	slbmfev	r3,r6
723	std	r8,VCPU_SLB_E(r7)
724	std	r3,VCPU_SLB_V(r7)
725	addi	r7,r7,VCPU_SLB_SIZE
726	addi	r5,r5,1
7272:	addi	r6,r6,1
728	bdnz	1b
729	stw	r5,VCPU_SLB_MAX(r9)
730
731	/*
732	 * Save the guest PURR/SPURR
733	 */
734BEGIN_FTR_SECTION
735	mfspr	r5,SPRN_PURR
736	mfspr	r6,SPRN_SPURR
737	ld	r7,VCPU_PURR(r9)
738	ld	r8,VCPU_SPURR(r9)
739	std	r5,VCPU_PURR(r9)
740	std	r6,VCPU_SPURR(r9)
741	subf	r5,r7,r5
742	subf	r6,r8,r6
743
744	/*
745	 * Restore host PURR/SPURR and add guest times
746	 * so that the time in the guest gets accounted.
747	 */
748	ld	r3,HSTATE_PURR(r13)
749	ld	r4,HSTATE_SPURR(r13)
750	add	r3,r3,r5
751	add	r4,r4,r6
752	mtspr	SPRN_PURR,r3
753	mtspr	SPRN_SPURR,r4
754END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
755
756	/* Clear out SLB */
757	li	r5,0
758	slbmte	r5,r5
759	slbia
760	ptesync
761
762hdec_soon:			/* r9 = vcpu, r12 = trap, r13 = paca */
763BEGIN_FTR_SECTION
764	b	32f
765END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
766	/*
767	 * POWER7 guest -> host partition switch code.
768	 * We don't have to lock against tlbies but we do
769	 * have to coordinate the hardware threads.
770	 */
771	/* Increment the threads-exiting-guest count in the 0xff00
772	   bits of vcore->entry_exit_count */
773	lwsync
774	ld	r5,HSTATE_KVM_VCORE(r13)
775	addi	r6,r5,VCORE_ENTRY_EXIT
77641:	lwarx	r3,0,r6
777	addi	r0,r3,0x100
778	stwcx.	r0,0,r6
779	bne	41b
780	lwsync
781
782	/*
783	 * At this point we have an interrupt that we have to pass
784	 * up to the kernel or qemu; we can't handle it in real mode.
785	 * Thus we have to do a partition switch, so we have to
786	 * collect the other threads, if we are the first thread
787	 * to take an interrupt.  To do this, we set the HDEC to 0,
788	 * which causes an HDEC interrupt in all threads within 2ns
789	 * because the HDEC register is shared between all 4 threads.
790	 * However, we don't need to bother if this is an HDEC
791	 * interrupt, since the other threads will already be on their
792	 * way here in that case.
793	 */
794	cmpwi	r3,0x100	/* Are we the first here? */
795	bge	43f
796	cmpwi	r3,1		/* Are any other threads in the guest? */
797	ble	43f
798	cmpwi	r12,BOOK3S_INTERRUPT_HV_DECREMENTER
799	beq	40f
800	li	r0,0
801	mtspr	SPRN_HDEC,r0
80240:
803	/*
804	 * Send an IPI to any napping threads, since an HDEC interrupt
805	 * doesn't wake CPUs up from nap.
806	 */
807	lwz	r3,VCORE_NAPPING_THREADS(r5)
808	lwz	r4,VCPU_PTID(r9)
809	li	r0,1
810	sld	r0,r0,r4
811	andc.	r3,r3,r0		/* no sense IPI'ing ourselves */
812	beq	43f
813	mulli	r4,r4,PACA_SIZE		/* get paca for thread 0 */
814	subf	r6,r4,r13
81542:	andi.	r0,r3,1
816	beq	44f
817	ld	r8,HSTATE_XICS_PHYS(r6)	/* get thread's XICS reg addr */
818	li	r0,IPI_PRIORITY
819	li	r7,XICS_QIRR
820	stbcix	r0,r7,r8		/* trigger the IPI */
82144:	srdi.	r3,r3,1
822	addi	r6,r6,PACA_SIZE
823	bne	42b
824
825	/* Secondary threads wait for primary to do partition switch */
82643:	ld	r4,VCPU_KVM(r9)		/* pointer to struct kvm */
827	ld	r5,HSTATE_KVM_VCORE(r13)
828	lwz	r3,VCPU_PTID(r9)
829	cmpwi	r3,0
830	beq	15f
831	HMT_LOW
83213:	lbz	r3,VCORE_IN_GUEST(r5)
833	cmpwi	r3,0
834	bne	13b
835	HMT_MEDIUM
836	b	16f
837
838	/* Primary thread waits for all the secondaries to exit guest */
83915:	lwz	r3,VCORE_ENTRY_EXIT(r5)
840	srwi	r0,r3,8
841	clrldi	r3,r3,56
842	cmpw	r3,r0
843	bne	15b
844	isync
845
846	/* Primary thread switches back to host partition */
847	ld	r6,KVM_HOST_SDR1(r4)
848	lwz	r7,KVM_HOST_LPID(r4)
849	li	r8,LPID_RSVD		/* switch to reserved LPID */
850	mtspr	SPRN_LPID,r8
851	ptesync
852	mtspr	SPRN_SDR1,r6		/* switch to partition page table */
853	mtspr	SPRN_LPID,r7
854	isync
855	li	r0,0
856	stb	r0,VCORE_IN_GUEST(r5)
857	lis	r8,0x7fff		/* MAX_INT@h */
858	mtspr	SPRN_HDEC,r8
859
86016:	ld	r8,KVM_HOST_LPCR(r4)
861	mtspr	SPRN_LPCR,r8
862	isync
863	b	33f
864
865	/*
866	 * PPC970 guest -> host partition switch code.
867	 * We have to lock against concurrent tlbies, and
868	 * we have to flush the whole TLB.
869	 */
87032:	ld	r4,VCPU_KVM(r9)		/* pointer to struct kvm */
871
872	/* Take the guest's tlbie_lock */
873	lwz	r8,PACA_LOCK_TOKEN(r13)
874	addi	r3,r4,KVM_TLBIE_LOCK
87524:	lwarx	r0,0,r3
876	cmpwi	r0,0
877	bne	24b
878	stwcx.	r8,0,r3
879	bne	24b
880	isync
881
882	ld	r7,KVM_HOST_LPCR(r4)	/* use kvm->arch.host_lpcr for HID4 */
883	li	r0,0x18f
884	rotldi	r0,r0,HID4_LPID5_SH	/* all lpid bits in HID4 = 1 */
885	or	r0,r7,r0
886	ptesync
887	sync
888	mtspr	SPRN_HID4,r0		/* switch to reserved LPID */
889	isync
890	li	r0,0
891	stw	r0,0(r3)		/* drop guest tlbie_lock */
892
893	/* invalidate the whole TLB */
894	li	r0,256
895	mtctr	r0
896	li	r6,0
89725:	tlbiel	r6
898	addi	r6,r6,0x1000
899	bdnz	25b
900	ptesync
901
902	/* take native_tlbie_lock */
903	ld	r3,toc_tlbie_lock@toc(2)
90424:	lwarx	r0,0,r3
905	cmpwi	r0,0
906	bne	24b
907	stwcx.	r8,0,r3
908	bne	24b
909	isync
910
911	ld	r6,KVM_HOST_SDR1(r4)
912	mtspr	SPRN_SDR1,r6		/* switch to host page table */
913
914	/* Set up host HID4 value */
915	sync
916	mtspr	SPRN_HID4,r7
917	isync
918	li	r0,0
919	stw	r0,0(r3)		/* drop native_tlbie_lock */
920
921	lis	r8,0x7fff		/* MAX_INT@h */
922	mtspr	SPRN_HDEC,r8
923
924	/* Disable HDEC interrupts */
925	mfspr	r0,SPRN_HID0
926	li	r3,0
927	rldimi	r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
928	sync
929	mtspr	SPRN_HID0,r0
930	mfspr	r0,SPRN_HID0
931	mfspr	r0,SPRN_HID0
932	mfspr	r0,SPRN_HID0
933	mfspr	r0,SPRN_HID0
934	mfspr	r0,SPRN_HID0
935	mfspr	r0,SPRN_HID0
936
937	/* load host SLB entries */
93833:	ld	r8,PACA_SLBSHADOWPTR(r13)
939
940	.rept	SLB_NUM_BOLTED
941	ld	r5,SLBSHADOW_SAVEAREA(r8)
942	ld	r6,SLBSHADOW_SAVEAREA+8(r8)
943	andis.	r7,r5,SLB_ESID_V@h
944	beq	1f
945	slbmte	r6,r5
9461:	addi	r8,r8,16
947	.endr
948
949	/* Save and reset AMR and UAMOR before turning on the MMU */
950BEGIN_FTR_SECTION
951	mfspr	r5,SPRN_AMR
952	mfspr	r6,SPRN_UAMOR
953	std	r5,VCPU_AMR(r9)
954	std	r6,VCPU_UAMOR(r9)
955	li	r6,0
956	mtspr	SPRN_AMR,r6
957END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
958
959	/* Switch DSCR back to host value */
960BEGIN_FTR_SECTION
961	mfspr	r8, SPRN_DSCR
962	ld	r7, HSTATE_DSCR(r13)
963	std	r8, VCPU_DSCR(r7)
964	mtspr	SPRN_DSCR, r7
965END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
966
967	/* Save non-volatile GPRs */
968	std	r14, VCPU_GPR(R14)(r9)
969	std	r15, VCPU_GPR(R15)(r9)
970	std	r16, VCPU_GPR(R16)(r9)
971	std	r17, VCPU_GPR(R17)(r9)
972	std	r18, VCPU_GPR(R18)(r9)
973	std	r19, VCPU_GPR(R19)(r9)
974	std	r20, VCPU_GPR(R20)(r9)
975	std	r21, VCPU_GPR(R21)(r9)
976	std	r22, VCPU_GPR(R22)(r9)
977	std	r23, VCPU_GPR(R23)(r9)
978	std	r24, VCPU_GPR(R24)(r9)
979	std	r25, VCPU_GPR(R25)(r9)
980	std	r26, VCPU_GPR(R26)(r9)
981	std	r27, VCPU_GPR(R27)(r9)
982	std	r28, VCPU_GPR(R28)(r9)
983	std	r29, VCPU_GPR(R29)(r9)
984	std	r30, VCPU_GPR(R30)(r9)
985	std	r31, VCPU_GPR(R31)(r9)
986
987	/* Save SPRGs */
988	mfspr	r3, SPRN_SPRG0
989	mfspr	r4, SPRN_SPRG1
990	mfspr	r5, SPRN_SPRG2
991	mfspr	r6, SPRN_SPRG3
992	std	r3, VCPU_SPRG0(r9)
993	std	r4, VCPU_SPRG1(r9)
994	std	r5, VCPU_SPRG2(r9)
995	std	r6, VCPU_SPRG3(r9)
996
997	/* save FP state */
998	mr	r3, r9
999	bl	.kvmppc_save_fp
1000
1001	/* Increment yield count if they have a VPA */
1002	ld	r8, VCPU_VPA(r9)	/* do they have a VPA? */
1003	cmpdi	r8, 0
1004	beq	25f
1005	lwz	r3, LPPACA_YIELDCOUNT(r8)
1006	addi	r3, r3, 1
1007	stw	r3, LPPACA_YIELDCOUNT(r8)
100825:
1009	/* Save PMU registers if requested */
1010	/* r8 and cr0.eq are live here */
1011	li	r3, 1
1012	sldi	r3, r3, 31		/* MMCR0_FC (freeze counters) bit */
1013	mfspr	r4, SPRN_MMCR0		/* save MMCR0 */
1014	mtspr	SPRN_MMCR0, r3		/* freeze all counters, disable ints */
1015	mfspr	r6, SPRN_MMCRA
1016BEGIN_FTR_SECTION
1017	/* On P7, clear MMCRA in order to disable SDAR updates */
1018	li	r7, 0
1019	mtspr	SPRN_MMCRA, r7
1020END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1021	isync
1022	beq	21f			/* if no VPA, save PMU stuff anyway */
1023	lbz	r7, LPPACA_PMCINUSE(r8)
1024	cmpwi	r7, 0			/* did they ask for PMU stuff to be saved? */
1025	bne	21f
1026	std	r3, VCPU_MMCR(r9)	/* if not, set saved MMCR0 to FC */
1027	b	22f
102821:	mfspr	r5, SPRN_MMCR1
1029	std	r4, VCPU_MMCR(r9)
1030	std	r5, VCPU_MMCR + 8(r9)
1031	std	r6, VCPU_MMCR + 16(r9)
1032	mfspr	r3, SPRN_PMC1
1033	mfspr	r4, SPRN_PMC2
1034	mfspr	r5, SPRN_PMC3
1035	mfspr	r6, SPRN_PMC4
1036	mfspr	r7, SPRN_PMC5
1037	mfspr	r8, SPRN_PMC6
1038BEGIN_FTR_SECTION
1039	mfspr	r10, SPRN_PMC7
1040	mfspr	r11, SPRN_PMC8
1041END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1042	stw	r3, VCPU_PMC(r9)
1043	stw	r4, VCPU_PMC + 4(r9)
1044	stw	r5, VCPU_PMC + 8(r9)
1045	stw	r6, VCPU_PMC + 12(r9)
1046	stw	r7, VCPU_PMC + 16(r9)
1047	stw	r8, VCPU_PMC + 20(r9)
1048BEGIN_FTR_SECTION
1049	stw	r10, VCPU_PMC + 24(r9)
1050	stw	r11, VCPU_PMC + 28(r9)
1051END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
105222:
1053
1054	/* Secondary threads go off to take a nap on POWER7 */
1055BEGIN_FTR_SECTION
1056	lwz	r0,VCPU_PTID(r9)
1057	cmpwi	r0,0
1058	bne	secondary_nap
1059END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1060
1061	/* Restore host DABR and DABRX */
1062	ld	r5,HSTATE_DABR(r13)
1063	li	r6,7
1064	mtspr	SPRN_DABR,r5
1065	mtspr	SPRN_DABRX,r6
1066
1067	/* Restore SPRG3 */
1068	ld	r3,HSTATE_SPRG3(r13)
1069	mtspr	SPRN_SPRG3,r3
1070
1071	/*
1072	 * Reload DEC.  HDEC interrupts were disabled when
1073	 * we reloaded the host's LPCR value.
1074	 */
1075	ld	r3, HSTATE_DECEXP(r13)
1076	mftb	r4
1077	subf	r4, r4, r3
1078	mtspr	SPRN_DEC, r4
1079
1080	/* Reload the host's PMU registers */
1081	ld	r3, PACALPPACAPTR(r13)	/* is the host using the PMU? */
1082	lbz	r4, LPPACA_PMCINUSE(r3)
1083	cmpwi	r4, 0
1084	beq	23f			/* skip if not */
1085	lwz	r3, HSTATE_PMC(r13)
1086	lwz	r4, HSTATE_PMC + 4(r13)
1087	lwz	r5, HSTATE_PMC + 8(r13)
1088	lwz	r6, HSTATE_PMC + 12(r13)
1089	lwz	r8, HSTATE_PMC + 16(r13)
1090	lwz	r9, HSTATE_PMC + 20(r13)
1091BEGIN_FTR_SECTION
1092	lwz	r10, HSTATE_PMC + 24(r13)
1093	lwz	r11, HSTATE_PMC + 28(r13)
1094END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1095	mtspr	SPRN_PMC1, r3
1096	mtspr	SPRN_PMC2, r4
1097	mtspr	SPRN_PMC3, r5
1098	mtspr	SPRN_PMC4, r6
1099	mtspr	SPRN_PMC5, r8
1100	mtspr	SPRN_PMC6, r9
1101BEGIN_FTR_SECTION
1102	mtspr	SPRN_PMC7, r10
1103	mtspr	SPRN_PMC8, r11
1104END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1105	ld	r3, HSTATE_MMCR(r13)
1106	ld	r4, HSTATE_MMCR + 8(r13)
1107	ld	r5, HSTATE_MMCR + 16(r13)
1108	mtspr	SPRN_MMCR1, r4
1109	mtspr	SPRN_MMCRA, r5
1110	mtspr	SPRN_MMCR0, r3
1111	isync
111223:
1113	/*
1114	 * For external and machine check interrupts, we need
1115	 * to call the Linux handler to process the interrupt.
1116	 * We do that by jumping to the interrupt vector address
1117	 * which we have in r12.  The [h]rfid at the end of the
1118	 * handler will return to the book3s_hv_interrupts.S code.
1119	 * For other interrupts we do the rfid to get back
1120	 * to the book3s_interrupts.S code here.
1121	 */
1122	ld	r8, HSTATE_VMHANDLER(r13)
1123	ld	r7, HSTATE_HOST_MSR(r13)
1124
1125	cmpwi	r12, BOOK3S_INTERRUPT_EXTERNAL
1126	beq	11f
1127	cmpwi	r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1128
1129	/* RFI into the highmem handler, or branch to interrupt handler */
113012:	mfmsr	r6
1131	mtctr	r12
1132	li	r0, MSR_RI
1133	andc	r6, r6, r0
1134	mtmsrd	r6, 1			/* Clear RI in MSR */
1135	mtsrr0	r8
1136	mtsrr1	r7
1137	beqctr
1138	RFI
1139
114011:
1141BEGIN_FTR_SECTION
1142	b	12b
1143END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1144	mtspr	SPRN_HSRR0, r8
1145	mtspr	SPRN_HSRR1, r7
1146	ba	0x500
1147
1148/*
1149 * Check whether an HDSI is an HPTE not found fault or something else.
1150 * If it is an HPTE not found fault that is due to the guest accessing
1151 * a page that they have mapped but which we have paged out, then
1152 * we continue on with the guest exit path.  In all other cases,
1153 * reflect the HDSI to the guest as a DSI.
1154 */
1155kvmppc_hdsi:
1156	mfspr	r4, SPRN_HDAR
1157	mfspr	r6, SPRN_HDSISR
1158	/* HPTE not found fault or protection fault? */
1159	andis.	r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1160	beq	1f			/* if not, send it to the guest */
1161	andi.	r0, r11, MSR_DR		/* data relocation enabled? */
1162	beq	3f
1163	clrrdi	r0, r4, 28
1164	PPC_SLBFEE_DOT(R5, R0)		/* if so, look up SLB */
1165	bne	1f			/* if no SLB entry found */
11664:	std	r4, VCPU_FAULT_DAR(r9)
1167	stw	r6, VCPU_FAULT_DSISR(r9)
1168
1169	/* Search the hash table. */
1170	mr	r3, r9			/* vcpu pointer */
1171	li	r7, 1			/* data fault */
1172	bl	.kvmppc_hpte_hv_fault
1173	ld	r9, HSTATE_KVM_VCPU(r13)
1174	ld	r10, VCPU_PC(r9)
1175	ld	r11, VCPU_MSR(r9)
1176	li	r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1177	cmpdi	r3, 0			/* retry the instruction */
1178	beq	6f
1179	cmpdi	r3, -1			/* handle in kernel mode */
1180	beq	nohpte_cont
1181	cmpdi	r3, -2			/* MMIO emulation; need instr word */
1182	beq	2f
1183
1184	/* Synthesize a DSI for the guest */
1185	ld	r4, VCPU_FAULT_DAR(r9)
1186	mr	r6, r3
11871:	mtspr	SPRN_DAR, r4
1188	mtspr	SPRN_DSISR, r6
1189	mtspr	SPRN_SRR0, r10
1190	mtspr	SPRN_SRR1, r11
1191	li	r10, BOOK3S_INTERRUPT_DATA_STORAGE
1192	li	r11, (MSR_ME << 1) | 1	/* synthesize MSR_SF | MSR_ME */
1193	rotldi	r11, r11, 63
11946:	ld	r7, VCPU_CTR(r9)
1195	lwz	r8, VCPU_XER(r9)
1196	mtctr	r7
1197	mtxer	r8
1198	mr	r4, r9
1199	b	fast_guest_return
1200
12013:	ld	r5, VCPU_KVM(r9)	/* not relocated, use VRMA */
1202	ld	r5, KVM_VRMA_SLB_V(r5)
1203	b	4b
1204
1205	/* If this is for emulated MMIO, load the instruction word */
12062:	li	r8, KVM_INST_FETCH_FAILED	/* In case lwz faults */
1207
1208	/* Set guest mode to 'jump over instruction' so if lwz faults
1209	 * we'll just continue at the next IP. */
1210	li	r0, KVM_GUEST_MODE_SKIP
1211	stb	r0, HSTATE_IN_GUEST(r13)
1212
1213	/* Do the access with MSR:DR enabled */
1214	mfmsr	r3
1215	ori	r4, r3, MSR_DR		/* Enable paging for data */
1216	mtmsrd	r4
1217	lwz	r8, 0(r10)
1218	mtmsrd	r3
1219
1220	/* Store the result */
1221	stw	r8, VCPU_LAST_INST(r9)
1222
1223	/* Unset guest mode. */
1224	li	r0, KVM_GUEST_MODE_NONE
1225	stb	r0, HSTATE_IN_GUEST(r13)
1226	b	nohpte_cont
1227
1228/*
1229 * Similarly for an HISI, reflect it to the guest as an ISI unless
1230 * it is an HPTE not found fault for a page that we have paged out.
1231 */
1232kvmppc_hisi:
1233	andis.	r0, r11, SRR1_ISI_NOPT@h
1234	beq	1f
1235	andi.	r0, r11, MSR_IR		/* instruction relocation enabled? */
1236	beq	3f
1237	clrrdi	r0, r10, 28
1238	PPC_SLBFEE_DOT(R5, R0)		/* if so, look up SLB */
1239	bne	1f			/* if no SLB entry found */
12404:
1241	/* Search the hash table. */
1242	mr	r3, r9			/* vcpu pointer */
1243	mr	r4, r10
1244	mr	r6, r11
1245	li	r7, 0			/* instruction fault */
1246	bl	.kvmppc_hpte_hv_fault
1247	ld	r9, HSTATE_KVM_VCPU(r13)
1248	ld	r10, VCPU_PC(r9)
1249	ld	r11, VCPU_MSR(r9)
1250	li	r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1251	cmpdi	r3, 0			/* retry the instruction */
1252	beq	6f
1253	cmpdi	r3, -1			/* handle in kernel mode */
1254	beq	nohpte_cont
1255
1256	/* Synthesize an ISI for the guest */
1257	mr	r11, r3
12581:	mtspr	SPRN_SRR0, r10
1259	mtspr	SPRN_SRR1, r11
1260	li	r10, BOOK3S_INTERRUPT_INST_STORAGE
1261	li	r11, (MSR_ME << 1) | 1	/* synthesize MSR_SF | MSR_ME */
1262	rotldi	r11, r11, 63
12636:	ld	r7, VCPU_CTR(r9)
1264	lwz	r8, VCPU_XER(r9)
1265	mtctr	r7
1266	mtxer	r8
1267	mr	r4, r9
1268	b	fast_guest_return
1269
12703:	ld	r6, VCPU_KVM(r9)	/* not relocated, use VRMA */
1271	ld	r5, KVM_VRMA_SLB_V(r6)
1272	b	4b
1273
1274/*
1275 * Try to handle an hcall in real mode.
1276 * Returns to the guest if we handle it, or continues on up to
1277 * the kernel if we can't (i.e. if we don't have a handler for
1278 * it, or if the handler returns H_TOO_HARD).
1279 */
1280	.globl	hcall_try_real_mode
1281hcall_try_real_mode:
1282	ld	r3,VCPU_GPR(R3)(r9)
1283	andi.	r0,r11,MSR_PR
1284	bne	hcall_real_cont
1285	clrrdi	r3,r3,2
1286	cmpldi	r3,hcall_real_table_end - hcall_real_table
1287	bge	hcall_real_cont
1288	LOAD_REG_ADDR(r4, hcall_real_table)
1289	lwzx	r3,r3,r4
1290	cmpwi	r3,0
1291	beq	hcall_real_cont
1292	add	r3,r3,r4
1293	mtctr	r3
1294	mr	r3,r9		/* get vcpu pointer */
1295	ld	r4,VCPU_GPR(R4)(r9)
1296	bctrl
1297	cmpdi	r3,H_TOO_HARD
1298	beq	hcall_real_fallback
1299	ld	r4,HSTATE_KVM_VCPU(r13)
1300	std	r3,VCPU_GPR(R3)(r4)
1301	ld	r10,VCPU_PC(r4)
1302	ld	r11,VCPU_MSR(r4)
1303	b	fast_guest_return
1304
1305	/* We've attempted a real mode hcall, but it's punted it back
1306	 * to userspace.  We need to restore some clobbered volatiles
1307	 * before resuming the pass-it-to-qemu path */
1308hcall_real_fallback:
1309	li	r12,BOOK3S_INTERRUPT_SYSCALL
1310	ld	r9, HSTATE_KVM_VCPU(r13)
1311
1312	b	hcall_real_cont
1313
1314	.globl	hcall_real_table
1315hcall_real_table:
1316	.long	0		/* 0 - unused */
1317	.long	.kvmppc_h_remove - hcall_real_table
1318	.long	.kvmppc_h_enter - hcall_real_table
1319	.long	.kvmppc_h_read - hcall_real_table
1320	.long	0		/* 0x10 - H_CLEAR_MOD */
1321	.long	0		/* 0x14 - H_CLEAR_REF */
1322	.long	.kvmppc_h_protect - hcall_real_table
1323	.long	0		/* 0x1c - H_GET_TCE */
1324	.long	.kvmppc_h_put_tce - hcall_real_table
1325	.long	0		/* 0x24 - H_SET_SPRG0 */
1326	.long	.kvmppc_h_set_dabr - hcall_real_table
1327	.long	0		/* 0x2c */
1328	.long	0		/* 0x30 */
1329	.long	0		/* 0x34 */
1330	.long	0		/* 0x38 */
1331	.long	0		/* 0x3c */
1332	.long	0		/* 0x40 */
1333	.long	0		/* 0x44 */
1334	.long	0		/* 0x48 */
1335	.long	0		/* 0x4c */
1336	.long	0		/* 0x50 */
1337	.long	0		/* 0x54 */
1338	.long	0		/* 0x58 */
1339	.long	0		/* 0x5c */
1340	.long	0		/* 0x60 */
1341	.long	0		/* 0x64 */
1342	.long	0		/* 0x68 */
1343	.long	0		/* 0x6c */
1344	.long	0		/* 0x70 */
1345	.long	0		/* 0x74 */
1346	.long	0		/* 0x78 */
1347	.long	0		/* 0x7c */
1348	.long	0		/* 0x80 */
1349	.long	0		/* 0x84 */
1350	.long	0		/* 0x88 */
1351	.long	0		/* 0x8c */
1352	.long	0		/* 0x90 */
1353	.long	0		/* 0x94 */
1354	.long	0		/* 0x98 */
1355	.long	0		/* 0x9c */
1356	.long	0		/* 0xa0 */
1357	.long	0		/* 0xa4 */
1358	.long	0		/* 0xa8 */
1359	.long	0		/* 0xac */
1360	.long	0		/* 0xb0 */
1361	.long	0		/* 0xb4 */
1362	.long	0		/* 0xb8 */
1363	.long	0		/* 0xbc */
1364	.long	0		/* 0xc0 */
1365	.long	0		/* 0xc4 */
1366	.long	0		/* 0xc8 */
1367	.long	0		/* 0xcc */
1368	.long	0		/* 0xd0 */
1369	.long	0		/* 0xd4 */
1370	.long	0		/* 0xd8 */
1371	.long	0		/* 0xdc */
1372	.long	.kvmppc_h_cede - hcall_real_table
1373	.long	0		/* 0xe4 */
1374	.long	0		/* 0xe8 */
1375	.long	0		/* 0xec */
1376	.long	0		/* 0xf0 */
1377	.long	0		/* 0xf4 */
1378	.long	0		/* 0xf8 */
1379	.long	0		/* 0xfc */
1380	.long	0		/* 0x100 */
1381	.long	0		/* 0x104 */
1382	.long	0		/* 0x108 */
1383	.long	0		/* 0x10c */
1384	.long	0		/* 0x110 */
1385	.long	0		/* 0x114 */
1386	.long	0		/* 0x118 */
1387	.long	0		/* 0x11c */
1388	.long	0		/* 0x120 */
1389	.long	.kvmppc_h_bulk_remove - hcall_real_table
1390hcall_real_table_end:
1391
1392ignore_hdec:
1393	mr	r4,r9
1394	b	fast_guest_return
1395
1396bounce_ext_interrupt:
1397	mr	r4,r9
1398	mtspr	SPRN_SRR0,r10
1399	mtspr	SPRN_SRR1,r11
1400	li	r10,BOOK3S_INTERRUPT_EXTERNAL
1401	li	r11,(MSR_ME << 1) | 1	/* synthesize MSR_SF | MSR_ME */
1402	rotldi	r11,r11,63
1403	b	fast_guest_return
1404
1405_GLOBAL(kvmppc_h_set_dabr)
1406	std	r4,VCPU_DABR(r3)
1407	/* Work around P7 bug where DABR can get corrupted on mtspr */
14081:	mtspr	SPRN_DABR,r4
1409	mfspr	r5, SPRN_DABR
1410	cmpd	r4, r5
1411	bne	1b
1412	isync
1413	li	r3,0
1414	blr
1415
1416_GLOBAL(kvmppc_h_cede)
1417	ori	r11,r11,MSR_EE
1418	std	r11,VCPU_MSR(r3)
1419	li	r0,1
1420	stb	r0,VCPU_CEDED(r3)
1421	sync			/* order setting ceded vs. testing prodded */
1422	lbz	r5,VCPU_PRODDED(r3)
1423	cmpwi	r5,0
1424	bne	kvm_cede_prodded
1425	li	r0,0		/* set trap to 0 to say hcall is handled */
1426	stw	r0,VCPU_TRAP(r3)
1427	li	r0,H_SUCCESS
1428	std	r0,VCPU_GPR(R3)(r3)
1429BEGIN_FTR_SECTION
1430	b	kvm_cede_exit	/* just send it up to host on 970 */
1431END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
1432
1433	/*
1434	 * Set our bit in the bitmask of napping threads unless all the
1435	 * other threads are already napping, in which case we send this
1436	 * up to the host.
1437	 */
1438	ld	r5,HSTATE_KVM_VCORE(r13)
1439	lwz	r6,VCPU_PTID(r3)
1440	lwz	r8,VCORE_ENTRY_EXIT(r5)
1441	clrldi	r8,r8,56
1442	li	r0,1
1443	sld	r0,r0,r6
1444	addi	r6,r5,VCORE_NAPPING_THREADS
144531:	lwarx	r4,0,r6
1446	or	r4,r4,r0
1447	PPC_POPCNTW(R7,R4)
1448	cmpw	r7,r8
1449	bge	kvm_cede_exit
1450	stwcx.	r4,0,r6
1451	bne	31b
1452	li	r0,1
1453	stb	r0,HSTATE_NAPPING(r13)
1454	/* order napping_threads update vs testing entry_exit_count */
1455	lwsync
1456	mr	r4,r3
1457	lwz	r7,VCORE_ENTRY_EXIT(r5)
1458	cmpwi	r7,0x100
1459	bge	33f		/* another thread already exiting */
1460
1461/*
1462 * Although not specifically required by the architecture, POWER7
1463 * preserves the following registers in nap mode, even if an SMT mode
1464 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
1465 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
1466 */
1467	/* Save non-volatile GPRs */
1468	std	r14, VCPU_GPR(R14)(r3)
1469	std	r15, VCPU_GPR(R15)(r3)
1470	std	r16, VCPU_GPR(R16)(r3)
1471	std	r17, VCPU_GPR(R17)(r3)
1472	std	r18, VCPU_GPR(R18)(r3)
1473	std	r19, VCPU_GPR(R19)(r3)
1474	std	r20, VCPU_GPR(R20)(r3)
1475	std	r21, VCPU_GPR(R21)(r3)
1476	std	r22, VCPU_GPR(R22)(r3)
1477	std	r23, VCPU_GPR(R23)(r3)
1478	std	r24, VCPU_GPR(R24)(r3)
1479	std	r25, VCPU_GPR(R25)(r3)
1480	std	r26, VCPU_GPR(R26)(r3)
1481	std	r27, VCPU_GPR(R27)(r3)
1482	std	r28, VCPU_GPR(R28)(r3)
1483	std	r29, VCPU_GPR(R29)(r3)
1484	std	r30, VCPU_GPR(R30)(r3)
1485	std	r31, VCPU_GPR(R31)(r3)
1486
1487	/* save FP state */
1488	bl	.kvmppc_save_fp
1489
1490	/*
1491	 * Take a nap until a decrementer or external interrupt occurs,
1492	 * with PECE1 (wake on decr) and PECE0 (wake on external) set in LPCR
1493	 */
1494	li	r0,1
1495	stb	r0,HSTATE_HWTHREAD_REQ(r13)
1496	mfspr	r5,SPRN_LPCR
1497	ori	r5,r5,LPCR_PECE0 | LPCR_PECE1
1498	mtspr	SPRN_LPCR,r5
1499	isync
1500	li	r0, 0
1501	std	r0, HSTATE_SCRATCH0(r13)
1502	ptesync
1503	ld	r0, HSTATE_SCRATCH0(r13)
15041:	cmpd	r0, r0
1505	bne	1b
1506	nap
1507	b	.
1508
1509kvm_end_cede:
1510	/* Woken by external or decrementer interrupt */
1511	ld	r1, HSTATE_HOST_R1(r13)
1512
1513	/* load up FP state */
1514	bl	kvmppc_load_fp
1515
1516	/* Load NV GPRS */
1517	ld	r14, VCPU_GPR(R14)(r4)
1518	ld	r15, VCPU_GPR(R15)(r4)
1519	ld	r16, VCPU_GPR(R16)(r4)
1520	ld	r17, VCPU_GPR(R17)(r4)
1521	ld	r18, VCPU_GPR(R18)(r4)
1522	ld	r19, VCPU_GPR(R19)(r4)
1523	ld	r20, VCPU_GPR(R20)(r4)
1524	ld	r21, VCPU_GPR(R21)(r4)
1525	ld	r22, VCPU_GPR(R22)(r4)
1526	ld	r23, VCPU_GPR(R23)(r4)
1527	ld	r24, VCPU_GPR(R24)(r4)
1528	ld	r25, VCPU_GPR(R25)(r4)
1529	ld	r26, VCPU_GPR(R26)(r4)
1530	ld	r27, VCPU_GPR(R27)(r4)
1531	ld	r28, VCPU_GPR(R28)(r4)
1532	ld	r29, VCPU_GPR(R29)(r4)
1533	ld	r30, VCPU_GPR(R30)(r4)
1534	ld	r31, VCPU_GPR(R31)(r4)
1535
1536	/* clear our bit in vcore->napping_threads */
153733:	ld	r5,HSTATE_KVM_VCORE(r13)
1538	lwz	r3,VCPU_PTID(r4)
1539	li	r0,1
1540	sld	r0,r0,r3
1541	addi	r6,r5,VCORE_NAPPING_THREADS
154232:	lwarx	r7,0,r6
1543	andc	r7,r7,r0
1544	stwcx.	r7,0,r6
1545	bne	32b
1546	li	r0,0
1547	stb	r0,HSTATE_NAPPING(r13)
1548
1549	/* see if any other thread is already exiting */
1550	lwz	r0,VCORE_ENTRY_EXIT(r5)
1551	cmpwi	r0,0x100
1552	blt	kvmppc_cede_reentry	/* if not go back to guest */
1553
1554	/* some threads are exiting, so go to the guest exit path */
1555	b	hcall_real_fallback
1556
1557	/* cede when already previously prodded case */
1558kvm_cede_prodded:
1559	li	r0,0
1560	stb	r0,VCPU_PRODDED(r3)
1561	sync			/* order testing prodded vs. clearing ceded */
1562	stb	r0,VCPU_CEDED(r3)
1563	li	r3,H_SUCCESS
1564	blr
1565
1566	/* we've ceded but we want to give control to the host */
1567kvm_cede_exit:
1568	li	r3,H_TOO_HARD
1569	blr
1570
1571secondary_too_late:
1572	ld	r5,HSTATE_KVM_VCORE(r13)
1573	HMT_LOW
157413:	lbz	r3,VCORE_IN_GUEST(r5)
1575	cmpwi	r3,0
1576	bne	13b
1577	HMT_MEDIUM
1578	ld	r11,PACA_SLBSHADOWPTR(r13)
1579
1580	.rept	SLB_NUM_BOLTED
1581	ld	r5,SLBSHADOW_SAVEAREA(r11)
1582	ld	r6,SLBSHADOW_SAVEAREA+8(r11)
1583	andis.	r7,r5,SLB_ESID_V@h
1584	beq	1f
1585	slbmte	r6,r5
15861:	addi	r11,r11,16
1587	.endr
1588
1589secondary_nap:
1590	/* Clear any pending IPI - assume we're a secondary thread */
1591	ld	r5, HSTATE_XICS_PHYS(r13)
1592	li	r7, XICS_XIRR
1593	lwzcix	r3, r5, r7		/* ack any pending interrupt */
1594	rlwinm.	r0, r3, 0, 0xffffff	/* any pending? */
1595	beq	37f
1596	sync
1597	li	r0, 0xff
1598	li	r6, XICS_QIRR
1599	stbcix	r0, r5, r6		/* clear the IPI */
1600	stwcix	r3, r5, r7		/* EOI it */
160137:	sync
1602
1603	/* increment the nap count and then go to nap mode */
1604	ld	r4, HSTATE_KVM_VCORE(r13)
1605	addi	r4, r4, VCORE_NAP_COUNT
1606	lwsync				/* make previous updates visible */
160751:	lwarx	r3, 0, r4
1608	addi	r3, r3, 1
1609	stwcx.	r3, 0, r4
1610	bne	51b
1611
1612kvm_no_guest:
1613	li	r0, KVM_HWTHREAD_IN_NAP
1614	stb	r0, HSTATE_HWTHREAD_STATE(r13)
1615	li	r0, 0
1616	std	r0, HSTATE_KVM_VCPU(r13)
1617
1618	li	r3, LPCR_PECE0
1619	mfspr	r4, SPRN_LPCR
1620	rlwimi	r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
1621	mtspr	SPRN_LPCR, r4
1622	isync
1623	std	r0, HSTATE_SCRATCH0(r13)
1624	ptesync
1625	ld	r0, HSTATE_SCRATCH0(r13)
16261:	cmpd	r0, r0
1627	bne	1b
1628	nap
1629	b	.
1630
1631/*
1632 * Save away FP, VMX and VSX registers.
1633 * r3 = vcpu pointer
1634 */
1635_GLOBAL(kvmppc_save_fp)
1636	mfmsr	r5
1637	ori	r8,r5,MSR_FP
1638#ifdef CONFIG_ALTIVEC
1639BEGIN_FTR_SECTION
1640	oris	r8,r8,MSR_VEC@h
1641END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1642#endif
1643#ifdef CONFIG_VSX
1644BEGIN_FTR_SECTION
1645	oris	r8,r8,MSR_VSX@h
1646END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1647#endif
1648	mtmsrd	r8
1649	isync
1650#ifdef CONFIG_VSX
1651BEGIN_FTR_SECTION
1652	reg = 0
1653	.rept	32
1654	li	r6,reg*16+VCPU_VSRS
1655	STXVD2X(reg,R6,R3)
1656	reg = reg + 1
1657	.endr
1658FTR_SECTION_ELSE
1659#endif
1660	reg = 0
1661	.rept	32
1662	stfd	reg,reg*8+VCPU_FPRS(r3)
1663	reg = reg + 1
1664	.endr
1665#ifdef CONFIG_VSX
1666ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
1667#endif
1668	mffs	fr0
1669	stfd	fr0,VCPU_FPSCR(r3)
1670
1671#ifdef CONFIG_ALTIVEC
1672BEGIN_FTR_SECTION
1673	reg = 0
1674	.rept	32
1675	li	r6,reg*16+VCPU_VRS
1676	stvx	reg,r6,r3
1677	reg = reg + 1
1678	.endr
1679	mfvscr	vr0
1680	li	r6,VCPU_VSCR
1681	stvx	vr0,r6,r3
1682END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1683#endif
1684	mfspr	r6,SPRN_VRSAVE
1685	stw	r6,VCPU_VRSAVE(r3)
1686	mtmsrd	r5
1687	isync
1688	blr
1689
1690/*
1691 * Load up FP, VMX and VSX registers
1692 * r4 = vcpu pointer
1693 */
1694	.globl	kvmppc_load_fp
1695kvmppc_load_fp:
1696	mfmsr	r9
1697	ori	r8,r9,MSR_FP
1698#ifdef CONFIG_ALTIVEC
1699BEGIN_FTR_SECTION
1700	oris	r8,r8,MSR_VEC@h
1701END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1702#endif
1703#ifdef CONFIG_VSX
1704BEGIN_FTR_SECTION
1705	oris	r8,r8,MSR_VSX@h
1706END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1707#endif
1708	mtmsrd	r8
1709	isync
1710	lfd	fr0,VCPU_FPSCR(r4)
1711	MTFSF_L(fr0)
1712#ifdef CONFIG_VSX
1713BEGIN_FTR_SECTION
1714	reg = 0
1715	.rept	32
1716	li	r7,reg*16+VCPU_VSRS
1717	LXVD2X(reg,R7,R4)
1718	reg = reg + 1
1719	.endr
1720FTR_SECTION_ELSE
1721#endif
1722	reg = 0
1723	.rept	32
1724	lfd	reg,reg*8+VCPU_FPRS(r4)
1725	reg = reg + 1
1726	.endr
1727#ifdef CONFIG_VSX
1728ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
1729#endif
1730
1731#ifdef CONFIG_ALTIVEC
1732BEGIN_FTR_SECTION
1733	li	r7,VCPU_VSCR
1734	lvx	vr0,r7,r4
1735	mtvscr	vr0
1736	reg = 0
1737	.rept	32
1738	li	r7,reg*16+VCPU_VRS
1739	lvx	reg,r7,r4
1740	reg = reg + 1
1741	.endr
1742END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1743#endif
1744	lwz	r7,VCPU_VRSAVE(r4)
1745	mtspr	SPRN_VRSAVE,r7
1746	blr
1747