1 /* 2 * Copyright 2012 Michael Ellerman, IBM Corporation. 3 * Copyright 2012 Benjamin Herrenschmidt, IBM Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License, version 2, as 7 * published by the Free Software Foundation. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/kvm_host.h> 12 #include <linux/err.h> 13 #include <linux/kernel_stat.h> 14 15 #include <asm/kvm_book3s.h> 16 #include <asm/kvm_ppc.h> 17 #include <asm/hvcall.h> 18 #include <asm/xics.h> 19 #include <asm/debug.h> 20 #include <asm/synch.h> 21 #include <asm/cputhreads.h> 22 #include <asm/pgtable.h> 23 #include <asm/ppc-opcode.h> 24 #include <asm/pnv-pci.h> 25 #include <asm/opal.h> 26 #include <asm/smp.h> 27 28 #include "book3s_xics.h" 29 30 #define DEBUG_PASSUP 31 32 int h_ipi_redirect = 1; 33 EXPORT_SYMBOL(h_ipi_redirect); 34 int kvm_irq_bypass = 1; 35 EXPORT_SYMBOL(kvm_irq_bypass); 36 37 static void icp_rm_deliver_irq(struct kvmppc_xics *xics, struct kvmppc_icp *icp, 38 u32 new_irq, bool check_resend); 39 static int xics_opal_set_server(unsigned int hw_irq, int server_cpu); 40 41 /* -- ICS routines -- */ 42 static void ics_rm_check_resend(struct kvmppc_xics *xics, 43 struct kvmppc_ics *ics, struct kvmppc_icp *icp) 44 { 45 int i; 46 47 for (i = 0; i < KVMPPC_XICS_IRQ_PER_ICS; i++) { 48 struct ics_irq_state *state = &ics->irq_state[i]; 49 if (state->resend) 50 icp_rm_deliver_irq(xics, icp, state->number, true); 51 } 52 53 } 54 55 /* -- ICP routines -- */ 56 57 #ifdef CONFIG_SMP 58 static inline void icp_send_hcore_msg(int hcore, struct kvm_vcpu *vcpu) 59 { 60 int hcpu; 61 62 hcpu = hcore << threads_shift; 63 kvmppc_host_rm_ops_hv->rm_core[hcore].rm_data = vcpu; 64 smp_muxed_ipi_set_message(hcpu, PPC_MSG_RM_HOST_ACTION); 65 kvmppc_set_host_ipi(hcpu, 1); 66 smp_mb(); 67 kvmhv_rm_send_ipi(hcpu); 68 } 69 #else 70 static inline void icp_send_hcore_msg(int hcore, struct kvm_vcpu *vcpu) { } 71 #endif 72 73 /* 74 * We start the search from our current CPU Id in the core map 75 * and go in a circle until we get back to our ID looking for a 76 * core that is running in host context and that hasn't already 77 * been targeted for another rm_host_ops. 78 * 79 * In the future, could consider using a fairer algorithm (one 80 * that distributes the IPIs better) 81 * 82 * Returns -1, if no CPU could be found in the host 83 * Else, returns a CPU Id which has been reserved for use 84 */ 85 static inline int grab_next_hostcore(int start, 86 struct kvmppc_host_rm_core *rm_core, int max, int action) 87 { 88 bool success; 89 int core; 90 union kvmppc_rm_state old, new; 91 92 for (core = start + 1; core < max; core++) { 93 old = new = READ_ONCE(rm_core[core].rm_state); 94 95 if (!old.in_host || old.rm_action) 96 continue; 97 98 /* Try to grab this host core if not taken already. */ 99 new.rm_action = action; 100 101 success = cmpxchg64(&rm_core[core].rm_state.raw, 102 old.raw, new.raw) == old.raw; 103 if (success) { 104 /* 105 * Make sure that the store to the rm_action is made 106 * visible before we return to caller (and the 107 * subsequent store to rm_data) to synchronize with 108 * the IPI handler. 109 */ 110 smp_wmb(); 111 return core; 112 } 113 } 114 115 return -1; 116 } 117 118 static inline int find_available_hostcore(int action) 119 { 120 int core; 121 int my_core = smp_processor_id() >> threads_shift; 122 struct kvmppc_host_rm_core *rm_core = kvmppc_host_rm_ops_hv->rm_core; 123 124 core = grab_next_hostcore(my_core, rm_core, cpu_nr_cores(), action); 125 if (core == -1) 126 core = grab_next_hostcore(core, rm_core, my_core, action); 127 128 return core; 129 } 130 131 static void icp_rm_set_vcpu_irq(struct kvm_vcpu *vcpu, 132 struct kvm_vcpu *this_vcpu) 133 { 134 struct kvmppc_icp *this_icp = this_vcpu->arch.icp; 135 int cpu; 136 int hcore; 137 138 /* Mark the target VCPU as having an interrupt pending */ 139 vcpu->stat.queue_intr++; 140 set_bit(BOOK3S_IRQPRIO_EXTERNAL_LEVEL, &vcpu->arch.pending_exceptions); 141 142 /* Kick self ? Just set MER and return */ 143 if (vcpu == this_vcpu) { 144 mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) | LPCR_MER); 145 return; 146 } 147 148 /* 149 * Check if the core is loaded, 150 * if not, find an available host core to post to wake the VCPU, 151 * if we can't find one, set up state to eventually return too hard. 152 */ 153 cpu = vcpu->arch.thread_cpu; 154 if (cpu < 0 || cpu >= nr_cpu_ids) { 155 hcore = -1; 156 if (kvmppc_host_rm_ops_hv && h_ipi_redirect) 157 hcore = find_available_hostcore(XICS_RM_KICK_VCPU); 158 if (hcore != -1) { 159 icp_send_hcore_msg(hcore, vcpu); 160 } else { 161 this_icp->rm_action |= XICS_RM_KICK_VCPU; 162 this_icp->rm_kick_target = vcpu; 163 } 164 return; 165 } 166 167 smp_mb(); 168 kvmhv_rm_send_ipi(cpu); 169 } 170 171 static void icp_rm_clr_vcpu_irq(struct kvm_vcpu *vcpu) 172 { 173 /* Note: Only called on self ! */ 174 clear_bit(BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 175 &vcpu->arch.pending_exceptions); 176 mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) & ~LPCR_MER); 177 } 178 179 static inline bool icp_rm_try_update(struct kvmppc_icp *icp, 180 union kvmppc_icp_state old, 181 union kvmppc_icp_state new) 182 { 183 struct kvm_vcpu *this_vcpu = local_paca->kvm_hstate.kvm_vcpu; 184 bool success; 185 186 /* Calculate new output value */ 187 new.out_ee = (new.xisr && (new.pending_pri < new.cppr)); 188 189 /* Attempt atomic update */ 190 success = cmpxchg64(&icp->state.raw, old.raw, new.raw) == old.raw; 191 if (!success) 192 goto bail; 193 194 /* 195 * Check for output state update 196 * 197 * Note that this is racy since another processor could be updating 198 * the state already. This is why we never clear the interrupt output 199 * here, we only ever set it. The clear only happens prior to doing 200 * an update and only by the processor itself. Currently we do it 201 * in Accept (H_XIRR) and Up_Cppr (H_XPPR). 202 * 203 * We also do not try to figure out whether the EE state has changed, 204 * we unconditionally set it if the new state calls for it. The reason 205 * for that is that we opportunistically remove the pending interrupt 206 * flag when raising CPPR, so we need to set it back here if an 207 * interrupt is still pending. 208 */ 209 if (new.out_ee) 210 icp_rm_set_vcpu_irq(icp->vcpu, this_vcpu); 211 212 /* Expose the state change for debug purposes */ 213 this_vcpu->arch.icp->rm_dbgstate = new; 214 this_vcpu->arch.icp->rm_dbgtgt = icp->vcpu; 215 216 bail: 217 return success; 218 } 219 220 static inline int check_too_hard(struct kvmppc_xics *xics, 221 struct kvmppc_icp *icp) 222 { 223 return (xics->real_mode_dbg || icp->rm_action) ? H_TOO_HARD : H_SUCCESS; 224 } 225 226 static void icp_rm_check_resend(struct kvmppc_xics *xics, 227 struct kvmppc_icp *icp) 228 { 229 u32 icsid; 230 231 /* Order this load with the test for need_resend in the caller */ 232 smp_rmb(); 233 for_each_set_bit(icsid, icp->resend_map, xics->max_icsid + 1) { 234 struct kvmppc_ics *ics = xics->ics[icsid]; 235 236 if (!test_and_clear_bit(icsid, icp->resend_map)) 237 continue; 238 if (!ics) 239 continue; 240 ics_rm_check_resend(xics, ics, icp); 241 } 242 } 243 244 static bool icp_rm_try_to_deliver(struct kvmppc_icp *icp, u32 irq, u8 priority, 245 u32 *reject) 246 { 247 union kvmppc_icp_state old_state, new_state; 248 bool success; 249 250 do { 251 old_state = new_state = READ_ONCE(icp->state); 252 253 *reject = 0; 254 255 /* See if we can deliver */ 256 success = new_state.cppr > priority && 257 new_state.mfrr > priority && 258 new_state.pending_pri > priority; 259 260 /* 261 * If we can, check for a rejection and perform the 262 * delivery 263 */ 264 if (success) { 265 *reject = new_state.xisr; 266 new_state.xisr = irq; 267 new_state.pending_pri = priority; 268 } else { 269 /* 270 * If we failed to deliver we set need_resend 271 * so a subsequent CPPR state change causes us 272 * to try a new delivery. 273 */ 274 new_state.need_resend = true; 275 } 276 277 } while (!icp_rm_try_update(icp, old_state, new_state)); 278 279 return success; 280 } 281 282 static void icp_rm_deliver_irq(struct kvmppc_xics *xics, struct kvmppc_icp *icp, 283 u32 new_irq, bool check_resend) 284 { 285 struct ics_irq_state *state; 286 struct kvmppc_ics *ics; 287 u32 reject; 288 u16 src; 289 290 /* 291 * This is used both for initial delivery of an interrupt and 292 * for subsequent rejection. 293 * 294 * Rejection can be racy vs. resends. We have evaluated the 295 * rejection in an atomic ICP transaction which is now complete, 296 * so potentially the ICP can already accept the interrupt again. 297 * 298 * So we need to retry the delivery. Essentially the reject path 299 * boils down to a failed delivery. Always. 300 * 301 * Now the interrupt could also have moved to a different target, 302 * thus we may need to re-do the ICP lookup as well 303 */ 304 305 again: 306 /* Get the ICS state and lock it */ 307 ics = kvmppc_xics_find_ics(xics, new_irq, &src); 308 if (!ics) { 309 /* Unsafe increment, but this does not need to be accurate */ 310 xics->err_noics++; 311 return; 312 } 313 state = &ics->irq_state[src]; 314 315 /* Get a lock on the ICS */ 316 arch_spin_lock(&ics->lock); 317 318 /* Get our server */ 319 if (!icp || state->server != icp->server_num) { 320 icp = kvmppc_xics_find_server(xics->kvm, state->server); 321 if (!icp) { 322 /* Unsafe increment again*/ 323 xics->err_noicp++; 324 goto out; 325 } 326 } 327 328 if (check_resend) 329 if (!state->resend) 330 goto out; 331 332 /* Clear the resend bit of that interrupt */ 333 state->resend = 0; 334 335 /* 336 * If masked, bail out 337 * 338 * Note: PAPR doesn't mention anything about masked pending 339 * when doing a resend, only when doing a delivery. 340 * 341 * However that would have the effect of losing a masked 342 * interrupt that was rejected and isn't consistent with 343 * the whole masked_pending business which is about not 344 * losing interrupts that occur while masked. 345 * 346 * I don't differentiate normal deliveries and resends, this 347 * implementation will differ from PAPR and not lose such 348 * interrupts. 349 */ 350 if (state->priority == MASKED) { 351 state->masked_pending = 1; 352 goto out; 353 } 354 355 /* 356 * Try the delivery, this will set the need_resend flag 357 * in the ICP as part of the atomic transaction if the 358 * delivery is not possible. 359 * 360 * Note that if successful, the new delivery might have itself 361 * rejected an interrupt that was "delivered" before we took the 362 * ics spin lock. 363 * 364 * In this case we do the whole sequence all over again for the 365 * new guy. We cannot assume that the rejected interrupt is less 366 * favored than the new one, and thus doesn't need to be delivered, 367 * because by the time we exit icp_rm_try_to_deliver() the target 368 * processor may well have already consumed & completed it, and thus 369 * the rejected interrupt might actually be already acceptable. 370 */ 371 if (icp_rm_try_to_deliver(icp, new_irq, state->priority, &reject)) { 372 /* 373 * Delivery was successful, did we reject somebody else ? 374 */ 375 if (reject && reject != XICS_IPI) { 376 arch_spin_unlock(&ics->lock); 377 icp->n_reject++; 378 new_irq = reject; 379 check_resend = 0; 380 goto again; 381 } 382 } else { 383 /* 384 * We failed to deliver the interrupt we need to set the 385 * resend map bit and mark the ICS state as needing a resend 386 */ 387 state->resend = 1; 388 389 /* 390 * Make sure when checking resend, we don't miss the resend 391 * if resend_map bit is seen and cleared. 392 */ 393 smp_wmb(); 394 set_bit(ics->icsid, icp->resend_map); 395 396 /* 397 * If the need_resend flag got cleared in the ICP some time 398 * between icp_rm_try_to_deliver() atomic update and now, then 399 * we know it might have missed the resend_map bit. So we 400 * retry 401 */ 402 smp_mb(); 403 if (!icp->state.need_resend) { 404 state->resend = 0; 405 arch_spin_unlock(&ics->lock); 406 check_resend = 0; 407 goto again; 408 } 409 } 410 out: 411 arch_spin_unlock(&ics->lock); 412 } 413 414 static void icp_rm_down_cppr(struct kvmppc_xics *xics, struct kvmppc_icp *icp, 415 u8 new_cppr) 416 { 417 union kvmppc_icp_state old_state, new_state; 418 bool resend; 419 420 /* 421 * This handles several related states in one operation: 422 * 423 * ICP State: Down_CPPR 424 * 425 * Load CPPR with new value and if the XISR is 0 426 * then check for resends: 427 * 428 * ICP State: Resend 429 * 430 * If MFRR is more favored than CPPR, check for IPIs 431 * and notify ICS of a potential resend. This is done 432 * asynchronously (when used in real mode, we will have 433 * to exit here). 434 * 435 * We do not handle the complete Check_IPI as documented 436 * here. In the PAPR, this state will be used for both 437 * Set_MFRR and Down_CPPR. However, we know that we aren't 438 * changing the MFRR state here so we don't need to handle 439 * the case of an MFRR causing a reject of a pending irq, 440 * this will have been handled when the MFRR was set in the 441 * first place. 442 * 443 * Thus we don't have to handle rejects, only resends. 444 * 445 * When implementing real mode for HV KVM, resend will lead to 446 * a H_TOO_HARD return and the whole transaction will be handled 447 * in virtual mode. 448 */ 449 do { 450 old_state = new_state = READ_ONCE(icp->state); 451 452 /* Down_CPPR */ 453 new_state.cppr = new_cppr; 454 455 /* 456 * Cut down Resend / Check_IPI / IPI 457 * 458 * The logic is that we cannot have a pending interrupt 459 * trumped by an IPI at this point (see above), so we 460 * know that either the pending interrupt is already an 461 * IPI (in which case we don't care to override it) or 462 * it's either more favored than us or non existent 463 */ 464 if (new_state.mfrr < new_cppr && 465 new_state.mfrr <= new_state.pending_pri) { 466 new_state.pending_pri = new_state.mfrr; 467 new_state.xisr = XICS_IPI; 468 } 469 470 /* Latch/clear resend bit */ 471 resend = new_state.need_resend; 472 new_state.need_resend = 0; 473 474 } while (!icp_rm_try_update(icp, old_state, new_state)); 475 476 /* 477 * Now handle resend checks. Those are asynchronous to the ICP 478 * state update in HW (ie bus transactions) so we can handle them 479 * separately here as well. 480 */ 481 if (resend) { 482 icp->n_check_resend++; 483 icp_rm_check_resend(xics, icp); 484 } 485 } 486 487 488 unsigned long kvmppc_rm_h_xirr(struct kvm_vcpu *vcpu) 489 { 490 union kvmppc_icp_state old_state, new_state; 491 struct kvmppc_xics *xics = vcpu->kvm->arch.xics; 492 struct kvmppc_icp *icp = vcpu->arch.icp; 493 u32 xirr; 494 495 if (!xics || !xics->real_mode) 496 return H_TOO_HARD; 497 498 /* First clear the interrupt */ 499 icp_rm_clr_vcpu_irq(icp->vcpu); 500 501 /* 502 * ICP State: Accept_Interrupt 503 * 504 * Return the pending interrupt (if any) along with the 505 * current CPPR, then clear the XISR & set CPPR to the 506 * pending priority 507 */ 508 do { 509 old_state = new_state = READ_ONCE(icp->state); 510 511 xirr = old_state.xisr | (((u32)old_state.cppr) << 24); 512 if (!old_state.xisr) 513 break; 514 new_state.cppr = new_state.pending_pri; 515 new_state.pending_pri = 0xff; 516 new_state.xisr = 0; 517 518 } while (!icp_rm_try_update(icp, old_state, new_state)); 519 520 /* Return the result in GPR4 */ 521 vcpu->arch.gpr[4] = xirr; 522 523 return check_too_hard(xics, icp); 524 } 525 526 int kvmppc_rm_h_ipi(struct kvm_vcpu *vcpu, unsigned long server, 527 unsigned long mfrr) 528 { 529 union kvmppc_icp_state old_state, new_state; 530 struct kvmppc_xics *xics = vcpu->kvm->arch.xics; 531 struct kvmppc_icp *icp, *this_icp = vcpu->arch.icp; 532 u32 reject; 533 bool resend; 534 bool local; 535 536 if (!xics || !xics->real_mode) 537 return H_TOO_HARD; 538 539 local = this_icp->server_num == server; 540 if (local) 541 icp = this_icp; 542 else 543 icp = kvmppc_xics_find_server(vcpu->kvm, server); 544 if (!icp) 545 return H_PARAMETER; 546 547 /* 548 * ICP state: Set_MFRR 549 * 550 * If the CPPR is more favored than the new MFRR, then 551 * nothing needs to be done as there can be no XISR to 552 * reject. 553 * 554 * ICP state: Check_IPI 555 * 556 * If the CPPR is less favored, then we might be replacing 557 * an interrupt, and thus need to possibly reject it. 558 * 559 * ICP State: IPI 560 * 561 * Besides rejecting any pending interrupts, we also 562 * update XISR and pending_pri to mark IPI as pending. 563 * 564 * PAPR does not describe this state, but if the MFRR is being 565 * made less favored than its earlier value, there might be 566 * a previously-rejected interrupt needing to be resent. 567 * Ideally, we would want to resend only if 568 * prio(pending_interrupt) < mfrr && 569 * prio(pending_interrupt) < cppr 570 * where pending interrupt is the one that was rejected. But 571 * we don't have that state, so we simply trigger a resend 572 * whenever the MFRR is made less favored. 573 */ 574 do { 575 old_state = new_state = READ_ONCE(icp->state); 576 577 /* Set_MFRR */ 578 new_state.mfrr = mfrr; 579 580 /* Check_IPI */ 581 reject = 0; 582 resend = false; 583 if (mfrr < new_state.cppr) { 584 /* Reject a pending interrupt if not an IPI */ 585 if (mfrr <= new_state.pending_pri) { 586 reject = new_state.xisr; 587 new_state.pending_pri = mfrr; 588 new_state.xisr = XICS_IPI; 589 } 590 } 591 592 if (mfrr > old_state.mfrr) { 593 resend = new_state.need_resend; 594 new_state.need_resend = 0; 595 } 596 } while (!icp_rm_try_update(icp, old_state, new_state)); 597 598 /* Handle reject in real mode */ 599 if (reject && reject != XICS_IPI) { 600 this_icp->n_reject++; 601 icp_rm_deliver_irq(xics, icp, reject, false); 602 } 603 604 /* Handle resends in real mode */ 605 if (resend) { 606 this_icp->n_check_resend++; 607 icp_rm_check_resend(xics, icp); 608 } 609 610 return check_too_hard(xics, this_icp); 611 } 612 613 int kvmppc_rm_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr) 614 { 615 union kvmppc_icp_state old_state, new_state; 616 struct kvmppc_xics *xics = vcpu->kvm->arch.xics; 617 struct kvmppc_icp *icp = vcpu->arch.icp; 618 u32 reject; 619 620 if (!xics || !xics->real_mode) 621 return H_TOO_HARD; 622 623 /* 624 * ICP State: Set_CPPR 625 * 626 * We can safely compare the new value with the current 627 * value outside of the transaction as the CPPR is only 628 * ever changed by the processor on itself 629 */ 630 if (cppr > icp->state.cppr) { 631 icp_rm_down_cppr(xics, icp, cppr); 632 goto bail; 633 } else if (cppr == icp->state.cppr) 634 return H_SUCCESS; 635 636 /* 637 * ICP State: Up_CPPR 638 * 639 * The processor is raising its priority, this can result 640 * in a rejection of a pending interrupt: 641 * 642 * ICP State: Reject_Current 643 * 644 * We can remove EE from the current processor, the update 645 * transaction will set it again if needed 646 */ 647 icp_rm_clr_vcpu_irq(icp->vcpu); 648 649 do { 650 old_state = new_state = READ_ONCE(icp->state); 651 652 reject = 0; 653 new_state.cppr = cppr; 654 655 if (cppr <= new_state.pending_pri) { 656 reject = new_state.xisr; 657 new_state.xisr = 0; 658 new_state.pending_pri = 0xff; 659 } 660 661 } while (!icp_rm_try_update(icp, old_state, new_state)); 662 663 /* 664 * Check for rejects. They are handled by doing a new delivery 665 * attempt (see comments in icp_rm_deliver_irq). 666 */ 667 if (reject && reject != XICS_IPI) { 668 icp->n_reject++; 669 icp_rm_deliver_irq(xics, icp, reject, false); 670 } 671 bail: 672 return check_too_hard(xics, icp); 673 } 674 675 static int ics_rm_eoi(struct kvm_vcpu *vcpu, u32 irq) 676 { 677 struct kvmppc_xics *xics = vcpu->kvm->arch.xics; 678 struct kvmppc_icp *icp = vcpu->arch.icp; 679 struct kvmppc_ics *ics; 680 struct ics_irq_state *state; 681 u16 src; 682 u32 pq_old, pq_new; 683 684 /* 685 * ICS EOI handling: For LSI, if P bit is still set, we need to 686 * resend it. 687 * 688 * For MSI, we move Q bit into P (and clear Q). If it is set, 689 * resend it. 690 */ 691 692 ics = kvmppc_xics_find_ics(xics, irq, &src); 693 if (!ics) 694 goto bail; 695 696 state = &ics->irq_state[src]; 697 698 if (state->lsi) 699 pq_new = state->pq_state; 700 else 701 do { 702 pq_old = state->pq_state; 703 pq_new = pq_old >> 1; 704 } while (cmpxchg(&state->pq_state, pq_old, pq_new) != pq_old); 705 706 if (pq_new & PQ_PRESENTED) 707 icp_rm_deliver_irq(xics, NULL, irq, false); 708 709 if (!hlist_empty(&vcpu->kvm->irq_ack_notifier_list)) { 710 icp->rm_action |= XICS_RM_NOTIFY_EOI; 711 icp->rm_eoied_irq = irq; 712 } 713 714 if (state->host_irq) { 715 ++vcpu->stat.pthru_all; 716 if (state->intr_cpu != -1) { 717 int pcpu = raw_smp_processor_id(); 718 719 pcpu = cpu_first_thread_sibling(pcpu); 720 ++vcpu->stat.pthru_host; 721 if (state->intr_cpu != pcpu) { 722 ++vcpu->stat.pthru_bad_aff; 723 xics_opal_set_server(state->host_irq, pcpu); 724 } 725 state->intr_cpu = -1; 726 } 727 } 728 729 bail: 730 return check_too_hard(xics, icp); 731 } 732 733 int kvmppc_rm_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr) 734 { 735 struct kvmppc_xics *xics = vcpu->kvm->arch.xics; 736 struct kvmppc_icp *icp = vcpu->arch.icp; 737 u32 irq = xirr & 0x00ffffff; 738 739 if (!xics || !xics->real_mode) 740 return H_TOO_HARD; 741 742 /* 743 * ICP State: EOI 744 * 745 * Note: If EOI is incorrectly used by SW to lower the CPPR 746 * value (ie more favored), we do not check for rejection of 747 * a pending interrupt, this is a SW error and PAPR specifies 748 * that we don't have to deal with it. 749 * 750 * The sending of an EOI to the ICS is handled after the 751 * CPPR update 752 * 753 * ICP State: Down_CPPR which we handle 754 * in a separate function as it's shared with H_CPPR. 755 */ 756 icp_rm_down_cppr(xics, icp, xirr >> 24); 757 758 /* IPIs have no EOI */ 759 if (irq == XICS_IPI) 760 return check_too_hard(xics, icp); 761 762 return ics_rm_eoi(vcpu, irq); 763 } 764 765 unsigned long eoi_rc; 766 767 static void icp_eoi(struct irq_chip *c, u32 hwirq, __be32 xirr, bool *again) 768 { 769 unsigned long xics_phys; 770 int64_t rc; 771 772 rc = pnv_opal_pci_msi_eoi(c, hwirq); 773 774 if (rc) 775 eoi_rc = rc; 776 777 iosync(); 778 779 /* EOI it */ 780 xics_phys = local_paca->kvm_hstate.xics_phys; 781 if (xics_phys) { 782 _stwcix(xics_phys + XICS_XIRR, xirr); 783 } else { 784 rc = opal_int_eoi(be32_to_cpu(xirr)); 785 *again = rc > 0; 786 } 787 } 788 789 static int xics_opal_set_server(unsigned int hw_irq, int server_cpu) 790 { 791 unsigned int mangle_cpu = get_hard_smp_processor_id(server_cpu) << 2; 792 793 return opal_set_xive(hw_irq, mangle_cpu, DEFAULT_PRIORITY); 794 } 795 796 /* 797 * Increment a per-CPU 32-bit unsigned integer variable. 798 * Safe to call in real-mode. Handles vmalloc'ed addresses 799 * 800 * ToDo: Make this work for any integral type 801 */ 802 803 static inline void this_cpu_inc_rm(unsigned int __percpu *addr) 804 { 805 unsigned long l; 806 unsigned int *raddr; 807 int cpu = smp_processor_id(); 808 809 raddr = per_cpu_ptr(addr, cpu); 810 l = (unsigned long)raddr; 811 812 if (REGION_ID(l) == VMALLOC_REGION_ID) { 813 l = vmalloc_to_phys(raddr); 814 raddr = (unsigned int *)l; 815 } 816 ++*raddr; 817 } 818 819 /* 820 * We don't try to update the flags in the irq_desc 'istate' field in 821 * here as would happen in the normal IRQ handling path for several reasons: 822 * - state flags represent internal IRQ state and are not expected to be 823 * updated outside the IRQ subsystem 824 * - more importantly, these are useful for edge triggered interrupts, 825 * IRQ probing, etc., but we are only handling MSI/MSIx interrupts here 826 * and these states shouldn't apply to us. 827 * 828 * However, we do update irq_stats - we somewhat duplicate the code in 829 * kstat_incr_irqs_this_cpu() for this since this function is defined 830 * in irq/internal.h which we don't want to include here. 831 * The only difference is that desc->kstat_irqs is an allocated per CPU 832 * variable and could have been vmalloc'ed, so we can't directly 833 * call __this_cpu_inc() on it. The kstat structure is a static 834 * per CPU variable and it should be accessible by real-mode KVM. 835 * 836 */ 837 static void kvmppc_rm_handle_irq_desc(struct irq_desc *desc) 838 { 839 this_cpu_inc_rm(desc->kstat_irqs); 840 __this_cpu_inc(kstat.irqs_sum); 841 } 842 843 long kvmppc_deliver_irq_passthru(struct kvm_vcpu *vcpu, 844 __be32 xirr, 845 struct kvmppc_irq_map *irq_map, 846 struct kvmppc_passthru_irqmap *pimap, 847 bool *again) 848 { 849 struct kvmppc_xics *xics; 850 struct kvmppc_icp *icp; 851 struct kvmppc_ics *ics; 852 struct ics_irq_state *state; 853 u32 irq; 854 u16 src; 855 u32 pq_old, pq_new; 856 857 irq = irq_map->v_hwirq; 858 xics = vcpu->kvm->arch.xics; 859 icp = vcpu->arch.icp; 860 861 kvmppc_rm_handle_irq_desc(irq_map->desc); 862 863 ics = kvmppc_xics_find_ics(xics, irq, &src); 864 if (!ics) 865 return 2; 866 867 state = &ics->irq_state[src]; 868 869 /* only MSIs register bypass producers, so it must be MSI here */ 870 do { 871 pq_old = state->pq_state; 872 pq_new = ((pq_old << 1) & 3) | PQ_PRESENTED; 873 } while (cmpxchg(&state->pq_state, pq_old, pq_new) != pq_old); 874 875 /* Test P=1, Q=0, this is the only case where we present */ 876 if (pq_new == PQ_PRESENTED) 877 icp_rm_deliver_irq(xics, icp, irq, false); 878 879 /* EOI the interrupt */ 880 icp_eoi(irq_desc_get_chip(irq_map->desc), irq_map->r_hwirq, xirr, 881 again); 882 883 if (check_too_hard(xics, icp) == H_TOO_HARD) 884 return 2; 885 else 886 return -2; 887 } 888 889 /* --- Non-real mode XICS-related built-in routines --- */ 890 891 /** 892 * Host Operations poked by RM KVM 893 */ 894 static void rm_host_ipi_action(int action, void *data) 895 { 896 switch (action) { 897 case XICS_RM_KICK_VCPU: 898 kvmppc_host_rm_ops_hv->vcpu_kick(data); 899 break; 900 default: 901 WARN(1, "Unexpected rm_action=%d data=%p\n", action, data); 902 break; 903 } 904 905 } 906 907 void kvmppc_xics_ipi_action(void) 908 { 909 int core; 910 unsigned int cpu = smp_processor_id(); 911 struct kvmppc_host_rm_core *rm_corep; 912 913 core = cpu >> threads_shift; 914 rm_corep = &kvmppc_host_rm_ops_hv->rm_core[core]; 915 916 if (rm_corep->rm_data) { 917 rm_host_ipi_action(rm_corep->rm_state.rm_action, 918 rm_corep->rm_data); 919 /* Order these stores against the real mode KVM */ 920 rm_corep->rm_data = NULL; 921 smp_wmb(); 922 rm_corep->rm_state.rm_action = 0; 923 } 924 } 925