1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
14 *
15 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
16 *
17 * Derived from book3s_interrupts.S, which is:
18 * Copyright SUSE Linux Products GmbH 2009
19 *
20 * Authors: Alexander Graf <agraf@suse.de>
21 */
22
23#include <asm/ppc_asm.h>
24#include <asm/kvm_asm.h>
25#include <asm/reg.h>
26#include <asm/page.h>
27#include <asm/asm-offsets.h>
28#include <asm/exception-64s.h>
29#include <asm/ppc-opcode.h>
30#include <asm/asm-compat.h>
31#include <asm/feature-fixups.h>
32
33/*****************************************************************************
34 *                                                                           *
35 *     Guest entry / exit code that is in kernel module memory (vmalloc)     *
36 *                                                                           *
37 ****************************************************************************/
38
39/* Registers:
40 *  none
41 */
42_GLOBAL(__kvmppc_vcore_entry)
43
44	/* Write correct stack frame */
45	mflr	r0
46	std	r0,PPC_LR_STKOFF(r1)
47
48	/* Save host state to the stack */
49	stdu	r1, -SWITCH_FRAME_SIZE(r1)
50
51	/* Save non-volatile registers (r14 - r31) and CR */
52	SAVE_NVGPRS(r1)
53	mfcr	r3
54	std	r3, _CCR(r1)
55
56	/* Save host DSCR */
57	mfspr	r3, SPRN_DSCR
58	std	r3, HSTATE_DSCR(r13)
59
60BEGIN_FTR_SECTION
61	/* Save host DABR */
62	mfspr	r3, SPRN_DABR
63	std	r3, HSTATE_DABR(r13)
64END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
65
66	/* Save host PMU registers */
67	bl	kvmhv_save_host_pmu
68
69	/*
70	 * Put whatever is in the decrementer into the
71	 * hypervisor decrementer.
72	 */
73BEGIN_FTR_SECTION
74	ld	r5, HSTATE_KVM_VCORE(r13)
75	ld	r6, VCORE_KVM(r5)
76	ld	r9, KVM_HOST_LPCR(r6)
77	andis.	r9, r9, LPCR_LD@h
78END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
79	mfspr	r8,SPRN_DEC
80	mftb	r7
81BEGIN_FTR_SECTION
82	/* On POWER9, don't sign-extend if host LPCR[LD] bit is set */
83	bne	32f
84END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
85	extsw	r8,r8
8632:	mtspr	SPRN_HDEC,r8
87	add	r8,r8,r7
88	std	r8,HSTATE_DECEXP(r13)
89
90	/* Jump to partition switch code */
91	bl	kvmppc_hv_entry_trampoline
92	nop
93
94/*
95 * We return here in virtual mode after the guest exits
96 * with something that we can't handle in real mode.
97 * Interrupts are still hard-disabled.
98 */
99
100	/*
101	 * Register usage at this point:
102	 *
103	 * R1       = host R1
104	 * R2       = host R2
105	 * R3       = trap number on this thread
106	 * R12      = exit handler id
107	 * R13      = PACA
108	 */
109
110	/* Restore non-volatile host registers (r14 - r31) and CR */
111	REST_NVGPRS(r1)
112	ld	r4, _CCR(r1)
113	mtcr	r4
114
115	addi    r1, r1, SWITCH_FRAME_SIZE
116	ld	r0, PPC_LR_STKOFF(r1)
117	mtlr	r0
118	blr
119
120_GLOBAL(kvmhv_save_host_pmu)
121BEGIN_FTR_SECTION
122	/* Work around P8 PMAE bug */
123	li	r3, -1
124	clrrdi	r3, r3, 10
125	mfspr	r8, SPRN_MMCR2
126	mtspr	SPRN_MMCR2, r3		/* freeze all counters using MMCR2 */
127	isync
128END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
129	li	r3, 1
130	sldi	r3, r3, 31		/* MMCR0_FC (freeze counters) bit */
131	mfspr	r7, SPRN_MMCR0		/* save MMCR0 */
132	mtspr	SPRN_MMCR0, r3		/* freeze all counters, disable interrupts */
133	mfspr	r6, SPRN_MMCRA
134	/* Clear MMCRA in order to disable SDAR updates */
135	li	r5, 0
136	mtspr	SPRN_MMCRA, r5
137	isync
138	lbz	r5, PACA_PMCINUSE(r13)	/* is the host using the PMU? */
139	cmpwi	r5, 0
140	beq	31f			/* skip if not */
141	mfspr	r5, SPRN_MMCR1
142	mfspr	r9, SPRN_SIAR
143	mfspr	r10, SPRN_SDAR
144	std	r7, HSTATE_MMCR0(r13)
145	std	r5, HSTATE_MMCR1(r13)
146	std	r6, HSTATE_MMCRA(r13)
147	std	r9, HSTATE_SIAR(r13)
148	std	r10, HSTATE_SDAR(r13)
149BEGIN_FTR_SECTION
150	mfspr	r9, SPRN_SIER
151	std	r8, HSTATE_MMCR2(r13)
152	std	r9, HSTATE_SIER(r13)
153END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
154	mfspr	r3, SPRN_PMC1
155	mfspr	r5, SPRN_PMC2
156	mfspr	r6, SPRN_PMC3
157	mfspr	r7, SPRN_PMC4
158	mfspr	r8, SPRN_PMC5
159	mfspr	r9, SPRN_PMC6
160	stw	r3, HSTATE_PMC1(r13)
161	stw	r5, HSTATE_PMC2(r13)
162	stw	r6, HSTATE_PMC3(r13)
163	stw	r7, HSTATE_PMC4(r13)
164	stw	r8, HSTATE_PMC5(r13)
165	stw	r9, HSTATE_PMC6(r13)
16631:	blr
167