1 /* 2 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License, version 2, as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/cpu.h> 10 #include <linux/kvm_host.h> 11 #include <linux/preempt.h> 12 #include <linux/export.h> 13 #include <linux/sched.h> 14 #include <linux/spinlock.h> 15 #include <linux/init.h> 16 #include <linux/memblock.h> 17 #include <linux/sizes.h> 18 #include <linux/cma.h> 19 #include <linux/bitops.h> 20 21 #include <asm/cputable.h> 22 #include <asm/kvm_ppc.h> 23 #include <asm/kvm_book3s.h> 24 #include <asm/archrandom.h> 25 #include <asm/xics.h> 26 #include <asm/xive.h> 27 #include <asm/dbell.h> 28 #include <asm/cputhreads.h> 29 #include <asm/io.h> 30 #include <asm/opal.h> 31 #include <asm/smp.h> 32 33 #define KVM_CMA_CHUNK_ORDER 18 34 35 /* 36 * Hash page table alignment on newer cpus(CPU_FTR_ARCH_206) 37 * should be power of 2. 38 */ 39 #define HPT_ALIGN_PAGES ((1 << 18) >> PAGE_SHIFT) /* 256k */ 40 /* 41 * By default we reserve 5% of memory for hash pagetable allocation. 42 */ 43 static unsigned long kvm_cma_resv_ratio = 5; 44 45 static struct cma *kvm_cma; 46 47 static int __init early_parse_kvm_cma_resv(char *p) 48 { 49 pr_debug("%s(%s)\n", __func__, p); 50 if (!p) 51 return -EINVAL; 52 return kstrtoul(p, 0, &kvm_cma_resv_ratio); 53 } 54 early_param("kvm_cma_resv_ratio", early_parse_kvm_cma_resv); 55 56 struct page *kvm_alloc_hpt_cma(unsigned long nr_pages) 57 { 58 VM_BUG_ON(order_base_2(nr_pages) < KVM_CMA_CHUNK_ORDER - PAGE_SHIFT); 59 60 return cma_alloc(kvm_cma, nr_pages, order_base_2(HPT_ALIGN_PAGES), 61 GFP_KERNEL); 62 } 63 EXPORT_SYMBOL_GPL(kvm_alloc_hpt_cma); 64 65 void kvm_free_hpt_cma(struct page *page, unsigned long nr_pages) 66 { 67 cma_release(kvm_cma, page, nr_pages); 68 } 69 EXPORT_SYMBOL_GPL(kvm_free_hpt_cma); 70 71 /** 72 * kvm_cma_reserve() - reserve area for kvm hash pagetable 73 * 74 * This function reserves memory from early allocator. It should be 75 * called by arch specific code once the memblock allocator 76 * has been activated and all other subsystems have already allocated/reserved 77 * memory. 78 */ 79 void __init kvm_cma_reserve(void) 80 { 81 unsigned long align_size; 82 struct memblock_region *reg; 83 phys_addr_t selected_size = 0; 84 85 /* 86 * We need CMA reservation only when we are in HV mode 87 */ 88 if (!cpu_has_feature(CPU_FTR_HVMODE)) 89 return; 90 /* 91 * We cannot use memblock_phys_mem_size() here, because 92 * memblock_analyze() has not been called yet. 93 */ 94 for_each_memblock(memory, reg) 95 selected_size += memblock_region_memory_end_pfn(reg) - 96 memblock_region_memory_base_pfn(reg); 97 98 selected_size = (selected_size * kvm_cma_resv_ratio / 100) << PAGE_SHIFT; 99 if (selected_size) { 100 pr_debug("%s: reserving %ld MiB for global area\n", __func__, 101 (unsigned long)selected_size / SZ_1M); 102 align_size = HPT_ALIGN_PAGES << PAGE_SHIFT; 103 cma_declare_contiguous(0, selected_size, 0, align_size, 104 KVM_CMA_CHUNK_ORDER - PAGE_SHIFT, false, &kvm_cma); 105 } 106 } 107 108 /* 109 * Real-mode H_CONFER implementation. 110 * We check if we are the only vcpu out of this virtual core 111 * still running in the guest and not ceded. If so, we pop up 112 * to the virtual-mode implementation; if not, just return to 113 * the guest. 114 */ 115 long int kvmppc_rm_h_confer(struct kvm_vcpu *vcpu, int target, 116 unsigned int yield_count) 117 { 118 struct kvmppc_vcore *vc = local_paca->kvm_hstate.kvm_vcore; 119 int ptid = local_paca->kvm_hstate.ptid; 120 int threads_running; 121 int threads_ceded; 122 int threads_conferring; 123 u64 stop = get_tb() + 10 * tb_ticks_per_usec; 124 int rv = H_SUCCESS; /* => don't yield */ 125 126 set_bit(ptid, &vc->conferring_threads); 127 while ((get_tb() < stop) && !VCORE_IS_EXITING(vc)) { 128 threads_running = VCORE_ENTRY_MAP(vc); 129 threads_ceded = vc->napping_threads; 130 threads_conferring = vc->conferring_threads; 131 if ((threads_ceded | threads_conferring) == threads_running) { 132 rv = H_TOO_HARD; /* => do yield */ 133 break; 134 } 135 } 136 clear_bit(ptid, &vc->conferring_threads); 137 return rv; 138 } 139 140 /* 141 * When running HV mode KVM we need to block certain operations while KVM VMs 142 * exist in the system. We use a counter of VMs to track this. 143 * 144 * One of the operations we need to block is onlining of secondaries, so we 145 * protect hv_vm_count with get/put_online_cpus(). 146 */ 147 static atomic_t hv_vm_count; 148 149 void kvm_hv_vm_activated(void) 150 { 151 get_online_cpus(); 152 atomic_inc(&hv_vm_count); 153 put_online_cpus(); 154 } 155 EXPORT_SYMBOL_GPL(kvm_hv_vm_activated); 156 157 void kvm_hv_vm_deactivated(void) 158 { 159 get_online_cpus(); 160 atomic_dec(&hv_vm_count); 161 put_online_cpus(); 162 } 163 EXPORT_SYMBOL_GPL(kvm_hv_vm_deactivated); 164 165 bool kvm_hv_mode_active(void) 166 { 167 return atomic_read(&hv_vm_count) != 0; 168 } 169 170 extern int hcall_real_table[], hcall_real_table_end[]; 171 172 int kvmppc_hcall_impl_hv_realmode(unsigned long cmd) 173 { 174 cmd /= 4; 175 if (cmd < hcall_real_table_end - hcall_real_table && 176 hcall_real_table[cmd]) 177 return 1; 178 179 return 0; 180 } 181 EXPORT_SYMBOL_GPL(kvmppc_hcall_impl_hv_realmode); 182 183 int kvmppc_hwrng_present(void) 184 { 185 return powernv_hwrng_present(); 186 } 187 EXPORT_SYMBOL_GPL(kvmppc_hwrng_present); 188 189 long kvmppc_h_random(struct kvm_vcpu *vcpu) 190 { 191 if (powernv_get_random_real_mode(&vcpu->arch.gpr[4])) 192 return H_SUCCESS; 193 194 return H_HARDWARE; 195 } 196 197 static inline void rm_writeb(unsigned long paddr, u8 val) 198 { 199 __asm__ __volatile__("stbcix %0,0,%1" 200 : : "r" (val), "r" (paddr) : "memory"); 201 } 202 203 /* 204 * Send an interrupt or message to another CPU. 205 * The caller needs to include any barrier needed to order writes 206 * to memory vs. the IPI/message. 207 */ 208 void kvmhv_rm_send_ipi(int cpu) 209 { 210 unsigned long xics_phys; 211 unsigned long msg = PPC_DBELL_TYPE(PPC_DBELL_SERVER); 212 213 /* On POWER9 we can use msgsnd for any destination cpu. */ 214 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 215 msg |= get_hard_smp_processor_id(cpu); 216 __asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg)); 217 return; 218 } 219 /* On POWER8 for IPIs to threads in the same core, use msgsnd. */ 220 if (cpu_has_feature(CPU_FTR_ARCH_207S) && 221 cpu_first_thread_sibling(cpu) == 222 cpu_first_thread_sibling(raw_smp_processor_id())) { 223 msg |= cpu_thread_in_core(cpu); 224 __asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg)); 225 return; 226 } 227 228 /* We should never reach this */ 229 if (WARN_ON_ONCE(xive_enabled())) 230 return; 231 232 /* Else poke the target with an IPI */ 233 xics_phys = paca[cpu].kvm_hstate.xics_phys; 234 if (xics_phys) 235 rm_writeb(xics_phys + XICS_MFRR, IPI_PRIORITY); 236 else 237 opal_int_set_mfrr(get_hard_smp_processor_id(cpu), IPI_PRIORITY); 238 } 239 240 /* 241 * The following functions are called from the assembly code 242 * in book3s_hv_rmhandlers.S. 243 */ 244 static void kvmhv_interrupt_vcore(struct kvmppc_vcore *vc, int active) 245 { 246 int cpu = vc->pcpu; 247 248 /* Order setting of exit map vs. msgsnd/IPI */ 249 smp_mb(); 250 for (; active; active >>= 1, ++cpu) 251 if (active & 1) 252 kvmhv_rm_send_ipi(cpu); 253 } 254 255 void kvmhv_commence_exit(int trap) 256 { 257 struct kvmppc_vcore *vc = local_paca->kvm_hstate.kvm_vcore; 258 int ptid = local_paca->kvm_hstate.ptid; 259 struct kvm_split_mode *sip = local_paca->kvm_hstate.kvm_split_mode; 260 int me, ee, i; 261 262 /* Set our bit in the threads-exiting-guest map in the 0xff00 263 bits of vcore->entry_exit_map */ 264 me = 0x100 << ptid; 265 do { 266 ee = vc->entry_exit_map; 267 } while (cmpxchg(&vc->entry_exit_map, ee, ee | me) != ee); 268 269 /* Are we the first here? */ 270 if ((ee >> 8) != 0) 271 return; 272 273 /* 274 * Trigger the other threads in this vcore to exit the guest. 275 * If this is a hypervisor decrementer interrupt then they 276 * will be already on their way out of the guest. 277 */ 278 if (trap != BOOK3S_INTERRUPT_HV_DECREMENTER) 279 kvmhv_interrupt_vcore(vc, ee & ~(1 << ptid)); 280 281 /* 282 * If we are doing dynamic micro-threading, interrupt the other 283 * subcores to pull them out of their guests too. 284 */ 285 if (!sip) 286 return; 287 288 for (i = 0; i < MAX_SUBCORES; ++i) { 289 vc = sip->master_vcs[i]; 290 if (!vc) 291 break; 292 do { 293 ee = vc->entry_exit_map; 294 /* Already asked to exit? */ 295 if ((ee >> 8) != 0) 296 break; 297 } while (cmpxchg(&vc->entry_exit_map, ee, 298 ee | VCORE_EXIT_REQ) != ee); 299 if ((ee >> 8) == 0) 300 kvmhv_interrupt_vcore(vc, ee); 301 } 302 } 303 304 struct kvmppc_host_rm_ops *kvmppc_host_rm_ops_hv; 305 EXPORT_SYMBOL_GPL(kvmppc_host_rm_ops_hv); 306 307 #ifdef CONFIG_KVM_XICS 308 static struct kvmppc_irq_map *get_irqmap(struct kvmppc_passthru_irqmap *pimap, 309 u32 xisr) 310 { 311 int i; 312 313 /* 314 * We access the mapped array here without a lock. That 315 * is safe because we never reduce the number of entries 316 * in the array and we never change the v_hwirq field of 317 * an entry once it is set. 318 * 319 * We have also carefully ordered the stores in the writer 320 * and the loads here in the reader, so that if we find a matching 321 * hwirq here, the associated GSI and irq_desc fields are valid. 322 */ 323 for (i = 0; i < pimap->n_mapped; i++) { 324 if (xisr == pimap->mapped[i].r_hwirq) { 325 /* 326 * Order subsequent reads in the caller to serialize 327 * with the writer. 328 */ 329 smp_rmb(); 330 return &pimap->mapped[i]; 331 } 332 } 333 return NULL; 334 } 335 336 /* 337 * If we have an interrupt that's not an IPI, check if we have a 338 * passthrough adapter and if so, check if this external interrupt 339 * is for the adapter. 340 * We will attempt to deliver the IRQ directly to the target VCPU's 341 * ICP, the virtual ICP (based on affinity - the xive value in ICS). 342 * 343 * If the delivery fails or if this is not for a passthrough adapter, 344 * return to the host to handle this interrupt. We earlier 345 * saved a copy of the XIRR in the PACA, it will be picked up by 346 * the host ICP driver. 347 */ 348 static int kvmppc_check_passthru(u32 xisr, __be32 xirr, bool *again) 349 { 350 struct kvmppc_passthru_irqmap *pimap; 351 struct kvmppc_irq_map *irq_map; 352 struct kvm_vcpu *vcpu; 353 354 vcpu = local_paca->kvm_hstate.kvm_vcpu; 355 if (!vcpu) 356 return 1; 357 pimap = kvmppc_get_passthru_irqmap(vcpu->kvm); 358 if (!pimap) 359 return 1; 360 irq_map = get_irqmap(pimap, xisr); 361 if (!irq_map) 362 return 1; 363 364 /* We're handling this interrupt, generic code doesn't need to */ 365 local_paca->kvm_hstate.saved_xirr = 0; 366 367 return kvmppc_deliver_irq_passthru(vcpu, xirr, irq_map, pimap, again); 368 } 369 370 #else 371 static inline int kvmppc_check_passthru(u32 xisr, __be32 xirr, bool *again) 372 { 373 return 1; 374 } 375 #endif 376 377 /* 378 * Determine what sort of external interrupt is pending (if any). 379 * Returns: 380 * 0 if no interrupt is pending 381 * 1 if an interrupt is pending that needs to be handled by the host 382 * 2 Passthrough that needs completion in the host 383 * -1 if there was a guest wakeup IPI (which has now been cleared) 384 * -2 if there is PCI passthrough external interrupt that was handled 385 */ 386 static long kvmppc_read_one_intr(bool *again); 387 388 long kvmppc_read_intr(void) 389 { 390 long ret = 0; 391 long rc; 392 bool again; 393 394 if (xive_enabled()) 395 return 1; 396 397 do { 398 again = false; 399 rc = kvmppc_read_one_intr(&again); 400 if (rc && (ret == 0 || rc > ret)) 401 ret = rc; 402 } while (again); 403 return ret; 404 } 405 406 static long kvmppc_read_one_intr(bool *again) 407 { 408 unsigned long xics_phys; 409 u32 h_xirr; 410 __be32 xirr; 411 u32 xisr; 412 u8 host_ipi; 413 int64_t rc; 414 415 /* see if a host IPI is pending */ 416 host_ipi = local_paca->kvm_hstate.host_ipi; 417 if (host_ipi) 418 return 1; 419 420 /* Now read the interrupt from the ICP */ 421 xics_phys = local_paca->kvm_hstate.xics_phys; 422 rc = 0; 423 if (!xics_phys) 424 rc = opal_int_get_xirr(&xirr, false); 425 else 426 xirr = _lwzcix(xics_phys + XICS_XIRR); 427 if (rc < 0) 428 return 1; 429 430 /* 431 * Save XIRR for later. Since we get control in reverse endian 432 * on LE systems, save it byte reversed and fetch it back in 433 * host endian. Note that xirr is the value read from the 434 * XIRR register, while h_xirr is the host endian version. 435 */ 436 h_xirr = be32_to_cpu(xirr); 437 local_paca->kvm_hstate.saved_xirr = h_xirr; 438 xisr = h_xirr & 0xffffff; 439 /* 440 * Ensure that the store/load complete to guarantee all side 441 * effects of loading from XIRR has completed 442 */ 443 smp_mb(); 444 445 /* if nothing pending in the ICP */ 446 if (!xisr) 447 return 0; 448 449 /* We found something in the ICP... 450 * 451 * If it is an IPI, clear the MFRR and EOI it. 452 */ 453 if (xisr == XICS_IPI) { 454 rc = 0; 455 if (xics_phys) { 456 _stbcix(xics_phys + XICS_MFRR, 0xff); 457 _stwcix(xics_phys + XICS_XIRR, xirr); 458 } else { 459 opal_int_set_mfrr(hard_smp_processor_id(), 0xff); 460 rc = opal_int_eoi(h_xirr); 461 } 462 /* If rc > 0, there is another interrupt pending */ 463 *again = rc > 0; 464 465 /* 466 * Need to ensure side effects of above stores 467 * complete before proceeding. 468 */ 469 smp_mb(); 470 471 /* 472 * We need to re-check host IPI now in case it got set in the 473 * meantime. If it's clear, we bounce the interrupt to the 474 * guest 475 */ 476 host_ipi = local_paca->kvm_hstate.host_ipi; 477 if (unlikely(host_ipi != 0)) { 478 /* We raced with the host, 479 * we need to resend that IPI, bummer 480 */ 481 if (xics_phys) 482 _stbcix(xics_phys + XICS_MFRR, IPI_PRIORITY); 483 else 484 opal_int_set_mfrr(hard_smp_processor_id(), 485 IPI_PRIORITY); 486 /* Let side effects complete */ 487 smp_mb(); 488 return 1; 489 } 490 491 /* OK, it's an IPI for us */ 492 local_paca->kvm_hstate.saved_xirr = 0; 493 return -1; 494 } 495 496 return kvmppc_check_passthru(xisr, xirr, again); 497 } 498