1 /* 2 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License, version 2, as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/cpu.h> 10 #include <linux/kvm_host.h> 11 #include <linux/preempt.h> 12 #include <linux/export.h> 13 #include <linux/sched.h> 14 #include <linux/spinlock.h> 15 #include <linux/init.h> 16 #include <linux/memblock.h> 17 #include <linux/sizes.h> 18 #include <linux/cma.h> 19 #include <linux/bitops.h> 20 21 #include <asm/cputable.h> 22 #include <asm/kvm_ppc.h> 23 #include <asm/kvm_book3s.h> 24 #include <asm/archrandom.h> 25 #include <asm/xics.h> 26 #include <asm/xive.h> 27 #include <asm/dbell.h> 28 #include <asm/cputhreads.h> 29 #include <asm/io.h> 30 #include <asm/opal.h> 31 #include <asm/smp.h> 32 33 #define KVM_CMA_CHUNK_ORDER 18 34 35 #include "book3s_xics.h" 36 #include "book3s_xive.h" 37 38 /* 39 * The XIVE module will populate these when it loads 40 */ 41 unsigned long (*__xive_vm_h_xirr)(struct kvm_vcpu *vcpu); 42 unsigned long (*__xive_vm_h_ipoll)(struct kvm_vcpu *vcpu, unsigned long server); 43 int (*__xive_vm_h_ipi)(struct kvm_vcpu *vcpu, unsigned long server, 44 unsigned long mfrr); 45 int (*__xive_vm_h_cppr)(struct kvm_vcpu *vcpu, unsigned long cppr); 46 int (*__xive_vm_h_eoi)(struct kvm_vcpu *vcpu, unsigned long xirr); 47 EXPORT_SYMBOL_GPL(__xive_vm_h_xirr); 48 EXPORT_SYMBOL_GPL(__xive_vm_h_ipoll); 49 EXPORT_SYMBOL_GPL(__xive_vm_h_ipi); 50 EXPORT_SYMBOL_GPL(__xive_vm_h_cppr); 51 EXPORT_SYMBOL_GPL(__xive_vm_h_eoi); 52 53 /* 54 * Hash page table alignment on newer cpus(CPU_FTR_ARCH_206) 55 * should be power of 2. 56 */ 57 #define HPT_ALIGN_PAGES ((1 << 18) >> PAGE_SHIFT) /* 256k */ 58 /* 59 * By default we reserve 5% of memory for hash pagetable allocation. 60 */ 61 static unsigned long kvm_cma_resv_ratio = 5; 62 63 static struct cma *kvm_cma; 64 65 static int __init early_parse_kvm_cma_resv(char *p) 66 { 67 pr_debug("%s(%s)\n", __func__, p); 68 if (!p) 69 return -EINVAL; 70 return kstrtoul(p, 0, &kvm_cma_resv_ratio); 71 } 72 early_param("kvm_cma_resv_ratio", early_parse_kvm_cma_resv); 73 74 struct page *kvm_alloc_hpt_cma(unsigned long nr_pages) 75 { 76 VM_BUG_ON(order_base_2(nr_pages) < KVM_CMA_CHUNK_ORDER - PAGE_SHIFT); 77 78 return cma_alloc(kvm_cma, nr_pages, order_base_2(HPT_ALIGN_PAGES), 79 GFP_KERNEL); 80 } 81 EXPORT_SYMBOL_GPL(kvm_alloc_hpt_cma); 82 83 void kvm_free_hpt_cma(struct page *page, unsigned long nr_pages) 84 { 85 cma_release(kvm_cma, page, nr_pages); 86 } 87 EXPORT_SYMBOL_GPL(kvm_free_hpt_cma); 88 89 /** 90 * kvm_cma_reserve() - reserve area for kvm hash pagetable 91 * 92 * This function reserves memory from early allocator. It should be 93 * called by arch specific code once the memblock allocator 94 * has been activated and all other subsystems have already allocated/reserved 95 * memory. 96 */ 97 void __init kvm_cma_reserve(void) 98 { 99 unsigned long align_size; 100 struct memblock_region *reg; 101 phys_addr_t selected_size = 0; 102 103 /* 104 * We need CMA reservation only when we are in HV mode 105 */ 106 if (!cpu_has_feature(CPU_FTR_HVMODE)) 107 return; 108 /* 109 * We cannot use memblock_phys_mem_size() here, because 110 * memblock_analyze() has not been called yet. 111 */ 112 for_each_memblock(memory, reg) 113 selected_size += memblock_region_memory_end_pfn(reg) - 114 memblock_region_memory_base_pfn(reg); 115 116 selected_size = (selected_size * kvm_cma_resv_ratio / 100) << PAGE_SHIFT; 117 if (selected_size) { 118 pr_debug("%s: reserving %ld MiB for global area\n", __func__, 119 (unsigned long)selected_size / SZ_1M); 120 align_size = HPT_ALIGN_PAGES << PAGE_SHIFT; 121 cma_declare_contiguous(0, selected_size, 0, align_size, 122 KVM_CMA_CHUNK_ORDER - PAGE_SHIFT, false, "kvm_cma", 123 &kvm_cma); 124 } 125 } 126 127 /* 128 * Real-mode H_CONFER implementation. 129 * We check if we are the only vcpu out of this virtual core 130 * still running in the guest and not ceded. If so, we pop up 131 * to the virtual-mode implementation; if not, just return to 132 * the guest. 133 */ 134 long int kvmppc_rm_h_confer(struct kvm_vcpu *vcpu, int target, 135 unsigned int yield_count) 136 { 137 struct kvmppc_vcore *vc = local_paca->kvm_hstate.kvm_vcore; 138 int ptid = local_paca->kvm_hstate.ptid; 139 int threads_running; 140 int threads_ceded; 141 int threads_conferring; 142 u64 stop = get_tb() + 10 * tb_ticks_per_usec; 143 int rv = H_SUCCESS; /* => don't yield */ 144 145 set_bit(ptid, &vc->conferring_threads); 146 while ((get_tb() < stop) && !VCORE_IS_EXITING(vc)) { 147 threads_running = VCORE_ENTRY_MAP(vc); 148 threads_ceded = vc->napping_threads; 149 threads_conferring = vc->conferring_threads; 150 if ((threads_ceded | threads_conferring) == threads_running) { 151 rv = H_TOO_HARD; /* => do yield */ 152 break; 153 } 154 } 155 clear_bit(ptid, &vc->conferring_threads); 156 return rv; 157 } 158 159 /* 160 * When running HV mode KVM we need to block certain operations while KVM VMs 161 * exist in the system. We use a counter of VMs to track this. 162 * 163 * One of the operations we need to block is onlining of secondaries, so we 164 * protect hv_vm_count with get/put_online_cpus(). 165 */ 166 static atomic_t hv_vm_count; 167 168 void kvm_hv_vm_activated(void) 169 { 170 get_online_cpus(); 171 atomic_inc(&hv_vm_count); 172 put_online_cpus(); 173 } 174 EXPORT_SYMBOL_GPL(kvm_hv_vm_activated); 175 176 void kvm_hv_vm_deactivated(void) 177 { 178 get_online_cpus(); 179 atomic_dec(&hv_vm_count); 180 put_online_cpus(); 181 } 182 EXPORT_SYMBOL_GPL(kvm_hv_vm_deactivated); 183 184 bool kvm_hv_mode_active(void) 185 { 186 return atomic_read(&hv_vm_count) != 0; 187 } 188 189 extern int hcall_real_table[], hcall_real_table_end[]; 190 191 int kvmppc_hcall_impl_hv_realmode(unsigned long cmd) 192 { 193 cmd /= 4; 194 if (cmd < hcall_real_table_end - hcall_real_table && 195 hcall_real_table[cmd]) 196 return 1; 197 198 return 0; 199 } 200 EXPORT_SYMBOL_GPL(kvmppc_hcall_impl_hv_realmode); 201 202 int kvmppc_hwrng_present(void) 203 { 204 return powernv_hwrng_present(); 205 } 206 EXPORT_SYMBOL_GPL(kvmppc_hwrng_present); 207 208 long kvmppc_h_random(struct kvm_vcpu *vcpu) 209 { 210 int r; 211 212 /* Only need to do the expensive mfmsr() on radix */ 213 if (kvm_is_radix(vcpu->kvm) && (mfmsr() & MSR_IR)) 214 r = powernv_get_random_long(&vcpu->arch.regs.gpr[4]); 215 else 216 r = powernv_get_random_real_mode(&vcpu->arch.regs.gpr[4]); 217 if (r) 218 return H_SUCCESS; 219 220 return H_HARDWARE; 221 } 222 223 /* 224 * Send an interrupt or message to another CPU. 225 * The caller needs to include any barrier needed to order writes 226 * to memory vs. the IPI/message. 227 */ 228 void kvmhv_rm_send_ipi(int cpu) 229 { 230 void __iomem *xics_phys; 231 unsigned long msg = PPC_DBELL_TYPE(PPC_DBELL_SERVER); 232 233 /* On POWER9 we can use msgsnd for any destination cpu. */ 234 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 235 msg |= get_hard_smp_processor_id(cpu); 236 __asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg)); 237 return; 238 } 239 240 /* On POWER8 for IPIs to threads in the same core, use msgsnd. */ 241 if (cpu_has_feature(CPU_FTR_ARCH_207S) && 242 cpu_first_thread_sibling(cpu) == 243 cpu_first_thread_sibling(raw_smp_processor_id())) { 244 msg |= cpu_thread_in_core(cpu); 245 __asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg)); 246 return; 247 } 248 249 /* We should never reach this */ 250 if (WARN_ON_ONCE(xive_enabled())) 251 return; 252 253 /* Else poke the target with an IPI */ 254 xics_phys = paca_ptrs[cpu]->kvm_hstate.xics_phys; 255 if (xics_phys) 256 __raw_rm_writeb(IPI_PRIORITY, xics_phys + XICS_MFRR); 257 else 258 opal_int_set_mfrr(get_hard_smp_processor_id(cpu), IPI_PRIORITY); 259 } 260 261 /* 262 * The following functions are called from the assembly code 263 * in book3s_hv_rmhandlers.S. 264 */ 265 static void kvmhv_interrupt_vcore(struct kvmppc_vcore *vc, int active) 266 { 267 int cpu = vc->pcpu; 268 269 /* Order setting of exit map vs. msgsnd/IPI */ 270 smp_mb(); 271 for (; active; active >>= 1, ++cpu) 272 if (active & 1) 273 kvmhv_rm_send_ipi(cpu); 274 } 275 276 void kvmhv_commence_exit(int trap) 277 { 278 struct kvmppc_vcore *vc = local_paca->kvm_hstate.kvm_vcore; 279 int ptid = local_paca->kvm_hstate.ptid; 280 struct kvm_split_mode *sip = local_paca->kvm_hstate.kvm_split_mode; 281 int me, ee, i, t; 282 int cpu0; 283 284 /* Set our bit in the threads-exiting-guest map in the 0xff00 285 bits of vcore->entry_exit_map */ 286 me = 0x100 << ptid; 287 do { 288 ee = vc->entry_exit_map; 289 } while (cmpxchg(&vc->entry_exit_map, ee, ee | me) != ee); 290 291 /* Are we the first here? */ 292 if ((ee >> 8) != 0) 293 return; 294 295 /* 296 * Trigger the other threads in this vcore to exit the guest. 297 * If this is a hypervisor decrementer interrupt then they 298 * will be already on their way out of the guest. 299 */ 300 if (trap != BOOK3S_INTERRUPT_HV_DECREMENTER) 301 kvmhv_interrupt_vcore(vc, ee & ~(1 << ptid)); 302 303 /* 304 * If we are doing dynamic micro-threading, interrupt the other 305 * subcores to pull them out of their guests too. 306 */ 307 if (!sip) 308 return; 309 310 for (i = 0; i < MAX_SUBCORES; ++i) { 311 vc = sip->vc[i]; 312 if (!vc) 313 break; 314 do { 315 ee = vc->entry_exit_map; 316 /* Already asked to exit? */ 317 if ((ee >> 8) != 0) 318 break; 319 } while (cmpxchg(&vc->entry_exit_map, ee, 320 ee | VCORE_EXIT_REQ) != ee); 321 if ((ee >> 8) == 0) 322 kvmhv_interrupt_vcore(vc, ee); 323 } 324 325 /* 326 * On POWER9 when running a HPT guest on a radix host (sip != NULL), 327 * we have to interrupt inactive CPU threads to get them to 328 * restore the host LPCR value. 329 */ 330 if (sip->lpcr_req) { 331 if (cmpxchg(&sip->do_restore, 0, 1) == 0) { 332 vc = local_paca->kvm_hstate.kvm_vcore; 333 cpu0 = vc->pcpu + ptid - local_paca->kvm_hstate.tid; 334 for (t = 1; t < threads_per_core; ++t) { 335 if (sip->napped[t]) 336 kvmhv_rm_send_ipi(cpu0 + t); 337 } 338 } 339 } 340 } 341 342 struct kvmppc_host_rm_ops *kvmppc_host_rm_ops_hv; 343 EXPORT_SYMBOL_GPL(kvmppc_host_rm_ops_hv); 344 345 #ifdef CONFIG_KVM_XICS 346 static struct kvmppc_irq_map *get_irqmap(struct kvmppc_passthru_irqmap *pimap, 347 u32 xisr) 348 { 349 int i; 350 351 /* 352 * We access the mapped array here without a lock. That 353 * is safe because we never reduce the number of entries 354 * in the array and we never change the v_hwirq field of 355 * an entry once it is set. 356 * 357 * We have also carefully ordered the stores in the writer 358 * and the loads here in the reader, so that if we find a matching 359 * hwirq here, the associated GSI and irq_desc fields are valid. 360 */ 361 for (i = 0; i < pimap->n_mapped; i++) { 362 if (xisr == pimap->mapped[i].r_hwirq) { 363 /* 364 * Order subsequent reads in the caller to serialize 365 * with the writer. 366 */ 367 smp_rmb(); 368 return &pimap->mapped[i]; 369 } 370 } 371 return NULL; 372 } 373 374 /* 375 * If we have an interrupt that's not an IPI, check if we have a 376 * passthrough adapter and if so, check if this external interrupt 377 * is for the adapter. 378 * We will attempt to deliver the IRQ directly to the target VCPU's 379 * ICP, the virtual ICP (based on affinity - the xive value in ICS). 380 * 381 * If the delivery fails or if this is not for a passthrough adapter, 382 * return to the host to handle this interrupt. We earlier 383 * saved a copy of the XIRR in the PACA, it will be picked up by 384 * the host ICP driver. 385 */ 386 static int kvmppc_check_passthru(u32 xisr, __be32 xirr, bool *again) 387 { 388 struct kvmppc_passthru_irqmap *pimap; 389 struct kvmppc_irq_map *irq_map; 390 struct kvm_vcpu *vcpu; 391 392 vcpu = local_paca->kvm_hstate.kvm_vcpu; 393 if (!vcpu) 394 return 1; 395 pimap = kvmppc_get_passthru_irqmap(vcpu->kvm); 396 if (!pimap) 397 return 1; 398 irq_map = get_irqmap(pimap, xisr); 399 if (!irq_map) 400 return 1; 401 402 /* We're handling this interrupt, generic code doesn't need to */ 403 local_paca->kvm_hstate.saved_xirr = 0; 404 405 return kvmppc_deliver_irq_passthru(vcpu, xirr, irq_map, pimap, again); 406 } 407 408 #else 409 static inline int kvmppc_check_passthru(u32 xisr, __be32 xirr, bool *again) 410 { 411 return 1; 412 } 413 #endif 414 415 /* 416 * Determine what sort of external interrupt is pending (if any). 417 * Returns: 418 * 0 if no interrupt is pending 419 * 1 if an interrupt is pending that needs to be handled by the host 420 * 2 Passthrough that needs completion in the host 421 * -1 if there was a guest wakeup IPI (which has now been cleared) 422 * -2 if there is PCI passthrough external interrupt that was handled 423 */ 424 static long kvmppc_read_one_intr(bool *again); 425 426 long kvmppc_read_intr(void) 427 { 428 long ret = 0; 429 long rc; 430 bool again; 431 432 if (xive_enabled()) 433 return 1; 434 435 do { 436 again = false; 437 rc = kvmppc_read_one_intr(&again); 438 if (rc && (ret == 0 || rc > ret)) 439 ret = rc; 440 } while (again); 441 return ret; 442 } 443 444 static long kvmppc_read_one_intr(bool *again) 445 { 446 void __iomem *xics_phys; 447 u32 h_xirr; 448 __be32 xirr; 449 u32 xisr; 450 u8 host_ipi; 451 int64_t rc; 452 453 if (xive_enabled()) 454 return 1; 455 456 /* see if a host IPI is pending */ 457 host_ipi = local_paca->kvm_hstate.host_ipi; 458 if (host_ipi) 459 return 1; 460 461 /* Now read the interrupt from the ICP */ 462 xics_phys = local_paca->kvm_hstate.xics_phys; 463 rc = 0; 464 if (!xics_phys) 465 rc = opal_int_get_xirr(&xirr, false); 466 else 467 xirr = __raw_rm_readl(xics_phys + XICS_XIRR); 468 if (rc < 0) 469 return 1; 470 471 /* 472 * Save XIRR for later. Since we get control in reverse endian 473 * on LE systems, save it byte reversed and fetch it back in 474 * host endian. Note that xirr is the value read from the 475 * XIRR register, while h_xirr is the host endian version. 476 */ 477 h_xirr = be32_to_cpu(xirr); 478 local_paca->kvm_hstate.saved_xirr = h_xirr; 479 xisr = h_xirr & 0xffffff; 480 /* 481 * Ensure that the store/load complete to guarantee all side 482 * effects of loading from XIRR has completed 483 */ 484 smp_mb(); 485 486 /* if nothing pending in the ICP */ 487 if (!xisr) 488 return 0; 489 490 /* We found something in the ICP... 491 * 492 * If it is an IPI, clear the MFRR and EOI it. 493 */ 494 if (xisr == XICS_IPI) { 495 rc = 0; 496 if (xics_phys) { 497 __raw_rm_writeb(0xff, xics_phys + XICS_MFRR); 498 __raw_rm_writel(xirr, xics_phys + XICS_XIRR); 499 } else { 500 opal_int_set_mfrr(hard_smp_processor_id(), 0xff); 501 rc = opal_int_eoi(h_xirr); 502 } 503 /* If rc > 0, there is another interrupt pending */ 504 *again = rc > 0; 505 506 /* 507 * Need to ensure side effects of above stores 508 * complete before proceeding. 509 */ 510 smp_mb(); 511 512 /* 513 * We need to re-check host IPI now in case it got set in the 514 * meantime. If it's clear, we bounce the interrupt to the 515 * guest 516 */ 517 host_ipi = local_paca->kvm_hstate.host_ipi; 518 if (unlikely(host_ipi != 0)) { 519 /* We raced with the host, 520 * we need to resend that IPI, bummer 521 */ 522 if (xics_phys) 523 __raw_rm_writeb(IPI_PRIORITY, 524 xics_phys + XICS_MFRR); 525 else 526 opal_int_set_mfrr(hard_smp_processor_id(), 527 IPI_PRIORITY); 528 /* Let side effects complete */ 529 smp_mb(); 530 return 1; 531 } 532 533 /* OK, it's an IPI for us */ 534 local_paca->kvm_hstate.saved_xirr = 0; 535 return -1; 536 } 537 538 return kvmppc_check_passthru(xisr, xirr, again); 539 } 540 541 #ifdef CONFIG_KVM_XICS 542 static inline bool is_rm(void) 543 { 544 return !(mfmsr() & MSR_DR); 545 } 546 547 unsigned long kvmppc_rm_h_xirr(struct kvm_vcpu *vcpu) 548 { 549 if (!kvmppc_xics_enabled(vcpu)) 550 return H_TOO_HARD; 551 if (xive_enabled()) { 552 if (is_rm()) 553 return xive_rm_h_xirr(vcpu); 554 if (unlikely(!__xive_vm_h_xirr)) 555 return H_NOT_AVAILABLE; 556 return __xive_vm_h_xirr(vcpu); 557 } else 558 return xics_rm_h_xirr(vcpu); 559 } 560 561 unsigned long kvmppc_rm_h_xirr_x(struct kvm_vcpu *vcpu) 562 { 563 if (!kvmppc_xics_enabled(vcpu)) 564 return H_TOO_HARD; 565 vcpu->arch.regs.gpr[5] = get_tb(); 566 if (xive_enabled()) { 567 if (is_rm()) 568 return xive_rm_h_xirr(vcpu); 569 if (unlikely(!__xive_vm_h_xirr)) 570 return H_NOT_AVAILABLE; 571 return __xive_vm_h_xirr(vcpu); 572 } else 573 return xics_rm_h_xirr(vcpu); 574 } 575 576 unsigned long kvmppc_rm_h_ipoll(struct kvm_vcpu *vcpu, unsigned long server) 577 { 578 if (!kvmppc_xics_enabled(vcpu)) 579 return H_TOO_HARD; 580 if (xive_enabled()) { 581 if (is_rm()) 582 return xive_rm_h_ipoll(vcpu, server); 583 if (unlikely(!__xive_vm_h_ipoll)) 584 return H_NOT_AVAILABLE; 585 return __xive_vm_h_ipoll(vcpu, server); 586 } else 587 return H_TOO_HARD; 588 } 589 590 int kvmppc_rm_h_ipi(struct kvm_vcpu *vcpu, unsigned long server, 591 unsigned long mfrr) 592 { 593 if (!kvmppc_xics_enabled(vcpu)) 594 return H_TOO_HARD; 595 if (xive_enabled()) { 596 if (is_rm()) 597 return xive_rm_h_ipi(vcpu, server, mfrr); 598 if (unlikely(!__xive_vm_h_ipi)) 599 return H_NOT_AVAILABLE; 600 return __xive_vm_h_ipi(vcpu, server, mfrr); 601 } else 602 return xics_rm_h_ipi(vcpu, server, mfrr); 603 } 604 605 int kvmppc_rm_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr) 606 { 607 if (!kvmppc_xics_enabled(vcpu)) 608 return H_TOO_HARD; 609 if (xive_enabled()) { 610 if (is_rm()) 611 return xive_rm_h_cppr(vcpu, cppr); 612 if (unlikely(!__xive_vm_h_cppr)) 613 return H_NOT_AVAILABLE; 614 return __xive_vm_h_cppr(vcpu, cppr); 615 } else 616 return xics_rm_h_cppr(vcpu, cppr); 617 } 618 619 int kvmppc_rm_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr) 620 { 621 if (!kvmppc_xics_enabled(vcpu)) 622 return H_TOO_HARD; 623 if (xive_enabled()) { 624 if (is_rm()) 625 return xive_rm_h_eoi(vcpu, xirr); 626 if (unlikely(!__xive_vm_h_eoi)) 627 return H_NOT_AVAILABLE; 628 return __xive_vm_h_eoi(vcpu, xirr); 629 } else 630 return xics_rm_h_eoi(vcpu, xirr); 631 } 632 #endif /* CONFIG_KVM_XICS */ 633 634 void kvmppc_bad_interrupt(struct pt_regs *regs) 635 { 636 die("Bad interrupt in KVM entry/exit code", regs, SIGABRT); 637 panic("Bad KVM trap"); 638 } 639 640 /* 641 * Functions used to switch LPCR HR and UPRT bits on all threads 642 * when entering and exiting HPT guests on a radix host. 643 */ 644 645 #define PHASE_REALMODE 1 /* in real mode */ 646 #define PHASE_SET_LPCR 2 /* have set LPCR */ 647 #define PHASE_OUT_OF_GUEST 4 /* have finished executing in guest */ 648 #define PHASE_RESET_LPCR 8 /* have reset LPCR to host value */ 649 650 #define ALL(p) (((p) << 24) | ((p) << 16) | ((p) << 8) | (p)) 651 652 static void wait_for_sync(struct kvm_split_mode *sip, int phase) 653 { 654 int thr = local_paca->kvm_hstate.tid; 655 656 sip->lpcr_sync.phase[thr] |= phase; 657 phase = ALL(phase); 658 while ((sip->lpcr_sync.allphases & phase) != phase) { 659 HMT_low(); 660 barrier(); 661 } 662 HMT_medium(); 663 } 664 665 void kvmhv_p9_set_lpcr(struct kvm_split_mode *sip) 666 { 667 unsigned long rb, set; 668 669 /* wait for every other thread to get to real mode */ 670 wait_for_sync(sip, PHASE_REALMODE); 671 672 /* Set LPCR and LPIDR */ 673 mtspr(SPRN_LPCR, sip->lpcr_req); 674 mtspr(SPRN_LPID, sip->lpidr_req); 675 isync(); 676 677 /* Invalidate the TLB on thread 0 */ 678 if (local_paca->kvm_hstate.tid == 0) { 679 sip->do_set = 0; 680 asm volatile("ptesync" : : : "memory"); 681 for (set = 0; set < POWER9_TLB_SETS_RADIX; ++set) { 682 rb = TLBIEL_INVAL_SET_LPID + 683 (set << TLBIEL_INVAL_SET_SHIFT); 684 asm volatile(PPC_TLBIEL(%0, %1, 0, 0, 0) : : 685 "r" (rb), "r" (0)); 686 } 687 asm volatile("ptesync" : : : "memory"); 688 } 689 690 /* indicate that we have done so and wait for others */ 691 wait_for_sync(sip, PHASE_SET_LPCR); 692 /* order read of sip->lpcr_sync.allphases vs. sip->do_set */ 693 smp_rmb(); 694 } 695 696 /* 697 * Called when a thread that has been in the guest needs 698 * to reload the host LPCR value - but only on POWER9 when 699 * running a HPT guest on a radix host. 700 */ 701 void kvmhv_p9_restore_lpcr(struct kvm_split_mode *sip) 702 { 703 /* we're out of the guest... */ 704 wait_for_sync(sip, PHASE_OUT_OF_GUEST); 705 706 mtspr(SPRN_LPID, 0); 707 mtspr(SPRN_LPCR, sip->host_lpcr); 708 isync(); 709 710 if (local_paca->kvm_hstate.tid == 0) { 711 sip->do_restore = 0; 712 smp_wmb(); /* order store of do_restore vs. phase */ 713 } 714 715 wait_for_sync(sip, PHASE_RESET_LPCR); 716 smp_mb(); 717 local_paca->kvm_hstate.kvm_split_mode = NULL; 718 } 719