1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2aa04b4ccSPaul Mackerras /* 3aa04b4ccSPaul Mackerras * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com> 4aa04b4ccSPaul Mackerras */ 5aa04b4ccSPaul Mackerras 6441c19c8SMichael Ellerman #include <linux/cpu.h> 7aa04b4ccSPaul Mackerras #include <linux/kvm_host.h> 8aa04b4ccSPaul Mackerras #include <linux/preempt.h> 966b15db6SPaul Gortmaker #include <linux/export.h> 10aa04b4ccSPaul Mackerras #include <linux/sched.h> 11aa04b4ccSPaul Mackerras #include <linux/spinlock.h> 12aa04b4ccSPaul Mackerras #include <linux/init.h> 13fa61a4e3SAneesh Kumar K.V #include <linux/memblock.h> 14fa61a4e3SAneesh Kumar K.V #include <linux/sizes.h> 15fc95ca72SJoonsoo Kim #include <linux/cma.h> 1690fd09f8SSam Bobroff #include <linux/bitops.h> 17aa04b4ccSPaul Mackerras 187c1bd80cSNicholas Piggin #include <asm/asm-prototypes.h> 19aa04b4ccSPaul Mackerras #include <asm/cputable.h> 203a96570fSNicholas Piggin #include <asm/interrupt.h> 21aa04b4ccSPaul Mackerras #include <asm/kvm_ppc.h> 22aa04b4ccSPaul Mackerras #include <asm/kvm_book3s.h> 23e928e9cbSMichael Ellerman #include <asm/archrandom.h> 24eddb60fbSPaul Mackerras #include <asm/xics.h> 25243e2511SBenjamin Herrenschmidt #include <asm/xive.h> 2666feed61SPaul Mackerras #include <asm/dbell.h> 2766feed61SPaul Mackerras #include <asm/cputhreads.h> 2837f55d30SSuresh Warrier #include <asm/io.h> 29f725758bSPaul Mackerras #include <asm/opal.h> 30e2702871SPaul Mackerras #include <asm/smp.h> 31aa04b4ccSPaul Mackerras 32fc95ca72SJoonsoo Kim #define KVM_CMA_CHUNK_ORDER 18 33fc95ca72SJoonsoo Kim 345af50993SBenjamin Herrenschmidt #include "book3s_xics.h" 355af50993SBenjamin Herrenschmidt #include "book3s_xive.h" 365af50993SBenjamin Herrenschmidt 375af50993SBenjamin Herrenschmidt /* 38fa61a4e3SAneesh Kumar K.V * Hash page table alignment on newer cpus(CPU_FTR_ARCH_206) 39fa61a4e3SAneesh Kumar K.V * should be power of 2. 40fa61a4e3SAneesh Kumar K.V */ 41fa61a4e3SAneesh Kumar K.V #define HPT_ALIGN_PAGES ((1 << 18) >> PAGE_SHIFT) /* 256k */ 42fa61a4e3SAneesh Kumar K.V /* 43fa61a4e3SAneesh Kumar K.V * By default we reserve 5% of memory for hash pagetable allocation. 44fa61a4e3SAneesh Kumar K.V */ 45fa61a4e3SAneesh Kumar K.V static unsigned long kvm_cma_resv_ratio = 5; 46aa04b4ccSPaul Mackerras 47fc95ca72SJoonsoo Kim static struct cma *kvm_cma; 48fc95ca72SJoonsoo Kim 49fa61a4e3SAneesh Kumar K.V static int __init early_parse_kvm_cma_resv(char *p) 50d2a1b483SAlexander Graf { 51fa61a4e3SAneesh Kumar K.V pr_debug("%s(%s)\n", __func__, p); 52d2a1b483SAlexander Graf if (!p) 53fa61a4e3SAneesh Kumar K.V return -EINVAL; 54fa61a4e3SAneesh Kumar K.V return kstrtoul(p, 0, &kvm_cma_resv_ratio); 55d2a1b483SAlexander Graf } 56fa61a4e3SAneesh Kumar K.V early_param("kvm_cma_resv_ratio", early_parse_kvm_cma_resv); 57d2a1b483SAlexander Graf 58db9a290dSDavid Gibson struct page *kvm_alloc_hpt_cma(unsigned long nr_pages) 59d2a1b483SAlexander Graf { 60c04fa583SAlexey Kardashevskiy VM_BUG_ON(order_base_2(nr_pages) < KVM_CMA_CHUNK_ORDER - PAGE_SHIFT); 61fc95ca72SJoonsoo Kim 62e2f466e3SLucas Stach return cma_alloc(kvm_cma, nr_pages, order_base_2(HPT_ALIGN_PAGES), 6365182029SMarek Szyprowski false); 64d2a1b483SAlexander Graf } 65db9a290dSDavid Gibson EXPORT_SYMBOL_GPL(kvm_alloc_hpt_cma); 66d2a1b483SAlexander Graf 67db9a290dSDavid Gibson void kvm_free_hpt_cma(struct page *page, unsigned long nr_pages) 68d2a1b483SAlexander Graf { 69fc95ca72SJoonsoo Kim cma_release(kvm_cma, page, nr_pages); 70d2a1b483SAlexander Graf } 71db9a290dSDavid Gibson EXPORT_SYMBOL_GPL(kvm_free_hpt_cma); 72d2a1b483SAlexander Graf 73fa61a4e3SAneesh Kumar K.V /** 74fa61a4e3SAneesh Kumar K.V * kvm_cma_reserve() - reserve area for kvm hash pagetable 75fa61a4e3SAneesh Kumar K.V * 76fa61a4e3SAneesh Kumar K.V * This function reserves memory from early allocator. It should be 7714ed7409SAnton Blanchard * called by arch specific code once the memblock allocator 78fa61a4e3SAneesh Kumar K.V * has been activated and all other subsystems have already allocated/reserved 79fa61a4e3SAneesh Kumar K.V * memory. 80fa61a4e3SAneesh Kumar K.V */ 81fa61a4e3SAneesh Kumar K.V void __init kvm_cma_reserve(void) 82fa61a4e3SAneesh Kumar K.V { 83fa61a4e3SAneesh Kumar K.V unsigned long align_size; 8404ba0a92SMike Rapoport phys_addr_t selected_size; 85cec26bc3SAneesh Kumar K.V 86cec26bc3SAneesh Kumar K.V /* 87cec26bc3SAneesh Kumar K.V * We need CMA reservation only when we are in HV mode 88cec26bc3SAneesh Kumar K.V */ 89cec26bc3SAneesh Kumar K.V if (!cpu_has_feature(CPU_FTR_HVMODE)) 90cec26bc3SAneesh Kumar K.V return; 91fa61a4e3SAneesh Kumar K.V 9204ba0a92SMike Rapoport selected_size = PAGE_ALIGN(memblock_phys_mem_size() * kvm_cma_resv_ratio / 100); 93fa61a4e3SAneesh Kumar K.V if (selected_size) { 94a5a8b258SAneesh Kumar K.V pr_info("%s: reserving %ld MiB for global area\n", __func__, 95fa61a4e3SAneesh Kumar K.V (unsigned long)selected_size / SZ_1M); 96fa61a4e3SAneesh Kumar K.V align_size = HPT_ALIGN_PAGES << PAGE_SHIFT; 97c1f733aaSJoonsoo Kim cma_declare_contiguous(0, selected_size, 0, align_size, 98f318dd08SLaura Abbott KVM_CMA_CHUNK_ORDER - PAGE_SHIFT, false, "kvm_cma", 99f318dd08SLaura Abbott &kvm_cma); 100fa61a4e3SAneesh Kumar K.V } 101fa61a4e3SAneesh Kumar K.V } 102441c19c8SMichael Ellerman 103441c19c8SMichael Ellerman /* 10490fd09f8SSam Bobroff * Real-mode H_CONFER implementation. 10590fd09f8SSam Bobroff * We check if we are the only vcpu out of this virtual core 10690fd09f8SSam Bobroff * still running in the guest and not ceded. If so, we pop up 10790fd09f8SSam Bobroff * to the virtual-mode implementation; if not, just return to 10890fd09f8SSam Bobroff * the guest. 10990fd09f8SSam Bobroff */ 11090fd09f8SSam Bobroff long int kvmppc_rm_h_confer(struct kvm_vcpu *vcpu, int target, 11190fd09f8SSam Bobroff unsigned int yield_count) 11290fd09f8SSam Bobroff { 113ec257165SPaul Mackerras struct kvmppc_vcore *vc = local_paca->kvm_hstate.kvm_vcore; 114ec257165SPaul Mackerras int ptid = local_paca->kvm_hstate.ptid; 11590fd09f8SSam Bobroff int threads_running; 11690fd09f8SSam Bobroff int threads_ceded; 11790fd09f8SSam Bobroff int threads_conferring; 11890fd09f8SSam Bobroff u64 stop = get_tb() + 10 * tb_ticks_per_usec; 11990fd09f8SSam Bobroff int rv = H_SUCCESS; /* => don't yield */ 12090fd09f8SSam Bobroff 121ec257165SPaul Mackerras set_bit(ptid, &vc->conferring_threads); 1227d6c40daSPaul Mackerras while ((get_tb() < stop) && !VCORE_IS_EXITING(vc)) { 1237d6c40daSPaul Mackerras threads_running = VCORE_ENTRY_MAP(vc); 1247d6c40daSPaul Mackerras threads_ceded = vc->napping_threads; 1257d6c40daSPaul Mackerras threads_conferring = vc->conferring_threads; 1267d6c40daSPaul Mackerras if ((threads_ceded | threads_conferring) == threads_running) { 12790fd09f8SSam Bobroff rv = H_TOO_HARD; /* => do yield */ 12890fd09f8SSam Bobroff break; 12990fd09f8SSam Bobroff } 13090fd09f8SSam Bobroff } 131ec257165SPaul Mackerras clear_bit(ptid, &vc->conferring_threads); 13290fd09f8SSam Bobroff return rv; 13390fd09f8SSam Bobroff } 13490fd09f8SSam Bobroff 13590fd09f8SSam Bobroff /* 136441c19c8SMichael Ellerman * When running HV mode KVM we need to block certain operations while KVM VMs 137441c19c8SMichael Ellerman * exist in the system. We use a counter of VMs to track this. 138441c19c8SMichael Ellerman * 139441c19c8SMichael Ellerman * One of the operations we need to block is onlining of secondaries, so we 140441c19c8SMichael Ellerman * protect hv_vm_count with get/put_online_cpus(). 141441c19c8SMichael Ellerman */ 142441c19c8SMichael Ellerman static atomic_t hv_vm_count; 143441c19c8SMichael Ellerman 144441c19c8SMichael Ellerman void kvm_hv_vm_activated(void) 145441c19c8SMichael Ellerman { 146441c19c8SMichael Ellerman get_online_cpus(); 147441c19c8SMichael Ellerman atomic_inc(&hv_vm_count); 148441c19c8SMichael Ellerman put_online_cpus(); 149441c19c8SMichael Ellerman } 150441c19c8SMichael Ellerman EXPORT_SYMBOL_GPL(kvm_hv_vm_activated); 151441c19c8SMichael Ellerman 152441c19c8SMichael Ellerman void kvm_hv_vm_deactivated(void) 153441c19c8SMichael Ellerman { 154441c19c8SMichael Ellerman get_online_cpus(); 155441c19c8SMichael Ellerman atomic_dec(&hv_vm_count); 156441c19c8SMichael Ellerman put_online_cpus(); 157441c19c8SMichael Ellerman } 158441c19c8SMichael Ellerman EXPORT_SYMBOL_GPL(kvm_hv_vm_deactivated); 159441c19c8SMichael Ellerman 160441c19c8SMichael Ellerman bool kvm_hv_mode_active(void) 161441c19c8SMichael Ellerman { 162441c19c8SMichael Ellerman return atomic_read(&hv_vm_count) != 0; 163441c19c8SMichael Ellerman } 164ae2113a4SPaul Mackerras 165ae2113a4SPaul Mackerras extern int hcall_real_table[], hcall_real_table_end[]; 166ae2113a4SPaul Mackerras 167ae2113a4SPaul Mackerras int kvmppc_hcall_impl_hv_realmode(unsigned long cmd) 168ae2113a4SPaul Mackerras { 169ae2113a4SPaul Mackerras cmd /= 4; 170ae2113a4SPaul Mackerras if (cmd < hcall_real_table_end - hcall_real_table && 171ae2113a4SPaul Mackerras hcall_real_table[cmd]) 172ae2113a4SPaul Mackerras return 1; 173ae2113a4SPaul Mackerras 174ae2113a4SPaul Mackerras return 0; 175ae2113a4SPaul Mackerras } 176ae2113a4SPaul Mackerras EXPORT_SYMBOL_GPL(kvmppc_hcall_impl_hv_realmode); 177e928e9cbSMichael Ellerman 178e928e9cbSMichael Ellerman int kvmppc_hwrng_present(void) 179e928e9cbSMichael Ellerman { 180e928e9cbSMichael Ellerman return powernv_hwrng_present(); 181e928e9cbSMichael Ellerman } 182e928e9cbSMichael Ellerman EXPORT_SYMBOL_GPL(kvmppc_hwrng_present); 183e928e9cbSMichael Ellerman 184*dcbac73aSNicholas Piggin long kvmppc_rm_h_random(struct kvm_vcpu *vcpu) 185e928e9cbSMichael Ellerman { 186*dcbac73aSNicholas Piggin if (powernv_get_random_real_mode(&vcpu->arch.regs.gpr[4])) 187e928e9cbSMichael Ellerman return H_SUCCESS; 188e928e9cbSMichael Ellerman 189e928e9cbSMichael Ellerman return H_HARDWARE; 190e928e9cbSMichael Ellerman } 191eddb60fbSPaul Mackerras 192eddb60fbSPaul Mackerras /* 19366feed61SPaul Mackerras * Send an interrupt or message to another CPU. 194eddb60fbSPaul Mackerras * The caller needs to include any barrier needed to order writes 195eddb60fbSPaul Mackerras * to memory vs. the IPI/message. 196eddb60fbSPaul Mackerras */ 197eddb60fbSPaul Mackerras void kvmhv_rm_send_ipi(int cpu) 198eddb60fbSPaul Mackerras { 199d381d7caSBenjamin Herrenschmidt void __iomem *xics_phys; 2001704a81cSPaul Mackerras unsigned long msg = PPC_DBELL_TYPE(PPC_DBELL_SERVER); 201eddb60fbSPaul Mackerras 202f3c18e93SPaul Mackerras /* For a nested hypervisor, use the XICS via hcall */ 203f3c18e93SPaul Mackerras if (kvmhv_on_pseries()) { 204f3c18e93SPaul Mackerras unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 205f3c18e93SPaul Mackerras 206f3c18e93SPaul Mackerras plpar_hcall_raw(H_IPI, retbuf, get_hard_smp_processor_id(cpu), 207f3c18e93SPaul Mackerras IPI_PRIORITY); 208f3c18e93SPaul Mackerras return; 209f3c18e93SPaul Mackerras } 210f3c18e93SPaul Mackerras 2111704a81cSPaul Mackerras /* On POWER9 we can use msgsnd for any destination cpu. */ 2121704a81cSPaul Mackerras if (cpu_has_feature(CPU_FTR_ARCH_300)) { 2131704a81cSPaul Mackerras msg |= get_hard_smp_processor_id(cpu); 2141704a81cSPaul Mackerras __asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg)); 2151704a81cSPaul Mackerras return; 2161704a81cSPaul Mackerras } 2175af50993SBenjamin Herrenschmidt 2181704a81cSPaul Mackerras /* On POWER8 for IPIs to threads in the same core, use msgsnd. */ 21966feed61SPaul Mackerras if (cpu_has_feature(CPU_FTR_ARCH_207S) && 22066feed61SPaul Mackerras cpu_first_thread_sibling(cpu) == 22166feed61SPaul Mackerras cpu_first_thread_sibling(raw_smp_processor_id())) { 22266feed61SPaul Mackerras msg |= cpu_thread_in_core(cpu); 22366feed61SPaul Mackerras __asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg)); 22466feed61SPaul Mackerras return; 22566feed61SPaul Mackerras } 22666feed61SPaul Mackerras 227243e2511SBenjamin Herrenschmidt /* We should never reach this */ 22803f95332SPaul Mackerras if (WARN_ON_ONCE(xics_on_xive())) 229243e2511SBenjamin Herrenschmidt return; 230243e2511SBenjamin Herrenschmidt 23166feed61SPaul Mackerras /* Else poke the target with an IPI */ 232d2e60075SNicholas Piggin xics_phys = paca_ptrs[cpu]->kvm_hstate.xics_phys; 233ab9bad0eSBenjamin Herrenschmidt if (xics_phys) 234d381d7caSBenjamin Herrenschmidt __raw_rm_writeb(IPI_PRIORITY, xics_phys + XICS_MFRR); 235f725758bSPaul Mackerras else 236ab9bad0eSBenjamin Herrenschmidt opal_int_set_mfrr(get_hard_smp_processor_id(cpu), IPI_PRIORITY); 237eddb60fbSPaul Mackerras } 238eddb60fbSPaul Mackerras 239eddb60fbSPaul Mackerras /* 240eddb60fbSPaul Mackerras * The following functions are called from the assembly code 241eddb60fbSPaul Mackerras * in book3s_hv_rmhandlers.S. 242eddb60fbSPaul Mackerras */ 243eddb60fbSPaul Mackerras static void kvmhv_interrupt_vcore(struct kvmppc_vcore *vc, int active) 244eddb60fbSPaul Mackerras { 245eddb60fbSPaul Mackerras int cpu = vc->pcpu; 246eddb60fbSPaul Mackerras 247eddb60fbSPaul Mackerras /* Order setting of exit map vs. msgsnd/IPI */ 248eddb60fbSPaul Mackerras smp_mb(); 249eddb60fbSPaul Mackerras for (; active; active >>= 1, ++cpu) 250eddb60fbSPaul Mackerras if (active & 1) 251eddb60fbSPaul Mackerras kvmhv_rm_send_ipi(cpu); 252eddb60fbSPaul Mackerras } 253eddb60fbSPaul Mackerras 254eddb60fbSPaul Mackerras void kvmhv_commence_exit(int trap) 255eddb60fbSPaul Mackerras { 256eddb60fbSPaul Mackerras struct kvmppc_vcore *vc = local_paca->kvm_hstate.kvm_vcore; 257eddb60fbSPaul Mackerras int ptid = local_paca->kvm_hstate.ptid; 258b4deba5cSPaul Mackerras struct kvm_split_mode *sip = local_paca->kvm_hstate.kvm_split_mode; 259b1b1697aSNicholas Piggin int me, ee, i; 260eddb60fbSPaul Mackerras 261eddb60fbSPaul Mackerras /* Set our bit in the threads-exiting-guest map in the 0xff00 262eddb60fbSPaul Mackerras bits of vcore->entry_exit_map */ 263eddb60fbSPaul Mackerras me = 0x100 << ptid; 264eddb60fbSPaul Mackerras do { 265eddb60fbSPaul Mackerras ee = vc->entry_exit_map; 266eddb60fbSPaul Mackerras } while (cmpxchg(&vc->entry_exit_map, ee, ee | me) != ee); 267eddb60fbSPaul Mackerras 268eddb60fbSPaul Mackerras /* Are we the first here? */ 269eddb60fbSPaul Mackerras if ((ee >> 8) != 0) 270eddb60fbSPaul Mackerras return; 271eddb60fbSPaul Mackerras 272eddb60fbSPaul Mackerras /* 273eddb60fbSPaul Mackerras * Trigger the other threads in this vcore to exit the guest. 274eddb60fbSPaul Mackerras * If this is a hypervisor decrementer interrupt then they 275eddb60fbSPaul Mackerras * will be already on their way out of the guest. 276eddb60fbSPaul Mackerras */ 277eddb60fbSPaul Mackerras if (trap != BOOK3S_INTERRUPT_HV_DECREMENTER) 278eddb60fbSPaul Mackerras kvmhv_interrupt_vcore(vc, ee & ~(1 << ptid)); 279b4deba5cSPaul Mackerras 280b4deba5cSPaul Mackerras /* 281b4deba5cSPaul Mackerras * If we are doing dynamic micro-threading, interrupt the other 282b4deba5cSPaul Mackerras * subcores to pull them out of their guests too. 283b4deba5cSPaul Mackerras */ 284b4deba5cSPaul Mackerras if (!sip) 285b4deba5cSPaul Mackerras return; 286b4deba5cSPaul Mackerras 287b4deba5cSPaul Mackerras for (i = 0; i < MAX_SUBCORES; ++i) { 288898b25b2SPaul Mackerras vc = sip->vc[i]; 289b4deba5cSPaul Mackerras if (!vc) 290b4deba5cSPaul Mackerras break; 291b4deba5cSPaul Mackerras do { 292b4deba5cSPaul Mackerras ee = vc->entry_exit_map; 293b4deba5cSPaul Mackerras /* Already asked to exit? */ 294b4deba5cSPaul Mackerras if ((ee >> 8) != 0) 295b4deba5cSPaul Mackerras break; 296b4deba5cSPaul Mackerras } while (cmpxchg(&vc->entry_exit_map, ee, 297b4deba5cSPaul Mackerras ee | VCORE_EXIT_REQ) != ee); 298b4deba5cSPaul Mackerras if ((ee >> 8) == 0) 299b4deba5cSPaul Mackerras kvmhv_interrupt_vcore(vc, ee); 300b4deba5cSPaul Mackerras } 301eddb60fbSPaul Mackerras } 30279b6c247SSuresh Warrier 30379b6c247SSuresh Warrier struct kvmppc_host_rm_ops *kvmppc_host_rm_ops_hv; 30479b6c247SSuresh Warrier EXPORT_SYMBOL_GPL(kvmppc_host_rm_ops_hv); 30537f55d30SSuresh Warrier 306e3c13e56SSuresh Warrier #ifdef CONFIG_KVM_XICS 307e3c13e56SSuresh Warrier static struct kvmppc_irq_map *get_irqmap(struct kvmppc_passthru_irqmap *pimap, 308e3c13e56SSuresh Warrier u32 xisr) 309e3c13e56SSuresh Warrier { 310e3c13e56SSuresh Warrier int i; 311e3c13e56SSuresh Warrier 312e3c13e56SSuresh Warrier /* 313e3c13e56SSuresh Warrier * We access the mapped array here without a lock. That 314e3c13e56SSuresh Warrier * is safe because we never reduce the number of entries 315e3c13e56SSuresh Warrier * in the array and we never change the v_hwirq field of 316e3c13e56SSuresh Warrier * an entry once it is set. 317e3c13e56SSuresh Warrier * 318e3c13e56SSuresh Warrier * We have also carefully ordered the stores in the writer 319e3c13e56SSuresh Warrier * and the loads here in the reader, so that if we find a matching 320e3c13e56SSuresh Warrier * hwirq here, the associated GSI and irq_desc fields are valid. 321e3c13e56SSuresh Warrier */ 322e3c13e56SSuresh Warrier for (i = 0; i < pimap->n_mapped; i++) { 323e3c13e56SSuresh Warrier if (xisr == pimap->mapped[i].r_hwirq) { 324e3c13e56SSuresh Warrier /* 325e3c13e56SSuresh Warrier * Order subsequent reads in the caller to serialize 326e3c13e56SSuresh Warrier * with the writer. 327e3c13e56SSuresh Warrier */ 328e3c13e56SSuresh Warrier smp_rmb(); 329e3c13e56SSuresh Warrier return &pimap->mapped[i]; 330e3c13e56SSuresh Warrier } 331e3c13e56SSuresh Warrier } 332e3c13e56SSuresh Warrier return NULL; 333e3c13e56SSuresh Warrier } 334e3c13e56SSuresh Warrier 335e3c13e56SSuresh Warrier /* 336e3c13e56SSuresh Warrier * If we have an interrupt that's not an IPI, check if we have a 337e3c13e56SSuresh Warrier * passthrough adapter and if so, check if this external interrupt 338e3c13e56SSuresh Warrier * is for the adapter. 339e3c13e56SSuresh Warrier * We will attempt to deliver the IRQ directly to the target VCPU's 340e3c13e56SSuresh Warrier * ICP, the virtual ICP (based on affinity - the xive value in ICS). 341e3c13e56SSuresh Warrier * 342e3c13e56SSuresh Warrier * If the delivery fails or if this is not for a passthrough adapter, 343e3c13e56SSuresh Warrier * return to the host to handle this interrupt. We earlier 344e3c13e56SSuresh Warrier * saved a copy of the XIRR in the PACA, it will be picked up by 345e3c13e56SSuresh Warrier * the host ICP driver. 346e3c13e56SSuresh Warrier */ 347f725758bSPaul Mackerras static int kvmppc_check_passthru(u32 xisr, __be32 xirr, bool *again) 348e3c13e56SSuresh Warrier { 349e3c13e56SSuresh Warrier struct kvmppc_passthru_irqmap *pimap; 350e3c13e56SSuresh Warrier struct kvmppc_irq_map *irq_map; 351e3c13e56SSuresh Warrier struct kvm_vcpu *vcpu; 352e3c13e56SSuresh Warrier 353e3c13e56SSuresh Warrier vcpu = local_paca->kvm_hstate.kvm_vcpu; 354e3c13e56SSuresh Warrier if (!vcpu) 355e3c13e56SSuresh Warrier return 1; 356e3c13e56SSuresh Warrier pimap = kvmppc_get_passthru_irqmap(vcpu->kvm); 357e3c13e56SSuresh Warrier if (!pimap) 358e3c13e56SSuresh Warrier return 1; 359e3c13e56SSuresh Warrier irq_map = get_irqmap(pimap, xisr); 360e3c13e56SSuresh Warrier if (!irq_map) 361e3c13e56SSuresh Warrier return 1; 362e3c13e56SSuresh Warrier 363e3c13e56SSuresh Warrier /* We're handling this interrupt, generic code doesn't need to */ 364e3c13e56SSuresh Warrier local_paca->kvm_hstate.saved_xirr = 0; 365e3c13e56SSuresh Warrier 366f725758bSPaul Mackerras return kvmppc_deliver_irq_passthru(vcpu, xirr, irq_map, pimap, again); 367e3c13e56SSuresh Warrier } 368e3c13e56SSuresh Warrier 369e3c13e56SSuresh Warrier #else 370e2702871SPaul Mackerras static inline int kvmppc_check_passthru(u32 xisr, __be32 xirr, bool *again) 371e3c13e56SSuresh Warrier { 372e3c13e56SSuresh Warrier return 1; 373e3c13e56SSuresh Warrier } 374e3c13e56SSuresh Warrier #endif 375e3c13e56SSuresh Warrier 37637f55d30SSuresh Warrier /* 37737f55d30SSuresh Warrier * Determine what sort of external interrupt is pending (if any). 37837f55d30SSuresh Warrier * Returns: 37937f55d30SSuresh Warrier * 0 if no interrupt is pending 38037f55d30SSuresh Warrier * 1 if an interrupt is pending that needs to be handled by the host 381f7af5209SSuresh Warrier * 2 Passthrough that needs completion in the host 38237f55d30SSuresh Warrier * -1 if there was a guest wakeup IPI (which has now been cleared) 383e3c13e56SSuresh Warrier * -2 if there is PCI passthrough external interrupt that was handled 38437f55d30SSuresh Warrier */ 385f725758bSPaul Mackerras static long kvmppc_read_one_intr(bool *again); 38637f55d30SSuresh Warrier 38737f55d30SSuresh Warrier long kvmppc_read_intr(void) 38837f55d30SSuresh Warrier { 389f725758bSPaul Mackerras long ret = 0; 390f725758bSPaul Mackerras long rc; 391f725758bSPaul Mackerras bool again; 392f725758bSPaul Mackerras 393243e2511SBenjamin Herrenschmidt if (xive_enabled()) 394243e2511SBenjamin Herrenschmidt return 1; 395243e2511SBenjamin Herrenschmidt 396f725758bSPaul Mackerras do { 397f725758bSPaul Mackerras again = false; 398f725758bSPaul Mackerras rc = kvmppc_read_one_intr(&again); 399f725758bSPaul Mackerras if (rc && (ret == 0 || rc > ret)) 400f725758bSPaul Mackerras ret = rc; 401f725758bSPaul Mackerras } while (again); 402f725758bSPaul Mackerras return ret; 403f725758bSPaul Mackerras } 404f725758bSPaul Mackerras 405f725758bSPaul Mackerras static long kvmppc_read_one_intr(bool *again) 406f725758bSPaul Mackerras { 407d381d7caSBenjamin Herrenschmidt void __iomem *xics_phys; 40837f55d30SSuresh Warrier u32 h_xirr; 40937f55d30SSuresh Warrier __be32 xirr; 41037f55d30SSuresh Warrier u32 xisr; 41137f55d30SSuresh Warrier u8 host_ipi; 412f725758bSPaul Mackerras int64_t rc; 41337f55d30SSuresh Warrier 4145af50993SBenjamin Herrenschmidt if (xive_enabled()) 4155af50993SBenjamin Herrenschmidt return 1; 4165af50993SBenjamin Herrenschmidt 41737f55d30SSuresh Warrier /* see if a host IPI is pending */ 41837f55d30SSuresh Warrier host_ipi = local_paca->kvm_hstate.host_ipi; 41937f55d30SSuresh Warrier if (host_ipi) 42037f55d30SSuresh Warrier return 1; 42137f55d30SSuresh Warrier 42237f55d30SSuresh Warrier /* Now read the interrupt from the ICP */ 423f3c18e93SPaul Mackerras if (kvmhv_on_pseries()) { 424f3c18e93SPaul Mackerras unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 425f3c18e93SPaul Mackerras 426f3c18e93SPaul Mackerras rc = plpar_hcall_raw(H_XIRR, retbuf, 0xFF); 427f3c18e93SPaul Mackerras xirr = cpu_to_be32(retbuf[0]); 428f3c18e93SPaul Mackerras } else { 42937f55d30SSuresh Warrier xics_phys = local_paca->kvm_hstate.xics_phys; 43053af3ba2SPaul Mackerras rc = 0; 431ab9bad0eSBenjamin Herrenschmidt if (!xics_phys) 43253af3ba2SPaul Mackerras rc = opal_int_get_xirr(&xirr, false); 43353af3ba2SPaul Mackerras else 434d381d7caSBenjamin Herrenschmidt xirr = __raw_rm_readl(xics_phys + XICS_XIRR); 435f3c18e93SPaul Mackerras } 436f725758bSPaul Mackerras if (rc < 0) 43737f55d30SSuresh Warrier return 1; 43837f55d30SSuresh Warrier 43937f55d30SSuresh Warrier /* 44037f55d30SSuresh Warrier * Save XIRR for later. Since we get control in reverse endian 44137f55d30SSuresh Warrier * on LE systems, save it byte reversed and fetch it back in 44237f55d30SSuresh Warrier * host endian. Note that xirr is the value read from the 44337f55d30SSuresh Warrier * XIRR register, while h_xirr is the host endian version. 44437f55d30SSuresh Warrier */ 44537f55d30SSuresh Warrier h_xirr = be32_to_cpu(xirr); 44637f55d30SSuresh Warrier local_paca->kvm_hstate.saved_xirr = h_xirr; 44737f55d30SSuresh Warrier xisr = h_xirr & 0xffffff; 44837f55d30SSuresh Warrier /* 44937f55d30SSuresh Warrier * Ensure that the store/load complete to guarantee all side 45037f55d30SSuresh Warrier * effects of loading from XIRR has completed 45137f55d30SSuresh Warrier */ 45237f55d30SSuresh Warrier smp_mb(); 45337f55d30SSuresh Warrier 45437f55d30SSuresh Warrier /* if nothing pending in the ICP */ 45537f55d30SSuresh Warrier if (!xisr) 45637f55d30SSuresh Warrier return 0; 45737f55d30SSuresh Warrier 45837f55d30SSuresh Warrier /* We found something in the ICP... 45937f55d30SSuresh Warrier * 46037f55d30SSuresh Warrier * If it is an IPI, clear the MFRR and EOI it. 46137f55d30SSuresh Warrier */ 46237f55d30SSuresh Warrier if (xisr == XICS_IPI) { 46353af3ba2SPaul Mackerras rc = 0; 464f3c18e93SPaul Mackerras if (kvmhv_on_pseries()) { 465f3c18e93SPaul Mackerras unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 466f3c18e93SPaul Mackerras 467f3c18e93SPaul Mackerras plpar_hcall_raw(H_IPI, retbuf, 468f3c18e93SPaul Mackerras hard_smp_processor_id(), 0xff); 469f3c18e93SPaul Mackerras plpar_hcall_raw(H_EOI, retbuf, h_xirr); 470f3c18e93SPaul Mackerras } else if (xics_phys) { 471d381d7caSBenjamin Herrenschmidt __raw_rm_writeb(0xff, xics_phys + XICS_MFRR); 472d381d7caSBenjamin Herrenschmidt __raw_rm_writel(xirr, xics_phys + XICS_XIRR); 473f725758bSPaul Mackerras } else { 474ab9bad0eSBenjamin Herrenschmidt opal_int_set_mfrr(hard_smp_processor_id(), 0xff); 475ab9bad0eSBenjamin Herrenschmidt rc = opal_int_eoi(h_xirr); 47653af3ba2SPaul Mackerras } 477f725758bSPaul Mackerras /* If rc > 0, there is another interrupt pending */ 478f725758bSPaul Mackerras *again = rc > 0; 479f725758bSPaul Mackerras 48037f55d30SSuresh Warrier /* 48137f55d30SSuresh Warrier * Need to ensure side effects of above stores 48237f55d30SSuresh Warrier * complete before proceeding. 48337f55d30SSuresh Warrier */ 48437f55d30SSuresh Warrier smp_mb(); 48537f55d30SSuresh Warrier 48637f55d30SSuresh Warrier /* 48737f55d30SSuresh Warrier * We need to re-check host IPI now in case it got set in the 48837f55d30SSuresh Warrier * meantime. If it's clear, we bounce the interrupt to the 48937f55d30SSuresh Warrier * guest 49037f55d30SSuresh Warrier */ 49137f55d30SSuresh Warrier host_ipi = local_paca->kvm_hstate.host_ipi; 49237f55d30SSuresh Warrier if (unlikely(host_ipi != 0)) { 49337f55d30SSuresh Warrier /* We raced with the host, 49437f55d30SSuresh Warrier * we need to resend that IPI, bummer 49537f55d30SSuresh Warrier */ 496f3c18e93SPaul Mackerras if (kvmhv_on_pseries()) { 497f3c18e93SPaul Mackerras unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 498f3c18e93SPaul Mackerras 499f3c18e93SPaul Mackerras plpar_hcall_raw(H_IPI, retbuf, 500f3c18e93SPaul Mackerras hard_smp_processor_id(), 501f3c18e93SPaul Mackerras IPI_PRIORITY); 502f3c18e93SPaul Mackerras } else if (xics_phys) 503d381d7caSBenjamin Herrenschmidt __raw_rm_writeb(IPI_PRIORITY, 504d381d7caSBenjamin Herrenschmidt xics_phys + XICS_MFRR); 505f725758bSPaul Mackerras else 506ab9bad0eSBenjamin Herrenschmidt opal_int_set_mfrr(hard_smp_processor_id(), 507f725758bSPaul Mackerras IPI_PRIORITY); 50837f55d30SSuresh Warrier /* Let side effects complete */ 50937f55d30SSuresh Warrier smp_mb(); 51037f55d30SSuresh Warrier return 1; 51137f55d30SSuresh Warrier } 51237f55d30SSuresh Warrier 51337f55d30SSuresh Warrier /* OK, it's an IPI for us */ 51437f55d30SSuresh Warrier local_paca->kvm_hstate.saved_xirr = 0; 51537f55d30SSuresh Warrier return -1; 51637f55d30SSuresh Warrier } 51737f55d30SSuresh Warrier 518f725758bSPaul Mackerras return kvmppc_check_passthru(xisr, xirr, again); 51937f55d30SSuresh Warrier } 5205af50993SBenjamin Herrenschmidt 5215af50993SBenjamin Herrenschmidt #ifdef CONFIG_KVM_XICS 5225af50993SBenjamin Herrenschmidt unsigned long kvmppc_rm_h_xirr(struct kvm_vcpu *vcpu) 5235af50993SBenjamin Herrenschmidt { 52400bb6ae5SPaul Mackerras if (!kvmppc_xics_enabled(vcpu)) 52500bb6ae5SPaul Mackerras return H_TOO_HARD; 526*dcbac73aSNicholas Piggin if (xics_on_xive()) 5275af50993SBenjamin Herrenschmidt return xive_rm_h_xirr(vcpu); 528*dcbac73aSNicholas Piggin else 5295af50993SBenjamin Herrenschmidt return xics_rm_h_xirr(vcpu); 5305af50993SBenjamin Herrenschmidt } 5315af50993SBenjamin Herrenschmidt 5325af50993SBenjamin Herrenschmidt unsigned long kvmppc_rm_h_xirr_x(struct kvm_vcpu *vcpu) 5335af50993SBenjamin Herrenschmidt { 53400bb6ae5SPaul Mackerras if (!kvmppc_xics_enabled(vcpu)) 53500bb6ae5SPaul Mackerras return H_TOO_HARD; 5361143a706SSimon Guo vcpu->arch.regs.gpr[5] = get_tb(); 537*dcbac73aSNicholas Piggin if (xics_on_xive()) 5385af50993SBenjamin Herrenschmidt return xive_rm_h_xirr(vcpu); 539*dcbac73aSNicholas Piggin else 5405af50993SBenjamin Herrenschmidt return xics_rm_h_xirr(vcpu); 5415af50993SBenjamin Herrenschmidt } 5425af50993SBenjamin Herrenschmidt 5435af50993SBenjamin Herrenschmidt unsigned long kvmppc_rm_h_ipoll(struct kvm_vcpu *vcpu, unsigned long server) 5445af50993SBenjamin Herrenschmidt { 54500bb6ae5SPaul Mackerras if (!kvmppc_xics_enabled(vcpu)) 54600bb6ae5SPaul Mackerras return H_TOO_HARD; 547*dcbac73aSNicholas Piggin if (xics_on_xive()) 5485af50993SBenjamin Herrenschmidt return xive_rm_h_ipoll(vcpu, server); 549*dcbac73aSNicholas Piggin else 5505af50993SBenjamin Herrenschmidt return H_TOO_HARD; 5515af50993SBenjamin Herrenschmidt } 5525af50993SBenjamin Herrenschmidt 5535af50993SBenjamin Herrenschmidt int kvmppc_rm_h_ipi(struct kvm_vcpu *vcpu, unsigned long server, 5545af50993SBenjamin Herrenschmidt unsigned long mfrr) 5555af50993SBenjamin Herrenschmidt { 55600bb6ae5SPaul Mackerras if (!kvmppc_xics_enabled(vcpu)) 55700bb6ae5SPaul Mackerras return H_TOO_HARD; 558*dcbac73aSNicholas Piggin if (xics_on_xive()) 5595af50993SBenjamin Herrenschmidt return xive_rm_h_ipi(vcpu, server, mfrr); 560*dcbac73aSNicholas Piggin else 5615af50993SBenjamin Herrenschmidt return xics_rm_h_ipi(vcpu, server, mfrr); 5625af50993SBenjamin Herrenschmidt } 5635af50993SBenjamin Herrenschmidt 5645af50993SBenjamin Herrenschmidt int kvmppc_rm_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr) 5655af50993SBenjamin Herrenschmidt { 56600bb6ae5SPaul Mackerras if (!kvmppc_xics_enabled(vcpu)) 56700bb6ae5SPaul Mackerras return H_TOO_HARD; 568*dcbac73aSNicholas Piggin if (xics_on_xive()) 5695af50993SBenjamin Herrenschmidt return xive_rm_h_cppr(vcpu, cppr); 570*dcbac73aSNicholas Piggin else 5715af50993SBenjamin Herrenschmidt return xics_rm_h_cppr(vcpu, cppr); 5725af50993SBenjamin Herrenschmidt } 5735af50993SBenjamin Herrenschmidt 5745af50993SBenjamin Herrenschmidt int kvmppc_rm_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr) 5755af50993SBenjamin Herrenschmidt { 57600bb6ae5SPaul Mackerras if (!kvmppc_xics_enabled(vcpu)) 57700bb6ae5SPaul Mackerras return H_TOO_HARD; 578*dcbac73aSNicholas Piggin if (xics_on_xive()) 5795af50993SBenjamin Herrenschmidt return xive_rm_h_eoi(vcpu, xirr); 580*dcbac73aSNicholas Piggin else 5815af50993SBenjamin Herrenschmidt return xics_rm_h_eoi(vcpu, xirr); 5825af50993SBenjamin Herrenschmidt } 5835af50993SBenjamin Herrenschmidt #endif /* CONFIG_KVM_XICS */ 584857b99e1SPaul Mackerras 585857b99e1SPaul Mackerras void kvmppc_bad_interrupt(struct pt_regs *regs) 586857b99e1SPaul Mackerras { 5877c1bd80cSNicholas Piggin /* 5887c1bd80cSNicholas Piggin * 100 could happen at any time, 200 can happen due to invalid real 5897c1bd80cSNicholas Piggin * address access for example (or any time due to a hardware problem). 5907c1bd80cSNicholas Piggin */ 5917c1bd80cSNicholas Piggin if (TRAP(regs) == 0x100) { 5927c1bd80cSNicholas Piggin get_paca()->in_nmi++; 5937c1bd80cSNicholas Piggin system_reset_exception(regs); 5947c1bd80cSNicholas Piggin get_paca()->in_nmi--; 5957c1bd80cSNicholas Piggin } else if (TRAP(regs) == 0x200) { 5967c1bd80cSNicholas Piggin machine_check_exception(regs); 5977c1bd80cSNicholas Piggin } else { 598857b99e1SPaul Mackerras die("Bad interrupt in KVM entry/exit code", regs, SIGABRT); 5997c1bd80cSNicholas Piggin } 600857b99e1SPaul Mackerras panic("Bad KVM trap"); 601857b99e1SPaul Mackerras } 602c0101509SPaul Mackerras 603268f4ef9SNicholas Piggin static void kvmppc_end_cede(struct kvm_vcpu *vcpu) 604268f4ef9SNicholas Piggin { 605268f4ef9SNicholas Piggin vcpu->arch.ceded = 0; 606268f4ef9SNicholas Piggin if (vcpu->arch.timer_running) { 607268f4ef9SNicholas Piggin hrtimer_try_to_cancel(&vcpu->arch.dec_timer); 608268f4ef9SNicholas Piggin vcpu->arch.timer_running = 0; 609268f4ef9SNicholas Piggin } 610268f4ef9SNicholas Piggin } 611268f4ef9SNicholas Piggin 612268f4ef9SNicholas Piggin void kvmppc_set_msr_hv(struct kvm_vcpu *vcpu, u64 msr) 613268f4ef9SNicholas Piggin { 614732f21a3SNicholas Piggin /* Guest must always run with ME enabled, HV disabled. */ 615732f21a3SNicholas Piggin msr = (msr | MSR_ME) & ~MSR_HV; 616946cf44aSNicholas Piggin 617268f4ef9SNicholas Piggin /* 618268f4ef9SNicholas Piggin * Check for illegal transactional state bit combination 619268f4ef9SNicholas Piggin * and if we find it, force the TS field to a safe state. 620268f4ef9SNicholas Piggin */ 621268f4ef9SNicholas Piggin if ((msr & MSR_TS_MASK) == MSR_TS_MASK) 622268f4ef9SNicholas Piggin msr &= ~MSR_TS_MASK; 623268f4ef9SNicholas Piggin vcpu->arch.shregs.msr = msr; 624268f4ef9SNicholas Piggin kvmppc_end_cede(vcpu); 625268f4ef9SNicholas Piggin } 626268f4ef9SNicholas Piggin EXPORT_SYMBOL_GPL(kvmppc_set_msr_hv); 627268f4ef9SNicholas Piggin 628268f4ef9SNicholas Piggin static void inject_interrupt(struct kvm_vcpu *vcpu, int vec, u64 srr1_flags) 629268f4ef9SNicholas Piggin { 630268f4ef9SNicholas Piggin unsigned long msr, pc, new_msr, new_pc; 631268f4ef9SNicholas Piggin 632268f4ef9SNicholas Piggin msr = kvmppc_get_msr(vcpu); 633268f4ef9SNicholas Piggin pc = kvmppc_get_pc(vcpu); 634268f4ef9SNicholas Piggin new_msr = vcpu->arch.intr_msr; 635268f4ef9SNicholas Piggin new_pc = vec; 636268f4ef9SNicholas Piggin 637268f4ef9SNicholas Piggin /* If transactional, change to suspend mode on IRQ delivery */ 638268f4ef9SNicholas Piggin if (MSR_TM_TRANSACTIONAL(msr)) 639268f4ef9SNicholas Piggin new_msr |= MSR_TS_S; 640268f4ef9SNicholas Piggin else 641268f4ef9SNicholas Piggin new_msr |= msr & MSR_TS_MASK; 642268f4ef9SNicholas Piggin 6436a13cb0cSNicholas Piggin /* 6446a13cb0cSNicholas Piggin * Perform MSR and PC adjustment for LPCR[AIL]=3 if it is set and 6456a13cb0cSNicholas Piggin * applicable. AIL=2 is not supported. 6466a13cb0cSNicholas Piggin * 6476a13cb0cSNicholas Piggin * AIL does not apply to SRESET, MCE, or HMI (which is never 6486a13cb0cSNicholas Piggin * delivered to the guest), and does not apply if IR=0 or DR=0. 6496a13cb0cSNicholas Piggin */ 6506a13cb0cSNicholas Piggin if (vec != BOOK3S_INTERRUPT_SYSTEM_RESET && 6516a13cb0cSNicholas Piggin vec != BOOK3S_INTERRUPT_MACHINE_CHECK && 6526a13cb0cSNicholas Piggin (vcpu->arch.vcore->lpcr & LPCR_AIL) == LPCR_AIL_3 && 6536a13cb0cSNicholas Piggin (msr & (MSR_IR|MSR_DR)) == (MSR_IR|MSR_DR) ) { 6546a13cb0cSNicholas Piggin new_msr |= MSR_IR | MSR_DR; 6556a13cb0cSNicholas Piggin new_pc += 0xC000000000004000ULL; 6566a13cb0cSNicholas Piggin } 6576a13cb0cSNicholas Piggin 658268f4ef9SNicholas Piggin kvmppc_set_srr0(vcpu, pc); 659268f4ef9SNicholas Piggin kvmppc_set_srr1(vcpu, (msr & SRR1_MSR_BITS) | srr1_flags); 660268f4ef9SNicholas Piggin kvmppc_set_pc(vcpu, new_pc); 661268f4ef9SNicholas Piggin vcpu->arch.shregs.msr = new_msr; 662268f4ef9SNicholas Piggin } 663268f4ef9SNicholas Piggin 664268f4ef9SNicholas Piggin void kvmppc_inject_interrupt_hv(struct kvm_vcpu *vcpu, int vec, u64 srr1_flags) 665268f4ef9SNicholas Piggin { 666268f4ef9SNicholas Piggin inject_interrupt(vcpu, vec, srr1_flags); 667268f4ef9SNicholas Piggin kvmppc_end_cede(vcpu); 668268f4ef9SNicholas Piggin } 669268f4ef9SNicholas Piggin EXPORT_SYMBOL_GPL(kvmppc_inject_interrupt_hv); 670268f4ef9SNicholas Piggin 671f7035ce9SPaul Mackerras /* 672f7035ce9SPaul Mackerras * Is there a PRIV_DOORBELL pending for the guest (on POWER9)? 673f7035ce9SPaul Mackerras * Can we inject a Decrementer or a External interrupt? 674f7035ce9SPaul Mackerras */ 675f7035ce9SPaul Mackerras void kvmppc_guest_entry_inject_int(struct kvm_vcpu *vcpu) 676f7035ce9SPaul Mackerras { 677f7035ce9SPaul Mackerras int ext; 678f7035ce9SPaul Mackerras unsigned long lpcr; 679f7035ce9SPaul Mackerras 680f7035ce9SPaul Mackerras /* Insert EXTERNAL bit into LPCR at the MER bit position */ 681f7035ce9SPaul Mackerras ext = (vcpu->arch.pending_exceptions >> BOOK3S_IRQPRIO_EXTERNAL) & 1; 682f7035ce9SPaul Mackerras lpcr = mfspr(SPRN_LPCR); 683f7035ce9SPaul Mackerras lpcr |= ext << LPCR_MER_SH; 684f7035ce9SPaul Mackerras mtspr(SPRN_LPCR, lpcr); 685f7035ce9SPaul Mackerras isync(); 686f7035ce9SPaul Mackerras 687f7035ce9SPaul Mackerras if (vcpu->arch.shregs.msr & MSR_EE) { 688f7035ce9SPaul Mackerras if (ext) { 689268f4ef9SNicholas Piggin inject_interrupt(vcpu, BOOK3S_INTERRUPT_EXTERNAL, 0); 690f7035ce9SPaul Mackerras } else { 691f7035ce9SPaul Mackerras long int dec = mfspr(SPRN_DEC); 692f7035ce9SPaul Mackerras if (!(lpcr & LPCR_LD)) 693f7035ce9SPaul Mackerras dec = (int) dec; 694f7035ce9SPaul Mackerras if (dec < 0) 695268f4ef9SNicholas Piggin inject_interrupt(vcpu, 696268f4ef9SNicholas Piggin BOOK3S_INTERRUPT_DECREMENTER, 0); 697f7035ce9SPaul Mackerras } 698f7035ce9SPaul Mackerras } 699f7035ce9SPaul Mackerras 700f7035ce9SPaul Mackerras if (vcpu->arch.doorbell_request) { 701f7035ce9SPaul Mackerras mtspr(SPRN_DPDES, 1); 702f7035ce9SPaul Mackerras vcpu->arch.vcore->dpdes = 1; 703f7035ce9SPaul Mackerras smp_wmb(); 704f7035ce9SPaul Mackerras vcpu->arch.doorbell_request = 0; 705f7035ce9SPaul Mackerras } 706f7035ce9SPaul Mackerras } 7072940ba0cSPaul Mackerras 70870ea13f6SPaul Mackerras static void flush_guest_tlb(struct kvm *kvm) 7092940ba0cSPaul Mackerras { 7102940ba0cSPaul Mackerras unsigned long rb, set; 7112940ba0cSPaul Mackerras 71270ea13f6SPaul Mackerras rb = PPC_BIT(52); /* IS = 2 */ 71370ea13f6SPaul Mackerras if (kvm_is_radix(kvm)) { 71470ea13f6SPaul Mackerras /* R=1 PRS=1 RIC=2 */ 71570ea13f6SPaul Mackerras asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1) 71670ea13f6SPaul Mackerras : : "r" (rb), "i" (1), "i" (1), "i" (2), 71770ea13f6SPaul Mackerras "r" (0) : "memory"); 71870ea13f6SPaul Mackerras for (set = 1; set < kvm->arch.tlb_sets; ++set) { 71970ea13f6SPaul Mackerras rb += PPC_BIT(51); /* increment set number */ 72070ea13f6SPaul Mackerras /* R=1 PRS=1 RIC=0 */ 72170ea13f6SPaul Mackerras asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1) 72270ea13f6SPaul Mackerras : : "r" (rb), "i" (1), "i" (1), "i" (0), 72370ea13f6SPaul Mackerras "r" (0) : "memory"); 72470ea13f6SPaul Mackerras } 7256c46fcceSNicholas Piggin asm volatile("ptesync": : :"memory"); 7266c46fcceSNicholas Piggin asm volatile(PPC_RADIX_INVALIDATE_ERAT_GUEST : : :"memory"); 72770ea13f6SPaul Mackerras } else { 72870ea13f6SPaul Mackerras for (set = 0; set < kvm->arch.tlb_sets; ++set) { 72970ea13f6SPaul Mackerras /* R=0 PRS=0 RIC=0 */ 73070ea13f6SPaul Mackerras asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1) 73170ea13f6SPaul Mackerras : : "r" (rb), "i" (0), "i" (0), "i" (0), 73270ea13f6SPaul Mackerras "r" (0) : "memory"); 73370ea13f6SPaul Mackerras rb += PPC_BIT(51); /* increment set number */ 73470ea13f6SPaul Mackerras } 73570ea13f6SPaul Mackerras asm volatile("ptesync": : :"memory"); 736fe7946ceSNicholas Piggin asm volatile(PPC_ISA_3_0_INVALIDATE_ERAT : : :"memory"); 73770ea13f6SPaul Mackerras } 73870ea13f6SPaul Mackerras } 73970ea13f6SPaul Mackerras 74070ea13f6SPaul Mackerras void kvmppc_check_need_tlb_flush(struct kvm *kvm, int pcpu, 74170ea13f6SPaul Mackerras struct kvm_nested_guest *nested) 74270ea13f6SPaul Mackerras { 74370ea13f6SPaul Mackerras cpumask_t *need_tlb_flush; 74470ea13f6SPaul Mackerras 7452940ba0cSPaul Mackerras /* 7462940ba0cSPaul Mackerras * On POWER9, individual threads can come in here, but the 7472940ba0cSPaul Mackerras * TLB is shared between the 4 threads in a core, hence 7482940ba0cSPaul Mackerras * invalidating on one thread invalidates for all. 7492940ba0cSPaul Mackerras * Thus we make all 4 threads use the same bit. 7502940ba0cSPaul Mackerras */ 7512940ba0cSPaul Mackerras if (cpu_has_feature(CPU_FTR_ARCH_300)) 7522940ba0cSPaul Mackerras pcpu = cpu_first_thread_sibling(pcpu); 7532940ba0cSPaul Mackerras 75470ea13f6SPaul Mackerras if (nested) 75570ea13f6SPaul Mackerras need_tlb_flush = &nested->need_tlb_flush; 75670ea13f6SPaul Mackerras else 75770ea13f6SPaul Mackerras need_tlb_flush = &kvm->arch.need_tlb_flush; 75870ea13f6SPaul Mackerras 75970ea13f6SPaul Mackerras if (cpumask_test_cpu(pcpu, need_tlb_flush)) { 76070ea13f6SPaul Mackerras flush_guest_tlb(kvm); 7612940ba0cSPaul Mackerras 7622940ba0cSPaul Mackerras /* Clear the bit after the TLB flush */ 76370ea13f6SPaul Mackerras cpumask_clear_cpu(pcpu, need_tlb_flush); 7642940ba0cSPaul Mackerras } 7652940ba0cSPaul Mackerras } 76670ea13f6SPaul Mackerras EXPORT_SYMBOL_GPL(kvmppc_check_need_tlb_flush); 767