1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2aa04b4ccSPaul Mackerras /* 3aa04b4ccSPaul Mackerras * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com> 4aa04b4ccSPaul Mackerras */ 5aa04b4ccSPaul Mackerras 6441c19c8SMichael Ellerman #include <linux/cpu.h> 7aa04b4ccSPaul Mackerras #include <linux/kvm_host.h> 8aa04b4ccSPaul Mackerras #include <linux/preempt.h> 966b15db6SPaul Gortmaker #include <linux/export.h> 10aa04b4ccSPaul Mackerras #include <linux/sched.h> 11aa04b4ccSPaul Mackerras #include <linux/spinlock.h> 12aa04b4ccSPaul Mackerras #include <linux/init.h> 13fa61a4e3SAneesh Kumar K.V #include <linux/memblock.h> 14fa61a4e3SAneesh Kumar K.V #include <linux/sizes.h> 15fc95ca72SJoonsoo Kim #include <linux/cma.h> 1690fd09f8SSam Bobroff #include <linux/bitops.h> 17aa04b4ccSPaul Mackerras 187c1bd80cSNicholas Piggin #include <asm/asm-prototypes.h> 19aa04b4ccSPaul Mackerras #include <asm/cputable.h> 20aa04b4ccSPaul Mackerras #include <asm/kvm_ppc.h> 21aa04b4ccSPaul Mackerras #include <asm/kvm_book3s.h> 22e928e9cbSMichael Ellerman #include <asm/archrandom.h> 23eddb60fbSPaul Mackerras #include <asm/xics.h> 24243e2511SBenjamin Herrenschmidt #include <asm/xive.h> 2566feed61SPaul Mackerras #include <asm/dbell.h> 2666feed61SPaul Mackerras #include <asm/cputhreads.h> 2737f55d30SSuresh Warrier #include <asm/io.h> 28f725758bSPaul Mackerras #include <asm/opal.h> 29e2702871SPaul Mackerras #include <asm/smp.h> 30aa04b4ccSPaul Mackerras 31fc95ca72SJoonsoo Kim #define KVM_CMA_CHUNK_ORDER 18 32fc95ca72SJoonsoo Kim 335af50993SBenjamin Herrenschmidt #include "book3s_xics.h" 345af50993SBenjamin Herrenschmidt #include "book3s_xive.h" 355af50993SBenjamin Herrenschmidt 365af50993SBenjamin Herrenschmidt /* 375af50993SBenjamin Herrenschmidt * The XIVE module will populate these when it loads 385af50993SBenjamin Herrenschmidt */ 395af50993SBenjamin Herrenschmidt unsigned long (*__xive_vm_h_xirr)(struct kvm_vcpu *vcpu); 405af50993SBenjamin Herrenschmidt unsigned long (*__xive_vm_h_ipoll)(struct kvm_vcpu *vcpu, unsigned long server); 415af50993SBenjamin Herrenschmidt int (*__xive_vm_h_ipi)(struct kvm_vcpu *vcpu, unsigned long server, 425af50993SBenjamin Herrenschmidt unsigned long mfrr); 435af50993SBenjamin Herrenschmidt int (*__xive_vm_h_cppr)(struct kvm_vcpu *vcpu, unsigned long cppr); 445af50993SBenjamin Herrenschmidt int (*__xive_vm_h_eoi)(struct kvm_vcpu *vcpu, unsigned long xirr); 455af50993SBenjamin Herrenschmidt EXPORT_SYMBOL_GPL(__xive_vm_h_xirr); 465af50993SBenjamin Herrenschmidt EXPORT_SYMBOL_GPL(__xive_vm_h_ipoll); 475af50993SBenjamin Herrenschmidt EXPORT_SYMBOL_GPL(__xive_vm_h_ipi); 485af50993SBenjamin Herrenschmidt EXPORT_SYMBOL_GPL(__xive_vm_h_cppr); 495af50993SBenjamin Herrenschmidt EXPORT_SYMBOL_GPL(__xive_vm_h_eoi); 505af50993SBenjamin Herrenschmidt 51fa61a4e3SAneesh Kumar K.V /* 52fa61a4e3SAneesh Kumar K.V * Hash page table alignment on newer cpus(CPU_FTR_ARCH_206) 53fa61a4e3SAneesh Kumar K.V * should be power of 2. 54fa61a4e3SAneesh Kumar K.V */ 55fa61a4e3SAneesh Kumar K.V #define HPT_ALIGN_PAGES ((1 << 18) >> PAGE_SHIFT) /* 256k */ 56fa61a4e3SAneesh Kumar K.V /* 57fa61a4e3SAneesh Kumar K.V * By default we reserve 5% of memory for hash pagetable allocation. 58fa61a4e3SAneesh Kumar K.V */ 59fa61a4e3SAneesh Kumar K.V static unsigned long kvm_cma_resv_ratio = 5; 60aa04b4ccSPaul Mackerras 61fc95ca72SJoonsoo Kim static struct cma *kvm_cma; 62fc95ca72SJoonsoo Kim 63fa61a4e3SAneesh Kumar K.V static int __init early_parse_kvm_cma_resv(char *p) 64d2a1b483SAlexander Graf { 65fa61a4e3SAneesh Kumar K.V pr_debug("%s(%s)\n", __func__, p); 66d2a1b483SAlexander Graf if (!p) 67fa61a4e3SAneesh Kumar K.V return -EINVAL; 68fa61a4e3SAneesh Kumar K.V return kstrtoul(p, 0, &kvm_cma_resv_ratio); 69d2a1b483SAlexander Graf } 70fa61a4e3SAneesh Kumar K.V early_param("kvm_cma_resv_ratio", early_parse_kvm_cma_resv); 71d2a1b483SAlexander Graf 72db9a290dSDavid Gibson struct page *kvm_alloc_hpt_cma(unsigned long nr_pages) 73d2a1b483SAlexander Graf { 74c04fa583SAlexey Kardashevskiy VM_BUG_ON(order_base_2(nr_pages) < KVM_CMA_CHUNK_ORDER - PAGE_SHIFT); 75fc95ca72SJoonsoo Kim 76e2f466e3SLucas Stach return cma_alloc(kvm_cma, nr_pages, order_base_2(HPT_ALIGN_PAGES), 7765182029SMarek Szyprowski false); 78d2a1b483SAlexander Graf } 79db9a290dSDavid Gibson EXPORT_SYMBOL_GPL(kvm_alloc_hpt_cma); 80d2a1b483SAlexander Graf 81db9a290dSDavid Gibson void kvm_free_hpt_cma(struct page *page, unsigned long nr_pages) 82d2a1b483SAlexander Graf { 83fc95ca72SJoonsoo Kim cma_release(kvm_cma, page, nr_pages); 84d2a1b483SAlexander Graf } 85db9a290dSDavid Gibson EXPORT_SYMBOL_GPL(kvm_free_hpt_cma); 86d2a1b483SAlexander Graf 87fa61a4e3SAneesh Kumar K.V /** 88fa61a4e3SAneesh Kumar K.V * kvm_cma_reserve() - reserve area for kvm hash pagetable 89fa61a4e3SAneesh Kumar K.V * 90fa61a4e3SAneesh Kumar K.V * This function reserves memory from early allocator. It should be 9114ed7409SAnton Blanchard * called by arch specific code once the memblock allocator 92fa61a4e3SAneesh Kumar K.V * has been activated and all other subsystems have already allocated/reserved 93fa61a4e3SAneesh Kumar K.V * memory. 94fa61a4e3SAneesh Kumar K.V */ 95fa61a4e3SAneesh Kumar K.V void __init kvm_cma_reserve(void) 96fa61a4e3SAneesh Kumar K.V { 97fa61a4e3SAneesh Kumar K.V unsigned long align_size; 9804ba0a92SMike Rapoport phys_addr_t selected_size; 99cec26bc3SAneesh Kumar K.V 100cec26bc3SAneesh Kumar K.V /* 101cec26bc3SAneesh Kumar K.V * We need CMA reservation only when we are in HV mode 102cec26bc3SAneesh Kumar K.V */ 103cec26bc3SAneesh Kumar K.V if (!cpu_has_feature(CPU_FTR_HVMODE)) 104cec26bc3SAneesh Kumar K.V return; 105fa61a4e3SAneesh Kumar K.V 10604ba0a92SMike Rapoport selected_size = PAGE_ALIGN(memblock_phys_mem_size() * kvm_cma_resv_ratio / 100); 107fa61a4e3SAneesh Kumar K.V if (selected_size) { 108a5a8b258SAneesh Kumar K.V pr_info("%s: reserving %ld MiB for global area\n", __func__, 109fa61a4e3SAneesh Kumar K.V (unsigned long)selected_size / SZ_1M); 110fa61a4e3SAneesh Kumar K.V align_size = HPT_ALIGN_PAGES << PAGE_SHIFT; 111c1f733aaSJoonsoo Kim cma_declare_contiguous(0, selected_size, 0, align_size, 112f318dd08SLaura Abbott KVM_CMA_CHUNK_ORDER - PAGE_SHIFT, false, "kvm_cma", 113f318dd08SLaura Abbott &kvm_cma); 114fa61a4e3SAneesh Kumar K.V } 115fa61a4e3SAneesh Kumar K.V } 116441c19c8SMichael Ellerman 117441c19c8SMichael Ellerman /* 11890fd09f8SSam Bobroff * Real-mode H_CONFER implementation. 11990fd09f8SSam Bobroff * We check if we are the only vcpu out of this virtual core 12090fd09f8SSam Bobroff * still running in the guest and not ceded. If so, we pop up 12190fd09f8SSam Bobroff * to the virtual-mode implementation; if not, just return to 12290fd09f8SSam Bobroff * the guest. 12390fd09f8SSam Bobroff */ 12490fd09f8SSam Bobroff long int kvmppc_rm_h_confer(struct kvm_vcpu *vcpu, int target, 12590fd09f8SSam Bobroff unsigned int yield_count) 12690fd09f8SSam Bobroff { 127ec257165SPaul Mackerras struct kvmppc_vcore *vc = local_paca->kvm_hstate.kvm_vcore; 128ec257165SPaul Mackerras int ptid = local_paca->kvm_hstate.ptid; 12990fd09f8SSam Bobroff int threads_running; 13090fd09f8SSam Bobroff int threads_ceded; 13190fd09f8SSam Bobroff int threads_conferring; 13290fd09f8SSam Bobroff u64 stop = get_tb() + 10 * tb_ticks_per_usec; 13390fd09f8SSam Bobroff int rv = H_SUCCESS; /* => don't yield */ 13490fd09f8SSam Bobroff 135ec257165SPaul Mackerras set_bit(ptid, &vc->conferring_threads); 1367d6c40daSPaul Mackerras while ((get_tb() < stop) && !VCORE_IS_EXITING(vc)) { 1377d6c40daSPaul Mackerras threads_running = VCORE_ENTRY_MAP(vc); 1387d6c40daSPaul Mackerras threads_ceded = vc->napping_threads; 1397d6c40daSPaul Mackerras threads_conferring = vc->conferring_threads; 1407d6c40daSPaul Mackerras if ((threads_ceded | threads_conferring) == threads_running) { 14190fd09f8SSam Bobroff rv = H_TOO_HARD; /* => do yield */ 14290fd09f8SSam Bobroff break; 14390fd09f8SSam Bobroff } 14490fd09f8SSam Bobroff } 145ec257165SPaul Mackerras clear_bit(ptid, &vc->conferring_threads); 14690fd09f8SSam Bobroff return rv; 14790fd09f8SSam Bobroff } 14890fd09f8SSam Bobroff 14990fd09f8SSam Bobroff /* 150441c19c8SMichael Ellerman * When running HV mode KVM we need to block certain operations while KVM VMs 151441c19c8SMichael Ellerman * exist in the system. We use a counter of VMs to track this. 152441c19c8SMichael Ellerman * 153441c19c8SMichael Ellerman * One of the operations we need to block is onlining of secondaries, so we 154441c19c8SMichael Ellerman * protect hv_vm_count with get/put_online_cpus(). 155441c19c8SMichael Ellerman */ 156441c19c8SMichael Ellerman static atomic_t hv_vm_count; 157441c19c8SMichael Ellerman 158441c19c8SMichael Ellerman void kvm_hv_vm_activated(void) 159441c19c8SMichael Ellerman { 160441c19c8SMichael Ellerman get_online_cpus(); 161441c19c8SMichael Ellerman atomic_inc(&hv_vm_count); 162441c19c8SMichael Ellerman put_online_cpus(); 163441c19c8SMichael Ellerman } 164441c19c8SMichael Ellerman EXPORT_SYMBOL_GPL(kvm_hv_vm_activated); 165441c19c8SMichael Ellerman 166441c19c8SMichael Ellerman void kvm_hv_vm_deactivated(void) 167441c19c8SMichael Ellerman { 168441c19c8SMichael Ellerman get_online_cpus(); 169441c19c8SMichael Ellerman atomic_dec(&hv_vm_count); 170441c19c8SMichael Ellerman put_online_cpus(); 171441c19c8SMichael Ellerman } 172441c19c8SMichael Ellerman EXPORT_SYMBOL_GPL(kvm_hv_vm_deactivated); 173441c19c8SMichael Ellerman 174441c19c8SMichael Ellerman bool kvm_hv_mode_active(void) 175441c19c8SMichael Ellerman { 176441c19c8SMichael Ellerman return atomic_read(&hv_vm_count) != 0; 177441c19c8SMichael Ellerman } 178ae2113a4SPaul Mackerras 179ae2113a4SPaul Mackerras extern int hcall_real_table[], hcall_real_table_end[]; 180ae2113a4SPaul Mackerras 181ae2113a4SPaul Mackerras int kvmppc_hcall_impl_hv_realmode(unsigned long cmd) 182ae2113a4SPaul Mackerras { 183ae2113a4SPaul Mackerras cmd /= 4; 184ae2113a4SPaul Mackerras if (cmd < hcall_real_table_end - hcall_real_table && 185ae2113a4SPaul Mackerras hcall_real_table[cmd]) 186ae2113a4SPaul Mackerras return 1; 187ae2113a4SPaul Mackerras 188ae2113a4SPaul Mackerras return 0; 189ae2113a4SPaul Mackerras } 190ae2113a4SPaul Mackerras EXPORT_SYMBOL_GPL(kvmppc_hcall_impl_hv_realmode); 191e928e9cbSMichael Ellerman 192e928e9cbSMichael Ellerman int kvmppc_hwrng_present(void) 193e928e9cbSMichael Ellerman { 194e928e9cbSMichael Ellerman return powernv_hwrng_present(); 195e928e9cbSMichael Ellerman } 196e928e9cbSMichael Ellerman EXPORT_SYMBOL_GPL(kvmppc_hwrng_present); 197e928e9cbSMichael Ellerman 198e928e9cbSMichael Ellerman long kvmppc_h_random(struct kvm_vcpu *vcpu) 199e928e9cbSMichael Ellerman { 200acde2572SPaul Mackerras int r; 201acde2572SPaul Mackerras 202acde2572SPaul Mackerras /* Only need to do the expensive mfmsr() on radix */ 203acde2572SPaul Mackerras if (kvm_is_radix(vcpu->kvm) && (mfmsr() & MSR_IR)) 2041143a706SSimon Guo r = powernv_get_random_long(&vcpu->arch.regs.gpr[4]); 205acde2572SPaul Mackerras else 2061143a706SSimon Guo r = powernv_get_random_real_mode(&vcpu->arch.regs.gpr[4]); 207acde2572SPaul Mackerras if (r) 208e928e9cbSMichael Ellerman return H_SUCCESS; 209e928e9cbSMichael Ellerman 210e928e9cbSMichael Ellerman return H_HARDWARE; 211e928e9cbSMichael Ellerman } 212eddb60fbSPaul Mackerras 213eddb60fbSPaul Mackerras /* 21466feed61SPaul Mackerras * Send an interrupt or message to another CPU. 215eddb60fbSPaul Mackerras * The caller needs to include any barrier needed to order writes 216eddb60fbSPaul Mackerras * to memory vs. the IPI/message. 217eddb60fbSPaul Mackerras */ 218eddb60fbSPaul Mackerras void kvmhv_rm_send_ipi(int cpu) 219eddb60fbSPaul Mackerras { 220d381d7caSBenjamin Herrenschmidt void __iomem *xics_phys; 2211704a81cSPaul Mackerras unsigned long msg = PPC_DBELL_TYPE(PPC_DBELL_SERVER); 222eddb60fbSPaul Mackerras 223f3c18e93SPaul Mackerras /* For a nested hypervisor, use the XICS via hcall */ 224f3c18e93SPaul Mackerras if (kvmhv_on_pseries()) { 225f3c18e93SPaul Mackerras unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 226f3c18e93SPaul Mackerras 227f3c18e93SPaul Mackerras plpar_hcall_raw(H_IPI, retbuf, get_hard_smp_processor_id(cpu), 228f3c18e93SPaul Mackerras IPI_PRIORITY); 229f3c18e93SPaul Mackerras return; 230f3c18e93SPaul Mackerras } 231f3c18e93SPaul Mackerras 2321704a81cSPaul Mackerras /* On POWER9 we can use msgsnd for any destination cpu. */ 2331704a81cSPaul Mackerras if (cpu_has_feature(CPU_FTR_ARCH_300)) { 2341704a81cSPaul Mackerras msg |= get_hard_smp_processor_id(cpu); 2351704a81cSPaul Mackerras __asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg)); 2361704a81cSPaul Mackerras return; 2371704a81cSPaul Mackerras } 2385af50993SBenjamin Herrenschmidt 2391704a81cSPaul Mackerras /* On POWER8 for IPIs to threads in the same core, use msgsnd. */ 24066feed61SPaul Mackerras if (cpu_has_feature(CPU_FTR_ARCH_207S) && 24166feed61SPaul Mackerras cpu_first_thread_sibling(cpu) == 24266feed61SPaul Mackerras cpu_first_thread_sibling(raw_smp_processor_id())) { 24366feed61SPaul Mackerras msg |= cpu_thread_in_core(cpu); 24466feed61SPaul Mackerras __asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg)); 24566feed61SPaul Mackerras return; 24666feed61SPaul Mackerras } 24766feed61SPaul Mackerras 248243e2511SBenjamin Herrenschmidt /* We should never reach this */ 24903f95332SPaul Mackerras if (WARN_ON_ONCE(xics_on_xive())) 250243e2511SBenjamin Herrenschmidt return; 251243e2511SBenjamin Herrenschmidt 25266feed61SPaul Mackerras /* Else poke the target with an IPI */ 253d2e60075SNicholas Piggin xics_phys = paca_ptrs[cpu]->kvm_hstate.xics_phys; 254ab9bad0eSBenjamin Herrenschmidt if (xics_phys) 255d381d7caSBenjamin Herrenschmidt __raw_rm_writeb(IPI_PRIORITY, xics_phys + XICS_MFRR); 256f725758bSPaul Mackerras else 257ab9bad0eSBenjamin Herrenschmidt opal_int_set_mfrr(get_hard_smp_processor_id(cpu), IPI_PRIORITY); 258eddb60fbSPaul Mackerras } 259eddb60fbSPaul Mackerras 260eddb60fbSPaul Mackerras /* 261eddb60fbSPaul Mackerras * The following functions are called from the assembly code 262eddb60fbSPaul Mackerras * in book3s_hv_rmhandlers.S. 263eddb60fbSPaul Mackerras */ 264eddb60fbSPaul Mackerras static void kvmhv_interrupt_vcore(struct kvmppc_vcore *vc, int active) 265eddb60fbSPaul Mackerras { 266eddb60fbSPaul Mackerras int cpu = vc->pcpu; 267eddb60fbSPaul Mackerras 268eddb60fbSPaul Mackerras /* Order setting of exit map vs. msgsnd/IPI */ 269eddb60fbSPaul Mackerras smp_mb(); 270eddb60fbSPaul Mackerras for (; active; active >>= 1, ++cpu) 271eddb60fbSPaul Mackerras if (active & 1) 272eddb60fbSPaul Mackerras kvmhv_rm_send_ipi(cpu); 273eddb60fbSPaul Mackerras } 274eddb60fbSPaul Mackerras 275eddb60fbSPaul Mackerras void kvmhv_commence_exit(int trap) 276eddb60fbSPaul Mackerras { 277eddb60fbSPaul Mackerras struct kvmppc_vcore *vc = local_paca->kvm_hstate.kvm_vcore; 278eddb60fbSPaul Mackerras int ptid = local_paca->kvm_hstate.ptid; 279b4deba5cSPaul Mackerras struct kvm_split_mode *sip = local_paca->kvm_hstate.kvm_split_mode; 280*b1b1697aSNicholas Piggin int me, ee, i; 281eddb60fbSPaul Mackerras 282eddb60fbSPaul Mackerras /* Set our bit in the threads-exiting-guest map in the 0xff00 283eddb60fbSPaul Mackerras bits of vcore->entry_exit_map */ 284eddb60fbSPaul Mackerras me = 0x100 << ptid; 285eddb60fbSPaul Mackerras do { 286eddb60fbSPaul Mackerras ee = vc->entry_exit_map; 287eddb60fbSPaul Mackerras } while (cmpxchg(&vc->entry_exit_map, ee, ee | me) != ee); 288eddb60fbSPaul Mackerras 289eddb60fbSPaul Mackerras /* Are we the first here? */ 290eddb60fbSPaul Mackerras if ((ee >> 8) != 0) 291eddb60fbSPaul Mackerras return; 292eddb60fbSPaul Mackerras 293eddb60fbSPaul Mackerras /* 294eddb60fbSPaul Mackerras * Trigger the other threads in this vcore to exit the guest. 295eddb60fbSPaul Mackerras * If this is a hypervisor decrementer interrupt then they 296eddb60fbSPaul Mackerras * will be already on their way out of the guest. 297eddb60fbSPaul Mackerras */ 298eddb60fbSPaul Mackerras if (trap != BOOK3S_INTERRUPT_HV_DECREMENTER) 299eddb60fbSPaul Mackerras kvmhv_interrupt_vcore(vc, ee & ~(1 << ptid)); 300b4deba5cSPaul Mackerras 301b4deba5cSPaul Mackerras /* 302b4deba5cSPaul Mackerras * If we are doing dynamic micro-threading, interrupt the other 303b4deba5cSPaul Mackerras * subcores to pull them out of their guests too. 304b4deba5cSPaul Mackerras */ 305b4deba5cSPaul Mackerras if (!sip) 306b4deba5cSPaul Mackerras return; 307b4deba5cSPaul Mackerras 308b4deba5cSPaul Mackerras for (i = 0; i < MAX_SUBCORES; ++i) { 309898b25b2SPaul Mackerras vc = sip->vc[i]; 310b4deba5cSPaul Mackerras if (!vc) 311b4deba5cSPaul Mackerras break; 312b4deba5cSPaul Mackerras do { 313b4deba5cSPaul Mackerras ee = vc->entry_exit_map; 314b4deba5cSPaul Mackerras /* Already asked to exit? */ 315b4deba5cSPaul Mackerras if ((ee >> 8) != 0) 316b4deba5cSPaul Mackerras break; 317b4deba5cSPaul Mackerras } while (cmpxchg(&vc->entry_exit_map, ee, 318b4deba5cSPaul Mackerras ee | VCORE_EXIT_REQ) != ee); 319b4deba5cSPaul Mackerras if ((ee >> 8) == 0) 320b4deba5cSPaul Mackerras kvmhv_interrupt_vcore(vc, ee); 321b4deba5cSPaul Mackerras } 322eddb60fbSPaul Mackerras } 32379b6c247SSuresh Warrier 32479b6c247SSuresh Warrier struct kvmppc_host_rm_ops *kvmppc_host_rm_ops_hv; 32579b6c247SSuresh Warrier EXPORT_SYMBOL_GPL(kvmppc_host_rm_ops_hv); 32637f55d30SSuresh Warrier 327e3c13e56SSuresh Warrier #ifdef CONFIG_KVM_XICS 328e3c13e56SSuresh Warrier static struct kvmppc_irq_map *get_irqmap(struct kvmppc_passthru_irqmap *pimap, 329e3c13e56SSuresh Warrier u32 xisr) 330e3c13e56SSuresh Warrier { 331e3c13e56SSuresh Warrier int i; 332e3c13e56SSuresh Warrier 333e3c13e56SSuresh Warrier /* 334e3c13e56SSuresh Warrier * We access the mapped array here without a lock. That 335e3c13e56SSuresh Warrier * is safe because we never reduce the number of entries 336e3c13e56SSuresh Warrier * in the array and we never change the v_hwirq field of 337e3c13e56SSuresh Warrier * an entry once it is set. 338e3c13e56SSuresh Warrier * 339e3c13e56SSuresh Warrier * We have also carefully ordered the stores in the writer 340e3c13e56SSuresh Warrier * and the loads here in the reader, so that if we find a matching 341e3c13e56SSuresh Warrier * hwirq here, the associated GSI and irq_desc fields are valid. 342e3c13e56SSuresh Warrier */ 343e3c13e56SSuresh Warrier for (i = 0; i < pimap->n_mapped; i++) { 344e3c13e56SSuresh Warrier if (xisr == pimap->mapped[i].r_hwirq) { 345e3c13e56SSuresh Warrier /* 346e3c13e56SSuresh Warrier * Order subsequent reads in the caller to serialize 347e3c13e56SSuresh Warrier * with the writer. 348e3c13e56SSuresh Warrier */ 349e3c13e56SSuresh Warrier smp_rmb(); 350e3c13e56SSuresh Warrier return &pimap->mapped[i]; 351e3c13e56SSuresh Warrier } 352e3c13e56SSuresh Warrier } 353e3c13e56SSuresh Warrier return NULL; 354e3c13e56SSuresh Warrier } 355e3c13e56SSuresh Warrier 356e3c13e56SSuresh Warrier /* 357e3c13e56SSuresh Warrier * If we have an interrupt that's not an IPI, check if we have a 358e3c13e56SSuresh Warrier * passthrough adapter and if so, check if this external interrupt 359e3c13e56SSuresh Warrier * is for the adapter. 360e3c13e56SSuresh Warrier * We will attempt to deliver the IRQ directly to the target VCPU's 361e3c13e56SSuresh Warrier * ICP, the virtual ICP (based on affinity - the xive value in ICS). 362e3c13e56SSuresh Warrier * 363e3c13e56SSuresh Warrier * If the delivery fails or if this is not for a passthrough adapter, 364e3c13e56SSuresh Warrier * return to the host to handle this interrupt. We earlier 365e3c13e56SSuresh Warrier * saved a copy of the XIRR in the PACA, it will be picked up by 366e3c13e56SSuresh Warrier * the host ICP driver. 367e3c13e56SSuresh Warrier */ 368f725758bSPaul Mackerras static int kvmppc_check_passthru(u32 xisr, __be32 xirr, bool *again) 369e3c13e56SSuresh Warrier { 370e3c13e56SSuresh Warrier struct kvmppc_passthru_irqmap *pimap; 371e3c13e56SSuresh Warrier struct kvmppc_irq_map *irq_map; 372e3c13e56SSuresh Warrier struct kvm_vcpu *vcpu; 373e3c13e56SSuresh Warrier 374e3c13e56SSuresh Warrier vcpu = local_paca->kvm_hstate.kvm_vcpu; 375e3c13e56SSuresh Warrier if (!vcpu) 376e3c13e56SSuresh Warrier return 1; 377e3c13e56SSuresh Warrier pimap = kvmppc_get_passthru_irqmap(vcpu->kvm); 378e3c13e56SSuresh Warrier if (!pimap) 379e3c13e56SSuresh Warrier return 1; 380e3c13e56SSuresh Warrier irq_map = get_irqmap(pimap, xisr); 381e3c13e56SSuresh Warrier if (!irq_map) 382e3c13e56SSuresh Warrier return 1; 383e3c13e56SSuresh Warrier 384e3c13e56SSuresh Warrier /* We're handling this interrupt, generic code doesn't need to */ 385e3c13e56SSuresh Warrier local_paca->kvm_hstate.saved_xirr = 0; 386e3c13e56SSuresh Warrier 387f725758bSPaul Mackerras return kvmppc_deliver_irq_passthru(vcpu, xirr, irq_map, pimap, again); 388e3c13e56SSuresh Warrier } 389e3c13e56SSuresh Warrier 390e3c13e56SSuresh Warrier #else 391e2702871SPaul Mackerras static inline int kvmppc_check_passthru(u32 xisr, __be32 xirr, bool *again) 392e3c13e56SSuresh Warrier { 393e3c13e56SSuresh Warrier return 1; 394e3c13e56SSuresh Warrier } 395e3c13e56SSuresh Warrier #endif 396e3c13e56SSuresh Warrier 39737f55d30SSuresh Warrier /* 39837f55d30SSuresh Warrier * Determine what sort of external interrupt is pending (if any). 39937f55d30SSuresh Warrier * Returns: 40037f55d30SSuresh Warrier * 0 if no interrupt is pending 40137f55d30SSuresh Warrier * 1 if an interrupt is pending that needs to be handled by the host 402f7af5209SSuresh Warrier * 2 Passthrough that needs completion in the host 40337f55d30SSuresh Warrier * -1 if there was a guest wakeup IPI (which has now been cleared) 404e3c13e56SSuresh Warrier * -2 if there is PCI passthrough external interrupt that was handled 40537f55d30SSuresh Warrier */ 406f725758bSPaul Mackerras static long kvmppc_read_one_intr(bool *again); 40737f55d30SSuresh Warrier 40837f55d30SSuresh Warrier long kvmppc_read_intr(void) 40937f55d30SSuresh Warrier { 410f725758bSPaul Mackerras long ret = 0; 411f725758bSPaul Mackerras long rc; 412f725758bSPaul Mackerras bool again; 413f725758bSPaul Mackerras 414243e2511SBenjamin Herrenschmidt if (xive_enabled()) 415243e2511SBenjamin Herrenschmidt return 1; 416243e2511SBenjamin Herrenschmidt 417f725758bSPaul Mackerras do { 418f725758bSPaul Mackerras again = false; 419f725758bSPaul Mackerras rc = kvmppc_read_one_intr(&again); 420f725758bSPaul Mackerras if (rc && (ret == 0 || rc > ret)) 421f725758bSPaul Mackerras ret = rc; 422f725758bSPaul Mackerras } while (again); 423f725758bSPaul Mackerras return ret; 424f725758bSPaul Mackerras } 425f725758bSPaul Mackerras 426f725758bSPaul Mackerras static long kvmppc_read_one_intr(bool *again) 427f725758bSPaul Mackerras { 428d381d7caSBenjamin Herrenschmidt void __iomem *xics_phys; 42937f55d30SSuresh Warrier u32 h_xirr; 43037f55d30SSuresh Warrier __be32 xirr; 43137f55d30SSuresh Warrier u32 xisr; 43237f55d30SSuresh Warrier u8 host_ipi; 433f725758bSPaul Mackerras int64_t rc; 43437f55d30SSuresh Warrier 4355af50993SBenjamin Herrenschmidt if (xive_enabled()) 4365af50993SBenjamin Herrenschmidt return 1; 4375af50993SBenjamin Herrenschmidt 43837f55d30SSuresh Warrier /* see if a host IPI is pending */ 43937f55d30SSuresh Warrier host_ipi = local_paca->kvm_hstate.host_ipi; 44037f55d30SSuresh Warrier if (host_ipi) 44137f55d30SSuresh Warrier return 1; 44237f55d30SSuresh Warrier 44337f55d30SSuresh Warrier /* Now read the interrupt from the ICP */ 444f3c18e93SPaul Mackerras if (kvmhv_on_pseries()) { 445f3c18e93SPaul Mackerras unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 446f3c18e93SPaul Mackerras 447f3c18e93SPaul Mackerras rc = plpar_hcall_raw(H_XIRR, retbuf, 0xFF); 448f3c18e93SPaul Mackerras xirr = cpu_to_be32(retbuf[0]); 449f3c18e93SPaul Mackerras } else { 45037f55d30SSuresh Warrier xics_phys = local_paca->kvm_hstate.xics_phys; 45153af3ba2SPaul Mackerras rc = 0; 452ab9bad0eSBenjamin Herrenschmidt if (!xics_phys) 45353af3ba2SPaul Mackerras rc = opal_int_get_xirr(&xirr, false); 45453af3ba2SPaul Mackerras else 455d381d7caSBenjamin Herrenschmidt xirr = __raw_rm_readl(xics_phys + XICS_XIRR); 456f3c18e93SPaul Mackerras } 457f725758bSPaul Mackerras if (rc < 0) 45837f55d30SSuresh Warrier return 1; 45937f55d30SSuresh Warrier 46037f55d30SSuresh Warrier /* 46137f55d30SSuresh Warrier * Save XIRR for later. Since we get control in reverse endian 46237f55d30SSuresh Warrier * on LE systems, save it byte reversed and fetch it back in 46337f55d30SSuresh Warrier * host endian. Note that xirr is the value read from the 46437f55d30SSuresh Warrier * XIRR register, while h_xirr is the host endian version. 46537f55d30SSuresh Warrier */ 46637f55d30SSuresh Warrier h_xirr = be32_to_cpu(xirr); 46737f55d30SSuresh Warrier local_paca->kvm_hstate.saved_xirr = h_xirr; 46837f55d30SSuresh Warrier xisr = h_xirr & 0xffffff; 46937f55d30SSuresh Warrier /* 47037f55d30SSuresh Warrier * Ensure that the store/load complete to guarantee all side 47137f55d30SSuresh Warrier * effects of loading from XIRR has completed 47237f55d30SSuresh Warrier */ 47337f55d30SSuresh Warrier smp_mb(); 47437f55d30SSuresh Warrier 47537f55d30SSuresh Warrier /* if nothing pending in the ICP */ 47637f55d30SSuresh Warrier if (!xisr) 47737f55d30SSuresh Warrier return 0; 47837f55d30SSuresh Warrier 47937f55d30SSuresh Warrier /* We found something in the ICP... 48037f55d30SSuresh Warrier * 48137f55d30SSuresh Warrier * If it is an IPI, clear the MFRR and EOI it. 48237f55d30SSuresh Warrier */ 48337f55d30SSuresh Warrier if (xisr == XICS_IPI) { 48453af3ba2SPaul Mackerras rc = 0; 485f3c18e93SPaul Mackerras if (kvmhv_on_pseries()) { 486f3c18e93SPaul Mackerras unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 487f3c18e93SPaul Mackerras 488f3c18e93SPaul Mackerras plpar_hcall_raw(H_IPI, retbuf, 489f3c18e93SPaul Mackerras hard_smp_processor_id(), 0xff); 490f3c18e93SPaul Mackerras plpar_hcall_raw(H_EOI, retbuf, h_xirr); 491f3c18e93SPaul Mackerras } else if (xics_phys) { 492d381d7caSBenjamin Herrenschmidt __raw_rm_writeb(0xff, xics_phys + XICS_MFRR); 493d381d7caSBenjamin Herrenschmidt __raw_rm_writel(xirr, xics_phys + XICS_XIRR); 494f725758bSPaul Mackerras } else { 495ab9bad0eSBenjamin Herrenschmidt opal_int_set_mfrr(hard_smp_processor_id(), 0xff); 496ab9bad0eSBenjamin Herrenschmidt rc = opal_int_eoi(h_xirr); 49753af3ba2SPaul Mackerras } 498f725758bSPaul Mackerras /* If rc > 0, there is another interrupt pending */ 499f725758bSPaul Mackerras *again = rc > 0; 500f725758bSPaul Mackerras 50137f55d30SSuresh Warrier /* 50237f55d30SSuresh Warrier * Need to ensure side effects of above stores 50337f55d30SSuresh Warrier * complete before proceeding. 50437f55d30SSuresh Warrier */ 50537f55d30SSuresh Warrier smp_mb(); 50637f55d30SSuresh Warrier 50737f55d30SSuresh Warrier /* 50837f55d30SSuresh Warrier * We need to re-check host IPI now in case it got set in the 50937f55d30SSuresh Warrier * meantime. If it's clear, we bounce the interrupt to the 51037f55d30SSuresh Warrier * guest 51137f55d30SSuresh Warrier */ 51237f55d30SSuresh Warrier host_ipi = local_paca->kvm_hstate.host_ipi; 51337f55d30SSuresh Warrier if (unlikely(host_ipi != 0)) { 51437f55d30SSuresh Warrier /* We raced with the host, 51537f55d30SSuresh Warrier * we need to resend that IPI, bummer 51637f55d30SSuresh Warrier */ 517f3c18e93SPaul Mackerras if (kvmhv_on_pseries()) { 518f3c18e93SPaul Mackerras unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 519f3c18e93SPaul Mackerras 520f3c18e93SPaul Mackerras plpar_hcall_raw(H_IPI, retbuf, 521f3c18e93SPaul Mackerras hard_smp_processor_id(), 522f3c18e93SPaul Mackerras IPI_PRIORITY); 523f3c18e93SPaul Mackerras } else if (xics_phys) 524d381d7caSBenjamin Herrenschmidt __raw_rm_writeb(IPI_PRIORITY, 525d381d7caSBenjamin Herrenschmidt xics_phys + XICS_MFRR); 526f725758bSPaul Mackerras else 527ab9bad0eSBenjamin Herrenschmidt opal_int_set_mfrr(hard_smp_processor_id(), 528f725758bSPaul Mackerras IPI_PRIORITY); 52937f55d30SSuresh Warrier /* Let side effects complete */ 53037f55d30SSuresh Warrier smp_mb(); 53137f55d30SSuresh Warrier return 1; 53237f55d30SSuresh Warrier } 53337f55d30SSuresh Warrier 53437f55d30SSuresh Warrier /* OK, it's an IPI for us */ 53537f55d30SSuresh Warrier local_paca->kvm_hstate.saved_xirr = 0; 53637f55d30SSuresh Warrier return -1; 53737f55d30SSuresh Warrier } 53837f55d30SSuresh Warrier 539f725758bSPaul Mackerras return kvmppc_check_passthru(xisr, xirr, again); 54037f55d30SSuresh Warrier } 5415af50993SBenjamin Herrenschmidt 5425af50993SBenjamin Herrenschmidt #ifdef CONFIG_KVM_XICS 5435af50993SBenjamin Herrenschmidt static inline bool is_rm(void) 5445af50993SBenjamin Herrenschmidt { 5455af50993SBenjamin Herrenschmidt return !(mfmsr() & MSR_DR); 5465af50993SBenjamin Herrenschmidt } 5475af50993SBenjamin Herrenschmidt 5485af50993SBenjamin Herrenschmidt unsigned long kvmppc_rm_h_xirr(struct kvm_vcpu *vcpu) 5495af50993SBenjamin Herrenschmidt { 55000bb6ae5SPaul Mackerras if (!kvmppc_xics_enabled(vcpu)) 55100bb6ae5SPaul Mackerras return H_TOO_HARD; 55203f95332SPaul Mackerras if (xics_on_xive()) { 5535af50993SBenjamin Herrenschmidt if (is_rm()) 5545af50993SBenjamin Herrenschmidt return xive_rm_h_xirr(vcpu); 5555af50993SBenjamin Herrenschmidt if (unlikely(!__xive_vm_h_xirr)) 5565af50993SBenjamin Herrenschmidt return H_NOT_AVAILABLE; 5575af50993SBenjamin Herrenschmidt return __xive_vm_h_xirr(vcpu); 5585af50993SBenjamin Herrenschmidt } else 5595af50993SBenjamin Herrenschmidt return xics_rm_h_xirr(vcpu); 5605af50993SBenjamin Herrenschmidt } 5615af50993SBenjamin Herrenschmidt 5625af50993SBenjamin Herrenschmidt unsigned long kvmppc_rm_h_xirr_x(struct kvm_vcpu *vcpu) 5635af50993SBenjamin Herrenschmidt { 56400bb6ae5SPaul Mackerras if (!kvmppc_xics_enabled(vcpu)) 56500bb6ae5SPaul Mackerras return H_TOO_HARD; 5661143a706SSimon Guo vcpu->arch.regs.gpr[5] = get_tb(); 56703f95332SPaul Mackerras if (xics_on_xive()) { 5685af50993SBenjamin Herrenschmidt if (is_rm()) 5695af50993SBenjamin Herrenschmidt return xive_rm_h_xirr(vcpu); 5705af50993SBenjamin Herrenschmidt if (unlikely(!__xive_vm_h_xirr)) 5715af50993SBenjamin Herrenschmidt return H_NOT_AVAILABLE; 5725af50993SBenjamin Herrenschmidt return __xive_vm_h_xirr(vcpu); 5735af50993SBenjamin Herrenschmidt } else 5745af50993SBenjamin Herrenschmidt return xics_rm_h_xirr(vcpu); 5755af50993SBenjamin Herrenschmidt } 5765af50993SBenjamin Herrenschmidt 5775af50993SBenjamin Herrenschmidt unsigned long kvmppc_rm_h_ipoll(struct kvm_vcpu *vcpu, unsigned long server) 5785af50993SBenjamin Herrenschmidt { 57900bb6ae5SPaul Mackerras if (!kvmppc_xics_enabled(vcpu)) 58000bb6ae5SPaul Mackerras return H_TOO_HARD; 58103f95332SPaul Mackerras if (xics_on_xive()) { 5825af50993SBenjamin Herrenschmidt if (is_rm()) 5835af50993SBenjamin Herrenschmidt return xive_rm_h_ipoll(vcpu, server); 5845af50993SBenjamin Herrenschmidt if (unlikely(!__xive_vm_h_ipoll)) 5855af50993SBenjamin Herrenschmidt return H_NOT_AVAILABLE; 5865af50993SBenjamin Herrenschmidt return __xive_vm_h_ipoll(vcpu, server); 5875af50993SBenjamin Herrenschmidt } else 5885af50993SBenjamin Herrenschmidt return H_TOO_HARD; 5895af50993SBenjamin Herrenschmidt } 5905af50993SBenjamin Herrenschmidt 5915af50993SBenjamin Herrenschmidt int kvmppc_rm_h_ipi(struct kvm_vcpu *vcpu, unsigned long server, 5925af50993SBenjamin Herrenschmidt unsigned long mfrr) 5935af50993SBenjamin Herrenschmidt { 59400bb6ae5SPaul Mackerras if (!kvmppc_xics_enabled(vcpu)) 59500bb6ae5SPaul Mackerras return H_TOO_HARD; 59603f95332SPaul Mackerras if (xics_on_xive()) { 5975af50993SBenjamin Herrenschmidt if (is_rm()) 5985af50993SBenjamin Herrenschmidt return xive_rm_h_ipi(vcpu, server, mfrr); 5995af50993SBenjamin Herrenschmidt if (unlikely(!__xive_vm_h_ipi)) 6005af50993SBenjamin Herrenschmidt return H_NOT_AVAILABLE; 6015af50993SBenjamin Herrenschmidt return __xive_vm_h_ipi(vcpu, server, mfrr); 6025af50993SBenjamin Herrenschmidt } else 6035af50993SBenjamin Herrenschmidt return xics_rm_h_ipi(vcpu, server, mfrr); 6045af50993SBenjamin Herrenschmidt } 6055af50993SBenjamin Herrenschmidt 6065af50993SBenjamin Herrenschmidt int kvmppc_rm_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr) 6075af50993SBenjamin Herrenschmidt { 60800bb6ae5SPaul Mackerras if (!kvmppc_xics_enabled(vcpu)) 60900bb6ae5SPaul Mackerras return H_TOO_HARD; 61003f95332SPaul Mackerras if (xics_on_xive()) { 6115af50993SBenjamin Herrenschmidt if (is_rm()) 6125af50993SBenjamin Herrenschmidt return xive_rm_h_cppr(vcpu, cppr); 6135af50993SBenjamin Herrenschmidt if (unlikely(!__xive_vm_h_cppr)) 6145af50993SBenjamin Herrenschmidt return H_NOT_AVAILABLE; 6155af50993SBenjamin Herrenschmidt return __xive_vm_h_cppr(vcpu, cppr); 6165af50993SBenjamin Herrenschmidt } else 6175af50993SBenjamin Herrenschmidt return xics_rm_h_cppr(vcpu, cppr); 6185af50993SBenjamin Herrenschmidt } 6195af50993SBenjamin Herrenschmidt 6205af50993SBenjamin Herrenschmidt int kvmppc_rm_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr) 6215af50993SBenjamin Herrenschmidt { 62200bb6ae5SPaul Mackerras if (!kvmppc_xics_enabled(vcpu)) 62300bb6ae5SPaul Mackerras return H_TOO_HARD; 62403f95332SPaul Mackerras if (xics_on_xive()) { 6255af50993SBenjamin Herrenschmidt if (is_rm()) 6265af50993SBenjamin Herrenschmidt return xive_rm_h_eoi(vcpu, xirr); 6275af50993SBenjamin Herrenschmidt if (unlikely(!__xive_vm_h_eoi)) 6285af50993SBenjamin Herrenschmidt return H_NOT_AVAILABLE; 6295af50993SBenjamin Herrenschmidt return __xive_vm_h_eoi(vcpu, xirr); 6305af50993SBenjamin Herrenschmidt } else 6315af50993SBenjamin Herrenschmidt return xics_rm_h_eoi(vcpu, xirr); 6325af50993SBenjamin Herrenschmidt } 6335af50993SBenjamin Herrenschmidt #endif /* CONFIG_KVM_XICS */ 634857b99e1SPaul Mackerras 635857b99e1SPaul Mackerras void kvmppc_bad_interrupt(struct pt_regs *regs) 636857b99e1SPaul Mackerras { 6377c1bd80cSNicholas Piggin /* 6387c1bd80cSNicholas Piggin * 100 could happen at any time, 200 can happen due to invalid real 6397c1bd80cSNicholas Piggin * address access for example (or any time due to a hardware problem). 6407c1bd80cSNicholas Piggin */ 6417c1bd80cSNicholas Piggin if (TRAP(regs) == 0x100) { 6427c1bd80cSNicholas Piggin get_paca()->in_nmi++; 6437c1bd80cSNicholas Piggin system_reset_exception(regs); 6447c1bd80cSNicholas Piggin get_paca()->in_nmi--; 6457c1bd80cSNicholas Piggin } else if (TRAP(regs) == 0x200) { 6467c1bd80cSNicholas Piggin machine_check_exception(regs); 6477c1bd80cSNicholas Piggin } else { 648857b99e1SPaul Mackerras die("Bad interrupt in KVM entry/exit code", regs, SIGABRT); 6497c1bd80cSNicholas Piggin } 650857b99e1SPaul Mackerras panic("Bad KVM trap"); 651857b99e1SPaul Mackerras } 652c0101509SPaul Mackerras 653268f4ef9SNicholas Piggin static void kvmppc_end_cede(struct kvm_vcpu *vcpu) 654268f4ef9SNicholas Piggin { 655268f4ef9SNicholas Piggin vcpu->arch.ceded = 0; 656268f4ef9SNicholas Piggin if (vcpu->arch.timer_running) { 657268f4ef9SNicholas Piggin hrtimer_try_to_cancel(&vcpu->arch.dec_timer); 658268f4ef9SNicholas Piggin vcpu->arch.timer_running = 0; 659268f4ef9SNicholas Piggin } 660268f4ef9SNicholas Piggin } 661268f4ef9SNicholas Piggin 662268f4ef9SNicholas Piggin void kvmppc_set_msr_hv(struct kvm_vcpu *vcpu, u64 msr) 663268f4ef9SNicholas Piggin { 664268f4ef9SNicholas Piggin /* 665268f4ef9SNicholas Piggin * Check for illegal transactional state bit combination 666268f4ef9SNicholas Piggin * and if we find it, force the TS field to a safe state. 667268f4ef9SNicholas Piggin */ 668268f4ef9SNicholas Piggin if ((msr & MSR_TS_MASK) == MSR_TS_MASK) 669268f4ef9SNicholas Piggin msr &= ~MSR_TS_MASK; 670268f4ef9SNicholas Piggin vcpu->arch.shregs.msr = msr; 671268f4ef9SNicholas Piggin kvmppc_end_cede(vcpu); 672268f4ef9SNicholas Piggin } 673268f4ef9SNicholas Piggin EXPORT_SYMBOL_GPL(kvmppc_set_msr_hv); 674268f4ef9SNicholas Piggin 675268f4ef9SNicholas Piggin static void inject_interrupt(struct kvm_vcpu *vcpu, int vec, u64 srr1_flags) 676268f4ef9SNicholas Piggin { 677268f4ef9SNicholas Piggin unsigned long msr, pc, new_msr, new_pc; 678268f4ef9SNicholas Piggin 679268f4ef9SNicholas Piggin msr = kvmppc_get_msr(vcpu); 680268f4ef9SNicholas Piggin pc = kvmppc_get_pc(vcpu); 681268f4ef9SNicholas Piggin new_msr = vcpu->arch.intr_msr; 682268f4ef9SNicholas Piggin new_pc = vec; 683268f4ef9SNicholas Piggin 684268f4ef9SNicholas Piggin /* If transactional, change to suspend mode on IRQ delivery */ 685268f4ef9SNicholas Piggin if (MSR_TM_TRANSACTIONAL(msr)) 686268f4ef9SNicholas Piggin new_msr |= MSR_TS_S; 687268f4ef9SNicholas Piggin else 688268f4ef9SNicholas Piggin new_msr |= msr & MSR_TS_MASK; 689268f4ef9SNicholas Piggin 6906a13cb0cSNicholas Piggin /* 6916a13cb0cSNicholas Piggin * Perform MSR and PC adjustment for LPCR[AIL]=3 if it is set and 6926a13cb0cSNicholas Piggin * applicable. AIL=2 is not supported. 6936a13cb0cSNicholas Piggin * 6946a13cb0cSNicholas Piggin * AIL does not apply to SRESET, MCE, or HMI (which is never 6956a13cb0cSNicholas Piggin * delivered to the guest), and does not apply if IR=0 or DR=0. 6966a13cb0cSNicholas Piggin */ 6976a13cb0cSNicholas Piggin if (vec != BOOK3S_INTERRUPT_SYSTEM_RESET && 6986a13cb0cSNicholas Piggin vec != BOOK3S_INTERRUPT_MACHINE_CHECK && 6996a13cb0cSNicholas Piggin (vcpu->arch.vcore->lpcr & LPCR_AIL) == LPCR_AIL_3 && 7006a13cb0cSNicholas Piggin (msr & (MSR_IR|MSR_DR)) == (MSR_IR|MSR_DR) ) { 7016a13cb0cSNicholas Piggin new_msr |= MSR_IR | MSR_DR; 7026a13cb0cSNicholas Piggin new_pc += 0xC000000000004000ULL; 7036a13cb0cSNicholas Piggin } 7046a13cb0cSNicholas Piggin 705268f4ef9SNicholas Piggin kvmppc_set_srr0(vcpu, pc); 706268f4ef9SNicholas Piggin kvmppc_set_srr1(vcpu, (msr & SRR1_MSR_BITS) | srr1_flags); 707268f4ef9SNicholas Piggin kvmppc_set_pc(vcpu, new_pc); 708268f4ef9SNicholas Piggin vcpu->arch.shregs.msr = new_msr; 709268f4ef9SNicholas Piggin } 710268f4ef9SNicholas Piggin 711268f4ef9SNicholas Piggin void kvmppc_inject_interrupt_hv(struct kvm_vcpu *vcpu, int vec, u64 srr1_flags) 712268f4ef9SNicholas Piggin { 713268f4ef9SNicholas Piggin inject_interrupt(vcpu, vec, srr1_flags); 714268f4ef9SNicholas Piggin kvmppc_end_cede(vcpu); 715268f4ef9SNicholas Piggin } 716268f4ef9SNicholas Piggin EXPORT_SYMBOL_GPL(kvmppc_inject_interrupt_hv); 717268f4ef9SNicholas Piggin 718f7035ce9SPaul Mackerras /* 719f7035ce9SPaul Mackerras * Is there a PRIV_DOORBELL pending for the guest (on POWER9)? 720f7035ce9SPaul Mackerras * Can we inject a Decrementer or a External interrupt? 721f7035ce9SPaul Mackerras */ 722f7035ce9SPaul Mackerras void kvmppc_guest_entry_inject_int(struct kvm_vcpu *vcpu) 723f7035ce9SPaul Mackerras { 724f7035ce9SPaul Mackerras int ext; 725f7035ce9SPaul Mackerras unsigned long lpcr; 726f7035ce9SPaul Mackerras 727f7035ce9SPaul Mackerras /* Insert EXTERNAL bit into LPCR at the MER bit position */ 728f7035ce9SPaul Mackerras ext = (vcpu->arch.pending_exceptions >> BOOK3S_IRQPRIO_EXTERNAL) & 1; 729f7035ce9SPaul Mackerras lpcr = mfspr(SPRN_LPCR); 730f7035ce9SPaul Mackerras lpcr |= ext << LPCR_MER_SH; 731f7035ce9SPaul Mackerras mtspr(SPRN_LPCR, lpcr); 732f7035ce9SPaul Mackerras isync(); 733f7035ce9SPaul Mackerras 734f7035ce9SPaul Mackerras if (vcpu->arch.shregs.msr & MSR_EE) { 735f7035ce9SPaul Mackerras if (ext) { 736268f4ef9SNicholas Piggin inject_interrupt(vcpu, BOOK3S_INTERRUPT_EXTERNAL, 0); 737f7035ce9SPaul Mackerras } else { 738f7035ce9SPaul Mackerras long int dec = mfspr(SPRN_DEC); 739f7035ce9SPaul Mackerras if (!(lpcr & LPCR_LD)) 740f7035ce9SPaul Mackerras dec = (int) dec; 741f7035ce9SPaul Mackerras if (dec < 0) 742268f4ef9SNicholas Piggin inject_interrupt(vcpu, 743268f4ef9SNicholas Piggin BOOK3S_INTERRUPT_DECREMENTER, 0); 744f7035ce9SPaul Mackerras } 745f7035ce9SPaul Mackerras } 746f7035ce9SPaul Mackerras 747f7035ce9SPaul Mackerras if (vcpu->arch.doorbell_request) { 748f7035ce9SPaul Mackerras mtspr(SPRN_DPDES, 1); 749f7035ce9SPaul Mackerras vcpu->arch.vcore->dpdes = 1; 750f7035ce9SPaul Mackerras smp_wmb(); 751f7035ce9SPaul Mackerras vcpu->arch.doorbell_request = 0; 752f7035ce9SPaul Mackerras } 753f7035ce9SPaul Mackerras } 7542940ba0cSPaul Mackerras 75570ea13f6SPaul Mackerras static void flush_guest_tlb(struct kvm *kvm) 7562940ba0cSPaul Mackerras { 7572940ba0cSPaul Mackerras unsigned long rb, set; 7582940ba0cSPaul Mackerras 75970ea13f6SPaul Mackerras rb = PPC_BIT(52); /* IS = 2 */ 76070ea13f6SPaul Mackerras if (kvm_is_radix(kvm)) { 76170ea13f6SPaul Mackerras /* R=1 PRS=1 RIC=2 */ 76270ea13f6SPaul Mackerras asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1) 76370ea13f6SPaul Mackerras : : "r" (rb), "i" (1), "i" (1), "i" (2), 76470ea13f6SPaul Mackerras "r" (0) : "memory"); 76570ea13f6SPaul Mackerras for (set = 1; set < kvm->arch.tlb_sets; ++set) { 76670ea13f6SPaul Mackerras rb += PPC_BIT(51); /* increment set number */ 76770ea13f6SPaul Mackerras /* R=1 PRS=1 RIC=0 */ 76870ea13f6SPaul Mackerras asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1) 76970ea13f6SPaul Mackerras : : "r" (rb), "i" (1), "i" (1), "i" (0), 77070ea13f6SPaul Mackerras "r" (0) : "memory"); 77170ea13f6SPaul Mackerras } 7726c46fcceSNicholas Piggin asm volatile("ptesync": : :"memory"); 7736c46fcceSNicholas Piggin asm volatile(PPC_RADIX_INVALIDATE_ERAT_GUEST : : :"memory"); 77470ea13f6SPaul Mackerras } else { 77570ea13f6SPaul Mackerras for (set = 0; set < kvm->arch.tlb_sets; ++set) { 77670ea13f6SPaul Mackerras /* R=0 PRS=0 RIC=0 */ 77770ea13f6SPaul Mackerras asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1) 77870ea13f6SPaul Mackerras : : "r" (rb), "i" (0), "i" (0), "i" (0), 77970ea13f6SPaul Mackerras "r" (0) : "memory"); 78070ea13f6SPaul Mackerras rb += PPC_BIT(51); /* increment set number */ 78170ea13f6SPaul Mackerras } 78270ea13f6SPaul Mackerras asm volatile("ptesync": : :"memory"); 783fe7946ceSNicholas Piggin asm volatile(PPC_ISA_3_0_INVALIDATE_ERAT : : :"memory"); 78470ea13f6SPaul Mackerras } 78570ea13f6SPaul Mackerras } 78670ea13f6SPaul Mackerras 78770ea13f6SPaul Mackerras void kvmppc_check_need_tlb_flush(struct kvm *kvm, int pcpu, 78870ea13f6SPaul Mackerras struct kvm_nested_guest *nested) 78970ea13f6SPaul Mackerras { 79070ea13f6SPaul Mackerras cpumask_t *need_tlb_flush; 79170ea13f6SPaul Mackerras 7922940ba0cSPaul Mackerras /* 7932940ba0cSPaul Mackerras * On POWER9, individual threads can come in here, but the 7942940ba0cSPaul Mackerras * TLB is shared between the 4 threads in a core, hence 7952940ba0cSPaul Mackerras * invalidating on one thread invalidates for all. 7962940ba0cSPaul Mackerras * Thus we make all 4 threads use the same bit. 7972940ba0cSPaul Mackerras */ 7982940ba0cSPaul Mackerras if (cpu_has_feature(CPU_FTR_ARCH_300)) 7992940ba0cSPaul Mackerras pcpu = cpu_first_thread_sibling(pcpu); 8002940ba0cSPaul Mackerras 80170ea13f6SPaul Mackerras if (nested) 80270ea13f6SPaul Mackerras need_tlb_flush = &nested->need_tlb_flush; 80370ea13f6SPaul Mackerras else 80470ea13f6SPaul Mackerras need_tlb_flush = &kvm->arch.need_tlb_flush; 80570ea13f6SPaul Mackerras 80670ea13f6SPaul Mackerras if (cpumask_test_cpu(pcpu, need_tlb_flush)) { 80770ea13f6SPaul Mackerras flush_guest_tlb(kvm); 8082940ba0cSPaul Mackerras 8092940ba0cSPaul Mackerras /* Clear the bit after the TLB flush */ 81070ea13f6SPaul Mackerras cpumask_clear_cpu(pcpu, need_tlb_flush); 8112940ba0cSPaul Mackerras } 8122940ba0cSPaul Mackerras } 81370ea13f6SPaul Mackerras EXPORT_SYMBOL_GPL(kvmppc_check_need_tlb_flush); 814