1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2aa04b4ccSPaul Mackerras /* 3aa04b4ccSPaul Mackerras * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com> 4aa04b4ccSPaul Mackerras */ 5aa04b4ccSPaul Mackerras 6441c19c8SMichael Ellerman #include <linux/cpu.h> 7aa04b4ccSPaul Mackerras #include <linux/kvm_host.h> 8aa04b4ccSPaul Mackerras #include <linux/preempt.h> 966b15db6SPaul Gortmaker #include <linux/export.h> 10aa04b4ccSPaul Mackerras #include <linux/sched.h> 11aa04b4ccSPaul Mackerras #include <linux/spinlock.h> 12aa04b4ccSPaul Mackerras #include <linux/init.h> 13fa61a4e3SAneesh Kumar K.V #include <linux/memblock.h> 14fa61a4e3SAneesh Kumar K.V #include <linux/sizes.h> 15fc95ca72SJoonsoo Kim #include <linux/cma.h> 1690fd09f8SSam Bobroff #include <linux/bitops.h> 17aa04b4ccSPaul Mackerras 18aa04b4ccSPaul Mackerras #include <asm/cputable.h> 193a96570fSNicholas Piggin #include <asm/interrupt.h> 20aa04b4ccSPaul Mackerras #include <asm/kvm_ppc.h> 21aa04b4ccSPaul Mackerras #include <asm/kvm_book3s.h> 22*7ef3d06fSJason A. Donenfeld #include <asm/machdep.h> 23eddb60fbSPaul Mackerras #include <asm/xics.h> 24243e2511SBenjamin Herrenschmidt #include <asm/xive.h> 2566feed61SPaul Mackerras #include <asm/dbell.h> 2666feed61SPaul Mackerras #include <asm/cputhreads.h> 2737f55d30SSuresh Warrier #include <asm/io.h> 28f725758bSPaul Mackerras #include <asm/opal.h> 29e2702871SPaul Mackerras #include <asm/smp.h> 30aa04b4ccSPaul Mackerras 31fc95ca72SJoonsoo Kim #define KVM_CMA_CHUNK_ORDER 18 32fc95ca72SJoonsoo Kim 335af50993SBenjamin Herrenschmidt #include "book3s_xics.h" 345af50993SBenjamin Herrenschmidt #include "book3s_xive.h" 355af50993SBenjamin Herrenschmidt 365af50993SBenjamin Herrenschmidt /* 37fa61a4e3SAneesh Kumar K.V * Hash page table alignment on newer cpus(CPU_FTR_ARCH_206) 38fa61a4e3SAneesh Kumar K.V * should be power of 2. 39fa61a4e3SAneesh Kumar K.V */ 40fa61a4e3SAneesh Kumar K.V #define HPT_ALIGN_PAGES ((1 << 18) >> PAGE_SHIFT) /* 256k */ 41fa61a4e3SAneesh Kumar K.V /* 42fa61a4e3SAneesh Kumar K.V * By default we reserve 5% of memory for hash pagetable allocation. 43fa61a4e3SAneesh Kumar K.V */ 44fa61a4e3SAneesh Kumar K.V static unsigned long kvm_cma_resv_ratio = 5; 45aa04b4ccSPaul Mackerras 46fc95ca72SJoonsoo Kim static struct cma *kvm_cma; 47fc95ca72SJoonsoo Kim 48fa61a4e3SAneesh Kumar K.V static int __init early_parse_kvm_cma_resv(char *p) 49d2a1b483SAlexander Graf { 50fa61a4e3SAneesh Kumar K.V pr_debug("%s(%s)\n", __func__, p); 51d2a1b483SAlexander Graf if (!p) 52fa61a4e3SAneesh Kumar K.V return -EINVAL; 53fa61a4e3SAneesh Kumar K.V return kstrtoul(p, 0, &kvm_cma_resv_ratio); 54d2a1b483SAlexander Graf } 55fa61a4e3SAneesh Kumar K.V early_param("kvm_cma_resv_ratio", early_parse_kvm_cma_resv); 56d2a1b483SAlexander Graf 57db9a290dSDavid Gibson struct page *kvm_alloc_hpt_cma(unsigned long nr_pages) 58d2a1b483SAlexander Graf { 59c04fa583SAlexey Kardashevskiy VM_BUG_ON(order_base_2(nr_pages) < KVM_CMA_CHUNK_ORDER - PAGE_SHIFT); 60fc95ca72SJoonsoo Kim 61e2f466e3SLucas Stach return cma_alloc(kvm_cma, nr_pages, order_base_2(HPT_ALIGN_PAGES), 6265182029SMarek Szyprowski false); 63d2a1b483SAlexander Graf } 64db9a290dSDavid Gibson EXPORT_SYMBOL_GPL(kvm_alloc_hpt_cma); 65d2a1b483SAlexander Graf 66db9a290dSDavid Gibson void kvm_free_hpt_cma(struct page *page, unsigned long nr_pages) 67d2a1b483SAlexander Graf { 68fc95ca72SJoonsoo Kim cma_release(kvm_cma, page, nr_pages); 69d2a1b483SAlexander Graf } 70db9a290dSDavid Gibson EXPORT_SYMBOL_GPL(kvm_free_hpt_cma); 71d2a1b483SAlexander Graf 72fa61a4e3SAneesh Kumar K.V /** 73fa61a4e3SAneesh Kumar K.V * kvm_cma_reserve() - reserve area for kvm hash pagetable 74fa61a4e3SAneesh Kumar K.V * 75fa61a4e3SAneesh Kumar K.V * This function reserves memory from early allocator. It should be 7614ed7409SAnton Blanchard * called by arch specific code once the memblock allocator 77fa61a4e3SAneesh Kumar K.V * has been activated and all other subsystems have already allocated/reserved 78fa61a4e3SAneesh Kumar K.V * memory. 79fa61a4e3SAneesh Kumar K.V */ 80fa61a4e3SAneesh Kumar K.V void __init kvm_cma_reserve(void) 81fa61a4e3SAneesh Kumar K.V { 82fa61a4e3SAneesh Kumar K.V unsigned long align_size; 8304ba0a92SMike Rapoport phys_addr_t selected_size; 84cec26bc3SAneesh Kumar K.V 85cec26bc3SAneesh Kumar K.V /* 86cec26bc3SAneesh Kumar K.V * We need CMA reservation only when we are in HV mode 87cec26bc3SAneesh Kumar K.V */ 88cec26bc3SAneesh Kumar K.V if (!cpu_has_feature(CPU_FTR_HVMODE)) 89cec26bc3SAneesh Kumar K.V return; 90fa61a4e3SAneesh Kumar K.V 9104ba0a92SMike Rapoport selected_size = PAGE_ALIGN(memblock_phys_mem_size() * kvm_cma_resv_ratio / 100); 92fa61a4e3SAneesh Kumar K.V if (selected_size) { 93a5a8b258SAneesh Kumar K.V pr_info("%s: reserving %ld MiB for global area\n", __func__, 94fa61a4e3SAneesh Kumar K.V (unsigned long)selected_size / SZ_1M); 95fa61a4e3SAneesh Kumar K.V align_size = HPT_ALIGN_PAGES << PAGE_SHIFT; 96c1f733aaSJoonsoo Kim cma_declare_contiguous(0, selected_size, 0, align_size, 97f318dd08SLaura Abbott KVM_CMA_CHUNK_ORDER - PAGE_SHIFT, false, "kvm_cma", 98f318dd08SLaura Abbott &kvm_cma); 99fa61a4e3SAneesh Kumar K.V } 100fa61a4e3SAneesh Kumar K.V } 101441c19c8SMichael Ellerman 102441c19c8SMichael Ellerman /* 10390fd09f8SSam Bobroff * Real-mode H_CONFER implementation. 10490fd09f8SSam Bobroff * We check if we are the only vcpu out of this virtual core 10590fd09f8SSam Bobroff * still running in the guest and not ceded. If so, we pop up 10690fd09f8SSam Bobroff * to the virtual-mode implementation; if not, just return to 10790fd09f8SSam Bobroff * the guest. 10890fd09f8SSam Bobroff */ 10990fd09f8SSam Bobroff long int kvmppc_rm_h_confer(struct kvm_vcpu *vcpu, int target, 11090fd09f8SSam Bobroff unsigned int yield_count) 11190fd09f8SSam Bobroff { 112ec257165SPaul Mackerras struct kvmppc_vcore *vc = local_paca->kvm_hstate.kvm_vcore; 113ec257165SPaul Mackerras int ptid = local_paca->kvm_hstate.ptid; 11490fd09f8SSam Bobroff int threads_running; 11590fd09f8SSam Bobroff int threads_ceded; 11690fd09f8SSam Bobroff int threads_conferring; 11790fd09f8SSam Bobroff u64 stop = get_tb() + 10 * tb_ticks_per_usec; 11890fd09f8SSam Bobroff int rv = H_SUCCESS; /* => don't yield */ 11990fd09f8SSam Bobroff 120ec257165SPaul Mackerras set_bit(ptid, &vc->conferring_threads); 1217d6c40daSPaul Mackerras while ((get_tb() < stop) && !VCORE_IS_EXITING(vc)) { 1227d6c40daSPaul Mackerras threads_running = VCORE_ENTRY_MAP(vc); 1237d6c40daSPaul Mackerras threads_ceded = vc->napping_threads; 1247d6c40daSPaul Mackerras threads_conferring = vc->conferring_threads; 1257d6c40daSPaul Mackerras if ((threads_ceded | threads_conferring) == threads_running) { 12690fd09f8SSam Bobroff rv = H_TOO_HARD; /* => do yield */ 12790fd09f8SSam Bobroff break; 12890fd09f8SSam Bobroff } 12990fd09f8SSam Bobroff } 130ec257165SPaul Mackerras clear_bit(ptid, &vc->conferring_threads); 13190fd09f8SSam Bobroff return rv; 13290fd09f8SSam Bobroff } 13390fd09f8SSam Bobroff 13490fd09f8SSam Bobroff /* 135441c19c8SMichael Ellerman * When running HV mode KVM we need to block certain operations while KVM VMs 136441c19c8SMichael Ellerman * exist in the system. We use a counter of VMs to track this. 137441c19c8SMichael Ellerman * 138441c19c8SMichael Ellerman * One of the operations we need to block is onlining of secondaries, so we 1395ae36401SSebastian Andrzej Siewior * protect hv_vm_count with cpus_read_lock/unlock(). 140441c19c8SMichael Ellerman */ 141441c19c8SMichael Ellerman static atomic_t hv_vm_count; 142441c19c8SMichael Ellerman 143441c19c8SMichael Ellerman void kvm_hv_vm_activated(void) 144441c19c8SMichael Ellerman { 1455ae36401SSebastian Andrzej Siewior cpus_read_lock(); 146441c19c8SMichael Ellerman atomic_inc(&hv_vm_count); 1475ae36401SSebastian Andrzej Siewior cpus_read_unlock(); 148441c19c8SMichael Ellerman } 149441c19c8SMichael Ellerman EXPORT_SYMBOL_GPL(kvm_hv_vm_activated); 150441c19c8SMichael Ellerman 151441c19c8SMichael Ellerman void kvm_hv_vm_deactivated(void) 152441c19c8SMichael Ellerman { 1535ae36401SSebastian Andrzej Siewior cpus_read_lock(); 154441c19c8SMichael Ellerman atomic_dec(&hv_vm_count); 1555ae36401SSebastian Andrzej Siewior cpus_read_unlock(); 156441c19c8SMichael Ellerman } 157441c19c8SMichael Ellerman EXPORT_SYMBOL_GPL(kvm_hv_vm_deactivated); 158441c19c8SMichael Ellerman 159441c19c8SMichael Ellerman bool kvm_hv_mode_active(void) 160441c19c8SMichael Ellerman { 161441c19c8SMichael Ellerman return atomic_read(&hv_vm_count) != 0; 162441c19c8SMichael Ellerman } 163ae2113a4SPaul Mackerras 164ae2113a4SPaul Mackerras extern int hcall_real_table[], hcall_real_table_end[]; 165ae2113a4SPaul Mackerras 166ae2113a4SPaul Mackerras int kvmppc_hcall_impl_hv_realmode(unsigned long cmd) 167ae2113a4SPaul Mackerras { 168ae2113a4SPaul Mackerras cmd /= 4; 169ae2113a4SPaul Mackerras if (cmd < hcall_real_table_end - hcall_real_table && 170ae2113a4SPaul Mackerras hcall_real_table[cmd]) 171ae2113a4SPaul Mackerras return 1; 172ae2113a4SPaul Mackerras 173ae2113a4SPaul Mackerras return 0; 174ae2113a4SPaul Mackerras } 175ae2113a4SPaul Mackerras EXPORT_SYMBOL_GPL(kvmppc_hcall_impl_hv_realmode); 176e928e9cbSMichael Ellerman 177e928e9cbSMichael Ellerman int kvmppc_hwrng_present(void) 178e928e9cbSMichael Ellerman { 179*7ef3d06fSJason A. Donenfeld return ppc_md.get_random_seed != NULL; 180e928e9cbSMichael Ellerman } 181e928e9cbSMichael Ellerman EXPORT_SYMBOL_GPL(kvmppc_hwrng_present); 182e928e9cbSMichael Ellerman 183dcbac73aSNicholas Piggin long kvmppc_rm_h_random(struct kvm_vcpu *vcpu) 184e928e9cbSMichael Ellerman { 185*7ef3d06fSJason A. Donenfeld if (ppc_md.get_random_seed && 186*7ef3d06fSJason A. Donenfeld ppc_md.get_random_seed(&vcpu->arch.regs.gpr[4])) 187e928e9cbSMichael Ellerman return H_SUCCESS; 188e928e9cbSMichael Ellerman 189e928e9cbSMichael Ellerman return H_HARDWARE; 190e928e9cbSMichael Ellerman } 191eddb60fbSPaul Mackerras 192eddb60fbSPaul Mackerras /* 19366feed61SPaul Mackerras * Send an interrupt or message to another CPU. 194eddb60fbSPaul Mackerras * The caller needs to include any barrier needed to order writes 195eddb60fbSPaul Mackerras * to memory vs. the IPI/message. 196eddb60fbSPaul Mackerras */ 197eddb60fbSPaul Mackerras void kvmhv_rm_send_ipi(int cpu) 198eddb60fbSPaul Mackerras { 199d381d7caSBenjamin Herrenschmidt void __iomem *xics_phys; 2001704a81cSPaul Mackerras unsigned long msg = PPC_DBELL_TYPE(PPC_DBELL_SERVER); 201eddb60fbSPaul Mackerras 2021704a81cSPaul Mackerras /* On POWER9 we can use msgsnd for any destination cpu. */ 2031704a81cSPaul Mackerras if (cpu_has_feature(CPU_FTR_ARCH_300)) { 2041704a81cSPaul Mackerras msg |= get_hard_smp_processor_id(cpu); 2051704a81cSPaul Mackerras __asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg)); 2061704a81cSPaul Mackerras return; 2071704a81cSPaul Mackerras } 2085af50993SBenjamin Herrenschmidt 2091704a81cSPaul Mackerras /* On POWER8 for IPIs to threads in the same core, use msgsnd. */ 21066feed61SPaul Mackerras if (cpu_has_feature(CPU_FTR_ARCH_207S) && 21166feed61SPaul Mackerras cpu_first_thread_sibling(cpu) == 21266feed61SPaul Mackerras cpu_first_thread_sibling(raw_smp_processor_id())) { 21366feed61SPaul Mackerras msg |= cpu_thread_in_core(cpu); 21466feed61SPaul Mackerras __asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg)); 21566feed61SPaul Mackerras return; 21666feed61SPaul Mackerras } 21766feed61SPaul Mackerras 218243e2511SBenjamin Herrenschmidt /* We should never reach this */ 21903f95332SPaul Mackerras if (WARN_ON_ONCE(xics_on_xive())) 220243e2511SBenjamin Herrenschmidt return; 221243e2511SBenjamin Herrenschmidt 22266feed61SPaul Mackerras /* Else poke the target with an IPI */ 223d2e60075SNicholas Piggin xics_phys = paca_ptrs[cpu]->kvm_hstate.xics_phys; 224ab9bad0eSBenjamin Herrenschmidt if (xics_phys) 225d381d7caSBenjamin Herrenschmidt __raw_rm_writeb(IPI_PRIORITY, xics_phys + XICS_MFRR); 226f725758bSPaul Mackerras else 227ab9bad0eSBenjamin Herrenschmidt opal_int_set_mfrr(get_hard_smp_processor_id(cpu), IPI_PRIORITY); 228eddb60fbSPaul Mackerras } 229eddb60fbSPaul Mackerras 230eddb60fbSPaul Mackerras /* 231eddb60fbSPaul Mackerras * The following functions are called from the assembly code 232eddb60fbSPaul Mackerras * in book3s_hv_rmhandlers.S. 233eddb60fbSPaul Mackerras */ 234eddb60fbSPaul Mackerras static void kvmhv_interrupt_vcore(struct kvmppc_vcore *vc, int active) 235eddb60fbSPaul Mackerras { 236eddb60fbSPaul Mackerras int cpu = vc->pcpu; 237eddb60fbSPaul Mackerras 238eddb60fbSPaul Mackerras /* Order setting of exit map vs. msgsnd/IPI */ 239eddb60fbSPaul Mackerras smp_mb(); 240eddb60fbSPaul Mackerras for (; active; active >>= 1, ++cpu) 241eddb60fbSPaul Mackerras if (active & 1) 242eddb60fbSPaul Mackerras kvmhv_rm_send_ipi(cpu); 243eddb60fbSPaul Mackerras } 244eddb60fbSPaul Mackerras 245eddb60fbSPaul Mackerras void kvmhv_commence_exit(int trap) 246eddb60fbSPaul Mackerras { 247eddb60fbSPaul Mackerras struct kvmppc_vcore *vc = local_paca->kvm_hstate.kvm_vcore; 248eddb60fbSPaul Mackerras int ptid = local_paca->kvm_hstate.ptid; 249b4deba5cSPaul Mackerras struct kvm_split_mode *sip = local_paca->kvm_hstate.kvm_split_mode; 250b1b1697aSNicholas Piggin int me, ee, i; 251eddb60fbSPaul Mackerras 252eddb60fbSPaul Mackerras /* Set our bit in the threads-exiting-guest map in the 0xff00 253eddb60fbSPaul Mackerras bits of vcore->entry_exit_map */ 254eddb60fbSPaul Mackerras me = 0x100 << ptid; 255eddb60fbSPaul Mackerras do { 256eddb60fbSPaul Mackerras ee = vc->entry_exit_map; 257eddb60fbSPaul Mackerras } while (cmpxchg(&vc->entry_exit_map, ee, ee | me) != ee); 258eddb60fbSPaul Mackerras 259eddb60fbSPaul Mackerras /* Are we the first here? */ 260eddb60fbSPaul Mackerras if ((ee >> 8) != 0) 261eddb60fbSPaul Mackerras return; 262eddb60fbSPaul Mackerras 263eddb60fbSPaul Mackerras /* 264eddb60fbSPaul Mackerras * Trigger the other threads in this vcore to exit the guest. 265eddb60fbSPaul Mackerras * If this is a hypervisor decrementer interrupt then they 266eddb60fbSPaul Mackerras * will be already on their way out of the guest. 267eddb60fbSPaul Mackerras */ 268eddb60fbSPaul Mackerras if (trap != BOOK3S_INTERRUPT_HV_DECREMENTER) 269eddb60fbSPaul Mackerras kvmhv_interrupt_vcore(vc, ee & ~(1 << ptid)); 270b4deba5cSPaul Mackerras 271b4deba5cSPaul Mackerras /* 272b4deba5cSPaul Mackerras * If we are doing dynamic micro-threading, interrupt the other 273b4deba5cSPaul Mackerras * subcores to pull them out of their guests too. 274b4deba5cSPaul Mackerras */ 275b4deba5cSPaul Mackerras if (!sip) 276b4deba5cSPaul Mackerras return; 277b4deba5cSPaul Mackerras 278b4deba5cSPaul Mackerras for (i = 0; i < MAX_SUBCORES; ++i) { 279898b25b2SPaul Mackerras vc = sip->vc[i]; 280b4deba5cSPaul Mackerras if (!vc) 281b4deba5cSPaul Mackerras break; 282b4deba5cSPaul Mackerras do { 283b4deba5cSPaul Mackerras ee = vc->entry_exit_map; 284b4deba5cSPaul Mackerras /* Already asked to exit? */ 285b4deba5cSPaul Mackerras if ((ee >> 8) != 0) 286b4deba5cSPaul Mackerras break; 287b4deba5cSPaul Mackerras } while (cmpxchg(&vc->entry_exit_map, ee, 288b4deba5cSPaul Mackerras ee | VCORE_EXIT_REQ) != ee); 289b4deba5cSPaul Mackerras if ((ee >> 8) == 0) 290b4deba5cSPaul Mackerras kvmhv_interrupt_vcore(vc, ee); 291b4deba5cSPaul Mackerras } 292eddb60fbSPaul Mackerras } 29379b6c247SSuresh Warrier 29479b6c247SSuresh Warrier struct kvmppc_host_rm_ops *kvmppc_host_rm_ops_hv; 29579b6c247SSuresh Warrier EXPORT_SYMBOL_GPL(kvmppc_host_rm_ops_hv); 29637f55d30SSuresh Warrier 297e3c13e56SSuresh Warrier #ifdef CONFIG_KVM_XICS 298e3c13e56SSuresh Warrier static struct kvmppc_irq_map *get_irqmap(struct kvmppc_passthru_irqmap *pimap, 299e3c13e56SSuresh Warrier u32 xisr) 300e3c13e56SSuresh Warrier { 301e3c13e56SSuresh Warrier int i; 302e3c13e56SSuresh Warrier 303e3c13e56SSuresh Warrier /* 304e3c13e56SSuresh Warrier * We access the mapped array here without a lock. That 305e3c13e56SSuresh Warrier * is safe because we never reduce the number of entries 306e3c13e56SSuresh Warrier * in the array and we never change the v_hwirq field of 307e3c13e56SSuresh Warrier * an entry once it is set. 308e3c13e56SSuresh Warrier * 309e3c13e56SSuresh Warrier * We have also carefully ordered the stores in the writer 310e3c13e56SSuresh Warrier * and the loads here in the reader, so that if we find a matching 311e3c13e56SSuresh Warrier * hwirq here, the associated GSI and irq_desc fields are valid. 312e3c13e56SSuresh Warrier */ 313e3c13e56SSuresh Warrier for (i = 0; i < pimap->n_mapped; i++) { 314e3c13e56SSuresh Warrier if (xisr == pimap->mapped[i].r_hwirq) { 315e3c13e56SSuresh Warrier /* 316e3c13e56SSuresh Warrier * Order subsequent reads in the caller to serialize 317e3c13e56SSuresh Warrier * with the writer. 318e3c13e56SSuresh Warrier */ 319e3c13e56SSuresh Warrier smp_rmb(); 320e3c13e56SSuresh Warrier return &pimap->mapped[i]; 321e3c13e56SSuresh Warrier } 322e3c13e56SSuresh Warrier } 323e3c13e56SSuresh Warrier return NULL; 324e3c13e56SSuresh Warrier } 325e3c13e56SSuresh Warrier 326e3c13e56SSuresh Warrier /* 327e3c13e56SSuresh Warrier * If we have an interrupt that's not an IPI, check if we have a 328e3c13e56SSuresh Warrier * passthrough adapter and if so, check if this external interrupt 329e3c13e56SSuresh Warrier * is for the adapter. 330e3c13e56SSuresh Warrier * We will attempt to deliver the IRQ directly to the target VCPU's 331e3c13e56SSuresh Warrier * ICP, the virtual ICP (based on affinity - the xive value in ICS). 332e3c13e56SSuresh Warrier * 333e3c13e56SSuresh Warrier * If the delivery fails or if this is not for a passthrough adapter, 334e3c13e56SSuresh Warrier * return to the host to handle this interrupt. We earlier 335e3c13e56SSuresh Warrier * saved a copy of the XIRR in the PACA, it will be picked up by 336e3c13e56SSuresh Warrier * the host ICP driver. 337e3c13e56SSuresh Warrier */ 338f725758bSPaul Mackerras static int kvmppc_check_passthru(u32 xisr, __be32 xirr, bool *again) 339e3c13e56SSuresh Warrier { 340e3c13e56SSuresh Warrier struct kvmppc_passthru_irqmap *pimap; 341e3c13e56SSuresh Warrier struct kvmppc_irq_map *irq_map; 342e3c13e56SSuresh Warrier struct kvm_vcpu *vcpu; 343e3c13e56SSuresh Warrier 344e3c13e56SSuresh Warrier vcpu = local_paca->kvm_hstate.kvm_vcpu; 345e3c13e56SSuresh Warrier if (!vcpu) 346e3c13e56SSuresh Warrier return 1; 347e3c13e56SSuresh Warrier pimap = kvmppc_get_passthru_irqmap(vcpu->kvm); 348e3c13e56SSuresh Warrier if (!pimap) 349e3c13e56SSuresh Warrier return 1; 350e3c13e56SSuresh Warrier irq_map = get_irqmap(pimap, xisr); 351e3c13e56SSuresh Warrier if (!irq_map) 352e3c13e56SSuresh Warrier return 1; 353e3c13e56SSuresh Warrier 354e3c13e56SSuresh Warrier /* We're handling this interrupt, generic code doesn't need to */ 355e3c13e56SSuresh Warrier local_paca->kvm_hstate.saved_xirr = 0; 356e3c13e56SSuresh Warrier 357f725758bSPaul Mackerras return kvmppc_deliver_irq_passthru(vcpu, xirr, irq_map, pimap, again); 358e3c13e56SSuresh Warrier } 359e3c13e56SSuresh Warrier 360e3c13e56SSuresh Warrier #else 361e2702871SPaul Mackerras static inline int kvmppc_check_passthru(u32 xisr, __be32 xirr, bool *again) 362e3c13e56SSuresh Warrier { 363e3c13e56SSuresh Warrier return 1; 364e3c13e56SSuresh Warrier } 365e3c13e56SSuresh Warrier #endif 366e3c13e56SSuresh Warrier 36737f55d30SSuresh Warrier /* 36837f55d30SSuresh Warrier * Determine what sort of external interrupt is pending (if any). 36937f55d30SSuresh Warrier * Returns: 37037f55d30SSuresh Warrier * 0 if no interrupt is pending 37137f55d30SSuresh Warrier * 1 if an interrupt is pending that needs to be handled by the host 372f7af5209SSuresh Warrier * 2 Passthrough that needs completion in the host 37337f55d30SSuresh Warrier * -1 if there was a guest wakeup IPI (which has now been cleared) 374e3c13e56SSuresh Warrier * -2 if there is PCI passthrough external interrupt that was handled 37537f55d30SSuresh Warrier */ 376f725758bSPaul Mackerras static long kvmppc_read_one_intr(bool *again); 37737f55d30SSuresh Warrier 37837f55d30SSuresh Warrier long kvmppc_read_intr(void) 37937f55d30SSuresh Warrier { 380f725758bSPaul Mackerras long ret = 0; 381f725758bSPaul Mackerras long rc; 382f725758bSPaul Mackerras bool again; 383f725758bSPaul Mackerras 384243e2511SBenjamin Herrenschmidt if (xive_enabled()) 385243e2511SBenjamin Herrenschmidt return 1; 386243e2511SBenjamin Herrenschmidt 387f725758bSPaul Mackerras do { 388f725758bSPaul Mackerras again = false; 389f725758bSPaul Mackerras rc = kvmppc_read_one_intr(&again); 390f725758bSPaul Mackerras if (rc && (ret == 0 || rc > ret)) 391f725758bSPaul Mackerras ret = rc; 392f725758bSPaul Mackerras } while (again); 393f725758bSPaul Mackerras return ret; 394f725758bSPaul Mackerras } 395f725758bSPaul Mackerras 396f725758bSPaul Mackerras static long kvmppc_read_one_intr(bool *again) 397f725758bSPaul Mackerras { 398d381d7caSBenjamin Herrenschmidt void __iomem *xics_phys; 39937f55d30SSuresh Warrier u32 h_xirr; 40037f55d30SSuresh Warrier __be32 xirr; 40137f55d30SSuresh Warrier u32 xisr; 40237f55d30SSuresh Warrier u8 host_ipi; 403f725758bSPaul Mackerras int64_t rc; 40437f55d30SSuresh Warrier 4055af50993SBenjamin Herrenschmidt if (xive_enabled()) 4065af50993SBenjamin Herrenschmidt return 1; 4075af50993SBenjamin Herrenschmidt 40837f55d30SSuresh Warrier /* see if a host IPI is pending */ 40937f55d30SSuresh Warrier host_ipi = local_paca->kvm_hstate.host_ipi; 41037f55d30SSuresh Warrier if (host_ipi) 41137f55d30SSuresh Warrier return 1; 41237f55d30SSuresh Warrier 41337f55d30SSuresh Warrier /* Now read the interrupt from the ICP */ 41437f55d30SSuresh Warrier xics_phys = local_paca->kvm_hstate.xics_phys; 41553af3ba2SPaul Mackerras rc = 0; 416ab9bad0eSBenjamin Herrenschmidt if (!xics_phys) 41753af3ba2SPaul Mackerras rc = opal_int_get_xirr(&xirr, false); 41853af3ba2SPaul Mackerras else 419d381d7caSBenjamin Herrenschmidt xirr = __raw_rm_readl(xics_phys + XICS_XIRR); 420f725758bSPaul Mackerras if (rc < 0) 42137f55d30SSuresh Warrier return 1; 42237f55d30SSuresh Warrier 42337f55d30SSuresh Warrier /* 42437f55d30SSuresh Warrier * Save XIRR for later. Since we get control in reverse endian 42537f55d30SSuresh Warrier * on LE systems, save it byte reversed and fetch it back in 42637f55d30SSuresh Warrier * host endian. Note that xirr is the value read from the 42737f55d30SSuresh Warrier * XIRR register, while h_xirr is the host endian version. 42837f55d30SSuresh Warrier */ 42937f55d30SSuresh Warrier h_xirr = be32_to_cpu(xirr); 43037f55d30SSuresh Warrier local_paca->kvm_hstate.saved_xirr = h_xirr; 43137f55d30SSuresh Warrier xisr = h_xirr & 0xffffff; 43237f55d30SSuresh Warrier /* 43337f55d30SSuresh Warrier * Ensure that the store/load complete to guarantee all side 43437f55d30SSuresh Warrier * effects of loading from XIRR has completed 43537f55d30SSuresh Warrier */ 43637f55d30SSuresh Warrier smp_mb(); 43737f55d30SSuresh Warrier 43837f55d30SSuresh Warrier /* if nothing pending in the ICP */ 43937f55d30SSuresh Warrier if (!xisr) 44037f55d30SSuresh Warrier return 0; 44137f55d30SSuresh Warrier 44237f55d30SSuresh Warrier /* We found something in the ICP... 44337f55d30SSuresh Warrier * 44437f55d30SSuresh Warrier * If it is an IPI, clear the MFRR and EOI it. 44537f55d30SSuresh Warrier */ 44637f55d30SSuresh Warrier if (xisr == XICS_IPI) { 44753af3ba2SPaul Mackerras rc = 0; 4482ce008c8SNicholas Piggin if (xics_phys) { 449d381d7caSBenjamin Herrenschmidt __raw_rm_writeb(0xff, xics_phys + XICS_MFRR); 450d381d7caSBenjamin Herrenschmidt __raw_rm_writel(xirr, xics_phys + XICS_XIRR); 451f725758bSPaul Mackerras } else { 452ab9bad0eSBenjamin Herrenschmidt opal_int_set_mfrr(hard_smp_processor_id(), 0xff); 453ab9bad0eSBenjamin Herrenschmidt rc = opal_int_eoi(h_xirr); 45453af3ba2SPaul Mackerras } 455f725758bSPaul Mackerras /* If rc > 0, there is another interrupt pending */ 456f725758bSPaul Mackerras *again = rc > 0; 457f725758bSPaul Mackerras 45837f55d30SSuresh Warrier /* 45937f55d30SSuresh Warrier * Need to ensure side effects of above stores 46037f55d30SSuresh Warrier * complete before proceeding. 46137f55d30SSuresh Warrier */ 46237f55d30SSuresh Warrier smp_mb(); 46337f55d30SSuresh Warrier 46437f55d30SSuresh Warrier /* 46537f55d30SSuresh Warrier * We need to re-check host IPI now in case it got set in the 46637f55d30SSuresh Warrier * meantime. If it's clear, we bounce the interrupt to the 46737f55d30SSuresh Warrier * guest 46837f55d30SSuresh Warrier */ 46937f55d30SSuresh Warrier host_ipi = local_paca->kvm_hstate.host_ipi; 47037f55d30SSuresh Warrier if (unlikely(host_ipi != 0)) { 47137f55d30SSuresh Warrier /* We raced with the host, 47237f55d30SSuresh Warrier * we need to resend that IPI, bummer 47337f55d30SSuresh Warrier */ 4742ce008c8SNicholas Piggin if (xics_phys) 475d381d7caSBenjamin Herrenschmidt __raw_rm_writeb(IPI_PRIORITY, 476d381d7caSBenjamin Herrenschmidt xics_phys + XICS_MFRR); 477f725758bSPaul Mackerras else 478ab9bad0eSBenjamin Herrenschmidt opal_int_set_mfrr(hard_smp_processor_id(), 479f725758bSPaul Mackerras IPI_PRIORITY); 48037f55d30SSuresh Warrier /* Let side effects complete */ 48137f55d30SSuresh Warrier smp_mb(); 48237f55d30SSuresh Warrier return 1; 48337f55d30SSuresh Warrier } 48437f55d30SSuresh Warrier 48537f55d30SSuresh Warrier /* OK, it's an IPI for us */ 48637f55d30SSuresh Warrier local_paca->kvm_hstate.saved_xirr = 0; 48737f55d30SSuresh Warrier return -1; 48837f55d30SSuresh Warrier } 48937f55d30SSuresh Warrier 490f725758bSPaul Mackerras return kvmppc_check_passthru(xisr, xirr, again); 49137f55d30SSuresh Warrier } 4925af50993SBenjamin Herrenschmidt 493857b99e1SPaul Mackerras void kvmppc_bad_interrupt(struct pt_regs *regs) 494857b99e1SPaul Mackerras { 4957c1bd80cSNicholas Piggin /* 4967c1bd80cSNicholas Piggin * 100 could happen at any time, 200 can happen due to invalid real 4977c1bd80cSNicholas Piggin * address access for example (or any time due to a hardware problem). 4987c1bd80cSNicholas Piggin */ 4997c1bd80cSNicholas Piggin if (TRAP(regs) == 0x100) { 5007c1bd80cSNicholas Piggin get_paca()->in_nmi++; 5017c1bd80cSNicholas Piggin system_reset_exception(regs); 5027c1bd80cSNicholas Piggin get_paca()->in_nmi--; 5037c1bd80cSNicholas Piggin } else if (TRAP(regs) == 0x200) { 5047c1bd80cSNicholas Piggin machine_check_exception(regs); 5057c1bd80cSNicholas Piggin } else { 506857b99e1SPaul Mackerras die("Bad interrupt in KVM entry/exit code", regs, SIGABRT); 5077c1bd80cSNicholas Piggin } 508857b99e1SPaul Mackerras panic("Bad KVM trap"); 509857b99e1SPaul Mackerras } 510c0101509SPaul Mackerras 511268f4ef9SNicholas Piggin static void kvmppc_end_cede(struct kvm_vcpu *vcpu) 512268f4ef9SNicholas Piggin { 513268f4ef9SNicholas Piggin vcpu->arch.ceded = 0; 514268f4ef9SNicholas Piggin if (vcpu->arch.timer_running) { 515268f4ef9SNicholas Piggin hrtimer_try_to_cancel(&vcpu->arch.dec_timer); 516268f4ef9SNicholas Piggin vcpu->arch.timer_running = 0; 517268f4ef9SNicholas Piggin } 518268f4ef9SNicholas Piggin } 519268f4ef9SNicholas Piggin 520268f4ef9SNicholas Piggin void kvmppc_set_msr_hv(struct kvm_vcpu *vcpu, u64 msr) 521268f4ef9SNicholas Piggin { 522732f21a3SNicholas Piggin /* Guest must always run with ME enabled, HV disabled. */ 523732f21a3SNicholas Piggin msr = (msr | MSR_ME) & ~MSR_HV; 524946cf44aSNicholas Piggin 525268f4ef9SNicholas Piggin /* 526268f4ef9SNicholas Piggin * Check for illegal transactional state bit combination 527268f4ef9SNicholas Piggin * and if we find it, force the TS field to a safe state. 528268f4ef9SNicholas Piggin */ 529268f4ef9SNicholas Piggin if ((msr & MSR_TS_MASK) == MSR_TS_MASK) 530268f4ef9SNicholas Piggin msr &= ~MSR_TS_MASK; 531268f4ef9SNicholas Piggin vcpu->arch.shregs.msr = msr; 532268f4ef9SNicholas Piggin kvmppc_end_cede(vcpu); 533268f4ef9SNicholas Piggin } 534268f4ef9SNicholas Piggin EXPORT_SYMBOL_GPL(kvmppc_set_msr_hv); 535268f4ef9SNicholas Piggin 536268f4ef9SNicholas Piggin static void inject_interrupt(struct kvm_vcpu *vcpu, int vec, u64 srr1_flags) 537268f4ef9SNicholas Piggin { 538268f4ef9SNicholas Piggin unsigned long msr, pc, new_msr, new_pc; 539268f4ef9SNicholas Piggin 540268f4ef9SNicholas Piggin msr = kvmppc_get_msr(vcpu); 541268f4ef9SNicholas Piggin pc = kvmppc_get_pc(vcpu); 542268f4ef9SNicholas Piggin new_msr = vcpu->arch.intr_msr; 543268f4ef9SNicholas Piggin new_pc = vec; 544268f4ef9SNicholas Piggin 545268f4ef9SNicholas Piggin /* If transactional, change to suspend mode on IRQ delivery */ 546268f4ef9SNicholas Piggin if (MSR_TM_TRANSACTIONAL(msr)) 547268f4ef9SNicholas Piggin new_msr |= MSR_TS_S; 548268f4ef9SNicholas Piggin else 549268f4ef9SNicholas Piggin new_msr |= msr & MSR_TS_MASK; 550268f4ef9SNicholas Piggin 5516a13cb0cSNicholas Piggin /* 5526a13cb0cSNicholas Piggin * Perform MSR and PC adjustment for LPCR[AIL]=3 if it is set and 5536a13cb0cSNicholas Piggin * applicable. AIL=2 is not supported. 5546a13cb0cSNicholas Piggin * 5556a13cb0cSNicholas Piggin * AIL does not apply to SRESET, MCE, or HMI (which is never 5566a13cb0cSNicholas Piggin * delivered to the guest), and does not apply if IR=0 or DR=0. 5576a13cb0cSNicholas Piggin */ 5586a13cb0cSNicholas Piggin if (vec != BOOK3S_INTERRUPT_SYSTEM_RESET && 5596a13cb0cSNicholas Piggin vec != BOOK3S_INTERRUPT_MACHINE_CHECK && 5606a13cb0cSNicholas Piggin (vcpu->arch.vcore->lpcr & LPCR_AIL) == LPCR_AIL_3 && 5616a13cb0cSNicholas Piggin (msr & (MSR_IR|MSR_DR)) == (MSR_IR|MSR_DR) ) { 5626a13cb0cSNicholas Piggin new_msr |= MSR_IR | MSR_DR; 5636a13cb0cSNicholas Piggin new_pc += 0xC000000000004000ULL; 5646a13cb0cSNicholas Piggin } 5656a13cb0cSNicholas Piggin 566268f4ef9SNicholas Piggin kvmppc_set_srr0(vcpu, pc); 567268f4ef9SNicholas Piggin kvmppc_set_srr1(vcpu, (msr & SRR1_MSR_BITS) | srr1_flags); 568268f4ef9SNicholas Piggin kvmppc_set_pc(vcpu, new_pc); 569268f4ef9SNicholas Piggin vcpu->arch.shregs.msr = new_msr; 570268f4ef9SNicholas Piggin } 571268f4ef9SNicholas Piggin 572268f4ef9SNicholas Piggin void kvmppc_inject_interrupt_hv(struct kvm_vcpu *vcpu, int vec, u64 srr1_flags) 573268f4ef9SNicholas Piggin { 574268f4ef9SNicholas Piggin inject_interrupt(vcpu, vec, srr1_flags); 575268f4ef9SNicholas Piggin kvmppc_end_cede(vcpu); 576268f4ef9SNicholas Piggin } 577268f4ef9SNicholas Piggin EXPORT_SYMBOL_GPL(kvmppc_inject_interrupt_hv); 578268f4ef9SNicholas Piggin 579f7035ce9SPaul Mackerras /* 580f7035ce9SPaul Mackerras * Is there a PRIV_DOORBELL pending for the guest (on POWER9)? 581f7035ce9SPaul Mackerras * Can we inject a Decrementer or a External interrupt? 582f7035ce9SPaul Mackerras */ 583f7035ce9SPaul Mackerras void kvmppc_guest_entry_inject_int(struct kvm_vcpu *vcpu) 584f7035ce9SPaul Mackerras { 585f7035ce9SPaul Mackerras int ext; 586f7035ce9SPaul Mackerras unsigned long lpcr; 587f7035ce9SPaul Mackerras 5886398326bSNicholas Piggin WARN_ON_ONCE(cpu_has_feature(CPU_FTR_ARCH_300)); 5896398326bSNicholas Piggin 590f7035ce9SPaul Mackerras /* Insert EXTERNAL bit into LPCR at the MER bit position */ 591f7035ce9SPaul Mackerras ext = (vcpu->arch.pending_exceptions >> BOOK3S_IRQPRIO_EXTERNAL) & 1; 592f7035ce9SPaul Mackerras lpcr = mfspr(SPRN_LPCR); 593f7035ce9SPaul Mackerras lpcr |= ext << LPCR_MER_SH; 594f7035ce9SPaul Mackerras mtspr(SPRN_LPCR, lpcr); 595f7035ce9SPaul Mackerras isync(); 596f7035ce9SPaul Mackerras 597f7035ce9SPaul Mackerras if (vcpu->arch.shregs.msr & MSR_EE) { 598f7035ce9SPaul Mackerras if (ext) { 599268f4ef9SNicholas Piggin inject_interrupt(vcpu, BOOK3S_INTERRUPT_EXTERNAL, 0); 600f7035ce9SPaul Mackerras } else { 601f7035ce9SPaul Mackerras long int dec = mfspr(SPRN_DEC); 602f7035ce9SPaul Mackerras if (!(lpcr & LPCR_LD)) 603f7035ce9SPaul Mackerras dec = (int) dec; 604f7035ce9SPaul Mackerras if (dec < 0) 605268f4ef9SNicholas Piggin inject_interrupt(vcpu, 606268f4ef9SNicholas Piggin BOOK3S_INTERRUPT_DECREMENTER, 0); 607f7035ce9SPaul Mackerras } 608f7035ce9SPaul Mackerras } 609f7035ce9SPaul Mackerras 610f7035ce9SPaul Mackerras if (vcpu->arch.doorbell_request) { 611f7035ce9SPaul Mackerras mtspr(SPRN_DPDES, 1); 612f7035ce9SPaul Mackerras vcpu->arch.vcore->dpdes = 1; 613f7035ce9SPaul Mackerras smp_wmb(); 614f7035ce9SPaul Mackerras vcpu->arch.doorbell_request = 0; 615f7035ce9SPaul Mackerras } 616f7035ce9SPaul Mackerras } 6172940ba0cSPaul Mackerras 61870ea13f6SPaul Mackerras static void flush_guest_tlb(struct kvm *kvm) 6192940ba0cSPaul Mackerras { 6202940ba0cSPaul Mackerras unsigned long rb, set; 6212940ba0cSPaul Mackerras 62270ea13f6SPaul Mackerras rb = PPC_BIT(52); /* IS = 2 */ 62370ea13f6SPaul Mackerras for (set = 0; set < kvm->arch.tlb_sets; ++set) { 62470ea13f6SPaul Mackerras /* R=0 PRS=0 RIC=0 */ 62570ea13f6SPaul Mackerras asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1) 62670ea13f6SPaul Mackerras : : "r" (rb), "i" (0), "i" (0), "i" (0), 62770ea13f6SPaul Mackerras "r" (0) : "memory"); 62870ea13f6SPaul Mackerras rb += PPC_BIT(51); /* increment set number */ 62970ea13f6SPaul Mackerras } 63070ea13f6SPaul Mackerras asm volatile("ptesync": : :"memory"); 63170ea13f6SPaul Mackerras } 63270ea13f6SPaul Mackerras 6330ba0e5d5SNicholas Piggin void kvmppc_check_need_tlb_flush(struct kvm *kvm, int pcpu) 63470ea13f6SPaul Mackerras { 6350ba0e5d5SNicholas Piggin if (cpumask_test_cpu(pcpu, &kvm->arch.need_tlb_flush)) { 63670ea13f6SPaul Mackerras flush_guest_tlb(kvm); 6372940ba0cSPaul Mackerras 6382940ba0cSPaul Mackerras /* Clear the bit after the TLB flush */ 6390ba0e5d5SNicholas Piggin cpumask_clear_cpu(pcpu, &kvm->arch.need_tlb_flush); 6402940ba0cSPaul Mackerras } 6412940ba0cSPaul Mackerras } 64270ea13f6SPaul Mackerras EXPORT_SYMBOL_GPL(kvmppc_check_need_tlb_flush); 643