1aa04b4ccSPaul Mackerras /* 2aa04b4ccSPaul Mackerras * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com> 3aa04b4ccSPaul Mackerras * 4aa04b4ccSPaul Mackerras * This program is free software; you can redistribute it and/or modify 5aa04b4ccSPaul Mackerras * it under the terms of the GNU General Public License, version 2, as 6aa04b4ccSPaul Mackerras * published by the Free Software Foundation. 7aa04b4ccSPaul Mackerras */ 8aa04b4ccSPaul Mackerras 9441c19c8SMichael Ellerman #include <linux/cpu.h> 10aa04b4ccSPaul Mackerras #include <linux/kvm_host.h> 11aa04b4ccSPaul Mackerras #include <linux/preempt.h> 1266b15db6SPaul Gortmaker #include <linux/export.h> 13aa04b4ccSPaul Mackerras #include <linux/sched.h> 14aa04b4ccSPaul Mackerras #include <linux/spinlock.h> 15aa04b4ccSPaul Mackerras #include <linux/init.h> 16fa61a4e3SAneesh Kumar K.V #include <linux/memblock.h> 17fa61a4e3SAneesh Kumar K.V #include <linux/sizes.h> 18fc95ca72SJoonsoo Kim #include <linux/cma.h> 1990fd09f8SSam Bobroff #include <linux/bitops.h> 20aa04b4ccSPaul Mackerras 217c1bd80cSNicholas Piggin #include <asm/asm-prototypes.h> 22aa04b4ccSPaul Mackerras #include <asm/cputable.h> 23aa04b4ccSPaul Mackerras #include <asm/kvm_ppc.h> 24aa04b4ccSPaul Mackerras #include <asm/kvm_book3s.h> 25e928e9cbSMichael Ellerman #include <asm/archrandom.h> 26eddb60fbSPaul Mackerras #include <asm/xics.h> 27243e2511SBenjamin Herrenschmidt #include <asm/xive.h> 2866feed61SPaul Mackerras #include <asm/dbell.h> 2966feed61SPaul Mackerras #include <asm/cputhreads.h> 3037f55d30SSuresh Warrier #include <asm/io.h> 31f725758bSPaul Mackerras #include <asm/opal.h> 32e2702871SPaul Mackerras #include <asm/smp.h> 33aa04b4ccSPaul Mackerras 34fc95ca72SJoonsoo Kim #define KVM_CMA_CHUNK_ORDER 18 35fc95ca72SJoonsoo Kim 365af50993SBenjamin Herrenschmidt #include "book3s_xics.h" 375af50993SBenjamin Herrenschmidt #include "book3s_xive.h" 385af50993SBenjamin Herrenschmidt 395af50993SBenjamin Herrenschmidt /* 405af50993SBenjamin Herrenschmidt * The XIVE module will populate these when it loads 415af50993SBenjamin Herrenschmidt */ 425af50993SBenjamin Herrenschmidt unsigned long (*__xive_vm_h_xirr)(struct kvm_vcpu *vcpu); 435af50993SBenjamin Herrenschmidt unsigned long (*__xive_vm_h_ipoll)(struct kvm_vcpu *vcpu, unsigned long server); 445af50993SBenjamin Herrenschmidt int (*__xive_vm_h_ipi)(struct kvm_vcpu *vcpu, unsigned long server, 455af50993SBenjamin Herrenschmidt unsigned long mfrr); 465af50993SBenjamin Herrenschmidt int (*__xive_vm_h_cppr)(struct kvm_vcpu *vcpu, unsigned long cppr); 475af50993SBenjamin Herrenschmidt int (*__xive_vm_h_eoi)(struct kvm_vcpu *vcpu, unsigned long xirr); 485af50993SBenjamin Herrenschmidt EXPORT_SYMBOL_GPL(__xive_vm_h_xirr); 495af50993SBenjamin Herrenschmidt EXPORT_SYMBOL_GPL(__xive_vm_h_ipoll); 505af50993SBenjamin Herrenschmidt EXPORT_SYMBOL_GPL(__xive_vm_h_ipi); 515af50993SBenjamin Herrenschmidt EXPORT_SYMBOL_GPL(__xive_vm_h_cppr); 525af50993SBenjamin Herrenschmidt EXPORT_SYMBOL_GPL(__xive_vm_h_eoi); 535af50993SBenjamin Herrenschmidt 54fa61a4e3SAneesh Kumar K.V /* 55fa61a4e3SAneesh Kumar K.V * Hash page table alignment on newer cpus(CPU_FTR_ARCH_206) 56fa61a4e3SAneesh Kumar K.V * should be power of 2. 57fa61a4e3SAneesh Kumar K.V */ 58fa61a4e3SAneesh Kumar K.V #define HPT_ALIGN_PAGES ((1 << 18) >> PAGE_SHIFT) /* 256k */ 59fa61a4e3SAneesh Kumar K.V /* 60fa61a4e3SAneesh Kumar K.V * By default we reserve 5% of memory for hash pagetable allocation. 61fa61a4e3SAneesh Kumar K.V */ 62fa61a4e3SAneesh Kumar K.V static unsigned long kvm_cma_resv_ratio = 5; 63aa04b4ccSPaul Mackerras 64fc95ca72SJoonsoo Kim static struct cma *kvm_cma; 65fc95ca72SJoonsoo Kim 66fa61a4e3SAneesh Kumar K.V static int __init early_parse_kvm_cma_resv(char *p) 67d2a1b483SAlexander Graf { 68fa61a4e3SAneesh Kumar K.V pr_debug("%s(%s)\n", __func__, p); 69d2a1b483SAlexander Graf if (!p) 70fa61a4e3SAneesh Kumar K.V return -EINVAL; 71fa61a4e3SAneesh Kumar K.V return kstrtoul(p, 0, &kvm_cma_resv_ratio); 72d2a1b483SAlexander Graf } 73fa61a4e3SAneesh Kumar K.V early_param("kvm_cma_resv_ratio", early_parse_kvm_cma_resv); 74d2a1b483SAlexander Graf 75db9a290dSDavid Gibson struct page *kvm_alloc_hpt_cma(unsigned long nr_pages) 76d2a1b483SAlexander Graf { 77c04fa583SAlexey Kardashevskiy VM_BUG_ON(order_base_2(nr_pages) < KVM_CMA_CHUNK_ORDER - PAGE_SHIFT); 78fc95ca72SJoonsoo Kim 79e2f466e3SLucas Stach return cma_alloc(kvm_cma, nr_pages, order_base_2(HPT_ALIGN_PAGES), 8065182029SMarek Szyprowski false); 81d2a1b483SAlexander Graf } 82db9a290dSDavid Gibson EXPORT_SYMBOL_GPL(kvm_alloc_hpt_cma); 83d2a1b483SAlexander Graf 84db9a290dSDavid Gibson void kvm_free_hpt_cma(struct page *page, unsigned long nr_pages) 85d2a1b483SAlexander Graf { 86fc95ca72SJoonsoo Kim cma_release(kvm_cma, page, nr_pages); 87d2a1b483SAlexander Graf } 88db9a290dSDavid Gibson EXPORT_SYMBOL_GPL(kvm_free_hpt_cma); 89d2a1b483SAlexander Graf 90fa61a4e3SAneesh Kumar K.V /** 91fa61a4e3SAneesh Kumar K.V * kvm_cma_reserve() - reserve area for kvm hash pagetable 92fa61a4e3SAneesh Kumar K.V * 93fa61a4e3SAneesh Kumar K.V * This function reserves memory from early allocator. It should be 9414ed7409SAnton Blanchard * called by arch specific code once the memblock allocator 95fa61a4e3SAneesh Kumar K.V * has been activated and all other subsystems have already allocated/reserved 96fa61a4e3SAneesh Kumar K.V * memory. 97fa61a4e3SAneesh Kumar K.V */ 98fa61a4e3SAneesh Kumar K.V void __init kvm_cma_reserve(void) 99fa61a4e3SAneesh Kumar K.V { 100fa61a4e3SAneesh Kumar K.V unsigned long align_size; 101fa61a4e3SAneesh Kumar K.V struct memblock_region *reg; 102fa61a4e3SAneesh Kumar K.V phys_addr_t selected_size = 0; 103cec26bc3SAneesh Kumar K.V 104cec26bc3SAneesh Kumar K.V /* 105cec26bc3SAneesh Kumar K.V * We need CMA reservation only when we are in HV mode 106cec26bc3SAneesh Kumar K.V */ 107cec26bc3SAneesh Kumar K.V if (!cpu_has_feature(CPU_FTR_HVMODE)) 108cec26bc3SAneesh Kumar K.V return; 109fa61a4e3SAneesh Kumar K.V /* 110fa61a4e3SAneesh Kumar K.V * We cannot use memblock_phys_mem_size() here, because 111fa61a4e3SAneesh Kumar K.V * memblock_analyze() has not been called yet. 112fa61a4e3SAneesh Kumar K.V */ 113fa61a4e3SAneesh Kumar K.V for_each_memblock(memory, reg) 114fa61a4e3SAneesh Kumar K.V selected_size += memblock_region_memory_end_pfn(reg) - 115fa61a4e3SAneesh Kumar K.V memblock_region_memory_base_pfn(reg); 116fa61a4e3SAneesh Kumar K.V 117fa61a4e3SAneesh Kumar K.V selected_size = (selected_size * kvm_cma_resv_ratio / 100) << PAGE_SHIFT; 118fa61a4e3SAneesh Kumar K.V if (selected_size) { 119fa61a4e3SAneesh Kumar K.V pr_debug("%s: reserving %ld MiB for global area\n", __func__, 120fa61a4e3SAneesh Kumar K.V (unsigned long)selected_size / SZ_1M); 121fa61a4e3SAneesh Kumar K.V align_size = HPT_ALIGN_PAGES << PAGE_SHIFT; 122c1f733aaSJoonsoo Kim cma_declare_contiguous(0, selected_size, 0, align_size, 123f318dd08SLaura Abbott KVM_CMA_CHUNK_ORDER - PAGE_SHIFT, false, "kvm_cma", 124f318dd08SLaura Abbott &kvm_cma); 125fa61a4e3SAneesh Kumar K.V } 126fa61a4e3SAneesh Kumar K.V } 127441c19c8SMichael Ellerman 128441c19c8SMichael Ellerman /* 12990fd09f8SSam Bobroff * Real-mode H_CONFER implementation. 13090fd09f8SSam Bobroff * We check if we are the only vcpu out of this virtual core 13190fd09f8SSam Bobroff * still running in the guest and not ceded. If so, we pop up 13290fd09f8SSam Bobroff * to the virtual-mode implementation; if not, just return to 13390fd09f8SSam Bobroff * the guest. 13490fd09f8SSam Bobroff */ 13590fd09f8SSam Bobroff long int kvmppc_rm_h_confer(struct kvm_vcpu *vcpu, int target, 13690fd09f8SSam Bobroff unsigned int yield_count) 13790fd09f8SSam Bobroff { 138ec257165SPaul Mackerras struct kvmppc_vcore *vc = local_paca->kvm_hstate.kvm_vcore; 139ec257165SPaul Mackerras int ptid = local_paca->kvm_hstate.ptid; 14090fd09f8SSam Bobroff int threads_running; 14190fd09f8SSam Bobroff int threads_ceded; 14290fd09f8SSam Bobroff int threads_conferring; 14390fd09f8SSam Bobroff u64 stop = get_tb() + 10 * tb_ticks_per_usec; 14490fd09f8SSam Bobroff int rv = H_SUCCESS; /* => don't yield */ 14590fd09f8SSam Bobroff 146ec257165SPaul Mackerras set_bit(ptid, &vc->conferring_threads); 1477d6c40daSPaul Mackerras while ((get_tb() < stop) && !VCORE_IS_EXITING(vc)) { 1487d6c40daSPaul Mackerras threads_running = VCORE_ENTRY_MAP(vc); 1497d6c40daSPaul Mackerras threads_ceded = vc->napping_threads; 1507d6c40daSPaul Mackerras threads_conferring = vc->conferring_threads; 1517d6c40daSPaul Mackerras if ((threads_ceded | threads_conferring) == threads_running) { 15290fd09f8SSam Bobroff rv = H_TOO_HARD; /* => do yield */ 15390fd09f8SSam Bobroff break; 15490fd09f8SSam Bobroff } 15590fd09f8SSam Bobroff } 156ec257165SPaul Mackerras clear_bit(ptid, &vc->conferring_threads); 15790fd09f8SSam Bobroff return rv; 15890fd09f8SSam Bobroff } 15990fd09f8SSam Bobroff 16090fd09f8SSam Bobroff /* 161441c19c8SMichael Ellerman * When running HV mode KVM we need to block certain operations while KVM VMs 162441c19c8SMichael Ellerman * exist in the system. We use a counter of VMs to track this. 163441c19c8SMichael Ellerman * 164441c19c8SMichael Ellerman * One of the operations we need to block is onlining of secondaries, so we 165441c19c8SMichael Ellerman * protect hv_vm_count with get/put_online_cpus(). 166441c19c8SMichael Ellerman */ 167441c19c8SMichael Ellerman static atomic_t hv_vm_count; 168441c19c8SMichael Ellerman 169441c19c8SMichael Ellerman void kvm_hv_vm_activated(void) 170441c19c8SMichael Ellerman { 171441c19c8SMichael Ellerman get_online_cpus(); 172441c19c8SMichael Ellerman atomic_inc(&hv_vm_count); 173441c19c8SMichael Ellerman put_online_cpus(); 174441c19c8SMichael Ellerman } 175441c19c8SMichael Ellerman EXPORT_SYMBOL_GPL(kvm_hv_vm_activated); 176441c19c8SMichael Ellerman 177441c19c8SMichael Ellerman void kvm_hv_vm_deactivated(void) 178441c19c8SMichael Ellerman { 179441c19c8SMichael Ellerman get_online_cpus(); 180441c19c8SMichael Ellerman atomic_dec(&hv_vm_count); 181441c19c8SMichael Ellerman put_online_cpus(); 182441c19c8SMichael Ellerman } 183441c19c8SMichael Ellerman EXPORT_SYMBOL_GPL(kvm_hv_vm_deactivated); 184441c19c8SMichael Ellerman 185441c19c8SMichael Ellerman bool kvm_hv_mode_active(void) 186441c19c8SMichael Ellerman { 187441c19c8SMichael Ellerman return atomic_read(&hv_vm_count) != 0; 188441c19c8SMichael Ellerman } 189ae2113a4SPaul Mackerras 190ae2113a4SPaul Mackerras extern int hcall_real_table[], hcall_real_table_end[]; 191ae2113a4SPaul Mackerras 192ae2113a4SPaul Mackerras int kvmppc_hcall_impl_hv_realmode(unsigned long cmd) 193ae2113a4SPaul Mackerras { 194ae2113a4SPaul Mackerras cmd /= 4; 195ae2113a4SPaul Mackerras if (cmd < hcall_real_table_end - hcall_real_table && 196ae2113a4SPaul Mackerras hcall_real_table[cmd]) 197ae2113a4SPaul Mackerras return 1; 198ae2113a4SPaul Mackerras 199ae2113a4SPaul Mackerras return 0; 200ae2113a4SPaul Mackerras } 201ae2113a4SPaul Mackerras EXPORT_SYMBOL_GPL(kvmppc_hcall_impl_hv_realmode); 202e928e9cbSMichael Ellerman 203e928e9cbSMichael Ellerman int kvmppc_hwrng_present(void) 204e928e9cbSMichael Ellerman { 205e928e9cbSMichael Ellerman return powernv_hwrng_present(); 206e928e9cbSMichael Ellerman } 207e928e9cbSMichael Ellerman EXPORT_SYMBOL_GPL(kvmppc_hwrng_present); 208e928e9cbSMichael Ellerman 209e928e9cbSMichael Ellerman long kvmppc_h_random(struct kvm_vcpu *vcpu) 210e928e9cbSMichael Ellerman { 211acde2572SPaul Mackerras int r; 212acde2572SPaul Mackerras 213acde2572SPaul Mackerras /* Only need to do the expensive mfmsr() on radix */ 214acde2572SPaul Mackerras if (kvm_is_radix(vcpu->kvm) && (mfmsr() & MSR_IR)) 2151143a706SSimon Guo r = powernv_get_random_long(&vcpu->arch.regs.gpr[4]); 216acde2572SPaul Mackerras else 2171143a706SSimon Guo r = powernv_get_random_real_mode(&vcpu->arch.regs.gpr[4]); 218acde2572SPaul Mackerras if (r) 219e928e9cbSMichael Ellerman return H_SUCCESS; 220e928e9cbSMichael Ellerman 221e928e9cbSMichael Ellerman return H_HARDWARE; 222e928e9cbSMichael Ellerman } 223eddb60fbSPaul Mackerras 224eddb60fbSPaul Mackerras /* 22566feed61SPaul Mackerras * Send an interrupt or message to another CPU. 226eddb60fbSPaul Mackerras * The caller needs to include any barrier needed to order writes 227eddb60fbSPaul Mackerras * to memory vs. the IPI/message. 228eddb60fbSPaul Mackerras */ 229eddb60fbSPaul Mackerras void kvmhv_rm_send_ipi(int cpu) 230eddb60fbSPaul Mackerras { 231d381d7caSBenjamin Herrenschmidt void __iomem *xics_phys; 2321704a81cSPaul Mackerras unsigned long msg = PPC_DBELL_TYPE(PPC_DBELL_SERVER); 233eddb60fbSPaul Mackerras 2341704a81cSPaul Mackerras /* On POWER9 we can use msgsnd for any destination cpu. */ 2351704a81cSPaul Mackerras if (cpu_has_feature(CPU_FTR_ARCH_300)) { 2361704a81cSPaul Mackerras msg |= get_hard_smp_processor_id(cpu); 2371704a81cSPaul Mackerras __asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg)); 2381704a81cSPaul Mackerras return; 2391704a81cSPaul Mackerras } 2405af50993SBenjamin Herrenschmidt 2411704a81cSPaul Mackerras /* On POWER8 for IPIs to threads in the same core, use msgsnd. */ 24266feed61SPaul Mackerras if (cpu_has_feature(CPU_FTR_ARCH_207S) && 24366feed61SPaul Mackerras cpu_first_thread_sibling(cpu) == 24466feed61SPaul Mackerras cpu_first_thread_sibling(raw_smp_processor_id())) { 24566feed61SPaul Mackerras msg |= cpu_thread_in_core(cpu); 24666feed61SPaul Mackerras __asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg)); 24766feed61SPaul Mackerras return; 24866feed61SPaul Mackerras } 24966feed61SPaul Mackerras 250243e2511SBenjamin Herrenschmidt /* We should never reach this */ 251243e2511SBenjamin Herrenschmidt if (WARN_ON_ONCE(xive_enabled())) 252243e2511SBenjamin Herrenschmidt return; 253243e2511SBenjamin Herrenschmidt 25466feed61SPaul Mackerras /* Else poke the target with an IPI */ 255d2e60075SNicholas Piggin xics_phys = paca_ptrs[cpu]->kvm_hstate.xics_phys; 256ab9bad0eSBenjamin Herrenschmidt if (xics_phys) 257d381d7caSBenjamin Herrenschmidt __raw_rm_writeb(IPI_PRIORITY, xics_phys + XICS_MFRR); 258f725758bSPaul Mackerras else 259ab9bad0eSBenjamin Herrenschmidt opal_int_set_mfrr(get_hard_smp_processor_id(cpu), IPI_PRIORITY); 260eddb60fbSPaul Mackerras } 261eddb60fbSPaul Mackerras 262eddb60fbSPaul Mackerras /* 263eddb60fbSPaul Mackerras * The following functions are called from the assembly code 264eddb60fbSPaul Mackerras * in book3s_hv_rmhandlers.S. 265eddb60fbSPaul Mackerras */ 266eddb60fbSPaul Mackerras static void kvmhv_interrupt_vcore(struct kvmppc_vcore *vc, int active) 267eddb60fbSPaul Mackerras { 268eddb60fbSPaul Mackerras int cpu = vc->pcpu; 269eddb60fbSPaul Mackerras 270eddb60fbSPaul Mackerras /* Order setting of exit map vs. msgsnd/IPI */ 271eddb60fbSPaul Mackerras smp_mb(); 272eddb60fbSPaul Mackerras for (; active; active >>= 1, ++cpu) 273eddb60fbSPaul Mackerras if (active & 1) 274eddb60fbSPaul Mackerras kvmhv_rm_send_ipi(cpu); 275eddb60fbSPaul Mackerras } 276eddb60fbSPaul Mackerras 277eddb60fbSPaul Mackerras void kvmhv_commence_exit(int trap) 278eddb60fbSPaul Mackerras { 279eddb60fbSPaul Mackerras struct kvmppc_vcore *vc = local_paca->kvm_hstate.kvm_vcore; 280eddb60fbSPaul Mackerras int ptid = local_paca->kvm_hstate.ptid; 281b4deba5cSPaul Mackerras struct kvm_split_mode *sip = local_paca->kvm_hstate.kvm_split_mode; 282c0101509SPaul Mackerras int me, ee, i, t; 283c0101509SPaul Mackerras int cpu0; 284eddb60fbSPaul Mackerras 285eddb60fbSPaul Mackerras /* Set our bit in the threads-exiting-guest map in the 0xff00 286eddb60fbSPaul Mackerras bits of vcore->entry_exit_map */ 287eddb60fbSPaul Mackerras me = 0x100 << ptid; 288eddb60fbSPaul Mackerras do { 289eddb60fbSPaul Mackerras ee = vc->entry_exit_map; 290eddb60fbSPaul Mackerras } while (cmpxchg(&vc->entry_exit_map, ee, ee | me) != ee); 291eddb60fbSPaul Mackerras 292eddb60fbSPaul Mackerras /* Are we the first here? */ 293eddb60fbSPaul Mackerras if ((ee >> 8) != 0) 294eddb60fbSPaul Mackerras return; 295eddb60fbSPaul Mackerras 296eddb60fbSPaul Mackerras /* 297eddb60fbSPaul Mackerras * Trigger the other threads in this vcore to exit the guest. 298eddb60fbSPaul Mackerras * If this is a hypervisor decrementer interrupt then they 299eddb60fbSPaul Mackerras * will be already on their way out of the guest. 300eddb60fbSPaul Mackerras */ 301eddb60fbSPaul Mackerras if (trap != BOOK3S_INTERRUPT_HV_DECREMENTER) 302eddb60fbSPaul Mackerras kvmhv_interrupt_vcore(vc, ee & ~(1 << ptid)); 303b4deba5cSPaul Mackerras 304b4deba5cSPaul Mackerras /* 305b4deba5cSPaul Mackerras * If we are doing dynamic micro-threading, interrupt the other 306b4deba5cSPaul Mackerras * subcores to pull them out of their guests too. 307b4deba5cSPaul Mackerras */ 308b4deba5cSPaul Mackerras if (!sip) 309b4deba5cSPaul Mackerras return; 310b4deba5cSPaul Mackerras 311b4deba5cSPaul Mackerras for (i = 0; i < MAX_SUBCORES; ++i) { 312898b25b2SPaul Mackerras vc = sip->vc[i]; 313b4deba5cSPaul Mackerras if (!vc) 314b4deba5cSPaul Mackerras break; 315b4deba5cSPaul Mackerras do { 316b4deba5cSPaul Mackerras ee = vc->entry_exit_map; 317b4deba5cSPaul Mackerras /* Already asked to exit? */ 318b4deba5cSPaul Mackerras if ((ee >> 8) != 0) 319b4deba5cSPaul Mackerras break; 320b4deba5cSPaul Mackerras } while (cmpxchg(&vc->entry_exit_map, ee, 321b4deba5cSPaul Mackerras ee | VCORE_EXIT_REQ) != ee); 322b4deba5cSPaul Mackerras if ((ee >> 8) == 0) 323b4deba5cSPaul Mackerras kvmhv_interrupt_vcore(vc, ee); 324b4deba5cSPaul Mackerras } 325c0101509SPaul Mackerras 326c0101509SPaul Mackerras /* 327c0101509SPaul Mackerras * On POWER9 when running a HPT guest on a radix host (sip != NULL), 328c0101509SPaul Mackerras * we have to interrupt inactive CPU threads to get them to 329c0101509SPaul Mackerras * restore the host LPCR value. 330c0101509SPaul Mackerras */ 331c0101509SPaul Mackerras if (sip->lpcr_req) { 332c0101509SPaul Mackerras if (cmpxchg(&sip->do_restore, 0, 1) == 0) { 333c0101509SPaul Mackerras vc = local_paca->kvm_hstate.kvm_vcore; 334c0101509SPaul Mackerras cpu0 = vc->pcpu + ptid - local_paca->kvm_hstate.tid; 335c0101509SPaul Mackerras for (t = 1; t < threads_per_core; ++t) { 336c0101509SPaul Mackerras if (sip->napped[t]) 337c0101509SPaul Mackerras kvmhv_rm_send_ipi(cpu0 + t); 338c0101509SPaul Mackerras } 339c0101509SPaul Mackerras } 340c0101509SPaul Mackerras } 341eddb60fbSPaul Mackerras } 34279b6c247SSuresh Warrier 34379b6c247SSuresh Warrier struct kvmppc_host_rm_ops *kvmppc_host_rm_ops_hv; 34479b6c247SSuresh Warrier EXPORT_SYMBOL_GPL(kvmppc_host_rm_ops_hv); 34537f55d30SSuresh Warrier 346e3c13e56SSuresh Warrier #ifdef CONFIG_KVM_XICS 347e3c13e56SSuresh Warrier static struct kvmppc_irq_map *get_irqmap(struct kvmppc_passthru_irqmap *pimap, 348e3c13e56SSuresh Warrier u32 xisr) 349e3c13e56SSuresh Warrier { 350e3c13e56SSuresh Warrier int i; 351e3c13e56SSuresh Warrier 352e3c13e56SSuresh Warrier /* 353e3c13e56SSuresh Warrier * We access the mapped array here without a lock. That 354e3c13e56SSuresh Warrier * is safe because we never reduce the number of entries 355e3c13e56SSuresh Warrier * in the array and we never change the v_hwirq field of 356e3c13e56SSuresh Warrier * an entry once it is set. 357e3c13e56SSuresh Warrier * 358e3c13e56SSuresh Warrier * We have also carefully ordered the stores in the writer 359e3c13e56SSuresh Warrier * and the loads here in the reader, so that if we find a matching 360e3c13e56SSuresh Warrier * hwirq here, the associated GSI and irq_desc fields are valid. 361e3c13e56SSuresh Warrier */ 362e3c13e56SSuresh Warrier for (i = 0; i < pimap->n_mapped; i++) { 363e3c13e56SSuresh Warrier if (xisr == pimap->mapped[i].r_hwirq) { 364e3c13e56SSuresh Warrier /* 365e3c13e56SSuresh Warrier * Order subsequent reads in the caller to serialize 366e3c13e56SSuresh Warrier * with the writer. 367e3c13e56SSuresh Warrier */ 368e3c13e56SSuresh Warrier smp_rmb(); 369e3c13e56SSuresh Warrier return &pimap->mapped[i]; 370e3c13e56SSuresh Warrier } 371e3c13e56SSuresh Warrier } 372e3c13e56SSuresh Warrier return NULL; 373e3c13e56SSuresh Warrier } 374e3c13e56SSuresh Warrier 375e3c13e56SSuresh Warrier /* 376e3c13e56SSuresh Warrier * If we have an interrupt that's not an IPI, check if we have a 377e3c13e56SSuresh Warrier * passthrough adapter and if so, check if this external interrupt 378e3c13e56SSuresh Warrier * is for the adapter. 379e3c13e56SSuresh Warrier * We will attempt to deliver the IRQ directly to the target VCPU's 380e3c13e56SSuresh Warrier * ICP, the virtual ICP (based on affinity - the xive value in ICS). 381e3c13e56SSuresh Warrier * 382e3c13e56SSuresh Warrier * If the delivery fails or if this is not for a passthrough adapter, 383e3c13e56SSuresh Warrier * return to the host to handle this interrupt. We earlier 384e3c13e56SSuresh Warrier * saved a copy of the XIRR in the PACA, it will be picked up by 385e3c13e56SSuresh Warrier * the host ICP driver. 386e3c13e56SSuresh Warrier */ 387f725758bSPaul Mackerras static int kvmppc_check_passthru(u32 xisr, __be32 xirr, bool *again) 388e3c13e56SSuresh Warrier { 389e3c13e56SSuresh Warrier struct kvmppc_passthru_irqmap *pimap; 390e3c13e56SSuresh Warrier struct kvmppc_irq_map *irq_map; 391e3c13e56SSuresh Warrier struct kvm_vcpu *vcpu; 392e3c13e56SSuresh Warrier 393e3c13e56SSuresh Warrier vcpu = local_paca->kvm_hstate.kvm_vcpu; 394e3c13e56SSuresh Warrier if (!vcpu) 395e3c13e56SSuresh Warrier return 1; 396e3c13e56SSuresh Warrier pimap = kvmppc_get_passthru_irqmap(vcpu->kvm); 397e3c13e56SSuresh Warrier if (!pimap) 398e3c13e56SSuresh Warrier return 1; 399e3c13e56SSuresh Warrier irq_map = get_irqmap(pimap, xisr); 400e3c13e56SSuresh Warrier if (!irq_map) 401e3c13e56SSuresh Warrier return 1; 402e3c13e56SSuresh Warrier 403e3c13e56SSuresh Warrier /* We're handling this interrupt, generic code doesn't need to */ 404e3c13e56SSuresh Warrier local_paca->kvm_hstate.saved_xirr = 0; 405e3c13e56SSuresh Warrier 406f725758bSPaul Mackerras return kvmppc_deliver_irq_passthru(vcpu, xirr, irq_map, pimap, again); 407e3c13e56SSuresh Warrier } 408e3c13e56SSuresh Warrier 409e3c13e56SSuresh Warrier #else 410e2702871SPaul Mackerras static inline int kvmppc_check_passthru(u32 xisr, __be32 xirr, bool *again) 411e3c13e56SSuresh Warrier { 412e3c13e56SSuresh Warrier return 1; 413e3c13e56SSuresh Warrier } 414e3c13e56SSuresh Warrier #endif 415e3c13e56SSuresh Warrier 41637f55d30SSuresh Warrier /* 41737f55d30SSuresh Warrier * Determine what sort of external interrupt is pending (if any). 41837f55d30SSuresh Warrier * Returns: 41937f55d30SSuresh Warrier * 0 if no interrupt is pending 42037f55d30SSuresh Warrier * 1 if an interrupt is pending that needs to be handled by the host 421f7af5209SSuresh Warrier * 2 Passthrough that needs completion in the host 42237f55d30SSuresh Warrier * -1 if there was a guest wakeup IPI (which has now been cleared) 423e3c13e56SSuresh Warrier * -2 if there is PCI passthrough external interrupt that was handled 42437f55d30SSuresh Warrier */ 425f725758bSPaul Mackerras static long kvmppc_read_one_intr(bool *again); 42637f55d30SSuresh Warrier 42737f55d30SSuresh Warrier long kvmppc_read_intr(void) 42837f55d30SSuresh Warrier { 429f725758bSPaul Mackerras long ret = 0; 430f725758bSPaul Mackerras long rc; 431f725758bSPaul Mackerras bool again; 432f725758bSPaul Mackerras 433243e2511SBenjamin Herrenschmidt if (xive_enabled()) 434243e2511SBenjamin Herrenschmidt return 1; 435243e2511SBenjamin Herrenschmidt 436f725758bSPaul Mackerras do { 437f725758bSPaul Mackerras again = false; 438f725758bSPaul Mackerras rc = kvmppc_read_one_intr(&again); 439f725758bSPaul Mackerras if (rc && (ret == 0 || rc > ret)) 440f725758bSPaul Mackerras ret = rc; 441f725758bSPaul Mackerras } while (again); 442f725758bSPaul Mackerras return ret; 443f725758bSPaul Mackerras } 444f725758bSPaul Mackerras 445f725758bSPaul Mackerras static long kvmppc_read_one_intr(bool *again) 446f725758bSPaul Mackerras { 447d381d7caSBenjamin Herrenschmidt void __iomem *xics_phys; 44837f55d30SSuresh Warrier u32 h_xirr; 44937f55d30SSuresh Warrier __be32 xirr; 45037f55d30SSuresh Warrier u32 xisr; 45137f55d30SSuresh Warrier u8 host_ipi; 452f725758bSPaul Mackerras int64_t rc; 45337f55d30SSuresh Warrier 4545af50993SBenjamin Herrenschmidt if (xive_enabled()) 4555af50993SBenjamin Herrenschmidt return 1; 4565af50993SBenjamin Herrenschmidt 45737f55d30SSuresh Warrier /* see if a host IPI is pending */ 45837f55d30SSuresh Warrier host_ipi = local_paca->kvm_hstate.host_ipi; 45937f55d30SSuresh Warrier if (host_ipi) 46037f55d30SSuresh Warrier return 1; 46137f55d30SSuresh Warrier 46237f55d30SSuresh Warrier /* Now read the interrupt from the ICP */ 46337f55d30SSuresh Warrier xics_phys = local_paca->kvm_hstate.xics_phys; 46453af3ba2SPaul Mackerras rc = 0; 465ab9bad0eSBenjamin Herrenschmidt if (!xics_phys) 46653af3ba2SPaul Mackerras rc = opal_int_get_xirr(&xirr, false); 46753af3ba2SPaul Mackerras else 468d381d7caSBenjamin Herrenschmidt xirr = __raw_rm_readl(xics_phys + XICS_XIRR); 469f725758bSPaul Mackerras if (rc < 0) 47037f55d30SSuresh Warrier return 1; 47137f55d30SSuresh Warrier 47237f55d30SSuresh Warrier /* 47337f55d30SSuresh Warrier * Save XIRR for later. Since we get control in reverse endian 47437f55d30SSuresh Warrier * on LE systems, save it byte reversed and fetch it back in 47537f55d30SSuresh Warrier * host endian. Note that xirr is the value read from the 47637f55d30SSuresh Warrier * XIRR register, while h_xirr is the host endian version. 47737f55d30SSuresh Warrier */ 47837f55d30SSuresh Warrier h_xirr = be32_to_cpu(xirr); 47937f55d30SSuresh Warrier local_paca->kvm_hstate.saved_xirr = h_xirr; 48037f55d30SSuresh Warrier xisr = h_xirr & 0xffffff; 48137f55d30SSuresh Warrier /* 48237f55d30SSuresh Warrier * Ensure that the store/load complete to guarantee all side 48337f55d30SSuresh Warrier * effects of loading from XIRR has completed 48437f55d30SSuresh Warrier */ 48537f55d30SSuresh Warrier smp_mb(); 48637f55d30SSuresh Warrier 48737f55d30SSuresh Warrier /* if nothing pending in the ICP */ 48837f55d30SSuresh Warrier if (!xisr) 48937f55d30SSuresh Warrier return 0; 49037f55d30SSuresh Warrier 49137f55d30SSuresh Warrier /* We found something in the ICP... 49237f55d30SSuresh Warrier * 49337f55d30SSuresh Warrier * If it is an IPI, clear the MFRR and EOI it. 49437f55d30SSuresh Warrier */ 49537f55d30SSuresh Warrier if (xisr == XICS_IPI) { 49653af3ba2SPaul Mackerras rc = 0; 497ab9bad0eSBenjamin Herrenschmidt if (xics_phys) { 498d381d7caSBenjamin Herrenschmidt __raw_rm_writeb(0xff, xics_phys + XICS_MFRR); 499d381d7caSBenjamin Herrenschmidt __raw_rm_writel(xirr, xics_phys + XICS_XIRR); 500f725758bSPaul Mackerras } else { 501ab9bad0eSBenjamin Herrenschmidt opal_int_set_mfrr(hard_smp_processor_id(), 0xff); 502ab9bad0eSBenjamin Herrenschmidt rc = opal_int_eoi(h_xirr); 50353af3ba2SPaul Mackerras } 504f725758bSPaul Mackerras /* If rc > 0, there is another interrupt pending */ 505f725758bSPaul Mackerras *again = rc > 0; 506f725758bSPaul Mackerras 50737f55d30SSuresh Warrier /* 50837f55d30SSuresh Warrier * Need to ensure side effects of above stores 50937f55d30SSuresh Warrier * complete before proceeding. 51037f55d30SSuresh Warrier */ 51137f55d30SSuresh Warrier smp_mb(); 51237f55d30SSuresh Warrier 51337f55d30SSuresh Warrier /* 51437f55d30SSuresh Warrier * We need to re-check host IPI now in case it got set in the 51537f55d30SSuresh Warrier * meantime. If it's clear, we bounce the interrupt to the 51637f55d30SSuresh Warrier * guest 51737f55d30SSuresh Warrier */ 51837f55d30SSuresh Warrier host_ipi = local_paca->kvm_hstate.host_ipi; 51937f55d30SSuresh Warrier if (unlikely(host_ipi != 0)) { 52037f55d30SSuresh Warrier /* We raced with the host, 52137f55d30SSuresh Warrier * we need to resend that IPI, bummer 52237f55d30SSuresh Warrier */ 523ab9bad0eSBenjamin Herrenschmidt if (xics_phys) 524d381d7caSBenjamin Herrenschmidt __raw_rm_writeb(IPI_PRIORITY, 525d381d7caSBenjamin Herrenschmidt xics_phys + XICS_MFRR); 526f725758bSPaul Mackerras else 527ab9bad0eSBenjamin Herrenschmidt opal_int_set_mfrr(hard_smp_processor_id(), 528f725758bSPaul Mackerras IPI_PRIORITY); 52937f55d30SSuresh Warrier /* Let side effects complete */ 53037f55d30SSuresh Warrier smp_mb(); 53137f55d30SSuresh Warrier return 1; 53237f55d30SSuresh Warrier } 53337f55d30SSuresh Warrier 53437f55d30SSuresh Warrier /* OK, it's an IPI for us */ 53537f55d30SSuresh Warrier local_paca->kvm_hstate.saved_xirr = 0; 53637f55d30SSuresh Warrier return -1; 53737f55d30SSuresh Warrier } 53837f55d30SSuresh Warrier 539f725758bSPaul Mackerras return kvmppc_check_passthru(xisr, xirr, again); 54037f55d30SSuresh Warrier } 5415af50993SBenjamin Herrenschmidt 5425af50993SBenjamin Herrenschmidt #ifdef CONFIG_KVM_XICS 5435af50993SBenjamin Herrenschmidt static inline bool is_rm(void) 5445af50993SBenjamin Herrenschmidt { 5455af50993SBenjamin Herrenschmidt return !(mfmsr() & MSR_DR); 5465af50993SBenjamin Herrenschmidt } 5475af50993SBenjamin Herrenschmidt 5485af50993SBenjamin Herrenschmidt unsigned long kvmppc_rm_h_xirr(struct kvm_vcpu *vcpu) 5495af50993SBenjamin Herrenschmidt { 55000bb6ae5SPaul Mackerras if (!kvmppc_xics_enabled(vcpu)) 55100bb6ae5SPaul Mackerras return H_TOO_HARD; 5525af50993SBenjamin Herrenschmidt if (xive_enabled()) { 5535af50993SBenjamin Herrenschmidt if (is_rm()) 5545af50993SBenjamin Herrenschmidt return xive_rm_h_xirr(vcpu); 5555af50993SBenjamin Herrenschmidt if (unlikely(!__xive_vm_h_xirr)) 5565af50993SBenjamin Herrenschmidt return H_NOT_AVAILABLE; 5575af50993SBenjamin Herrenschmidt return __xive_vm_h_xirr(vcpu); 5585af50993SBenjamin Herrenschmidt } else 5595af50993SBenjamin Herrenschmidt return xics_rm_h_xirr(vcpu); 5605af50993SBenjamin Herrenschmidt } 5615af50993SBenjamin Herrenschmidt 5625af50993SBenjamin Herrenschmidt unsigned long kvmppc_rm_h_xirr_x(struct kvm_vcpu *vcpu) 5635af50993SBenjamin Herrenschmidt { 56400bb6ae5SPaul Mackerras if (!kvmppc_xics_enabled(vcpu)) 56500bb6ae5SPaul Mackerras return H_TOO_HARD; 5661143a706SSimon Guo vcpu->arch.regs.gpr[5] = get_tb(); 5675af50993SBenjamin Herrenschmidt if (xive_enabled()) { 5685af50993SBenjamin Herrenschmidt if (is_rm()) 5695af50993SBenjamin Herrenschmidt return xive_rm_h_xirr(vcpu); 5705af50993SBenjamin Herrenschmidt if (unlikely(!__xive_vm_h_xirr)) 5715af50993SBenjamin Herrenschmidt return H_NOT_AVAILABLE; 5725af50993SBenjamin Herrenschmidt return __xive_vm_h_xirr(vcpu); 5735af50993SBenjamin Herrenschmidt } else 5745af50993SBenjamin Herrenschmidt return xics_rm_h_xirr(vcpu); 5755af50993SBenjamin Herrenschmidt } 5765af50993SBenjamin Herrenschmidt 5775af50993SBenjamin Herrenschmidt unsigned long kvmppc_rm_h_ipoll(struct kvm_vcpu *vcpu, unsigned long server) 5785af50993SBenjamin Herrenschmidt { 57900bb6ae5SPaul Mackerras if (!kvmppc_xics_enabled(vcpu)) 58000bb6ae5SPaul Mackerras return H_TOO_HARD; 5815af50993SBenjamin Herrenschmidt if (xive_enabled()) { 5825af50993SBenjamin Herrenschmidt if (is_rm()) 5835af50993SBenjamin Herrenschmidt return xive_rm_h_ipoll(vcpu, server); 5845af50993SBenjamin Herrenschmidt if (unlikely(!__xive_vm_h_ipoll)) 5855af50993SBenjamin Herrenschmidt return H_NOT_AVAILABLE; 5865af50993SBenjamin Herrenschmidt return __xive_vm_h_ipoll(vcpu, server); 5875af50993SBenjamin Herrenschmidt } else 5885af50993SBenjamin Herrenschmidt return H_TOO_HARD; 5895af50993SBenjamin Herrenschmidt } 5905af50993SBenjamin Herrenschmidt 5915af50993SBenjamin Herrenschmidt int kvmppc_rm_h_ipi(struct kvm_vcpu *vcpu, unsigned long server, 5925af50993SBenjamin Herrenschmidt unsigned long mfrr) 5935af50993SBenjamin Herrenschmidt { 59400bb6ae5SPaul Mackerras if (!kvmppc_xics_enabled(vcpu)) 59500bb6ae5SPaul Mackerras return H_TOO_HARD; 5965af50993SBenjamin Herrenschmidt if (xive_enabled()) { 5975af50993SBenjamin Herrenschmidt if (is_rm()) 5985af50993SBenjamin Herrenschmidt return xive_rm_h_ipi(vcpu, server, mfrr); 5995af50993SBenjamin Herrenschmidt if (unlikely(!__xive_vm_h_ipi)) 6005af50993SBenjamin Herrenschmidt return H_NOT_AVAILABLE; 6015af50993SBenjamin Herrenschmidt return __xive_vm_h_ipi(vcpu, server, mfrr); 6025af50993SBenjamin Herrenschmidt } else 6035af50993SBenjamin Herrenschmidt return xics_rm_h_ipi(vcpu, server, mfrr); 6045af50993SBenjamin Herrenschmidt } 6055af50993SBenjamin Herrenschmidt 6065af50993SBenjamin Herrenschmidt int kvmppc_rm_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr) 6075af50993SBenjamin Herrenschmidt { 60800bb6ae5SPaul Mackerras if (!kvmppc_xics_enabled(vcpu)) 60900bb6ae5SPaul Mackerras return H_TOO_HARD; 6105af50993SBenjamin Herrenschmidt if (xive_enabled()) { 6115af50993SBenjamin Herrenschmidt if (is_rm()) 6125af50993SBenjamin Herrenschmidt return xive_rm_h_cppr(vcpu, cppr); 6135af50993SBenjamin Herrenschmidt if (unlikely(!__xive_vm_h_cppr)) 6145af50993SBenjamin Herrenschmidt return H_NOT_AVAILABLE; 6155af50993SBenjamin Herrenschmidt return __xive_vm_h_cppr(vcpu, cppr); 6165af50993SBenjamin Herrenschmidt } else 6175af50993SBenjamin Herrenschmidt return xics_rm_h_cppr(vcpu, cppr); 6185af50993SBenjamin Herrenschmidt } 6195af50993SBenjamin Herrenschmidt 6205af50993SBenjamin Herrenschmidt int kvmppc_rm_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr) 6215af50993SBenjamin Herrenschmidt { 62200bb6ae5SPaul Mackerras if (!kvmppc_xics_enabled(vcpu)) 62300bb6ae5SPaul Mackerras return H_TOO_HARD; 6245af50993SBenjamin Herrenschmidt if (xive_enabled()) { 6255af50993SBenjamin Herrenschmidt if (is_rm()) 6265af50993SBenjamin Herrenschmidt return xive_rm_h_eoi(vcpu, xirr); 6275af50993SBenjamin Herrenschmidt if (unlikely(!__xive_vm_h_eoi)) 6285af50993SBenjamin Herrenschmidt return H_NOT_AVAILABLE; 6295af50993SBenjamin Herrenschmidt return __xive_vm_h_eoi(vcpu, xirr); 6305af50993SBenjamin Herrenschmidt } else 6315af50993SBenjamin Herrenschmidt return xics_rm_h_eoi(vcpu, xirr); 6325af50993SBenjamin Herrenschmidt } 6335af50993SBenjamin Herrenschmidt #endif /* CONFIG_KVM_XICS */ 634857b99e1SPaul Mackerras 635857b99e1SPaul Mackerras void kvmppc_bad_interrupt(struct pt_regs *regs) 636857b99e1SPaul Mackerras { 6377c1bd80cSNicholas Piggin /* 6387c1bd80cSNicholas Piggin * 100 could happen at any time, 200 can happen due to invalid real 6397c1bd80cSNicholas Piggin * address access for example (or any time due to a hardware problem). 6407c1bd80cSNicholas Piggin */ 6417c1bd80cSNicholas Piggin if (TRAP(regs) == 0x100) { 6427c1bd80cSNicholas Piggin get_paca()->in_nmi++; 6437c1bd80cSNicholas Piggin system_reset_exception(regs); 6447c1bd80cSNicholas Piggin get_paca()->in_nmi--; 6457c1bd80cSNicholas Piggin } else if (TRAP(regs) == 0x200) { 6467c1bd80cSNicholas Piggin machine_check_exception(regs); 6477c1bd80cSNicholas Piggin } else { 648857b99e1SPaul Mackerras die("Bad interrupt in KVM entry/exit code", regs, SIGABRT); 6497c1bd80cSNicholas Piggin } 650857b99e1SPaul Mackerras panic("Bad KVM trap"); 651857b99e1SPaul Mackerras } 652c0101509SPaul Mackerras 653c0101509SPaul Mackerras /* 654c0101509SPaul Mackerras * Functions used to switch LPCR HR and UPRT bits on all threads 655c0101509SPaul Mackerras * when entering and exiting HPT guests on a radix host. 656c0101509SPaul Mackerras */ 657c0101509SPaul Mackerras 658c0101509SPaul Mackerras #define PHASE_REALMODE 1 /* in real mode */ 659c0101509SPaul Mackerras #define PHASE_SET_LPCR 2 /* have set LPCR */ 660c0101509SPaul Mackerras #define PHASE_OUT_OF_GUEST 4 /* have finished executing in guest */ 661c0101509SPaul Mackerras #define PHASE_RESET_LPCR 8 /* have reset LPCR to host value */ 662c0101509SPaul Mackerras 663c0101509SPaul Mackerras #define ALL(p) (((p) << 24) | ((p) << 16) | ((p) << 8) | (p)) 664c0101509SPaul Mackerras 665c0101509SPaul Mackerras static void wait_for_sync(struct kvm_split_mode *sip, int phase) 666c0101509SPaul Mackerras { 667c0101509SPaul Mackerras int thr = local_paca->kvm_hstate.tid; 668c0101509SPaul Mackerras 669c0101509SPaul Mackerras sip->lpcr_sync.phase[thr] |= phase; 670c0101509SPaul Mackerras phase = ALL(phase); 671c0101509SPaul Mackerras while ((sip->lpcr_sync.allphases & phase) != phase) { 672c0101509SPaul Mackerras HMT_low(); 673c0101509SPaul Mackerras barrier(); 674c0101509SPaul Mackerras } 675c0101509SPaul Mackerras HMT_medium(); 676c0101509SPaul Mackerras } 677c0101509SPaul Mackerras 678c0101509SPaul Mackerras void kvmhv_p9_set_lpcr(struct kvm_split_mode *sip) 679c0101509SPaul Mackerras { 680c0101509SPaul Mackerras unsigned long rb, set; 681c0101509SPaul Mackerras 682c0101509SPaul Mackerras /* wait for every other thread to get to real mode */ 683c0101509SPaul Mackerras wait_for_sync(sip, PHASE_REALMODE); 684c0101509SPaul Mackerras 685c0101509SPaul Mackerras /* Set LPCR and LPIDR */ 686c0101509SPaul Mackerras mtspr(SPRN_LPCR, sip->lpcr_req); 687c0101509SPaul Mackerras mtspr(SPRN_LPID, sip->lpidr_req); 688c0101509SPaul Mackerras isync(); 689c0101509SPaul Mackerras 690c0101509SPaul Mackerras /* Invalidate the TLB on thread 0 */ 691c0101509SPaul Mackerras if (local_paca->kvm_hstate.tid == 0) { 692c0101509SPaul Mackerras sip->do_set = 0; 693c0101509SPaul Mackerras asm volatile("ptesync" : : : "memory"); 694c0101509SPaul Mackerras for (set = 0; set < POWER9_TLB_SETS_RADIX; ++set) { 695c0101509SPaul Mackerras rb = TLBIEL_INVAL_SET_LPID + 696c0101509SPaul Mackerras (set << TLBIEL_INVAL_SET_SHIFT); 697c0101509SPaul Mackerras asm volatile(PPC_TLBIEL(%0, %1, 0, 0, 0) : : 698c0101509SPaul Mackerras "r" (rb), "r" (0)); 699c0101509SPaul Mackerras } 700c0101509SPaul Mackerras asm volatile("ptesync" : : : "memory"); 701c0101509SPaul Mackerras } 702c0101509SPaul Mackerras 703c0101509SPaul Mackerras /* indicate that we have done so and wait for others */ 704c0101509SPaul Mackerras wait_for_sync(sip, PHASE_SET_LPCR); 705c0101509SPaul Mackerras /* order read of sip->lpcr_sync.allphases vs. sip->do_set */ 706c0101509SPaul Mackerras smp_rmb(); 707c0101509SPaul Mackerras } 708c0101509SPaul Mackerras 709c0101509SPaul Mackerras /* 710c0101509SPaul Mackerras * Called when a thread that has been in the guest needs 711c0101509SPaul Mackerras * to reload the host LPCR value - but only on POWER9 when 712c0101509SPaul Mackerras * running a HPT guest on a radix host. 713c0101509SPaul Mackerras */ 714c0101509SPaul Mackerras void kvmhv_p9_restore_lpcr(struct kvm_split_mode *sip) 715c0101509SPaul Mackerras { 716c0101509SPaul Mackerras /* we're out of the guest... */ 717c0101509SPaul Mackerras wait_for_sync(sip, PHASE_OUT_OF_GUEST); 718c0101509SPaul Mackerras 719c0101509SPaul Mackerras mtspr(SPRN_LPID, 0); 720c0101509SPaul Mackerras mtspr(SPRN_LPCR, sip->host_lpcr); 721c0101509SPaul Mackerras isync(); 722c0101509SPaul Mackerras 723c0101509SPaul Mackerras if (local_paca->kvm_hstate.tid == 0) { 724c0101509SPaul Mackerras sip->do_restore = 0; 725c0101509SPaul Mackerras smp_wmb(); /* order store of do_restore vs. phase */ 726c0101509SPaul Mackerras } 727c0101509SPaul Mackerras 728c0101509SPaul Mackerras wait_for_sync(sip, PHASE_RESET_LPCR); 729c0101509SPaul Mackerras smp_mb(); 730c0101509SPaul Mackerras local_paca->kvm_hstate.kvm_split_mode = NULL; 731c0101509SPaul Mackerras } 732