1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2aa04b4ccSPaul Mackerras /* 3aa04b4ccSPaul Mackerras * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com> 4aa04b4ccSPaul Mackerras */ 5aa04b4ccSPaul Mackerras 6441c19c8SMichael Ellerman #include <linux/cpu.h> 7aa04b4ccSPaul Mackerras #include <linux/kvm_host.h> 8aa04b4ccSPaul Mackerras #include <linux/preempt.h> 966b15db6SPaul Gortmaker #include <linux/export.h> 10aa04b4ccSPaul Mackerras #include <linux/sched.h> 11aa04b4ccSPaul Mackerras #include <linux/spinlock.h> 12aa04b4ccSPaul Mackerras #include <linux/init.h> 13fa61a4e3SAneesh Kumar K.V #include <linux/memblock.h> 14fa61a4e3SAneesh Kumar K.V #include <linux/sizes.h> 15fc95ca72SJoonsoo Kim #include <linux/cma.h> 1690fd09f8SSam Bobroff #include <linux/bitops.h> 17aa04b4ccSPaul Mackerras 187c1bd80cSNicholas Piggin #include <asm/asm-prototypes.h> 19aa04b4ccSPaul Mackerras #include <asm/cputable.h> 20*3a96570fSNicholas Piggin #include <asm/interrupt.h> 21aa04b4ccSPaul Mackerras #include <asm/kvm_ppc.h> 22aa04b4ccSPaul Mackerras #include <asm/kvm_book3s.h> 23e928e9cbSMichael Ellerman #include <asm/archrandom.h> 24eddb60fbSPaul Mackerras #include <asm/xics.h> 25243e2511SBenjamin Herrenschmidt #include <asm/xive.h> 2666feed61SPaul Mackerras #include <asm/dbell.h> 2766feed61SPaul Mackerras #include <asm/cputhreads.h> 2837f55d30SSuresh Warrier #include <asm/io.h> 29f725758bSPaul Mackerras #include <asm/opal.h> 30e2702871SPaul Mackerras #include <asm/smp.h> 31aa04b4ccSPaul Mackerras 32fc95ca72SJoonsoo Kim #define KVM_CMA_CHUNK_ORDER 18 33fc95ca72SJoonsoo Kim 345af50993SBenjamin Herrenschmidt #include "book3s_xics.h" 355af50993SBenjamin Herrenschmidt #include "book3s_xive.h" 365af50993SBenjamin Herrenschmidt 375af50993SBenjamin Herrenschmidt /* 385af50993SBenjamin Herrenschmidt * The XIVE module will populate these when it loads 395af50993SBenjamin Herrenschmidt */ 405af50993SBenjamin Herrenschmidt unsigned long (*__xive_vm_h_xirr)(struct kvm_vcpu *vcpu); 415af50993SBenjamin Herrenschmidt unsigned long (*__xive_vm_h_ipoll)(struct kvm_vcpu *vcpu, unsigned long server); 425af50993SBenjamin Herrenschmidt int (*__xive_vm_h_ipi)(struct kvm_vcpu *vcpu, unsigned long server, 435af50993SBenjamin Herrenschmidt unsigned long mfrr); 445af50993SBenjamin Herrenschmidt int (*__xive_vm_h_cppr)(struct kvm_vcpu *vcpu, unsigned long cppr); 455af50993SBenjamin Herrenschmidt int (*__xive_vm_h_eoi)(struct kvm_vcpu *vcpu, unsigned long xirr); 465af50993SBenjamin Herrenschmidt EXPORT_SYMBOL_GPL(__xive_vm_h_xirr); 475af50993SBenjamin Herrenschmidt EXPORT_SYMBOL_GPL(__xive_vm_h_ipoll); 485af50993SBenjamin Herrenschmidt EXPORT_SYMBOL_GPL(__xive_vm_h_ipi); 495af50993SBenjamin Herrenschmidt EXPORT_SYMBOL_GPL(__xive_vm_h_cppr); 505af50993SBenjamin Herrenschmidt EXPORT_SYMBOL_GPL(__xive_vm_h_eoi); 515af50993SBenjamin Herrenschmidt 52fa61a4e3SAneesh Kumar K.V /* 53fa61a4e3SAneesh Kumar K.V * Hash page table alignment on newer cpus(CPU_FTR_ARCH_206) 54fa61a4e3SAneesh Kumar K.V * should be power of 2. 55fa61a4e3SAneesh Kumar K.V */ 56fa61a4e3SAneesh Kumar K.V #define HPT_ALIGN_PAGES ((1 << 18) >> PAGE_SHIFT) /* 256k */ 57fa61a4e3SAneesh Kumar K.V /* 58fa61a4e3SAneesh Kumar K.V * By default we reserve 5% of memory for hash pagetable allocation. 59fa61a4e3SAneesh Kumar K.V */ 60fa61a4e3SAneesh Kumar K.V static unsigned long kvm_cma_resv_ratio = 5; 61aa04b4ccSPaul Mackerras 62fc95ca72SJoonsoo Kim static struct cma *kvm_cma; 63fc95ca72SJoonsoo Kim 64fa61a4e3SAneesh Kumar K.V static int __init early_parse_kvm_cma_resv(char *p) 65d2a1b483SAlexander Graf { 66fa61a4e3SAneesh Kumar K.V pr_debug("%s(%s)\n", __func__, p); 67d2a1b483SAlexander Graf if (!p) 68fa61a4e3SAneesh Kumar K.V return -EINVAL; 69fa61a4e3SAneesh Kumar K.V return kstrtoul(p, 0, &kvm_cma_resv_ratio); 70d2a1b483SAlexander Graf } 71fa61a4e3SAneesh Kumar K.V early_param("kvm_cma_resv_ratio", early_parse_kvm_cma_resv); 72d2a1b483SAlexander Graf 73db9a290dSDavid Gibson struct page *kvm_alloc_hpt_cma(unsigned long nr_pages) 74d2a1b483SAlexander Graf { 75c04fa583SAlexey Kardashevskiy VM_BUG_ON(order_base_2(nr_pages) < KVM_CMA_CHUNK_ORDER - PAGE_SHIFT); 76fc95ca72SJoonsoo Kim 77e2f466e3SLucas Stach return cma_alloc(kvm_cma, nr_pages, order_base_2(HPT_ALIGN_PAGES), 7865182029SMarek Szyprowski false); 79d2a1b483SAlexander Graf } 80db9a290dSDavid Gibson EXPORT_SYMBOL_GPL(kvm_alloc_hpt_cma); 81d2a1b483SAlexander Graf 82db9a290dSDavid Gibson void kvm_free_hpt_cma(struct page *page, unsigned long nr_pages) 83d2a1b483SAlexander Graf { 84fc95ca72SJoonsoo Kim cma_release(kvm_cma, page, nr_pages); 85d2a1b483SAlexander Graf } 86db9a290dSDavid Gibson EXPORT_SYMBOL_GPL(kvm_free_hpt_cma); 87d2a1b483SAlexander Graf 88fa61a4e3SAneesh Kumar K.V /** 89fa61a4e3SAneesh Kumar K.V * kvm_cma_reserve() - reserve area for kvm hash pagetable 90fa61a4e3SAneesh Kumar K.V * 91fa61a4e3SAneesh Kumar K.V * This function reserves memory from early allocator. It should be 9214ed7409SAnton Blanchard * called by arch specific code once the memblock allocator 93fa61a4e3SAneesh Kumar K.V * has been activated and all other subsystems have already allocated/reserved 94fa61a4e3SAneesh Kumar K.V * memory. 95fa61a4e3SAneesh Kumar K.V */ 96fa61a4e3SAneesh Kumar K.V void __init kvm_cma_reserve(void) 97fa61a4e3SAneesh Kumar K.V { 98fa61a4e3SAneesh Kumar K.V unsigned long align_size; 9904ba0a92SMike Rapoport phys_addr_t selected_size; 100cec26bc3SAneesh Kumar K.V 101cec26bc3SAneesh Kumar K.V /* 102cec26bc3SAneesh Kumar K.V * We need CMA reservation only when we are in HV mode 103cec26bc3SAneesh Kumar K.V */ 104cec26bc3SAneesh Kumar K.V if (!cpu_has_feature(CPU_FTR_HVMODE)) 105cec26bc3SAneesh Kumar K.V return; 106fa61a4e3SAneesh Kumar K.V 10704ba0a92SMike Rapoport selected_size = PAGE_ALIGN(memblock_phys_mem_size() * kvm_cma_resv_ratio / 100); 108fa61a4e3SAneesh Kumar K.V if (selected_size) { 109a5a8b258SAneesh Kumar K.V pr_info("%s: reserving %ld MiB for global area\n", __func__, 110fa61a4e3SAneesh Kumar K.V (unsigned long)selected_size / SZ_1M); 111fa61a4e3SAneesh Kumar K.V align_size = HPT_ALIGN_PAGES << PAGE_SHIFT; 112c1f733aaSJoonsoo Kim cma_declare_contiguous(0, selected_size, 0, align_size, 113f318dd08SLaura Abbott KVM_CMA_CHUNK_ORDER - PAGE_SHIFT, false, "kvm_cma", 114f318dd08SLaura Abbott &kvm_cma); 115fa61a4e3SAneesh Kumar K.V } 116fa61a4e3SAneesh Kumar K.V } 117441c19c8SMichael Ellerman 118441c19c8SMichael Ellerman /* 11990fd09f8SSam Bobroff * Real-mode H_CONFER implementation. 12090fd09f8SSam Bobroff * We check if we are the only vcpu out of this virtual core 12190fd09f8SSam Bobroff * still running in the guest and not ceded. If so, we pop up 12290fd09f8SSam Bobroff * to the virtual-mode implementation; if not, just return to 12390fd09f8SSam Bobroff * the guest. 12490fd09f8SSam Bobroff */ 12590fd09f8SSam Bobroff long int kvmppc_rm_h_confer(struct kvm_vcpu *vcpu, int target, 12690fd09f8SSam Bobroff unsigned int yield_count) 12790fd09f8SSam Bobroff { 128ec257165SPaul Mackerras struct kvmppc_vcore *vc = local_paca->kvm_hstate.kvm_vcore; 129ec257165SPaul Mackerras int ptid = local_paca->kvm_hstate.ptid; 13090fd09f8SSam Bobroff int threads_running; 13190fd09f8SSam Bobroff int threads_ceded; 13290fd09f8SSam Bobroff int threads_conferring; 13390fd09f8SSam Bobroff u64 stop = get_tb() + 10 * tb_ticks_per_usec; 13490fd09f8SSam Bobroff int rv = H_SUCCESS; /* => don't yield */ 13590fd09f8SSam Bobroff 136ec257165SPaul Mackerras set_bit(ptid, &vc->conferring_threads); 1377d6c40daSPaul Mackerras while ((get_tb() < stop) && !VCORE_IS_EXITING(vc)) { 1387d6c40daSPaul Mackerras threads_running = VCORE_ENTRY_MAP(vc); 1397d6c40daSPaul Mackerras threads_ceded = vc->napping_threads; 1407d6c40daSPaul Mackerras threads_conferring = vc->conferring_threads; 1417d6c40daSPaul Mackerras if ((threads_ceded | threads_conferring) == threads_running) { 14290fd09f8SSam Bobroff rv = H_TOO_HARD; /* => do yield */ 14390fd09f8SSam Bobroff break; 14490fd09f8SSam Bobroff } 14590fd09f8SSam Bobroff } 146ec257165SPaul Mackerras clear_bit(ptid, &vc->conferring_threads); 14790fd09f8SSam Bobroff return rv; 14890fd09f8SSam Bobroff } 14990fd09f8SSam Bobroff 15090fd09f8SSam Bobroff /* 151441c19c8SMichael Ellerman * When running HV mode KVM we need to block certain operations while KVM VMs 152441c19c8SMichael Ellerman * exist in the system. We use a counter of VMs to track this. 153441c19c8SMichael Ellerman * 154441c19c8SMichael Ellerman * One of the operations we need to block is onlining of secondaries, so we 155441c19c8SMichael Ellerman * protect hv_vm_count with get/put_online_cpus(). 156441c19c8SMichael Ellerman */ 157441c19c8SMichael Ellerman static atomic_t hv_vm_count; 158441c19c8SMichael Ellerman 159441c19c8SMichael Ellerman void kvm_hv_vm_activated(void) 160441c19c8SMichael Ellerman { 161441c19c8SMichael Ellerman get_online_cpus(); 162441c19c8SMichael Ellerman atomic_inc(&hv_vm_count); 163441c19c8SMichael Ellerman put_online_cpus(); 164441c19c8SMichael Ellerman } 165441c19c8SMichael Ellerman EXPORT_SYMBOL_GPL(kvm_hv_vm_activated); 166441c19c8SMichael Ellerman 167441c19c8SMichael Ellerman void kvm_hv_vm_deactivated(void) 168441c19c8SMichael Ellerman { 169441c19c8SMichael Ellerman get_online_cpus(); 170441c19c8SMichael Ellerman atomic_dec(&hv_vm_count); 171441c19c8SMichael Ellerman put_online_cpus(); 172441c19c8SMichael Ellerman } 173441c19c8SMichael Ellerman EXPORT_SYMBOL_GPL(kvm_hv_vm_deactivated); 174441c19c8SMichael Ellerman 175441c19c8SMichael Ellerman bool kvm_hv_mode_active(void) 176441c19c8SMichael Ellerman { 177441c19c8SMichael Ellerman return atomic_read(&hv_vm_count) != 0; 178441c19c8SMichael Ellerman } 179ae2113a4SPaul Mackerras 180ae2113a4SPaul Mackerras extern int hcall_real_table[], hcall_real_table_end[]; 181ae2113a4SPaul Mackerras 182ae2113a4SPaul Mackerras int kvmppc_hcall_impl_hv_realmode(unsigned long cmd) 183ae2113a4SPaul Mackerras { 184ae2113a4SPaul Mackerras cmd /= 4; 185ae2113a4SPaul Mackerras if (cmd < hcall_real_table_end - hcall_real_table && 186ae2113a4SPaul Mackerras hcall_real_table[cmd]) 187ae2113a4SPaul Mackerras return 1; 188ae2113a4SPaul Mackerras 189ae2113a4SPaul Mackerras return 0; 190ae2113a4SPaul Mackerras } 191ae2113a4SPaul Mackerras EXPORT_SYMBOL_GPL(kvmppc_hcall_impl_hv_realmode); 192e928e9cbSMichael Ellerman 193e928e9cbSMichael Ellerman int kvmppc_hwrng_present(void) 194e928e9cbSMichael Ellerman { 195e928e9cbSMichael Ellerman return powernv_hwrng_present(); 196e928e9cbSMichael Ellerman } 197e928e9cbSMichael Ellerman EXPORT_SYMBOL_GPL(kvmppc_hwrng_present); 198e928e9cbSMichael Ellerman 199e928e9cbSMichael Ellerman long kvmppc_h_random(struct kvm_vcpu *vcpu) 200e928e9cbSMichael Ellerman { 201acde2572SPaul Mackerras int r; 202acde2572SPaul Mackerras 203acde2572SPaul Mackerras /* Only need to do the expensive mfmsr() on radix */ 204acde2572SPaul Mackerras if (kvm_is_radix(vcpu->kvm) && (mfmsr() & MSR_IR)) 2051143a706SSimon Guo r = powernv_get_random_long(&vcpu->arch.regs.gpr[4]); 206acde2572SPaul Mackerras else 2071143a706SSimon Guo r = powernv_get_random_real_mode(&vcpu->arch.regs.gpr[4]); 208acde2572SPaul Mackerras if (r) 209e928e9cbSMichael Ellerman return H_SUCCESS; 210e928e9cbSMichael Ellerman 211e928e9cbSMichael Ellerman return H_HARDWARE; 212e928e9cbSMichael Ellerman } 213eddb60fbSPaul Mackerras 214eddb60fbSPaul Mackerras /* 21566feed61SPaul Mackerras * Send an interrupt or message to another CPU. 216eddb60fbSPaul Mackerras * The caller needs to include any barrier needed to order writes 217eddb60fbSPaul Mackerras * to memory vs. the IPI/message. 218eddb60fbSPaul Mackerras */ 219eddb60fbSPaul Mackerras void kvmhv_rm_send_ipi(int cpu) 220eddb60fbSPaul Mackerras { 221d381d7caSBenjamin Herrenschmidt void __iomem *xics_phys; 2221704a81cSPaul Mackerras unsigned long msg = PPC_DBELL_TYPE(PPC_DBELL_SERVER); 223eddb60fbSPaul Mackerras 224f3c18e93SPaul Mackerras /* For a nested hypervisor, use the XICS via hcall */ 225f3c18e93SPaul Mackerras if (kvmhv_on_pseries()) { 226f3c18e93SPaul Mackerras unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 227f3c18e93SPaul Mackerras 228f3c18e93SPaul Mackerras plpar_hcall_raw(H_IPI, retbuf, get_hard_smp_processor_id(cpu), 229f3c18e93SPaul Mackerras IPI_PRIORITY); 230f3c18e93SPaul Mackerras return; 231f3c18e93SPaul Mackerras } 232f3c18e93SPaul Mackerras 2331704a81cSPaul Mackerras /* On POWER9 we can use msgsnd for any destination cpu. */ 2341704a81cSPaul Mackerras if (cpu_has_feature(CPU_FTR_ARCH_300)) { 2351704a81cSPaul Mackerras msg |= get_hard_smp_processor_id(cpu); 2361704a81cSPaul Mackerras __asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg)); 2371704a81cSPaul Mackerras return; 2381704a81cSPaul Mackerras } 2395af50993SBenjamin Herrenschmidt 2401704a81cSPaul Mackerras /* On POWER8 for IPIs to threads in the same core, use msgsnd. */ 24166feed61SPaul Mackerras if (cpu_has_feature(CPU_FTR_ARCH_207S) && 24266feed61SPaul Mackerras cpu_first_thread_sibling(cpu) == 24366feed61SPaul Mackerras cpu_first_thread_sibling(raw_smp_processor_id())) { 24466feed61SPaul Mackerras msg |= cpu_thread_in_core(cpu); 24566feed61SPaul Mackerras __asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg)); 24666feed61SPaul Mackerras return; 24766feed61SPaul Mackerras } 24866feed61SPaul Mackerras 249243e2511SBenjamin Herrenschmidt /* We should never reach this */ 25003f95332SPaul Mackerras if (WARN_ON_ONCE(xics_on_xive())) 251243e2511SBenjamin Herrenschmidt return; 252243e2511SBenjamin Herrenschmidt 25366feed61SPaul Mackerras /* Else poke the target with an IPI */ 254d2e60075SNicholas Piggin xics_phys = paca_ptrs[cpu]->kvm_hstate.xics_phys; 255ab9bad0eSBenjamin Herrenschmidt if (xics_phys) 256d381d7caSBenjamin Herrenschmidt __raw_rm_writeb(IPI_PRIORITY, xics_phys + XICS_MFRR); 257f725758bSPaul Mackerras else 258ab9bad0eSBenjamin Herrenschmidt opal_int_set_mfrr(get_hard_smp_processor_id(cpu), IPI_PRIORITY); 259eddb60fbSPaul Mackerras } 260eddb60fbSPaul Mackerras 261eddb60fbSPaul Mackerras /* 262eddb60fbSPaul Mackerras * The following functions are called from the assembly code 263eddb60fbSPaul Mackerras * in book3s_hv_rmhandlers.S. 264eddb60fbSPaul Mackerras */ 265eddb60fbSPaul Mackerras static void kvmhv_interrupt_vcore(struct kvmppc_vcore *vc, int active) 266eddb60fbSPaul Mackerras { 267eddb60fbSPaul Mackerras int cpu = vc->pcpu; 268eddb60fbSPaul Mackerras 269eddb60fbSPaul Mackerras /* Order setting of exit map vs. msgsnd/IPI */ 270eddb60fbSPaul Mackerras smp_mb(); 271eddb60fbSPaul Mackerras for (; active; active >>= 1, ++cpu) 272eddb60fbSPaul Mackerras if (active & 1) 273eddb60fbSPaul Mackerras kvmhv_rm_send_ipi(cpu); 274eddb60fbSPaul Mackerras } 275eddb60fbSPaul Mackerras 276eddb60fbSPaul Mackerras void kvmhv_commence_exit(int trap) 277eddb60fbSPaul Mackerras { 278eddb60fbSPaul Mackerras struct kvmppc_vcore *vc = local_paca->kvm_hstate.kvm_vcore; 279eddb60fbSPaul Mackerras int ptid = local_paca->kvm_hstate.ptid; 280b4deba5cSPaul Mackerras struct kvm_split_mode *sip = local_paca->kvm_hstate.kvm_split_mode; 281c0101509SPaul Mackerras int me, ee, i, t; 282c0101509SPaul Mackerras int cpu0; 283eddb60fbSPaul Mackerras 284eddb60fbSPaul Mackerras /* Set our bit in the threads-exiting-guest map in the 0xff00 285eddb60fbSPaul Mackerras bits of vcore->entry_exit_map */ 286eddb60fbSPaul Mackerras me = 0x100 << ptid; 287eddb60fbSPaul Mackerras do { 288eddb60fbSPaul Mackerras ee = vc->entry_exit_map; 289eddb60fbSPaul Mackerras } while (cmpxchg(&vc->entry_exit_map, ee, ee | me) != ee); 290eddb60fbSPaul Mackerras 291eddb60fbSPaul Mackerras /* Are we the first here? */ 292eddb60fbSPaul Mackerras if ((ee >> 8) != 0) 293eddb60fbSPaul Mackerras return; 294eddb60fbSPaul Mackerras 295eddb60fbSPaul Mackerras /* 296eddb60fbSPaul Mackerras * Trigger the other threads in this vcore to exit the guest. 297eddb60fbSPaul Mackerras * If this is a hypervisor decrementer interrupt then they 298eddb60fbSPaul Mackerras * will be already on their way out of the guest. 299eddb60fbSPaul Mackerras */ 300eddb60fbSPaul Mackerras if (trap != BOOK3S_INTERRUPT_HV_DECREMENTER) 301eddb60fbSPaul Mackerras kvmhv_interrupt_vcore(vc, ee & ~(1 << ptid)); 302b4deba5cSPaul Mackerras 303b4deba5cSPaul Mackerras /* 304b4deba5cSPaul Mackerras * If we are doing dynamic micro-threading, interrupt the other 305b4deba5cSPaul Mackerras * subcores to pull them out of their guests too. 306b4deba5cSPaul Mackerras */ 307b4deba5cSPaul Mackerras if (!sip) 308b4deba5cSPaul Mackerras return; 309b4deba5cSPaul Mackerras 310b4deba5cSPaul Mackerras for (i = 0; i < MAX_SUBCORES; ++i) { 311898b25b2SPaul Mackerras vc = sip->vc[i]; 312b4deba5cSPaul Mackerras if (!vc) 313b4deba5cSPaul Mackerras break; 314b4deba5cSPaul Mackerras do { 315b4deba5cSPaul Mackerras ee = vc->entry_exit_map; 316b4deba5cSPaul Mackerras /* Already asked to exit? */ 317b4deba5cSPaul Mackerras if ((ee >> 8) != 0) 318b4deba5cSPaul Mackerras break; 319b4deba5cSPaul Mackerras } while (cmpxchg(&vc->entry_exit_map, ee, 320b4deba5cSPaul Mackerras ee | VCORE_EXIT_REQ) != ee); 321b4deba5cSPaul Mackerras if ((ee >> 8) == 0) 322b4deba5cSPaul Mackerras kvmhv_interrupt_vcore(vc, ee); 323b4deba5cSPaul Mackerras } 324c0101509SPaul Mackerras 325c0101509SPaul Mackerras /* 326c0101509SPaul Mackerras * On POWER9 when running a HPT guest on a radix host (sip != NULL), 327c0101509SPaul Mackerras * we have to interrupt inactive CPU threads to get them to 328c0101509SPaul Mackerras * restore the host LPCR value. 329c0101509SPaul Mackerras */ 330c0101509SPaul Mackerras if (sip->lpcr_req) { 331c0101509SPaul Mackerras if (cmpxchg(&sip->do_restore, 0, 1) == 0) { 332c0101509SPaul Mackerras vc = local_paca->kvm_hstate.kvm_vcore; 333c0101509SPaul Mackerras cpu0 = vc->pcpu + ptid - local_paca->kvm_hstate.tid; 334c0101509SPaul Mackerras for (t = 1; t < threads_per_core; ++t) { 335c0101509SPaul Mackerras if (sip->napped[t]) 336c0101509SPaul Mackerras kvmhv_rm_send_ipi(cpu0 + t); 337c0101509SPaul Mackerras } 338c0101509SPaul Mackerras } 339c0101509SPaul Mackerras } 340eddb60fbSPaul Mackerras } 34179b6c247SSuresh Warrier 34279b6c247SSuresh Warrier struct kvmppc_host_rm_ops *kvmppc_host_rm_ops_hv; 34379b6c247SSuresh Warrier EXPORT_SYMBOL_GPL(kvmppc_host_rm_ops_hv); 34437f55d30SSuresh Warrier 345e3c13e56SSuresh Warrier #ifdef CONFIG_KVM_XICS 346e3c13e56SSuresh Warrier static struct kvmppc_irq_map *get_irqmap(struct kvmppc_passthru_irqmap *pimap, 347e3c13e56SSuresh Warrier u32 xisr) 348e3c13e56SSuresh Warrier { 349e3c13e56SSuresh Warrier int i; 350e3c13e56SSuresh Warrier 351e3c13e56SSuresh Warrier /* 352e3c13e56SSuresh Warrier * We access the mapped array here without a lock. That 353e3c13e56SSuresh Warrier * is safe because we never reduce the number of entries 354e3c13e56SSuresh Warrier * in the array and we never change the v_hwirq field of 355e3c13e56SSuresh Warrier * an entry once it is set. 356e3c13e56SSuresh Warrier * 357e3c13e56SSuresh Warrier * We have also carefully ordered the stores in the writer 358e3c13e56SSuresh Warrier * and the loads here in the reader, so that if we find a matching 359e3c13e56SSuresh Warrier * hwirq here, the associated GSI and irq_desc fields are valid. 360e3c13e56SSuresh Warrier */ 361e3c13e56SSuresh Warrier for (i = 0; i < pimap->n_mapped; i++) { 362e3c13e56SSuresh Warrier if (xisr == pimap->mapped[i].r_hwirq) { 363e3c13e56SSuresh Warrier /* 364e3c13e56SSuresh Warrier * Order subsequent reads in the caller to serialize 365e3c13e56SSuresh Warrier * with the writer. 366e3c13e56SSuresh Warrier */ 367e3c13e56SSuresh Warrier smp_rmb(); 368e3c13e56SSuresh Warrier return &pimap->mapped[i]; 369e3c13e56SSuresh Warrier } 370e3c13e56SSuresh Warrier } 371e3c13e56SSuresh Warrier return NULL; 372e3c13e56SSuresh Warrier } 373e3c13e56SSuresh Warrier 374e3c13e56SSuresh Warrier /* 375e3c13e56SSuresh Warrier * If we have an interrupt that's not an IPI, check if we have a 376e3c13e56SSuresh Warrier * passthrough adapter and if so, check if this external interrupt 377e3c13e56SSuresh Warrier * is for the adapter. 378e3c13e56SSuresh Warrier * We will attempt to deliver the IRQ directly to the target VCPU's 379e3c13e56SSuresh Warrier * ICP, the virtual ICP (based on affinity - the xive value in ICS). 380e3c13e56SSuresh Warrier * 381e3c13e56SSuresh Warrier * If the delivery fails or if this is not for a passthrough adapter, 382e3c13e56SSuresh Warrier * return to the host to handle this interrupt. We earlier 383e3c13e56SSuresh Warrier * saved a copy of the XIRR in the PACA, it will be picked up by 384e3c13e56SSuresh Warrier * the host ICP driver. 385e3c13e56SSuresh Warrier */ 386f725758bSPaul Mackerras static int kvmppc_check_passthru(u32 xisr, __be32 xirr, bool *again) 387e3c13e56SSuresh Warrier { 388e3c13e56SSuresh Warrier struct kvmppc_passthru_irqmap *pimap; 389e3c13e56SSuresh Warrier struct kvmppc_irq_map *irq_map; 390e3c13e56SSuresh Warrier struct kvm_vcpu *vcpu; 391e3c13e56SSuresh Warrier 392e3c13e56SSuresh Warrier vcpu = local_paca->kvm_hstate.kvm_vcpu; 393e3c13e56SSuresh Warrier if (!vcpu) 394e3c13e56SSuresh Warrier return 1; 395e3c13e56SSuresh Warrier pimap = kvmppc_get_passthru_irqmap(vcpu->kvm); 396e3c13e56SSuresh Warrier if (!pimap) 397e3c13e56SSuresh Warrier return 1; 398e3c13e56SSuresh Warrier irq_map = get_irqmap(pimap, xisr); 399e3c13e56SSuresh Warrier if (!irq_map) 400e3c13e56SSuresh Warrier return 1; 401e3c13e56SSuresh Warrier 402e3c13e56SSuresh Warrier /* We're handling this interrupt, generic code doesn't need to */ 403e3c13e56SSuresh Warrier local_paca->kvm_hstate.saved_xirr = 0; 404e3c13e56SSuresh Warrier 405f725758bSPaul Mackerras return kvmppc_deliver_irq_passthru(vcpu, xirr, irq_map, pimap, again); 406e3c13e56SSuresh Warrier } 407e3c13e56SSuresh Warrier 408e3c13e56SSuresh Warrier #else 409e2702871SPaul Mackerras static inline int kvmppc_check_passthru(u32 xisr, __be32 xirr, bool *again) 410e3c13e56SSuresh Warrier { 411e3c13e56SSuresh Warrier return 1; 412e3c13e56SSuresh Warrier } 413e3c13e56SSuresh Warrier #endif 414e3c13e56SSuresh Warrier 41537f55d30SSuresh Warrier /* 41637f55d30SSuresh Warrier * Determine what sort of external interrupt is pending (if any). 41737f55d30SSuresh Warrier * Returns: 41837f55d30SSuresh Warrier * 0 if no interrupt is pending 41937f55d30SSuresh Warrier * 1 if an interrupt is pending that needs to be handled by the host 420f7af5209SSuresh Warrier * 2 Passthrough that needs completion in the host 42137f55d30SSuresh Warrier * -1 if there was a guest wakeup IPI (which has now been cleared) 422e3c13e56SSuresh Warrier * -2 if there is PCI passthrough external interrupt that was handled 42337f55d30SSuresh Warrier */ 424f725758bSPaul Mackerras static long kvmppc_read_one_intr(bool *again); 42537f55d30SSuresh Warrier 42637f55d30SSuresh Warrier long kvmppc_read_intr(void) 42737f55d30SSuresh Warrier { 428f725758bSPaul Mackerras long ret = 0; 429f725758bSPaul Mackerras long rc; 430f725758bSPaul Mackerras bool again; 431f725758bSPaul Mackerras 432243e2511SBenjamin Herrenschmidt if (xive_enabled()) 433243e2511SBenjamin Herrenschmidt return 1; 434243e2511SBenjamin Herrenschmidt 435f725758bSPaul Mackerras do { 436f725758bSPaul Mackerras again = false; 437f725758bSPaul Mackerras rc = kvmppc_read_one_intr(&again); 438f725758bSPaul Mackerras if (rc && (ret == 0 || rc > ret)) 439f725758bSPaul Mackerras ret = rc; 440f725758bSPaul Mackerras } while (again); 441f725758bSPaul Mackerras return ret; 442f725758bSPaul Mackerras } 443f725758bSPaul Mackerras 444f725758bSPaul Mackerras static long kvmppc_read_one_intr(bool *again) 445f725758bSPaul Mackerras { 446d381d7caSBenjamin Herrenschmidt void __iomem *xics_phys; 44737f55d30SSuresh Warrier u32 h_xirr; 44837f55d30SSuresh Warrier __be32 xirr; 44937f55d30SSuresh Warrier u32 xisr; 45037f55d30SSuresh Warrier u8 host_ipi; 451f725758bSPaul Mackerras int64_t rc; 45237f55d30SSuresh Warrier 4535af50993SBenjamin Herrenschmidt if (xive_enabled()) 4545af50993SBenjamin Herrenschmidt return 1; 4555af50993SBenjamin Herrenschmidt 45637f55d30SSuresh Warrier /* see if a host IPI is pending */ 45737f55d30SSuresh Warrier host_ipi = local_paca->kvm_hstate.host_ipi; 45837f55d30SSuresh Warrier if (host_ipi) 45937f55d30SSuresh Warrier return 1; 46037f55d30SSuresh Warrier 46137f55d30SSuresh Warrier /* Now read the interrupt from the ICP */ 462f3c18e93SPaul Mackerras if (kvmhv_on_pseries()) { 463f3c18e93SPaul Mackerras unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 464f3c18e93SPaul Mackerras 465f3c18e93SPaul Mackerras rc = plpar_hcall_raw(H_XIRR, retbuf, 0xFF); 466f3c18e93SPaul Mackerras xirr = cpu_to_be32(retbuf[0]); 467f3c18e93SPaul Mackerras } else { 46837f55d30SSuresh Warrier xics_phys = local_paca->kvm_hstate.xics_phys; 46953af3ba2SPaul Mackerras rc = 0; 470ab9bad0eSBenjamin Herrenschmidt if (!xics_phys) 47153af3ba2SPaul Mackerras rc = opal_int_get_xirr(&xirr, false); 47253af3ba2SPaul Mackerras else 473d381d7caSBenjamin Herrenschmidt xirr = __raw_rm_readl(xics_phys + XICS_XIRR); 474f3c18e93SPaul Mackerras } 475f725758bSPaul Mackerras if (rc < 0) 47637f55d30SSuresh Warrier return 1; 47737f55d30SSuresh Warrier 47837f55d30SSuresh Warrier /* 47937f55d30SSuresh Warrier * Save XIRR for later. Since we get control in reverse endian 48037f55d30SSuresh Warrier * on LE systems, save it byte reversed and fetch it back in 48137f55d30SSuresh Warrier * host endian. Note that xirr is the value read from the 48237f55d30SSuresh Warrier * XIRR register, while h_xirr is the host endian version. 48337f55d30SSuresh Warrier */ 48437f55d30SSuresh Warrier h_xirr = be32_to_cpu(xirr); 48537f55d30SSuresh Warrier local_paca->kvm_hstate.saved_xirr = h_xirr; 48637f55d30SSuresh Warrier xisr = h_xirr & 0xffffff; 48737f55d30SSuresh Warrier /* 48837f55d30SSuresh Warrier * Ensure that the store/load complete to guarantee all side 48937f55d30SSuresh Warrier * effects of loading from XIRR has completed 49037f55d30SSuresh Warrier */ 49137f55d30SSuresh Warrier smp_mb(); 49237f55d30SSuresh Warrier 49337f55d30SSuresh Warrier /* if nothing pending in the ICP */ 49437f55d30SSuresh Warrier if (!xisr) 49537f55d30SSuresh Warrier return 0; 49637f55d30SSuresh Warrier 49737f55d30SSuresh Warrier /* We found something in the ICP... 49837f55d30SSuresh Warrier * 49937f55d30SSuresh Warrier * If it is an IPI, clear the MFRR and EOI it. 50037f55d30SSuresh Warrier */ 50137f55d30SSuresh Warrier if (xisr == XICS_IPI) { 50253af3ba2SPaul Mackerras rc = 0; 503f3c18e93SPaul Mackerras if (kvmhv_on_pseries()) { 504f3c18e93SPaul Mackerras unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 505f3c18e93SPaul Mackerras 506f3c18e93SPaul Mackerras plpar_hcall_raw(H_IPI, retbuf, 507f3c18e93SPaul Mackerras hard_smp_processor_id(), 0xff); 508f3c18e93SPaul Mackerras plpar_hcall_raw(H_EOI, retbuf, h_xirr); 509f3c18e93SPaul Mackerras } else if (xics_phys) { 510d381d7caSBenjamin Herrenschmidt __raw_rm_writeb(0xff, xics_phys + XICS_MFRR); 511d381d7caSBenjamin Herrenschmidt __raw_rm_writel(xirr, xics_phys + XICS_XIRR); 512f725758bSPaul Mackerras } else { 513ab9bad0eSBenjamin Herrenschmidt opal_int_set_mfrr(hard_smp_processor_id(), 0xff); 514ab9bad0eSBenjamin Herrenschmidt rc = opal_int_eoi(h_xirr); 51553af3ba2SPaul Mackerras } 516f725758bSPaul Mackerras /* If rc > 0, there is another interrupt pending */ 517f725758bSPaul Mackerras *again = rc > 0; 518f725758bSPaul Mackerras 51937f55d30SSuresh Warrier /* 52037f55d30SSuresh Warrier * Need to ensure side effects of above stores 52137f55d30SSuresh Warrier * complete before proceeding. 52237f55d30SSuresh Warrier */ 52337f55d30SSuresh Warrier smp_mb(); 52437f55d30SSuresh Warrier 52537f55d30SSuresh Warrier /* 52637f55d30SSuresh Warrier * We need to re-check host IPI now in case it got set in the 52737f55d30SSuresh Warrier * meantime. If it's clear, we bounce the interrupt to the 52837f55d30SSuresh Warrier * guest 52937f55d30SSuresh Warrier */ 53037f55d30SSuresh Warrier host_ipi = local_paca->kvm_hstate.host_ipi; 53137f55d30SSuresh Warrier if (unlikely(host_ipi != 0)) { 53237f55d30SSuresh Warrier /* We raced with the host, 53337f55d30SSuresh Warrier * we need to resend that IPI, bummer 53437f55d30SSuresh Warrier */ 535f3c18e93SPaul Mackerras if (kvmhv_on_pseries()) { 536f3c18e93SPaul Mackerras unsigned long retbuf[PLPAR_HCALL_BUFSIZE]; 537f3c18e93SPaul Mackerras 538f3c18e93SPaul Mackerras plpar_hcall_raw(H_IPI, retbuf, 539f3c18e93SPaul Mackerras hard_smp_processor_id(), 540f3c18e93SPaul Mackerras IPI_PRIORITY); 541f3c18e93SPaul Mackerras } else if (xics_phys) 542d381d7caSBenjamin Herrenschmidt __raw_rm_writeb(IPI_PRIORITY, 543d381d7caSBenjamin Herrenschmidt xics_phys + XICS_MFRR); 544f725758bSPaul Mackerras else 545ab9bad0eSBenjamin Herrenschmidt opal_int_set_mfrr(hard_smp_processor_id(), 546f725758bSPaul Mackerras IPI_PRIORITY); 54737f55d30SSuresh Warrier /* Let side effects complete */ 54837f55d30SSuresh Warrier smp_mb(); 54937f55d30SSuresh Warrier return 1; 55037f55d30SSuresh Warrier } 55137f55d30SSuresh Warrier 55237f55d30SSuresh Warrier /* OK, it's an IPI for us */ 55337f55d30SSuresh Warrier local_paca->kvm_hstate.saved_xirr = 0; 55437f55d30SSuresh Warrier return -1; 55537f55d30SSuresh Warrier } 55637f55d30SSuresh Warrier 557f725758bSPaul Mackerras return kvmppc_check_passthru(xisr, xirr, again); 55837f55d30SSuresh Warrier } 5595af50993SBenjamin Herrenschmidt 5605af50993SBenjamin Herrenschmidt #ifdef CONFIG_KVM_XICS 5615af50993SBenjamin Herrenschmidt static inline bool is_rm(void) 5625af50993SBenjamin Herrenschmidt { 5635af50993SBenjamin Herrenschmidt return !(mfmsr() & MSR_DR); 5645af50993SBenjamin Herrenschmidt } 5655af50993SBenjamin Herrenschmidt 5665af50993SBenjamin Herrenschmidt unsigned long kvmppc_rm_h_xirr(struct kvm_vcpu *vcpu) 5675af50993SBenjamin Herrenschmidt { 56800bb6ae5SPaul Mackerras if (!kvmppc_xics_enabled(vcpu)) 56900bb6ae5SPaul Mackerras return H_TOO_HARD; 57003f95332SPaul Mackerras if (xics_on_xive()) { 5715af50993SBenjamin Herrenschmidt if (is_rm()) 5725af50993SBenjamin Herrenschmidt return xive_rm_h_xirr(vcpu); 5735af50993SBenjamin Herrenschmidt if (unlikely(!__xive_vm_h_xirr)) 5745af50993SBenjamin Herrenschmidt return H_NOT_AVAILABLE; 5755af50993SBenjamin Herrenschmidt return __xive_vm_h_xirr(vcpu); 5765af50993SBenjamin Herrenschmidt } else 5775af50993SBenjamin Herrenschmidt return xics_rm_h_xirr(vcpu); 5785af50993SBenjamin Herrenschmidt } 5795af50993SBenjamin Herrenschmidt 5805af50993SBenjamin Herrenschmidt unsigned long kvmppc_rm_h_xirr_x(struct kvm_vcpu *vcpu) 5815af50993SBenjamin Herrenschmidt { 58200bb6ae5SPaul Mackerras if (!kvmppc_xics_enabled(vcpu)) 58300bb6ae5SPaul Mackerras return H_TOO_HARD; 5841143a706SSimon Guo vcpu->arch.regs.gpr[5] = get_tb(); 58503f95332SPaul Mackerras if (xics_on_xive()) { 5865af50993SBenjamin Herrenschmidt if (is_rm()) 5875af50993SBenjamin Herrenschmidt return xive_rm_h_xirr(vcpu); 5885af50993SBenjamin Herrenschmidt if (unlikely(!__xive_vm_h_xirr)) 5895af50993SBenjamin Herrenschmidt return H_NOT_AVAILABLE; 5905af50993SBenjamin Herrenschmidt return __xive_vm_h_xirr(vcpu); 5915af50993SBenjamin Herrenschmidt } else 5925af50993SBenjamin Herrenschmidt return xics_rm_h_xirr(vcpu); 5935af50993SBenjamin Herrenschmidt } 5945af50993SBenjamin Herrenschmidt 5955af50993SBenjamin Herrenschmidt unsigned long kvmppc_rm_h_ipoll(struct kvm_vcpu *vcpu, unsigned long server) 5965af50993SBenjamin Herrenschmidt { 59700bb6ae5SPaul Mackerras if (!kvmppc_xics_enabled(vcpu)) 59800bb6ae5SPaul Mackerras return H_TOO_HARD; 59903f95332SPaul Mackerras if (xics_on_xive()) { 6005af50993SBenjamin Herrenschmidt if (is_rm()) 6015af50993SBenjamin Herrenschmidt return xive_rm_h_ipoll(vcpu, server); 6025af50993SBenjamin Herrenschmidt if (unlikely(!__xive_vm_h_ipoll)) 6035af50993SBenjamin Herrenschmidt return H_NOT_AVAILABLE; 6045af50993SBenjamin Herrenschmidt return __xive_vm_h_ipoll(vcpu, server); 6055af50993SBenjamin Herrenschmidt } else 6065af50993SBenjamin Herrenschmidt return H_TOO_HARD; 6075af50993SBenjamin Herrenschmidt } 6085af50993SBenjamin Herrenschmidt 6095af50993SBenjamin Herrenschmidt int kvmppc_rm_h_ipi(struct kvm_vcpu *vcpu, unsigned long server, 6105af50993SBenjamin Herrenschmidt unsigned long mfrr) 6115af50993SBenjamin Herrenschmidt { 61200bb6ae5SPaul Mackerras if (!kvmppc_xics_enabled(vcpu)) 61300bb6ae5SPaul Mackerras return H_TOO_HARD; 61403f95332SPaul Mackerras if (xics_on_xive()) { 6155af50993SBenjamin Herrenschmidt if (is_rm()) 6165af50993SBenjamin Herrenschmidt return xive_rm_h_ipi(vcpu, server, mfrr); 6175af50993SBenjamin Herrenschmidt if (unlikely(!__xive_vm_h_ipi)) 6185af50993SBenjamin Herrenschmidt return H_NOT_AVAILABLE; 6195af50993SBenjamin Herrenschmidt return __xive_vm_h_ipi(vcpu, server, mfrr); 6205af50993SBenjamin Herrenschmidt } else 6215af50993SBenjamin Herrenschmidt return xics_rm_h_ipi(vcpu, server, mfrr); 6225af50993SBenjamin Herrenschmidt } 6235af50993SBenjamin Herrenschmidt 6245af50993SBenjamin Herrenschmidt int kvmppc_rm_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr) 6255af50993SBenjamin Herrenschmidt { 62600bb6ae5SPaul Mackerras if (!kvmppc_xics_enabled(vcpu)) 62700bb6ae5SPaul Mackerras return H_TOO_HARD; 62803f95332SPaul Mackerras if (xics_on_xive()) { 6295af50993SBenjamin Herrenschmidt if (is_rm()) 6305af50993SBenjamin Herrenschmidt return xive_rm_h_cppr(vcpu, cppr); 6315af50993SBenjamin Herrenschmidt if (unlikely(!__xive_vm_h_cppr)) 6325af50993SBenjamin Herrenschmidt return H_NOT_AVAILABLE; 6335af50993SBenjamin Herrenschmidt return __xive_vm_h_cppr(vcpu, cppr); 6345af50993SBenjamin Herrenschmidt } else 6355af50993SBenjamin Herrenschmidt return xics_rm_h_cppr(vcpu, cppr); 6365af50993SBenjamin Herrenschmidt } 6375af50993SBenjamin Herrenschmidt 6385af50993SBenjamin Herrenschmidt int kvmppc_rm_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr) 6395af50993SBenjamin Herrenschmidt { 64000bb6ae5SPaul Mackerras if (!kvmppc_xics_enabled(vcpu)) 64100bb6ae5SPaul Mackerras return H_TOO_HARD; 64203f95332SPaul Mackerras if (xics_on_xive()) { 6435af50993SBenjamin Herrenschmidt if (is_rm()) 6445af50993SBenjamin Herrenschmidt return xive_rm_h_eoi(vcpu, xirr); 6455af50993SBenjamin Herrenschmidt if (unlikely(!__xive_vm_h_eoi)) 6465af50993SBenjamin Herrenschmidt return H_NOT_AVAILABLE; 6475af50993SBenjamin Herrenschmidt return __xive_vm_h_eoi(vcpu, xirr); 6485af50993SBenjamin Herrenschmidt } else 6495af50993SBenjamin Herrenschmidt return xics_rm_h_eoi(vcpu, xirr); 6505af50993SBenjamin Herrenschmidt } 6515af50993SBenjamin Herrenschmidt #endif /* CONFIG_KVM_XICS */ 652857b99e1SPaul Mackerras 653857b99e1SPaul Mackerras void kvmppc_bad_interrupt(struct pt_regs *regs) 654857b99e1SPaul Mackerras { 6557c1bd80cSNicholas Piggin /* 6567c1bd80cSNicholas Piggin * 100 could happen at any time, 200 can happen due to invalid real 6577c1bd80cSNicholas Piggin * address access for example (or any time due to a hardware problem). 6587c1bd80cSNicholas Piggin */ 6597c1bd80cSNicholas Piggin if (TRAP(regs) == 0x100) { 6607c1bd80cSNicholas Piggin get_paca()->in_nmi++; 6617c1bd80cSNicholas Piggin system_reset_exception(regs); 6627c1bd80cSNicholas Piggin get_paca()->in_nmi--; 6637c1bd80cSNicholas Piggin } else if (TRAP(regs) == 0x200) { 6647c1bd80cSNicholas Piggin machine_check_exception(regs); 6657c1bd80cSNicholas Piggin } else { 666857b99e1SPaul Mackerras die("Bad interrupt in KVM entry/exit code", regs, SIGABRT); 6677c1bd80cSNicholas Piggin } 668857b99e1SPaul Mackerras panic("Bad KVM trap"); 669857b99e1SPaul Mackerras } 670c0101509SPaul Mackerras 671c0101509SPaul Mackerras /* 672c0101509SPaul Mackerras * Functions used to switch LPCR HR and UPRT bits on all threads 673c0101509SPaul Mackerras * when entering and exiting HPT guests on a radix host. 674c0101509SPaul Mackerras */ 675c0101509SPaul Mackerras 676c0101509SPaul Mackerras #define PHASE_REALMODE 1 /* in real mode */ 677c0101509SPaul Mackerras #define PHASE_SET_LPCR 2 /* have set LPCR */ 678c0101509SPaul Mackerras #define PHASE_OUT_OF_GUEST 4 /* have finished executing in guest */ 679c0101509SPaul Mackerras #define PHASE_RESET_LPCR 8 /* have reset LPCR to host value */ 680c0101509SPaul Mackerras 681c0101509SPaul Mackerras #define ALL(p) (((p) << 24) | ((p) << 16) | ((p) << 8) | (p)) 682c0101509SPaul Mackerras 683c0101509SPaul Mackerras static void wait_for_sync(struct kvm_split_mode *sip, int phase) 684c0101509SPaul Mackerras { 685c0101509SPaul Mackerras int thr = local_paca->kvm_hstate.tid; 686c0101509SPaul Mackerras 687c0101509SPaul Mackerras sip->lpcr_sync.phase[thr] |= phase; 688c0101509SPaul Mackerras phase = ALL(phase); 689c0101509SPaul Mackerras while ((sip->lpcr_sync.allphases & phase) != phase) { 690c0101509SPaul Mackerras HMT_low(); 691c0101509SPaul Mackerras barrier(); 692c0101509SPaul Mackerras } 693c0101509SPaul Mackerras HMT_medium(); 694c0101509SPaul Mackerras } 695c0101509SPaul Mackerras 696c0101509SPaul Mackerras void kvmhv_p9_set_lpcr(struct kvm_split_mode *sip) 697c0101509SPaul Mackerras { 698e8063940SAneesh Kumar K.V int num_sets; 699c0101509SPaul Mackerras unsigned long rb, set; 700c0101509SPaul Mackerras 701c0101509SPaul Mackerras /* wait for every other thread to get to real mode */ 702c0101509SPaul Mackerras wait_for_sync(sip, PHASE_REALMODE); 703c0101509SPaul Mackerras 704c0101509SPaul Mackerras /* Set LPCR and LPIDR */ 705c0101509SPaul Mackerras mtspr(SPRN_LPCR, sip->lpcr_req); 706c0101509SPaul Mackerras mtspr(SPRN_LPID, sip->lpidr_req); 707c0101509SPaul Mackerras isync(); 708c0101509SPaul Mackerras 709e8063940SAneesh Kumar K.V /* 710e8063940SAneesh Kumar K.V * P10 will flush all the congruence class with a single tlbiel 711e8063940SAneesh Kumar K.V */ 712e8063940SAneesh Kumar K.V if (cpu_has_feature(CPU_FTR_ARCH_31)) 713e8063940SAneesh Kumar K.V num_sets = 1; 714e8063940SAneesh Kumar K.V else 715e8063940SAneesh Kumar K.V num_sets = POWER9_TLB_SETS_RADIX; 716e8063940SAneesh Kumar K.V 717c0101509SPaul Mackerras /* Invalidate the TLB on thread 0 */ 718c0101509SPaul Mackerras if (local_paca->kvm_hstate.tid == 0) { 719c0101509SPaul Mackerras sip->do_set = 0; 720c0101509SPaul Mackerras asm volatile("ptesync" : : : "memory"); 721e8063940SAneesh Kumar K.V for (set = 0; set < num_sets; ++set) { 722c0101509SPaul Mackerras rb = TLBIEL_INVAL_SET_LPID + 723c0101509SPaul Mackerras (set << TLBIEL_INVAL_SET_SHIFT); 724c0101509SPaul Mackerras asm volatile(PPC_TLBIEL(%0, %1, 0, 0, 0) : : 725c0101509SPaul Mackerras "r" (rb), "r" (0)); 726c0101509SPaul Mackerras } 727c0101509SPaul Mackerras asm volatile("ptesync" : : : "memory"); 728c0101509SPaul Mackerras } 729c0101509SPaul Mackerras 730c0101509SPaul Mackerras /* indicate that we have done so and wait for others */ 731c0101509SPaul Mackerras wait_for_sync(sip, PHASE_SET_LPCR); 732c0101509SPaul Mackerras /* order read of sip->lpcr_sync.allphases vs. sip->do_set */ 733c0101509SPaul Mackerras smp_rmb(); 734c0101509SPaul Mackerras } 735c0101509SPaul Mackerras 736c0101509SPaul Mackerras /* 737c0101509SPaul Mackerras * Called when a thread that has been in the guest needs 738c0101509SPaul Mackerras * to reload the host LPCR value - but only on POWER9 when 739c0101509SPaul Mackerras * running a HPT guest on a radix host. 740c0101509SPaul Mackerras */ 741c0101509SPaul Mackerras void kvmhv_p9_restore_lpcr(struct kvm_split_mode *sip) 742c0101509SPaul Mackerras { 743c0101509SPaul Mackerras /* we're out of the guest... */ 744c0101509SPaul Mackerras wait_for_sync(sip, PHASE_OUT_OF_GUEST); 745c0101509SPaul Mackerras 746c0101509SPaul Mackerras mtspr(SPRN_LPID, 0); 747c0101509SPaul Mackerras mtspr(SPRN_LPCR, sip->host_lpcr); 748c0101509SPaul Mackerras isync(); 749c0101509SPaul Mackerras 750c0101509SPaul Mackerras if (local_paca->kvm_hstate.tid == 0) { 751c0101509SPaul Mackerras sip->do_restore = 0; 752c0101509SPaul Mackerras smp_wmb(); /* order store of do_restore vs. phase */ 753c0101509SPaul Mackerras } 754c0101509SPaul Mackerras 755c0101509SPaul Mackerras wait_for_sync(sip, PHASE_RESET_LPCR); 756c0101509SPaul Mackerras smp_mb(); 757c0101509SPaul Mackerras local_paca->kvm_hstate.kvm_split_mode = NULL; 758c0101509SPaul Mackerras } 759f7035ce9SPaul Mackerras 760268f4ef9SNicholas Piggin static void kvmppc_end_cede(struct kvm_vcpu *vcpu) 761268f4ef9SNicholas Piggin { 762268f4ef9SNicholas Piggin vcpu->arch.ceded = 0; 763268f4ef9SNicholas Piggin if (vcpu->arch.timer_running) { 764268f4ef9SNicholas Piggin hrtimer_try_to_cancel(&vcpu->arch.dec_timer); 765268f4ef9SNicholas Piggin vcpu->arch.timer_running = 0; 766268f4ef9SNicholas Piggin } 767268f4ef9SNicholas Piggin } 768268f4ef9SNicholas Piggin 769268f4ef9SNicholas Piggin void kvmppc_set_msr_hv(struct kvm_vcpu *vcpu, u64 msr) 770268f4ef9SNicholas Piggin { 771268f4ef9SNicholas Piggin /* 772268f4ef9SNicholas Piggin * Check for illegal transactional state bit combination 773268f4ef9SNicholas Piggin * and if we find it, force the TS field to a safe state. 774268f4ef9SNicholas Piggin */ 775268f4ef9SNicholas Piggin if ((msr & MSR_TS_MASK) == MSR_TS_MASK) 776268f4ef9SNicholas Piggin msr &= ~MSR_TS_MASK; 777268f4ef9SNicholas Piggin vcpu->arch.shregs.msr = msr; 778268f4ef9SNicholas Piggin kvmppc_end_cede(vcpu); 779268f4ef9SNicholas Piggin } 780268f4ef9SNicholas Piggin EXPORT_SYMBOL_GPL(kvmppc_set_msr_hv); 781268f4ef9SNicholas Piggin 782268f4ef9SNicholas Piggin static void inject_interrupt(struct kvm_vcpu *vcpu, int vec, u64 srr1_flags) 783268f4ef9SNicholas Piggin { 784268f4ef9SNicholas Piggin unsigned long msr, pc, new_msr, new_pc; 785268f4ef9SNicholas Piggin 786268f4ef9SNicholas Piggin msr = kvmppc_get_msr(vcpu); 787268f4ef9SNicholas Piggin pc = kvmppc_get_pc(vcpu); 788268f4ef9SNicholas Piggin new_msr = vcpu->arch.intr_msr; 789268f4ef9SNicholas Piggin new_pc = vec; 790268f4ef9SNicholas Piggin 791268f4ef9SNicholas Piggin /* If transactional, change to suspend mode on IRQ delivery */ 792268f4ef9SNicholas Piggin if (MSR_TM_TRANSACTIONAL(msr)) 793268f4ef9SNicholas Piggin new_msr |= MSR_TS_S; 794268f4ef9SNicholas Piggin else 795268f4ef9SNicholas Piggin new_msr |= msr & MSR_TS_MASK; 796268f4ef9SNicholas Piggin 7976a13cb0cSNicholas Piggin /* 7986a13cb0cSNicholas Piggin * Perform MSR and PC adjustment for LPCR[AIL]=3 if it is set and 7996a13cb0cSNicholas Piggin * applicable. AIL=2 is not supported. 8006a13cb0cSNicholas Piggin * 8016a13cb0cSNicholas Piggin * AIL does not apply to SRESET, MCE, or HMI (which is never 8026a13cb0cSNicholas Piggin * delivered to the guest), and does not apply if IR=0 or DR=0. 8036a13cb0cSNicholas Piggin */ 8046a13cb0cSNicholas Piggin if (vec != BOOK3S_INTERRUPT_SYSTEM_RESET && 8056a13cb0cSNicholas Piggin vec != BOOK3S_INTERRUPT_MACHINE_CHECK && 8066a13cb0cSNicholas Piggin (vcpu->arch.vcore->lpcr & LPCR_AIL) == LPCR_AIL_3 && 8076a13cb0cSNicholas Piggin (msr & (MSR_IR|MSR_DR)) == (MSR_IR|MSR_DR) ) { 8086a13cb0cSNicholas Piggin new_msr |= MSR_IR | MSR_DR; 8096a13cb0cSNicholas Piggin new_pc += 0xC000000000004000ULL; 8106a13cb0cSNicholas Piggin } 8116a13cb0cSNicholas Piggin 812268f4ef9SNicholas Piggin kvmppc_set_srr0(vcpu, pc); 813268f4ef9SNicholas Piggin kvmppc_set_srr1(vcpu, (msr & SRR1_MSR_BITS) | srr1_flags); 814268f4ef9SNicholas Piggin kvmppc_set_pc(vcpu, new_pc); 815268f4ef9SNicholas Piggin vcpu->arch.shregs.msr = new_msr; 816268f4ef9SNicholas Piggin } 817268f4ef9SNicholas Piggin 818268f4ef9SNicholas Piggin void kvmppc_inject_interrupt_hv(struct kvm_vcpu *vcpu, int vec, u64 srr1_flags) 819268f4ef9SNicholas Piggin { 820268f4ef9SNicholas Piggin inject_interrupt(vcpu, vec, srr1_flags); 821268f4ef9SNicholas Piggin kvmppc_end_cede(vcpu); 822268f4ef9SNicholas Piggin } 823268f4ef9SNicholas Piggin EXPORT_SYMBOL_GPL(kvmppc_inject_interrupt_hv); 824268f4ef9SNicholas Piggin 825f7035ce9SPaul Mackerras /* 826f7035ce9SPaul Mackerras * Is there a PRIV_DOORBELL pending for the guest (on POWER9)? 827f7035ce9SPaul Mackerras * Can we inject a Decrementer or a External interrupt? 828f7035ce9SPaul Mackerras */ 829f7035ce9SPaul Mackerras void kvmppc_guest_entry_inject_int(struct kvm_vcpu *vcpu) 830f7035ce9SPaul Mackerras { 831f7035ce9SPaul Mackerras int ext; 832f7035ce9SPaul Mackerras unsigned long lpcr; 833f7035ce9SPaul Mackerras 834f7035ce9SPaul Mackerras /* Insert EXTERNAL bit into LPCR at the MER bit position */ 835f7035ce9SPaul Mackerras ext = (vcpu->arch.pending_exceptions >> BOOK3S_IRQPRIO_EXTERNAL) & 1; 836f7035ce9SPaul Mackerras lpcr = mfspr(SPRN_LPCR); 837f7035ce9SPaul Mackerras lpcr |= ext << LPCR_MER_SH; 838f7035ce9SPaul Mackerras mtspr(SPRN_LPCR, lpcr); 839f7035ce9SPaul Mackerras isync(); 840f7035ce9SPaul Mackerras 841f7035ce9SPaul Mackerras if (vcpu->arch.shregs.msr & MSR_EE) { 842f7035ce9SPaul Mackerras if (ext) { 843268f4ef9SNicholas Piggin inject_interrupt(vcpu, BOOK3S_INTERRUPT_EXTERNAL, 0); 844f7035ce9SPaul Mackerras } else { 845f7035ce9SPaul Mackerras long int dec = mfspr(SPRN_DEC); 846f7035ce9SPaul Mackerras if (!(lpcr & LPCR_LD)) 847f7035ce9SPaul Mackerras dec = (int) dec; 848f7035ce9SPaul Mackerras if (dec < 0) 849268f4ef9SNicholas Piggin inject_interrupt(vcpu, 850268f4ef9SNicholas Piggin BOOK3S_INTERRUPT_DECREMENTER, 0); 851f7035ce9SPaul Mackerras } 852f7035ce9SPaul Mackerras } 853f7035ce9SPaul Mackerras 854f7035ce9SPaul Mackerras if (vcpu->arch.doorbell_request) { 855f7035ce9SPaul Mackerras mtspr(SPRN_DPDES, 1); 856f7035ce9SPaul Mackerras vcpu->arch.vcore->dpdes = 1; 857f7035ce9SPaul Mackerras smp_wmb(); 858f7035ce9SPaul Mackerras vcpu->arch.doorbell_request = 0; 859f7035ce9SPaul Mackerras } 860f7035ce9SPaul Mackerras } 8612940ba0cSPaul Mackerras 86270ea13f6SPaul Mackerras static void flush_guest_tlb(struct kvm *kvm) 8632940ba0cSPaul Mackerras { 8642940ba0cSPaul Mackerras unsigned long rb, set; 8652940ba0cSPaul Mackerras 86670ea13f6SPaul Mackerras rb = PPC_BIT(52); /* IS = 2 */ 86770ea13f6SPaul Mackerras if (kvm_is_radix(kvm)) { 86870ea13f6SPaul Mackerras /* R=1 PRS=1 RIC=2 */ 86970ea13f6SPaul Mackerras asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1) 87070ea13f6SPaul Mackerras : : "r" (rb), "i" (1), "i" (1), "i" (2), 87170ea13f6SPaul Mackerras "r" (0) : "memory"); 87270ea13f6SPaul Mackerras for (set = 1; set < kvm->arch.tlb_sets; ++set) { 87370ea13f6SPaul Mackerras rb += PPC_BIT(51); /* increment set number */ 87470ea13f6SPaul Mackerras /* R=1 PRS=1 RIC=0 */ 87570ea13f6SPaul Mackerras asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1) 87670ea13f6SPaul Mackerras : : "r" (rb), "i" (1), "i" (1), "i" (0), 87770ea13f6SPaul Mackerras "r" (0) : "memory"); 87870ea13f6SPaul Mackerras } 8796c46fcceSNicholas Piggin asm volatile("ptesync": : :"memory"); 8806c46fcceSNicholas Piggin asm volatile(PPC_RADIX_INVALIDATE_ERAT_GUEST : : :"memory"); 88170ea13f6SPaul Mackerras } else { 88270ea13f6SPaul Mackerras for (set = 0; set < kvm->arch.tlb_sets; ++set) { 88370ea13f6SPaul Mackerras /* R=0 PRS=0 RIC=0 */ 88470ea13f6SPaul Mackerras asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1) 88570ea13f6SPaul Mackerras : : "r" (rb), "i" (0), "i" (0), "i" (0), 88670ea13f6SPaul Mackerras "r" (0) : "memory"); 88770ea13f6SPaul Mackerras rb += PPC_BIT(51); /* increment set number */ 88870ea13f6SPaul Mackerras } 88970ea13f6SPaul Mackerras asm volatile("ptesync": : :"memory"); 890fe7946ceSNicholas Piggin asm volatile(PPC_ISA_3_0_INVALIDATE_ERAT : : :"memory"); 89170ea13f6SPaul Mackerras } 89270ea13f6SPaul Mackerras } 89370ea13f6SPaul Mackerras 89470ea13f6SPaul Mackerras void kvmppc_check_need_tlb_flush(struct kvm *kvm, int pcpu, 89570ea13f6SPaul Mackerras struct kvm_nested_guest *nested) 89670ea13f6SPaul Mackerras { 89770ea13f6SPaul Mackerras cpumask_t *need_tlb_flush; 89870ea13f6SPaul Mackerras 8992940ba0cSPaul Mackerras /* 9002940ba0cSPaul Mackerras * On POWER9, individual threads can come in here, but the 9012940ba0cSPaul Mackerras * TLB is shared between the 4 threads in a core, hence 9022940ba0cSPaul Mackerras * invalidating on one thread invalidates for all. 9032940ba0cSPaul Mackerras * Thus we make all 4 threads use the same bit. 9042940ba0cSPaul Mackerras */ 9052940ba0cSPaul Mackerras if (cpu_has_feature(CPU_FTR_ARCH_300)) 9062940ba0cSPaul Mackerras pcpu = cpu_first_thread_sibling(pcpu); 9072940ba0cSPaul Mackerras 90870ea13f6SPaul Mackerras if (nested) 90970ea13f6SPaul Mackerras need_tlb_flush = &nested->need_tlb_flush; 91070ea13f6SPaul Mackerras else 91170ea13f6SPaul Mackerras need_tlb_flush = &kvm->arch.need_tlb_flush; 91270ea13f6SPaul Mackerras 91370ea13f6SPaul Mackerras if (cpumask_test_cpu(pcpu, need_tlb_flush)) { 91470ea13f6SPaul Mackerras flush_guest_tlb(kvm); 9152940ba0cSPaul Mackerras 9162940ba0cSPaul Mackerras /* Clear the bit after the TLB flush */ 91770ea13f6SPaul Mackerras cpumask_clear_cpu(pcpu, need_tlb_flush); 9182940ba0cSPaul Mackerras } 9192940ba0cSPaul Mackerras } 92070ea13f6SPaul Mackerras EXPORT_SYMBOL_GPL(kvmppc_check_need_tlb_flush); 921