1 /* 2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 * 9 * Modified by Cort Dougan (cort@cs.nmt.edu) 10 * and Paul Mackerras (paulus@samba.org) 11 */ 12 13 /* 14 * This file handles the architecture-dependent parts of hardware exceptions 15 */ 16 17 #include <linux/errno.h> 18 #include <linux/sched.h> 19 #include <linux/kernel.h> 20 #include <linux/mm.h> 21 #include <linux/stddef.h> 22 #include <linux/unistd.h> 23 #include <linux/ptrace.h> 24 #include <linux/slab.h> 25 #include <linux/user.h> 26 #include <linux/interrupt.h> 27 #include <linux/init.h> 28 #include <linux/module.h> 29 #include <linux/prctl.h> 30 #include <linux/delay.h> 31 #include <linux/kprobes.h> 32 #include <linux/kexec.h> 33 #include <linux/backlight.h> 34 #include <linux/bug.h> 35 #include <linux/kdebug.h> 36 #include <linux/debugfs.h> 37 38 #include <asm/emulated_ops.h> 39 #include <asm/pgtable.h> 40 #include <asm/uaccess.h> 41 #include <asm/system.h> 42 #include <asm/io.h> 43 #include <asm/machdep.h> 44 #include <asm/rtas.h> 45 #include <asm/pmc.h> 46 #ifdef CONFIG_PPC32 47 #include <asm/reg.h> 48 #endif 49 #ifdef CONFIG_PMAC_BACKLIGHT 50 #include <asm/backlight.h> 51 #endif 52 #ifdef CONFIG_PPC64 53 #include <asm/firmware.h> 54 #include <asm/processor.h> 55 #endif 56 #include <asm/kexec.h> 57 #include <asm/ppc-opcode.h> 58 #ifdef CONFIG_FSL_BOOKE 59 #include <asm/dbell.h> 60 #endif 61 62 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) 63 int (*__debugger)(struct pt_regs *regs); 64 int (*__debugger_ipi)(struct pt_regs *regs); 65 int (*__debugger_bpt)(struct pt_regs *regs); 66 int (*__debugger_sstep)(struct pt_regs *regs); 67 int (*__debugger_iabr_match)(struct pt_regs *regs); 68 int (*__debugger_dabr_match)(struct pt_regs *regs); 69 int (*__debugger_fault_handler)(struct pt_regs *regs); 70 71 EXPORT_SYMBOL(__debugger); 72 EXPORT_SYMBOL(__debugger_ipi); 73 EXPORT_SYMBOL(__debugger_bpt); 74 EXPORT_SYMBOL(__debugger_sstep); 75 EXPORT_SYMBOL(__debugger_iabr_match); 76 EXPORT_SYMBOL(__debugger_dabr_match); 77 EXPORT_SYMBOL(__debugger_fault_handler); 78 #endif 79 80 /* 81 * Trap & Exception support 82 */ 83 84 #ifdef CONFIG_PMAC_BACKLIGHT 85 static void pmac_backlight_unblank(void) 86 { 87 mutex_lock(&pmac_backlight_mutex); 88 if (pmac_backlight) { 89 struct backlight_properties *props; 90 91 props = &pmac_backlight->props; 92 props->brightness = props->max_brightness; 93 props->power = FB_BLANK_UNBLANK; 94 backlight_update_status(pmac_backlight); 95 } 96 mutex_unlock(&pmac_backlight_mutex); 97 } 98 #else 99 static inline void pmac_backlight_unblank(void) { } 100 #endif 101 102 int die(const char *str, struct pt_regs *regs, long err) 103 { 104 static struct { 105 spinlock_t lock; 106 u32 lock_owner; 107 int lock_owner_depth; 108 } die = { 109 .lock = __SPIN_LOCK_UNLOCKED(die.lock), 110 .lock_owner = -1, 111 .lock_owner_depth = 0 112 }; 113 static int die_counter; 114 unsigned long flags; 115 116 if (debugger(regs)) 117 return 1; 118 119 oops_enter(); 120 121 if (die.lock_owner != raw_smp_processor_id()) { 122 console_verbose(); 123 spin_lock_irqsave(&die.lock, flags); 124 die.lock_owner = smp_processor_id(); 125 die.lock_owner_depth = 0; 126 bust_spinlocks(1); 127 if (machine_is(powermac)) 128 pmac_backlight_unblank(); 129 } else { 130 local_save_flags(flags); 131 } 132 133 if (++die.lock_owner_depth < 3) { 134 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); 135 #ifdef CONFIG_PREEMPT 136 printk("PREEMPT "); 137 #endif 138 #ifdef CONFIG_SMP 139 printk("SMP NR_CPUS=%d ", NR_CPUS); 140 #endif 141 #ifdef CONFIG_DEBUG_PAGEALLOC 142 printk("DEBUG_PAGEALLOC "); 143 #endif 144 #ifdef CONFIG_NUMA 145 printk("NUMA "); 146 #endif 147 printk("%s\n", ppc_md.name ? ppc_md.name : ""); 148 149 print_modules(); 150 show_regs(regs); 151 } else { 152 printk("Recursive die() failure, output suppressed\n"); 153 } 154 155 bust_spinlocks(0); 156 die.lock_owner = -1; 157 add_taint(TAINT_DIE); 158 spin_unlock_irqrestore(&die.lock, flags); 159 160 if (kexec_should_crash(current) || 161 kexec_sr_activated(smp_processor_id())) 162 crash_kexec(regs); 163 crash_kexec_secondary(regs); 164 165 if (in_interrupt()) 166 panic("Fatal exception in interrupt"); 167 168 if (panic_on_oops) 169 panic("Fatal exception"); 170 171 oops_exit(); 172 do_exit(err); 173 174 return 0; 175 } 176 177 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) 178 { 179 siginfo_t info; 180 const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \ 181 "at %08lx nip %08lx lr %08lx code %x\n"; 182 const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \ 183 "at %016lx nip %016lx lr %016lx code %x\n"; 184 185 if (!user_mode(regs)) { 186 if (die("Exception in kernel mode", regs, signr)) 187 return; 188 } else if (show_unhandled_signals && 189 unhandled_signal(current, signr) && 190 printk_ratelimit()) { 191 printk(regs->msr & MSR_SF ? fmt64 : fmt32, 192 current->comm, current->pid, signr, 193 addr, regs->nip, regs->link, code); 194 } 195 196 memset(&info, 0, sizeof(info)); 197 info.si_signo = signr; 198 info.si_code = code; 199 info.si_addr = (void __user *) addr; 200 force_sig_info(signr, &info, current); 201 202 /* 203 * Init gets no signals that it doesn't have a handler for. 204 * That's all very well, but if it has caused a synchronous 205 * exception and we ignore the resulting signal, it will just 206 * generate the same exception over and over again and we get 207 * nowhere. Better to kill it and let the kernel panic. 208 */ 209 if (is_global_init(current)) { 210 __sighandler_t handler; 211 212 spin_lock_irq(¤t->sighand->siglock); 213 handler = current->sighand->action[signr-1].sa.sa_handler; 214 spin_unlock_irq(¤t->sighand->siglock); 215 if (handler == SIG_DFL) { 216 /* init has generated a synchronous exception 217 and it doesn't have a handler for the signal */ 218 printk(KERN_CRIT "init has generated signal %d " 219 "but has no handler for it\n", signr); 220 do_exit(signr); 221 } 222 } 223 } 224 225 #ifdef CONFIG_PPC64 226 void system_reset_exception(struct pt_regs *regs) 227 { 228 /* See if any machine dependent calls */ 229 if (ppc_md.system_reset_exception) { 230 if (ppc_md.system_reset_exception(regs)) 231 return; 232 } 233 234 #ifdef CONFIG_KEXEC 235 cpu_set(smp_processor_id(), cpus_in_sr); 236 #endif 237 238 die("System Reset", regs, SIGABRT); 239 240 /* 241 * Some CPUs when released from the debugger will execute this path. 242 * These CPUs entered the debugger via a soft-reset. If the CPU was 243 * hung before entering the debugger it will return to the hung 244 * state when exiting this function. This causes a problem in 245 * kdump since the hung CPU(s) will not respond to the IPI sent 246 * from kdump. To prevent the problem we call crash_kexec_secondary() 247 * here. If a kdump had not been initiated or we exit the debugger 248 * with the "exit and recover" command (x) crash_kexec_secondary() 249 * will return after 5ms and the CPU returns to its previous state. 250 */ 251 crash_kexec_secondary(regs); 252 253 /* Must die if the interrupt is not recoverable */ 254 if (!(regs->msr & MSR_RI)) 255 panic("Unrecoverable System Reset"); 256 257 /* What should we do here? We could issue a shutdown or hard reset. */ 258 } 259 #endif 260 261 /* 262 * I/O accesses can cause machine checks on powermacs. 263 * Check if the NIP corresponds to the address of a sync 264 * instruction for which there is an entry in the exception 265 * table. 266 * Note that the 601 only takes a machine check on TEA 267 * (transfer error ack) signal assertion, and does not 268 * set any of the top 16 bits of SRR1. 269 * -- paulus. 270 */ 271 static inline int check_io_access(struct pt_regs *regs) 272 { 273 #ifdef CONFIG_PPC32 274 unsigned long msr = regs->msr; 275 const struct exception_table_entry *entry; 276 unsigned int *nip = (unsigned int *)regs->nip; 277 278 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) 279 && (entry = search_exception_tables(regs->nip)) != NULL) { 280 /* 281 * Check that it's a sync instruction, or somewhere 282 * in the twi; isync; nop sequence that inb/inw/inl uses. 283 * As the address is in the exception table 284 * we should be able to read the instr there. 285 * For the debug message, we look at the preceding 286 * load or store. 287 */ 288 if (*nip == 0x60000000) /* nop */ 289 nip -= 2; 290 else if (*nip == 0x4c00012c) /* isync */ 291 --nip; 292 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) { 293 /* sync or twi */ 294 unsigned int rb; 295 296 --nip; 297 rb = (*nip >> 11) & 0x1f; 298 printk(KERN_DEBUG "%s bad port %lx at %p\n", 299 (*nip & 0x100)? "OUT to": "IN from", 300 regs->gpr[rb] - _IO_BASE, nip); 301 regs->msr |= MSR_RI; 302 regs->nip = entry->fixup; 303 return 1; 304 } 305 } 306 #endif /* CONFIG_PPC32 */ 307 return 0; 308 } 309 310 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 311 /* On 4xx, the reason for the machine check or program exception 312 is in the ESR. */ 313 #define get_reason(regs) ((regs)->dsisr) 314 #ifndef CONFIG_FSL_BOOKE 315 #define get_mc_reason(regs) ((regs)->dsisr) 316 #else 317 #define get_mc_reason(regs) (mfspr(SPRN_MCSR) & MCSR_MASK) 318 #endif 319 #define REASON_FP ESR_FP 320 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) 321 #define REASON_PRIVILEGED ESR_PPR 322 #define REASON_TRAP ESR_PTR 323 324 /* single-step stuff */ 325 #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) 326 #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) 327 328 #else 329 /* On non-4xx, the reason for the machine check or program 330 exception is in the MSR. */ 331 #define get_reason(regs) ((regs)->msr) 332 #define get_mc_reason(regs) ((regs)->msr) 333 #define REASON_FP 0x100000 334 #define REASON_ILLEGAL 0x80000 335 #define REASON_PRIVILEGED 0x40000 336 #define REASON_TRAP 0x20000 337 338 #define single_stepping(regs) ((regs)->msr & MSR_SE) 339 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) 340 #endif 341 342 #if defined(CONFIG_4xx) 343 int machine_check_4xx(struct pt_regs *regs) 344 { 345 unsigned long reason = get_mc_reason(regs); 346 347 if (reason & ESR_IMCP) { 348 printk("Instruction"); 349 mtspr(SPRN_ESR, reason & ~ESR_IMCP); 350 } else 351 printk("Data"); 352 printk(" machine check in kernel mode.\n"); 353 354 return 0; 355 } 356 357 int machine_check_440A(struct pt_regs *regs) 358 { 359 unsigned long reason = get_mc_reason(regs); 360 361 printk("Machine check in kernel mode.\n"); 362 if (reason & ESR_IMCP){ 363 printk("Instruction Synchronous Machine Check exception\n"); 364 mtspr(SPRN_ESR, reason & ~ESR_IMCP); 365 } 366 else { 367 u32 mcsr = mfspr(SPRN_MCSR); 368 if (mcsr & MCSR_IB) 369 printk("Instruction Read PLB Error\n"); 370 if (mcsr & MCSR_DRB) 371 printk("Data Read PLB Error\n"); 372 if (mcsr & MCSR_DWB) 373 printk("Data Write PLB Error\n"); 374 if (mcsr & MCSR_TLBP) 375 printk("TLB Parity Error\n"); 376 if (mcsr & MCSR_ICP){ 377 flush_instruction_cache(); 378 printk("I-Cache Parity Error\n"); 379 } 380 if (mcsr & MCSR_DCSP) 381 printk("D-Cache Search Parity Error\n"); 382 if (mcsr & MCSR_DCFP) 383 printk("D-Cache Flush Parity Error\n"); 384 if (mcsr & MCSR_IMPE) 385 printk("Machine Check exception is imprecise\n"); 386 387 /* Clear MCSR */ 388 mtspr(SPRN_MCSR, mcsr); 389 } 390 return 0; 391 } 392 #elif defined(CONFIG_E500) 393 int machine_check_e500(struct pt_regs *regs) 394 { 395 unsigned long reason = get_mc_reason(regs); 396 397 printk("Machine check in kernel mode.\n"); 398 printk("Caused by (from MCSR=%lx): ", reason); 399 400 if (reason & MCSR_MCP) 401 printk("Machine Check Signal\n"); 402 if (reason & MCSR_ICPERR) 403 printk("Instruction Cache Parity Error\n"); 404 if (reason & MCSR_DCP_PERR) 405 printk("Data Cache Push Parity Error\n"); 406 if (reason & MCSR_DCPERR) 407 printk("Data Cache Parity Error\n"); 408 if (reason & MCSR_BUS_IAERR) 409 printk("Bus - Instruction Address Error\n"); 410 if (reason & MCSR_BUS_RAERR) 411 printk("Bus - Read Address Error\n"); 412 if (reason & MCSR_BUS_WAERR) 413 printk("Bus - Write Address Error\n"); 414 if (reason & MCSR_BUS_IBERR) 415 printk("Bus - Instruction Data Error\n"); 416 if (reason & MCSR_BUS_RBERR) 417 printk("Bus - Read Data Bus Error\n"); 418 if (reason & MCSR_BUS_WBERR) 419 printk("Bus - Read Data Bus Error\n"); 420 if (reason & MCSR_BUS_IPERR) 421 printk("Bus - Instruction Parity Error\n"); 422 if (reason & MCSR_BUS_RPERR) 423 printk("Bus - Read Parity Error\n"); 424 425 return 0; 426 } 427 #elif defined(CONFIG_E200) 428 int machine_check_e200(struct pt_regs *regs) 429 { 430 unsigned long reason = get_mc_reason(regs); 431 432 printk("Machine check in kernel mode.\n"); 433 printk("Caused by (from MCSR=%lx): ", reason); 434 435 if (reason & MCSR_MCP) 436 printk("Machine Check Signal\n"); 437 if (reason & MCSR_CP_PERR) 438 printk("Cache Push Parity Error\n"); 439 if (reason & MCSR_CPERR) 440 printk("Cache Parity Error\n"); 441 if (reason & MCSR_EXCP_ERR) 442 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); 443 if (reason & MCSR_BUS_IRERR) 444 printk("Bus - Read Bus Error on instruction fetch\n"); 445 if (reason & MCSR_BUS_DRERR) 446 printk("Bus - Read Bus Error on data load\n"); 447 if (reason & MCSR_BUS_WRERR) 448 printk("Bus - Write Bus Error on buffered store or cache line push\n"); 449 450 return 0; 451 } 452 #else 453 int machine_check_generic(struct pt_regs *regs) 454 { 455 unsigned long reason = get_mc_reason(regs); 456 457 printk("Machine check in kernel mode.\n"); 458 printk("Caused by (from SRR1=%lx): ", reason); 459 switch (reason & 0x601F0000) { 460 case 0x80000: 461 printk("Machine check signal\n"); 462 break; 463 case 0: /* for 601 */ 464 case 0x40000: 465 case 0x140000: /* 7450 MSS error and TEA */ 466 printk("Transfer error ack signal\n"); 467 break; 468 case 0x20000: 469 printk("Data parity error signal\n"); 470 break; 471 case 0x10000: 472 printk("Address parity error signal\n"); 473 break; 474 case 0x20000000: 475 printk("L1 Data Cache error\n"); 476 break; 477 case 0x40000000: 478 printk("L1 Instruction Cache error\n"); 479 break; 480 case 0x00100000: 481 printk("L2 data cache parity error\n"); 482 break; 483 default: 484 printk("Unknown values in msr\n"); 485 } 486 return 0; 487 } 488 #endif /* everything else */ 489 490 void machine_check_exception(struct pt_regs *regs) 491 { 492 int recover = 0; 493 494 /* See if any machine dependent calls. In theory, we would want 495 * to call the CPU first, and call the ppc_md. one if the CPU 496 * one returns a positive number. However there is existing code 497 * that assumes the board gets a first chance, so let's keep it 498 * that way for now and fix things later. --BenH. 499 */ 500 if (ppc_md.machine_check_exception) 501 recover = ppc_md.machine_check_exception(regs); 502 else if (cur_cpu_spec->machine_check) 503 recover = cur_cpu_spec->machine_check(regs); 504 505 if (recover > 0) 506 return; 507 508 if (user_mode(regs)) { 509 regs->msr |= MSR_RI; 510 _exception(SIGBUS, regs, BUS_ADRERR, regs->nip); 511 return; 512 } 513 514 #if defined(CONFIG_8xx) && defined(CONFIG_PCI) 515 /* the qspan pci read routines can cause machine checks -- Cort 516 * 517 * yuck !!! that totally needs to go away ! There are better ways 518 * to deal with that than having a wart in the mcheck handler. 519 * -- BenH 520 */ 521 bad_page_fault(regs, regs->dar, SIGBUS); 522 return; 523 #endif 524 525 if (debugger_fault_handler(regs)) { 526 regs->msr |= MSR_RI; 527 return; 528 } 529 530 if (check_io_access(regs)) 531 return; 532 533 if (debugger_fault_handler(regs)) 534 return; 535 die("Machine check", regs, SIGBUS); 536 537 /* Must die if the interrupt is not recoverable */ 538 if (!(regs->msr & MSR_RI)) 539 panic("Unrecoverable Machine check"); 540 } 541 542 void SMIException(struct pt_regs *regs) 543 { 544 die("System Management Interrupt", regs, SIGABRT); 545 } 546 547 void unknown_exception(struct pt_regs *regs) 548 { 549 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 550 regs->nip, regs->msr, regs->trap); 551 552 _exception(SIGTRAP, regs, 0, 0); 553 } 554 555 void instruction_breakpoint_exception(struct pt_regs *regs) 556 { 557 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, 558 5, SIGTRAP) == NOTIFY_STOP) 559 return; 560 if (debugger_iabr_match(regs)) 561 return; 562 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 563 } 564 565 void RunModeException(struct pt_regs *regs) 566 { 567 _exception(SIGTRAP, regs, 0, 0); 568 } 569 570 void __kprobes single_step_exception(struct pt_regs *regs) 571 { 572 regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */ 573 574 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 575 5, SIGTRAP) == NOTIFY_STOP) 576 return; 577 if (debugger_sstep(regs)) 578 return; 579 580 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 581 } 582 583 /* 584 * After we have successfully emulated an instruction, we have to 585 * check if the instruction was being single-stepped, and if so, 586 * pretend we got a single-step exception. This was pointed out 587 * by Kumar Gala. -- paulus 588 */ 589 static void emulate_single_step(struct pt_regs *regs) 590 { 591 if (single_stepping(regs)) { 592 clear_single_step(regs); 593 _exception(SIGTRAP, regs, TRAP_TRACE, 0); 594 } 595 } 596 597 static inline int __parse_fpscr(unsigned long fpscr) 598 { 599 int ret = 0; 600 601 /* Invalid operation */ 602 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) 603 ret = FPE_FLTINV; 604 605 /* Overflow */ 606 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) 607 ret = FPE_FLTOVF; 608 609 /* Underflow */ 610 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) 611 ret = FPE_FLTUND; 612 613 /* Divide by zero */ 614 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) 615 ret = FPE_FLTDIV; 616 617 /* Inexact result */ 618 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) 619 ret = FPE_FLTRES; 620 621 return ret; 622 } 623 624 static void parse_fpe(struct pt_regs *regs) 625 { 626 int code = 0; 627 628 flush_fp_to_thread(current); 629 630 code = __parse_fpscr(current->thread.fpscr.val); 631 632 _exception(SIGFPE, regs, code, regs->nip); 633 } 634 635 /* 636 * Illegal instruction emulation support. Originally written to 637 * provide the PVR to user applications using the mfspr rd, PVR. 638 * Return non-zero if we can't emulate, or -EFAULT if the associated 639 * memory access caused an access fault. Return zero on success. 640 * 641 * There are a couple of ways to do this, either "decode" the instruction 642 * or directly match lots of bits. In this case, matching lots of 643 * bits is faster and easier. 644 * 645 */ 646 static int emulate_string_inst(struct pt_regs *regs, u32 instword) 647 { 648 u8 rT = (instword >> 21) & 0x1f; 649 u8 rA = (instword >> 16) & 0x1f; 650 u8 NB_RB = (instword >> 11) & 0x1f; 651 u32 num_bytes; 652 unsigned long EA; 653 int pos = 0; 654 655 /* Early out if we are an invalid form of lswx */ 656 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) 657 if ((rT == rA) || (rT == NB_RB)) 658 return -EINVAL; 659 660 EA = (rA == 0) ? 0 : regs->gpr[rA]; 661 662 switch (instword & PPC_INST_STRING_MASK) { 663 case PPC_INST_LSWX: 664 case PPC_INST_STSWX: 665 EA += NB_RB; 666 num_bytes = regs->xer & 0x7f; 667 break; 668 case PPC_INST_LSWI: 669 case PPC_INST_STSWI: 670 num_bytes = (NB_RB == 0) ? 32 : NB_RB; 671 break; 672 default: 673 return -EINVAL; 674 } 675 676 while (num_bytes != 0) 677 { 678 u8 val; 679 u32 shift = 8 * (3 - (pos & 0x3)); 680 681 switch ((instword & PPC_INST_STRING_MASK)) { 682 case PPC_INST_LSWX: 683 case PPC_INST_LSWI: 684 if (get_user(val, (u8 __user *)EA)) 685 return -EFAULT; 686 /* first time updating this reg, 687 * zero it out */ 688 if (pos == 0) 689 regs->gpr[rT] = 0; 690 regs->gpr[rT] |= val << shift; 691 break; 692 case PPC_INST_STSWI: 693 case PPC_INST_STSWX: 694 val = regs->gpr[rT] >> shift; 695 if (put_user(val, (u8 __user *)EA)) 696 return -EFAULT; 697 break; 698 } 699 /* move EA to next address */ 700 EA += 1; 701 num_bytes--; 702 703 /* manage our position within the register */ 704 if (++pos == 4) { 705 pos = 0; 706 if (++rT == 32) 707 rT = 0; 708 } 709 } 710 711 return 0; 712 } 713 714 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) 715 { 716 u32 ra,rs; 717 unsigned long tmp; 718 719 ra = (instword >> 16) & 0x1f; 720 rs = (instword >> 21) & 0x1f; 721 722 tmp = regs->gpr[rs]; 723 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); 724 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); 725 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; 726 regs->gpr[ra] = tmp; 727 728 return 0; 729 } 730 731 static int emulate_isel(struct pt_regs *regs, u32 instword) 732 { 733 u8 rT = (instword >> 21) & 0x1f; 734 u8 rA = (instword >> 16) & 0x1f; 735 u8 rB = (instword >> 11) & 0x1f; 736 u8 BC = (instword >> 6) & 0x1f; 737 u8 bit; 738 unsigned long tmp; 739 740 tmp = (rA == 0) ? 0 : regs->gpr[rA]; 741 bit = (regs->ccr >> (31 - BC)) & 0x1; 742 743 regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; 744 745 return 0; 746 } 747 748 static int emulate_instruction(struct pt_regs *regs) 749 { 750 u32 instword; 751 u32 rd; 752 753 if (!user_mode(regs) || (regs->msr & MSR_LE)) 754 return -EINVAL; 755 CHECK_FULL_REGS(regs); 756 757 if (get_user(instword, (u32 __user *)(regs->nip))) 758 return -EFAULT; 759 760 /* Emulate the mfspr rD, PVR. */ 761 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { 762 PPC_WARN_EMULATED(mfpvr); 763 rd = (instword >> 21) & 0x1f; 764 regs->gpr[rd] = mfspr(SPRN_PVR); 765 return 0; 766 } 767 768 /* Emulating the dcba insn is just a no-op. */ 769 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { 770 PPC_WARN_EMULATED(dcba); 771 return 0; 772 } 773 774 /* Emulate the mcrxr insn. */ 775 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { 776 int shift = (instword >> 21) & 0x1c; 777 unsigned long msk = 0xf0000000UL >> shift; 778 779 PPC_WARN_EMULATED(mcrxr); 780 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); 781 regs->xer &= ~0xf0000000UL; 782 return 0; 783 } 784 785 /* Emulate load/store string insn. */ 786 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { 787 PPC_WARN_EMULATED(string); 788 return emulate_string_inst(regs, instword); 789 } 790 791 /* Emulate the popcntb (Population Count Bytes) instruction. */ 792 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { 793 PPC_WARN_EMULATED(popcntb); 794 return emulate_popcntb_inst(regs, instword); 795 } 796 797 /* Emulate isel (Integer Select) instruction */ 798 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { 799 PPC_WARN_EMULATED(isel); 800 return emulate_isel(regs, instword); 801 } 802 803 return -EINVAL; 804 } 805 806 int is_valid_bugaddr(unsigned long addr) 807 { 808 return is_kernel_addr(addr); 809 } 810 811 void __kprobes program_check_exception(struct pt_regs *regs) 812 { 813 unsigned int reason = get_reason(regs); 814 extern int do_mathemu(struct pt_regs *regs); 815 816 /* We can now get here via a FP Unavailable exception if the core 817 * has no FPU, in that case the reason flags will be 0 */ 818 819 if (reason & REASON_FP) { 820 /* IEEE FP exception */ 821 parse_fpe(regs); 822 return; 823 } 824 if (reason & REASON_TRAP) { 825 /* trap exception */ 826 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) 827 == NOTIFY_STOP) 828 return; 829 if (debugger_bpt(regs)) 830 return; 831 832 if (!(regs->msr & MSR_PR) && /* not user-mode */ 833 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { 834 regs->nip += 4; 835 return; 836 } 837 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 838 return; 839 } 840 841 local_irq_enable(); 842 843 #ifdef CONFIG_MATH_EMULATION 844 /* (reason & REASON_ILLEGAL) would be the obvious thing here, 845 * but there seems to be a hardware bug on the 405GP (RevD) 846 * that means ESR is sometimes set incorrectly - either to 847 * ESR_DST (!?) or 0. In the process of chasing this with the 848 * hardware people - not sure if it can happen on any illegal 849 * instruction or only on FP instructions, whether there is a 850 * pattern to occurences etc. -dgibson 31/Mar/2003 */ 851 switch (do_mathemu(regs)) { 852 case 0: 853 emulate_single_step(regs); 854 return; 855 case 1: { 856 int code = 0; 857 code = __parse_fpscr(current->thread.fpscr.val); 858 _exception(SIGFPE, regs, code, regs->nip); 859 return; 860 } 861 case -EFAULT: 862 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 863 return; 864 } 865 /* fall through on any other errors */ 866 #endif /* CONFIG_MATH_EMULATION */ 867 868 /* Try to emulate it if we should. */ 869 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { 870 switch (emulate_instruction(regs)) { 871 case 0: 872 regs->nip += 4; 873 emulate_single_step(regs); 874 return; 875 case -EFAULT: 876 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 877 return; 878 } 879 } 880 881 if (reason & REASON_PRIVILEGED) 882 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 883 else 884 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 885 } 886 887 void alignment_exception(struct pt_regs *regs) 888 { 889 int sig, code, fixed = 0; 890 891 /* we don't implement logging of alignment exceptions */ 892 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) 893 fixed = fix_alignment(regs); 894 895 if (fixed == 1) { 896 regs->nip += 4; /* skip over emulated instruction */ 897 emulate_single_step(regs); 898 return; 899 } 900 901 /* Operand address was bad */ 902 if (fixed == -EFAULT) { 903 sig = SIGSEGV; 904 code = SEGV_ACCERR; 905 } else { 906 sig = SIGBUS; 907 code = BUS_ADRALN; 908 } 909 if (user_mode(regs)) 910 _exception(sig, regs, code, regs->dar); 911 else 912 bad_page_fault(regs, regs->dar, sig); 913 } 914 915 void StackOverflow(struct pt_regs *regs) 916 { 917 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", 918 current, regs->gpr[1]); 919 debugger(regs); 920 show_regs(regs); 921 panic("kernel stack overflow"); 922 } 923 924 void nonrecoverable_exception(struct pt_regs *regs) 925 { 926 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", 927 regs->nip, regs->msr); 928 debugger(regs); 929 die("nonrecoverable exception", regs, SIGKILL); 930 } 931 932 void trace_syscall(struct pt_regs *regs) 933 { 934 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", 935 current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0], 936 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); 937 } 938 939 void kernel_fp_unavailable_exception(struct pt_regs *regs) 940 { 941 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " 942 "%lx at %lx\n", regs->trap, regs->nip); 943 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); 944 } 945 946 void altivec_unavailable_exception(struct pt_regs *regs) 947 { 948 if (user_mode(regs)) { 949 /* A user program has executed an altivec instruction, 950 but this kernel doesn't support altivec. */ 951 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 952 return; 953 } 954 955 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " 956 "%lx at %lx\n", regs->trap, regs->nip); 957 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); 958 } 959 960 void vsx_unavailable_exception(struct pt_regs *regs) 961 { 962 if (user_mode(regs)) { 963 /* A user program has executed an vsx instruction, 964 but this kernel doesn't support vsx. */ 965 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 966 return; 967 } 968 969 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " 970 "%lx at %lx\n", regs->trap, regs->nip); 971 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); 972 } 973 974 void performance_monitor_exception(struct pt_regs *regs) 975 { 976 perf_irq(regs); 977 } 978 979 #ifdef CONFIG_8xx 980 void SoftwareEmulation(struct pt_regs *regs) 981 { 982 extern int do_mathemu(struct pt_regs *); 983 extern int Soft_emulate_8xx(struct pt_regs *); 984 #if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU) 985 int errcode; 986 #endif 987 988 CHECK_FULL_REGS(regs); 989 990 if (!user_mode(regs)) { 991 debugger(regs); 992 die("Kernel Mode Software FPU Emulation", regs, SIGFPE); 993 } 994 995 #ifdef CONFIG_MATH_EMULATION 996 errcode = do_mathemu(regs); 997 if (errcode >= 0) 998 PPC_WARN_EMULATED(math); 999 1000 switch (errcode) { 1001 case 0: 1002 emulate_single_step(regs); 1003 return; 1004 case 1: { 1005 int code = 0; 1006 code = __parse_fpscr(current->thread.fpscr.val); 1007 _exception(SIGFPE, regs, code, regs->nip); 1008 return; 1009 } 1010 case -EFAULT: 1011 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1012 return; 1013 default: 1014 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1015 return; 1016 } 1017 1018 #elif defined(CONFIG_8XX_MINIMAL_FPEMU) 1019 errcode = Soft_emulate_8xx(regs); 1020 if (errcode >= 0) 1021 PPC_WARN_EMULATED(8xx); 1022 1023 switch (errcode) { 1024 case 0: 1025 emulate_single_step(regs); 1026 return; 1027 case 1: 1028 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1029 return; 1030 case -EFAULT: 1031 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1032 return; 1033 } 1034 #else 1035 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1036 #endif 1037 } 1038 #endif /* CONFIG_8xx */ 1039 1040 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) 1041 1042 void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status) 1043 { 1044 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while 1045 * on server, it stops on the target of the branch. In order to simulate 1046 * the server behaviour, we thus restart right away with a single step 1047 * instead of stopping here when hitting a BT 1048 */ 1049 if (debug_status & DBSR_BT) { 1050 regs->msr &= ~MSR_DE; 1051 1052 /* Disable BT */ 1053 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); 1054 /* Clear the BT event */ 1055 mtspr(SPRN_DBSR, DBSR_BT); 1056 1057 /* Do the single step trick only when coming from userspace */ 1058 if (user_mode(regs)) { 1059 current->thread.dbcr0 &= ~DBCR0_BT; 1060 current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC; 1061 regs->msr |= MSR_DE; 1062 return; 1063 } 1064 1065 if (notify_die(DIE_SSTEP, "block_step", regs, 5, 1066 5, SIGTRAP) == NOTIFY_STOP) { 1067 return; 1068 } 1069 if (debugger_sstep(regs)) 1070 return; 1071 } else if (debug_status & DBSR_IC) { /* Instruction complete */ 1072 regs->msr &= ~MSR_DE; 1073 1074 /* Disable instruction completion */ 1075 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); 1076 /* Clear the instruction completion event */ 1077 mtspr(SPRN_DBSR, DBSR_IC); 1078 1079 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 1080 5, SIGTRAP) == NOTIFY_STOP) { 1081 return; 1082 } 1083 1084 if (debugger_sstep(regs)) 1085 return; 1086 1087 if (user_mode(regs)) 1088 current->thread.dbcr0 &= ~(DBCR0_IC); 1089 1090 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 1091 } else if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { 1092 regs->msr &= ~MSR_DE; 1093 1094 if (user_mode(regs)) { 1095 current->thread.dbcr0 &= ~(DBSR_DAC1R | DBSR_DAC1W | 1096 DBCR0_IDM); 1097 } else { 1098 /* Disable DAC interupts */ 1099 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~(DBSR_DAC1R | 1100 DBSR_DAC1W | DBCR0_IDM)); 1101 1102 /* Clear the DAC event */ 1103 mtspr(SPRN_DBSR, (DBSR_DAC1R | DBSR_DAC1W)); 1104 } 1105 /* Setup and send the trap to the handler */ 1106 do_dabr(regs, mfspr(SPRN_DAC1), debug_status); 1107 } 1108 } 1109 #endif /* CONFIG_4xx || CONFIG_BOOKE */ 1110 1111 #if !defined(CONFIG_TAU_INT) 1112 void TAUException(struct pt_regs *regs) 1113 { 1114 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", 1115 regs->nip, regs->msr, regs->trap, print_tainted()); 1116 } 1117 #endif /* CONFIG_INT_TAU */ 1118 1119 #ifdef CONFIG_ALTIVEC 1120 void altivec_assist_exception(struct pt_regs *regs) 1121 { 1122 int err; 1123 1124 if (!user_mode(regs)) { 1125 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" 1126 " at %lx\n", regs->nip); 1127 die("Kernel VMX/Altivec assist exception", regs, SIGILL); 1128 } 1129 1130 flush_altivec_to_thread(current); 1131 1132 PPC_WARN_EMULATED(altivec); 1133 err = emulate_altivec(regs); 1134 if (err == 0) { 1135 regs->nip += 4; /* skip emulated instruction */ 1136 emulate_single_step(regs); 1137 return; 1138 } 1139 1140 if (err == -EFAULT) { 1141 /* got an error reading the instruction */ 1142 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 1143 } else { 1144 /* didn't recognize the instruction */ 1145 /* XXX quick hack for now: set the non-Java bit in the VSCR */ 1146 if (printk_ratelimit()) 1147 printk(KERN_ERR "Unrecognized altivec instruction " 1148 "in %s at %lx\n", current->comm, regs->nip); 1149 current->thread.vscr.u[3] |= 0x10000; 1150 } 1151 } 1152 #endif /* CONFIG_ALTIVEC */ 1153 1154 #ifdef CONFIG_VSX 1155 void vsx_assist_exception(struct pt_regs *regs) 1156 { 1157 if (!user_mode(regs)) { 1158 printk(KERN_EMERG "VSX assist exception in kernel mode" 1159 " at %lx\n", regs->nip); 1160 die("Kernel VSX assist exception", regs, SIGILL); 1161 } 1162 1163 flush_vsx_to_thread(current); 1164 printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip); 1165 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1166 } 1167 #endif /* CONFIG_VSX */ 1168 1169 #ifdef CONFIG_FSL_BOOKE 1170 1171 void doorbell_exception(struct pt_regs *regs) 1172 { 1173 #ifdef CONFIG_SMP 1174 int cpu = smp_processor_id(); 1175 int msg; 1176 1177 if (num_online_cpus() < 2) 1178 return; 1179 1180 for (msg = 0; msg < 4; msg++) 1181 if (test_and_clear_bit(msg, &dbell_smp_message[cpu])) 1182 smp_message_recv(msg); 1183 #else 1184 printk(KERN_WARNING "Received doorbell on non-smp system\n"); 1185 #endif 1186 } 1187 1188 void CacheLockingException(struct pt_regs *regs, unsigned long address, 1189 unsigned long error_code) 1190 { 1191 /* We treat cache locking instructions from the user 1192 * as priv ops, in the future we could try to do 1193 * something smarter 1194 */ 1195 if (error_code & (ESR_DLK|ESR_ILK)) 1196 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 1197 return; 1198 } 1199 #endif /* CONFIG_FSL_BOOKE */ 1200 1201 #ifdef CONFIG_SPE 1202 void SPEFloatingPointException(struct pt_regs *regs) 1203 { 1204 extern int do_spe_mathemu(struct pt_regs *regs); 1205 unsigned long spefscr; 1206 int fpexc_mode; 1207 int code = 0; 1208 int err; 1209 1210 preempt_disable(); 1211 if (regs->msr & MSR_SPE) 1212 giveup_spe(current); 1213 preempt_enable(); 1214 1215 spefscr = current->thread.spefscr; 1216 fpexc_mode = current->thread.fpexc_mode; 1217 1218 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { 1219 code = FPE_FLTOVF; 1220 } 1221 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { 1222 code = FPE_FLTUND; 1223 } 1224 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) 1225 code = FPE_FLTDIV; 1226 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { 1227 code = FPE_FLTINV; 1228 } 1229 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) 1230 code = FPE_FLTRES; 1231 1232 err = do_spe_mathemu(regs); 1233 if (err == 0) { 1234 regs->nip += 4; /* skip emulated instruction */ 1235 emulate_single_step(regs); 1236 return; 1237 } 1238 1239 if (err == -EFAULT) { 1240 /* got an error reading the instruction */ 1241 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 1242 } else if (err == -EINVAL) { 1243 /* didn't recognize the instruction */ 1244 printk(KERN_ERR "unrecognized spe instruction " 1245 "in %s at %lx\n", current->comm, regs->nip); 1246 } else { 1247 _exception(SIGFPE, regs, code, regs->nip); 1248 } 1249 1250 return; 1251 } 1252 1253 void SPEFloatingPointRoundException(struct pt_regs *regs) 1254 { 1255 extern int speround_handler(struct pt_regs *regs); 1256 int err; 1257 1258 preempt_disable(); 1259 if (regs->msr & MSR_SPE) 1260 giveup_spe(current); 1261 preempt_enable(); 1262 1263 regs->nip -= 4; 1264 err = speround_handler(regs); 1265 if (err == 0) { 1266 regs->nip += 4; /* skip emulated instruction */ 1267 emulate_single_step(regs); 1268 return; 1269 } 1270 1271 if (err == -EFAULT) { 1272 /* got an error reading the instruction */ 1273 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 1274 } else if (err == -EINVAL) { 1275 /* didn't recognize the instruction */ 1276 printk(KERN_ERR "unrecognized spe instruction " 1277 "in %s at %lx\n", current->comm, regs->nip); 1278 } else { 1279 _exception(SIGFPE, regs, 0, regs->nip); 1280 return; 1281 } 1282 } 1283 #endif 1284 1285 /* 1286 * We enter here if we get an unrecoverable exception, that is, one 1287 * that happened at a point where the RI (recoverable interrupt) bit 1288 * in the MSR is 0. This indicates that SRR0/1 are live, and that 1289 * we therefore lost state by taking this exception. 1290 */ 1291 void unrecoverable_exception(struct pt_regs *regs) 1292 { 1293 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", 1294 regs->trap, regs->nip); 1295 die("Unrecoverable exception", regs, SIGABRT); 1296 } 1297 1298 #ifdef CONFIG_BOOKE_WDT 1299 /* 1300 * Default handler for a Watchdog exception, 1301 * spins until a reboot occurs 1302 */ 1303 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) 1304 { 1305 /* Generic WatchdogHandler, implement your own */ 1306 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); 1307 return; 1308 } 1309 1310 void WatchdogException(struct pt_regs *regs) 1311 { 1312 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); 1313 WatchdogHandler(regs); 1314 } 1315 #endif 1316 1317 /* 1318 * We enter here if we discover during exception entry that we are 1319 * running in supervisor mode with a userspace value in the stack pointer. 1320 */ 1321 void kernel_bad_stack(struct pt_regs *regs) 1322 { 1323 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", 1324 regs->gpr[1], regs->nip); 1325 die("Bad kernel stack pointer", regs, SIGABRT); 1326 } 1327 1328 void __init trap_init(void) 1329 { 1330 } 1331 1332 1333 #ifdef CONFIG_PPC_EMULATED_STATS 1334 1335 #define WARN_EMULATED_SETUP(type) .type = { .name = #type } 1336 1337 struct ppc_emulated ppc_emulated = { 1338 #ifdef CONFIG_ALTIVEC 1339 WARN_EMULATED_SETUP(altivec), 1340 #endif 1341 WARN_EMULATED_SETUP(dcba), 1342 WARN_EMULATED_SETUP(dcbz), 1343 WARN_EMULATED_SETUP(fp_pair), 1344 WARN_EMULATED_SETUP(isel), 1345 WARN_EMULATED_SETUP(mcrxr), 1346 WARN_EMULATED_SETUP(mfpvr), 1347 WARN_EMULATED_SETUP(multiple), 1348 WARN_EMULATED_SETUP(popcntb), 1349 WARN_EMULATED_SETUP(spe), 1350 WARN_EMULATED_SETUP(string), 1351 WARN_EMULATED_SETUP(unaligned), 1352 #ifdef CONFIG_MATH_EMULATION 1353 WARN_EMULATED_SETUP(math), 1354 #elif defined(CONFIG_8XX_MINIMAL_FPEMU) 1355 WARN_EMULATED_SETUP(8xx), 1356 #endif 1357 #ifdef CONFIG_VSX 1358 WARN_EMULATED_SETUP(vsx), 1359 #endif 1360 }; 1361 1362 u32 ppc_warn_emulated; 1363 1364 void ppc_warn_emulated_print(const char *type) 1365 { 1366 if (printk_ratelimit()) 1367 pr_warning("%s used emulated %s instruction\n", current->comm, 1368 type); 1369 } 1370 1371 static int __init ppc_warn_emulated_init(void) 1372 { 1373 struct dentry *dir, *d; 1374 unsigned int i; 1375 struct ppc_emulated_entry *entries = (void *)&ppc_emulated; 1376 1377 if (!powerpc_debugfs_root) 1378 return -ENODEV; 1379 1380 dir = debugfs_create_dir("emulated_instructions", 1381 powerpc_debugfs_root); 1382 if (!dir) 1383 return -ENOMEM; 1384 1385 d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir, 1386 &ppc_warn_emulated); 1387 if (!d) 1388 goto fail; 1389 1390 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { 1391 d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir, 1392 (u32 *)&entries[i].val.counter); 1393 if (!d) 1394 goto fail; 1395 } 1396 1397 return 0; 1398 1399 fail: 1400 debugfs_remove_recursive(dir); 1401 return -ENOMEM; 1402 } 1403 1404 device_initcall(ppc_warn_emulated_init); 1405 1406 #endif /* CONFIG_PPC_EMULATED_STATS */ 1407