1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * Copyright 2007-2010 Freescale Semiconductor, Inc. 5 * 6 * Modified by Cort Dougan (cort@cs.nmt.edu) 7 * and Paul Mackerras (paulus@samba.org) 8 */ 9 10 /* 11 * This file handles the architecture-dependent parts of hardware exceptions 12 */ 13 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/sched/debug.h> 17 #include <linux/kernel.h> 18 #include <linux/mm.h> 19 #include <linux/pkeys.h> 20 #include <linux/stddef.h> 21 #include <linux/unistd.h> 22 #include <linux/ptrace.h> 23 #include <linux/user.h> 24 #include <linux/interrupt.h> 25 #include <linux/init.h> 26 #include <linux/extable.h> 27 #include <linux/module.h> /* print_modules */ 28 #include <linux/prctl.h> 29 #include <linux/delay.h> 30 #include <linux/kprobes.h> 31 #include <linux/kexec.h> 32 #include <linux/backlight.h> 33 #include <linux/bug.h> 34 #include <linux/kdebug.h> 35 #include <linux/ratelimit.h> 36 #include <linux/context_tracking.h> 37 #include <linux/smp.h> 38 #include <linux/console.h> 39 #include <linux/kmsg_dump.h> 40 41 #include <asm/emulated_ops.h> 42 #include <linux/uaccess.h> 43 #include <asm/debugfs.h> 44 #include <asm/io.h> 45 #include <asm/machdep.h> 46 #include <asm/rtas.h> 47 #include <asm/pmc.h> 48 #include <asm/reg.h> 49 #ifdef CONFIG_PMAC_BACKLIGHT 50 #include <asm/backlight.h> 51 #endif 52 #ifdef CONFIG_PPC64 53 #include <asm/firmware.h> 54 #include <asm/processor.h> 55 #include <asm/tm.h> 56 #endif 57 #include <asm/kexec.h> 58 #include <asm/ppc-opcode.h> 59 #include <asm/rio.h> 60 #include <asm/fadump.h> 61 #include <asm/switch_to.h> 62 #include <asm/tm.h> 63 #include <asm/debug.h> 64 #include <asm/asm-prototypes.h> 65 #include <asm/hmi.h> 66 #include <sysdev/fsl_pci.h> 67 #include <asm/kprobes.h> 68 #include <asm/stacktrace.h> 69 #include <asm/nmi.h> 70 71 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE) 72 int (*__debugger)(struct pt_regs *regs) __read_mostly; 73 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; 74 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; 75 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; 76 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; 77 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly; 78 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; 79 80 EXPORT_SYMBOL(__debugger); 81 EXPORT_SYMBOL(__debugger_ipi); 82 EXPORT_SYMBOL(__debugger_bpt); 83 EXPORT_SYMBOL(__debugger_sstep); 84 EXPORT_SYMBOL(__debugger_iabr_match); 85 EXPORT_SYMBOL(__debugger_break_match); 86 EXPORT_SYMBOL(__debugger_fault_handler); 87 #endif 88 89 /* Transactional Memory trap debug */ 90 #ifdef TM_DEBUG_SW 91 #define TM_DEBUG(x...) printk(KERN_INFO x) 92 #else 93 #define TM_DEBUG(x...) do { } while(0) 94 #endif 95 96 static const char *signame(int signr) 97 { 98 switch (signr) { 99 case SIGBUS: return "bus error"; 100 case SIGFPE: return "floating point exception"; 101 case SIGILL: return "illegal instruction"; 102 case SIGSEGV: return "segfault"; 103 case SIGTRAP: return "unhandled trap"; 104 } 105 106 return "unknown signal"; 107 } 108 109 /* 110 * Trap & Exception support 111 */ 112 113 #ifdef CONFIG_PMAC_BACKLIGHT 114 static void pmac_backlight_unblank(void) 115 { 116 mutex_lock(&pmac_backlight_mutex); 117 if (pmac_backlight) { 118 struct backlight_properties *props; 119 120 props = &pmac_backlight->props; 121 props->brightness = props->max_brightness; 122 props->power = FB_BLANK_UNBLANK; 123 backlight_update_status(pmac_backlight); 124 } 125 mutex_unlock(&pmac_backlight_mutex); 126 } 127 #else 128 static inline void pmac_backlight_unblank(void) { } 129 #endif 130 131 /* 132 * If oops/die is expected to crash the machine, return true here. 133 * 134 * This should not be expected to be 100% accurate, there may be 135 * notifiers registered or other unexpected conditions that may bring 136 * down the kernel. Or if the current process in the kernel is holding 137 * locks or has other critical state, the kernel may become effectively 138 * unusable anyway. 139 */ 140 bool die_will_crash(void) 141 { 142 if (should_fadump_crash()) 143 return true; 144 if (kexec_should_crash(current)) 145 return true; 146 if (in_interrupt() || panic_on_oops || 147 !current->pid || is_global_init(current)) 148 return true; 149 150 return false; 151 } 152 153 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; 154 static int die_owner = -1; 155 static unsigned int die_nest_count; 156 static int die_counter; 157 158 extern void panic_flush_kmsg_start(void) 159 { 160 /* 161 * These are mostly taken from kernel/panic.c, but tries to do 162 * relatively minimal work. Don't use delay functions (TB may 163 * be broken), don't crash dump (need to set a firmware log), 164 * don't run notifiers. We do want to get some information to 165 * Linux console. 166 */ 167 console_verbose(); 168 bust_spinlocks(1); 169 } 170 171 extern void panic_flush_kmsg_end(void) 172 { 173 printk_safe_flush_on_panic(); 174 kmsg_dump(KMSG_DUMP_PANIC); 175 bust_spinlocks(0); 176 debug_locks_off(); 177 console_flush_on_panic(CONSOLE_FLUSH_PENDING); 178 } 179 180 static unsigned long oops_begin(struct pt_regs *regs) 181 { 182 int cpu; 183 unsigned long flags; 184 185 oops_enter(); 186 187 /* racy, but better than risking deadlock. */ 188 raw_local_irq_save(flags); 189 cpu = smp_processor_id(); 190 if (!arch_spin_trylock(&die_lock)) { 191 if (cpu == die_owner) 192 /* nested oops. should stop eventually */; 193 else 194 arch_spin_lock(&die_lock); 195 } 196 die_nest_count++; 197 die_owner = cpu; 198 console_verbose(); 199 bust_spinlocks(1); 200 if (machine_is(powermac)) 201 pmac_backlight_unblank(); 202 return flags; 203 } 204 NOKPROBE_SYMBOL(oops_begin); 205 206 static void oops_end(unsigned long flags, struct pt_regs *regs, 207 int signr) 208 { 209 bust_spinlocks(0); 210 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 211 die_nest_count--; 212 oops_exit(); 213 printk("\n"); 214 if (!die_nest_count) { 215 /* Nest count reaches zero, release the lock. */ 216 die_owner = -1; 217 arch_spin_unlock(&die_lock); 218 } 219 raw_local_irq_restore(flags); 220 221 /* 222 * system_reset_excption handles debugger, crash dump, panic, for 0x100 223 */ 224 if (TRAP(regs) == 0x100) 225 return; 226 227 crash_fadump(regs, "die oops"); 228 229 if (kexec_should_crash(current)) 230 crash_kexec(regs); 231 232 if (!signr) 233 return; 234 235 /* 236 * While our oops output is serialised by a spinlock, output 237 * from panic() called below can race and corrupt it. If we 238 * know we are going to panic, delay for 1 second so we have a 239 * chance to get clean backtraces from all CPUs that are oopsing. 240 */ 241 if (in_interrupt() || panic_on_oops || !current->pid || 242 is_global_init(current)) { 243 mdelay(MSEC_PER_SEC); 244 } 245 246 if (panic_on_oops) 247 panic("Fatal exception"); 248 do_exit(signr); 249 } 250 NOKPROBE_SYMBOL(oops_end); 251 252 static char *get_mmu_str(void) 253 { 254 if (early_radix_enabled()) 255 return " MMU=Radix"; 256 if (early_mmu_has_feature(MMU_FTR_HPTE_TABLE)) 257 return " MMU=Hash"; 258 return ""; 259 } 260 261 static int __die(const char *str, struct pt_regs *regs, long err) 262 { 263 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); 264 265 printk("%s PAGE_SIZE=%luK%s%s%s%s%s%s %s\n", 266 IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN) ? "LE" : "BE", 267 PAGE_SIZE / 1024, get_mmu_str(), 268 IS_ENABLED(CONFIG_PREEMPT) ? " PREEMPT" : "", 269 IS_ENABLED(CONFIG_SMP) ? " SMP" : "", 270 IS_ENABLED(CONFIG_SMP) ? (" NR_CPUS=" __stringify(NR_CPUS)) : "", 271 debug_pagealloc_enabled() ? " DEBUG_PAGEALLOC" : "", 272 IS_ENABLED(CONFIG_NUMA) ? " NUMA" : "", 273 ppc_md.name ? ppc_md.name : ""); 274 275 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP) 276 return 1; 277 278 print_modules(); 279 show_regs(regs); 280 281 return 0; 282 } 283 NOKPROBE_SYMBOL(__die); 284 285 void die(const char *str, struct pt_regs *regs, long err) 286 { 287 unsigned long flags; 288 289 /* 290 * system_reset_excption handles debugger, crash dump, panic, for 0x100 291 */ 292 if (TRAP(regs) != 0x100) { 293 if (debugger(regs)) 294 return; 295 } 296 297 flags = oops_begin(regs); 298 if (__die(str, regs, err)) 299 err = 0; 300 oops_end(flags, regs, err); 301 } 302 NOKPROBE_SYMBOL(die); 303 304 void user_single_step_report(struct pt_regs *regs) 305 { 306 force_sig_fault(SIGTRAP, TRAP_TRACE, (void __user *)regs->nip); 307 } 308 309 static void show_signal_msg(int signr, struct pt_regs *regs, int code, 310 unsigned long addr) 311 { 312 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, 313 DEFAULT_RATELIMIT_BURST); 314 315 if (!show_unhandled_signals) 316 return; 317 318 if (!unhandled_signal(current, signr)) 319 return; 320 321 if (!__ratelimit(&rs)) 322 return; 323 324 pr_info("%s[%d]: %s (%d) at %lx nip %lx lr %lx code %x", 325 current->comm, current->pid, signame(signr), signr, 326 addr, regs->nip, regs->link, code); 327 328 print_vma_addr(KERN_CONT " in ", regs->nip); 329 330 pr_cont("\n"); 331 332 show_user_instructions(regs); 333 } 334 335 static bool exception_common(int signr, struct pt_regs *regs, int code, 336 unsigned long addr) 337 { 338 if (!user_mode(regs)) { 339 die("Exception in kernel mode", regs, signr); 340 return false; 341 } 342 343 show_signal_msg(signr, regs, code, addr); 344 345 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs)) 346 local_irq_enable(); 347 348 current->thread.trap_nr = code; 349 350 /* 351 * Save all the pkey registers AMR/IAMR/UAMOR. Eg: Core dumps need 352 * to capture the content, if the task gets killed. 353 */ 354 thread_pkey_regs_save(¤t->thread); 355 356 return true; 357 } 358 359 void _exception_pkey(struct pt_regs *regs, unsigned long addr, int key) 360 { 361 if (!exception_common(SIGSEGV, regs, SEGV_PKUERR, addr)) 362 return; 363 364 force_sig_pkuerr((void __user *) addr, key); 365 } 366 367 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) 368 { 369 if (!exception_common(signr, regs, code, addr)) 370 return; 371 372 force_sig_fault(signr, code, (void __user *)addr); 373 } 374 375 /* 376 * The interrupt architecture has a quirk in that the HV interrupts excluding 377 * the NMIs (0x100 and 0x200) do not clear MSR[RI] at entry. The first thing 378 * that an interrupt handler must do is save off a GPR into a scratch register, 379 * and all interrupts on POWERNV (HV=1) use the HSPRG1 register as scratch. 380 * Therefore an NMI can clobber an HV interrupt's live HSPRG1 without noticing 381 * that it is non-reentrant, which leads to random data corruption. 382 * 383 * The solution is for NMI interrupts in HV mode to check if they originated 384 * from these critical HV interrupt regions. If so, then mark them not 385 * recoverable. 386 * 387 * An alternative would be for HV NMIs to use SPRG for scratch to avoid the 388 * HSPRG1 clobber, however this would cause guest SPRG to be clobbered. Linux 389 * guests should always have MSR[RI]=0 when its scratch SPRG is in use, so 390 * that would work. However any other guest OS that may have the SPRG live 391 * and MSR[RI]=1 could encounter silent corruption. 392 * 393 * Builds that do not support KVM could take this second option to increase 394 * the recoverability of NMIs. 395 */ 396 void hv_nmi_check_nonrecoverable(struct pt_regs *regs) 397 { 398 #ifdef CONFIG_PPC_POWERNV 399 unsigned long kbase = (unsigned long)_stext; 400 unsigned long nip = regs->nip; 401 402 if (!(regs->msr & MSR_RI)) 403 return; 404 if (!(regs->msr & MSR_HV)) 405 return; 406 if (regs->msr & MSR_PR) 407 return; 408 409 /* 410 * Now test if the interrupt has hit a range that may be using 411 * HSPRG1 without having RI=0 (i.e., an HSRR interrupt). The 412 * problem ranges all run un-relocated. Test real and virt modes 413 * at the same time by droping the high bit of the nip (virt mode 414 * entry points still have the +0x4000 offset). 415 */ 416 nip &= ~0xc000000000000000ULL; 417 if ((nip >= 0x500 && nip < 0x600) || (nip >= 0x4500 && nip < 0x4600)) 418 goto nonrecoverable; 419 if ((nip >= 0x980 && nip < 0xa00) || (nip >= 0x4980 && nip < 0x4a00)) 420 goto nonrecoverable; 421 if ((nip >= 0xe00 && nip < 0xec0) || (nip >= 0x4e00 && nip < 0x4ec0)) 422 goto nonrecoverable; 423 if ((nip >= 0xf80 && nip < 0xfa0) || (nip >= 0x4f80 && nip < 0x4fa0)) 424 goto nonrecoverable; 425 426 /* Trampoline code runs un-relocated so subtract kbase. */ 427 if (nip >= (unsigned long)(start_real_trampolines - kbase) && 428 nip < (unsigned long)(end_real_trampolines - kbase)) 429 goto nonrecoverable; 430 if (nip >= (unsigned long)(start_virt_trampolines - kbase) && 431 nip < (unsigned long)(end_virt_trampolines - kbase)) 432 goto nonrecoverable; 433 return; 434 435 nonrecoverable: 436 regs->msr &= ~MSR_RI; 437 #endif 438 } 439 440 void system_reset_exception(struct pt_regs *regs) 441 { 442 unsigned long hsrr0, hsrr1; 443 bool saved_hsrrs = false; 444 u8 ftrace_enabled = this_cpu_get_ftrace_enabled(); 445 446 this_cpu_set_ftrace_enabled(0); 447 448 nmi_enter(); 449 450 /* 451 * System reset can interrupt code where HSRRs are live and MSR[RI]=1. 452 * The system reset interrupt itself may clobber HSRRs (e.g., to call 453 * OPAL), so save them here and restore them before returning. 454 * 455 * Machine checks don't need to save HSRRs, as the real mode handler 456 * is careful to avoid them, and the regular handler is not delivered 457 * as an NMI. 458 */ 459 if (cpu_has_feature(CPU_FTR_HVMODE)) { 460 hsrr0 = mfspr(SPRN_HSRR0); 461 hsrr1 = mfspr(SPRN_HSRR1); 462 saved_hsrrs = true; 463 } 464 465 hv_nmi_check_nonrecoverable(regs); 466 467 __this_cpu_inc(irq_stat.sreset_irqs); 468 469 /* See if any machine dependent calls */ 470 if (ppc_md.system_reset_exception) { 471 if (ppc_md.system_reset_exception(regs)) 472 goto out; 473 } 474 475 if (debugger(regs)) 476 goto out; 477 478 kmsg_dump(KMSG_DUMP_OOPS); 479 /* 480 * A system reset is a request to dump, so we always send 481 * it through the crashdump code (if fadump or kdump are 482 * registered). 483 */ 484 crash_fadump(regs, "System Reset"); 485 486 crash_kexec(regs); 487 488 /* 489 * We aren't the primary crash CPU. We need to send it 490 * to a holding pattern to avoid it ending up in the panic 491 * code. 492 */ 493 crash_kexec_secondary(regs); 494 495 /* 496 * No debugger or crash dump registered, print logs then 497 * panic. 498 */ 499 die("System Reset", regs, SIGABRT); 500 501 mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */ 502 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 503 nmi_panic(regs, "System Reset"); 504 505 out: 506 #ifdef CONFIG_PPC_BOOK3S_64 507 BUG_ON(get_paca()->in_nmi == 0); 508 if (get_paca()->in_nmi > 1) 509 die("Unrecoverable nested System Reset", regs, SIGABRT); 510 #endif 511 /* Must die if the interrupt is not recoverable */ 512 if (!(regs->msr & MSR_RI)) 513 die("Unrecoverable System Reset", regs, SIGABRT); 514 515 if (saved_hsrrs) { 516 mtspr(SPRN_HSRR0, hsrr0); 517 mtspr(SPRN_HSRR1, hsrr1); 518 } 519 520 nmi_exit(); 521 522 this_cpu_set_ftrace_enabled(ftrace_enabled); 523 524 /* What should we do here? We could issue a shutdown or hard reset. */ 525 } 526 527 /* 528 * I/O accesses can cause machine checks on powermacs. 529 * Check if the NIP corresponds to the address of a sync 530 * instruction for which there is an entry in the exception 531 * table. 532 * -- paulus. 533 */ 534 static inline int check_io_access(struct pt_regs *regs) 535 { 536 #ifdef CONFIG_PPC32 537 unsigned long msr = regs->msr; 538 const struct exception_table_entry *entry; 539 unsigned int *nip = (unsigned int *)regs->nip; 540 541 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) 542 && (entry = search_exception_tables(regs->nip)) != NULL) { 543 /* 544 * Check that it's a sync instruction, or somewhere 545 * in the twi; isync; nop sequence that inb/inw/inl uses. 546 * As the address is in the exception table 547 * we should be able to read the instr there. 548 * For the debug message, we look at the preceding 549 * load or store. 550 */ 551 if (*nip == PPC_INST_NOP) 552 nip -= 2; 553 else if (*nip == PPC_INST_ISYNC) 554 --nip; 555 if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) { 556 unsigned int rb; 557 558 --nip; 559 rb = (*nip >> 11) & 0x1f; 560 printk(KERN_DEBUG "%s bad port %lx at %p\n", 561 (*nip & 0x100)? "OUT to": "IN from", 562 regs->gpr[rb] - _IO_BASE, nip); 563 regs->msr |= MSR_RI; 564 regs->nip = extable_fixup(entry); 565 return 1; 566 } 567 } 568 #endif /* CONFIG_PPC32 */ 569 return 0; 570 } 571 572 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 573 /* On 4xx, the reason for the machine check or program exception 574 is in the ESR. */ 575 #define get_reason(regs) ((regs)->dsisr) 576 #define REASON_FP ESR_FP 577 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) 578 #define REASON_PRIVILEGED ESR_PPR 579 #define REASON_TRAP ESR_PTR 580 #define REASON_PREFIXED 0 581 #define REASON_BOUNDARY 0 582 583 /* single-step stuff */ 584 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC) 585 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC) 586 #define clear_br_trace(regs) do {} while(0) 587 #else 588 /* On non-4xx, the reason for the machine check or program 589 exception is in the MSR. */ 590 #define get_reason(regs) ((regs)->msr) 591 #define REASON_TM SRR1_PROGTM 592 #define REASON_FP SRR1_PROGFPE 593 #define REASON_ILLEGAL SRR1_PROGILL 594 #define REASON_PRIVILEGED SRR1_PROGPRIV 595 #define REASON_TRAP SRR1_PROGTRAP 596 #define REASON_PREFIXED SRR1_PREFIXED 597 #define REASON_BOUNDARY SRR1_BOUNDARY 598 599 #define single_stepping(regs) ((regs)->msr & MSR_SE) 600 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) 601 #define clear_br_trace(regs) ((regs)->msr &= ~MSR_BE) 602 #endif 603 604 #define inst_length(reason) (((reason) & REASON_PREFIXED) ? 8 : 4) 605 606 #if defined(CONFIG_E500) 607 int machine_check_e500mc(struct pt_regs *regs) 608 { 609 unsigned long mcsr = mfspr(SPRN_MCSR); 610 unsigned long pvr = mfspr(SPRN_PVR); 611 unsigned long reason = mcsr; 612 int recoverable = 1; 613 614 if (reason & MCSR_LD) { 615 recoverable = fsl_rio_mcheck_exception(regs); 616 if (recoverable == 1) 617 goto silent_out; 618 } 619 620 printk("Machine check in kernel mode.\n"); 621 printk("Caused by (from MCSR=%lx): ", reason); 622 623 if (reason & MCSR_MCP) 624 pr_cont("Machine Check Signal\n"); 625 626 if (reason & MCSR_ICPERR) { 627 pr_cont("Instruction Cache Parity Error\n"); 628 629 /* 630 * This is recoverable by invalidating the i-cache. 631 */ 632 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); 633 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) 634 ; 635 636 /* 637 * This will generally be accompanied by an instruction 638 * fetch error report -- only treat MCSR_IF as fatal 639 * if it wasn't due to an L1 parity error. 640 */ 641 reason &= ~MCSR_IF; 642 } 643 644 if (reason & MCSR_DCPERR_MC) { 645 pr_cont("Data Cache Parity Error\n"); 646 647 /* 648 * In write shadow mode we auto-recover from the error, but it 649 * may still get logged and cause a machine check. We should 650 * only treat the non-write shadow case as non-recoverable. 651 */ 652 /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit 653 * is not implemented but L1 data cache always runs in write 654 * shadow mode. Hence on data cache parity errors HW will 655 * automatically invalidate the L1 Data Cache. 656 */ 657 if (PVR_VER(pvr) != PVR_VER_E6500) { 658 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) 659 recoverable = 0; 660 } 661 } 662 663 if (reason & MCSR_L2MMU_MHIT) { 664 pr_cont("Hit on multiple TLB entries\n"); 665 recoverable = 0; 666 } 667 668 if (reason & MCSR_NMI) 669 pr_cont("Non-maskable interrupt\n"); 670 671 if (reason & MCSR_IF) { 672 pr_cont("Instruction Fetch Error Report\n"); 673 recoverable = 0; 674 } 675 676 if (reason & MCSR_LD) { 677 pr_cont("Load Error Report\n"); 678 recoverable = 0; 679 } 680 681 if (reason & MCSR_ST) { 682 pr_cont("Store Error Report\n"); 683 recoverable = 0; 684 } 685 686 if (reason & MCSR_LDG) { 687 pr_cont("Guarded Load Error Report\n"); 688 recoverable = 0; 689 } 690 691 if (reason & MCSR_TLBSYNC) 692 pr_cont("Simultaneous tlbsync operations\n"); 693 694 if (reason & MCSR_BSL2_ERR) { 695 pr_cont("Level 2 Cache Error\n"); 696 recoverable = 0; 697 } 698 699 if (reason & MCSR_MAV) { 700 u64 addr; 701 702 addr = mfspr(SPRN_MCAR); 703 addr |= (u64)mfspr(SPRN_MCARU) << 32; 704 705 pr_cont("Machine Check %s Address: %#llx\n", 706 reason & MCSR_MEA ? "Effective" : "Physical", addr); 707 } 708 709 silent_out: 710 mtspr(SPRN_MCSR, mcsr); 711 return mfspr(SPRN_MCSR) == 0 && recoverable; 712 } 713 714 int machine_check_e500(struct pt_regs *regs) 715 { 716 unsigned long reason = mfspr(SPRN_MCSR); 717 718 if (reason & MCSR_BUS_RBERR) { 719 if (fsl_rio_mcheck_exception(regs)) 720 return 1; 721 if (fsl_pci_mcheck_exception(regs)) 722 return 1; 723 } 724 725 printk("Machine check in kernel mode.\n"); 726 printk("Caused by (from MCSR=%lx): ", reason); 727 728 if (reason & MCSR_MCP) 729 pr_cont("Machine Check Signal\n"); 730 if (reason & MCSR_ICPERR) 731 pr_cont("Instruction Cache Parity Error\n"); 732 if (reason & MCSR_DCP_PERR) 733 pr_cont("Data Cache Push Parity Error\n"); 734 if (reason & MCSR_DCPERR) 735 pr_cont("Data Cache Parity Error\n"); 736 if (reason & MCSR_BUS_IAERR) 737 pr_cont("Bus - Instruction Address Error\n"); 738 if (reason & MCSR_BUS_RAERR) 739 pr_cont("Bus - Read Address Error\n"); 740 if (reason & MCSR_BUS_WAERR) 741 pr_cont("Bus - Write Address Error\n"); 742 if (reason & MCSR_BUS_IBERR) 743 pr_cont("Bus - Instruction Data Error\n"); 744 if (reason & MCSR_BUS_RBERR) 745 pr_cont("Bus - Read Data Bus Error\n"); 746 if (reason & MCSR_BUS_WBERR) 747 pr_cont("Bus - Write Data Bus Error\n"); 748 if (reason & MCSR_BUS_IPERR) 749 pr_cont("Bus - Instruction Parity Error\n"); 750 if (reason & MCSR_BUS_RPERR) 751 pr_cont("Bus - Read Parity Error\n"); 752 753 return 0; 754 } 755 756 int machine_check_generic(struct pt_regs *regs) 757 { 758 return 0; 759 } 760 #elif defined(CONFIG_E200) 761 int machine_check_e200(struct pt_regs *regs) 762 { 763 unsigned long reason = mfspr(SPRN_MCSR); 764 765 printk("Machine check in kernel mode.\n"); 766 printk("Caused by (from MCSR=%lx): ", reason); 767 768 if (reason & MCSR_MCP) 769 pr_cont("Machine Check Signal\n"); 770 if (reason & MCSR_CP_PERR) 771 pr_cont("Cache Push Parity Error\n"); 772 if (reason & MCSR_CPERR) 773 pr_cont("Cache Parity Error\n"); 774 if (reason & MCSR_EXCP_ERR) 775 pr_cont("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); 776 if (reason & MCSR_BUS_IRERR) 777 pr_cont("Bus - Read Bus Error on instruction fetch\n"); 778 if (reason & MCSR_BUS_DRERR) 779 pr_cont("Bus - Read Bus Error on data load\n"); 780 if (reason & MCSR_BUS_WRERR) 781 pr_cont("Bus - Write Bus Error on buffered store or cache line push\n"); 782 783 return 0; 784 } 785 #elif defined(CONFIG_PPC32) 786 int machine_check_generic(struct pt_regs *regs) 787 { 788 unsigned long reason = regs->msr; 789 790 printk("Machine check in kernel mode.\n"); 791 printk("Caused by (from SRR1=%lx): ", reason); 792 switch (reason & 0x601F0000) { 793 case 0x80000: 794 pr_cont("Machine check signal\n"); 795 break; 796 case 0x40000: 797 case 0x140000: /* 7450 MSS error and TEA */ 798 pr_cont("Transfer error ack signal\n"); 799 break; 800 case 0x20000: 801 pr_cont("Data parity error signal\n"); 802 break; 803 case 0x10000: 804 pr_cont("Address parity error signal\n"); 805 break; 806 case 0x20000000: 807 pr_cont("L1 Data Cache error\n"); 808 break; 809 case 0x40000000: 810 pr_cont("L1 Instruction Cache error\n"); 811 break; 812 case 0x00100000: 813 pr_cont("L2 data cache parity error\n"); 814 break; 815 default: 816 pr_cont("Unknown values in msr\n"); 817 } 818 return 0; 819 } 820 #endif /* everything else */ 821 822 void machine_check_exception(struct pt_regs *regs) 823 { 824 int recover = 0; 825 826 /* 827 * BOOK3S_64 does not call this handler as a non-maskable interrupt 828 * (it uses its own early real-mode handler to handle the MCE proper 829 * and then raises irq_work to call this handler when interrupts are 830 * enabled). 831 * 832 * This is silly. The BOOK3S_64 should just call a different function 833 * rather than expecting semantics to magically change. Something 834 * like 'non_nmi_machine_check_exception()', perhaps? 835 */ 836 const bool nmi = !IS_ENABLED(CONFIG_PPC_BOOK3S_64); 837 838 if (nmi) nmi_enter(); 839 840 __this_cpu_inc(irq_stat.mce_exceptions); 841 842 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 843 844 /* See if any machine dependent calls. In theory, we would want 845 * to call the CPU first, and call the ppc_md. one if the CPU 846 * one returns a positive number. However there is existing code 847 * that assumes the board gets a first chance, so let's keep it 848 * that way for now and fix things later. --BenH. 849 */ 850 if (ppc_md.machine_check_exception) 851 recover = ppc_md.machine_check_exception(regs); 852 else if (cur_cpu_spec->machine_check) 853 recover = cur_cpu_spec->machine_check(regs); 854 855 if (recover > 0) 856 goto bail; 857 858 if (debugger_fault_handler(regs)) 859 goto bail; 860 861 if (check_io_access(regs)) 862 goto bail; 863 864 if (nmi) nmi_exit(); 865 866 die("Machine check", regs, SIGBUS); 867 868 /* Must die if the interrupt is not recoverable */ 869 if (!(regs->msr & MSR_RI)) 870 die("Unrecoverable Machine check", regs, SIGBUS); 871 872 return; 873 874 bail: 875 if (nmi) nmi_exit(); 876 } 877 878 void SMIException(struct pt_regs *regs) 879 { 880 die("System Management Interrupt", regs, SIGABRT); 881 } 882 883 #ifdef CONFIG_VSX 884 static void p9_hmi_special_emu(struct pt_regs *regs) 885 { 886 unsigned int ra, rb, t, i, sel, instr, rc; 887 const void __user *addr; 888 u8 vbuf[16] __aligned(16), *vdst; 889 unsigned long ea, msr, msr_mask; 890 bool swap; 891 892 if (__get_user_inatomic(instr, (unsigned int __user *)regs->nip)) 893 return; 894 895 /* 896 * lxvb16x opcode: 0x7c0006d8 897 * lxvd2x opcode: 0x7c000698 898 * lxvh8x opcode: 0x7c000658 899 * lxvw4x opcode: 0x7c000618 900 */ 901 if ((instr & 0xfc00073e) != 0x7c000618) { 902 pr_devel("HMI vec emu: not vector CI %i:%s[%d] nip=%016lx" 903 " instr=%08x\n", 904 smp_processor_id(), current->comm, current->pid, 905 regs->nip, instr); 906 return; 907 } 908 909 /* Grab vector registers into the task struct */ 910 msr = regs->msr; /* Grab msr before we flush the bits */ 911 flush_vsx_to_thread(current); 912 enable_kernel_altivec(); 913 914 /* 915 * Is userspace running with a different endian (this is rare but 916 * not impossible) 917 */ 918 swap = (msr & MSR_LE) != (MSR_KERNEL & MSR_LE); 919 920 /* Decode the instruction */ 921 ra = (instr >> 16) & 0x1f; 922 rb = (instr >> 11) & 0x1f; 923 t = (instr >> 21) & 0x1f; 924 if (instr & 1) 925 vdst = (u8 *)¤t->thread.vr_state.vr[t]; 926 else 927 vdst = (u8 *)¤t->thread.fp_state.fpr[t][0]; 928 929 /* Grab the vector address */ 930 ea = regs->gpr[rb] + (ra ? regs->gpr[ra] : 0); 931 if (is_32bit_task()) 932 ea &= 0xfffffffful; 933 addr = (__force const void __user *)ea; 934 935 /* Check it */ 936 if (!access_ok(addr, 16)) { 937 pr_devel("HMI vec emu: bad access %i:%s[%d] nip=%016lx" 938 " instr=%08x addr=%016lx\n", 939 smp_processor_id(), current->comm, current->pid, 940 regs->nip, instr, (unsigned long)addr); 941 return; 942 } 943 944 /* Read the vector */ 945 rc = 0; 946 if ((unsigned long)addr & 0xfUL) 947 /* unaligned case */ 948 rc = __copy_from_user_inatomic(vbuf, addr, 16); 949 else 950 __get_user_atomic_128_aligned(vbuf, addr, rc); 951 if (rc) { 952 pr_devel("HMI vec emu: page fault %i:%s[%d] nip=%016lx" 953 " instr=%08x addr=%016lx\n", 954 smp_processor_id(), current->comm, current->pid, 955 regs->nip, instr, (unsigned long)addr); 956 return; 957 } 958 959 pr_devel("HMI vec emu: emulated vector CI %i:%s[%d] nip=%016lx" 960 " instr=%08x addr=%016lx\n", 961 smp_processor_id(), current->comm, current->pid, regs->nip, 962 instr, (unsigned long) addr); 963 964 /* Grab instruction "selector" */ 965 sel = (instr >> 6) & 3; 966 967 /* 968 * Check to make sure the facility is actually enabled. This 969 * could happen if we get a false positive hit. 970 * 971 * lxvd2x/lxvw4x always check MSR VSX sel = 0,2 972 * lxvh8x/lxvb16x check MSR VSX or VEC depending on VSR used sel = 1,3 973 */ 974 msr_mask = MSR_VSX; 975 if ((sel & 1) && (instr & 1)) /* lxvh8x & lxvb16x + VSR >= 32 */ 976 msr_mask = MSR_VEC; 977 if (!(msr & msr_mask)) { 978 pr_devel("HMI vec emu: MSR fac clear %i:%s[%d] nip=%016lx" 979 " instr=%08x msr:%016lx\n", 980 smp_processor_id(), current->comm, current->pid, 981 regs->nip, instr, msr); 982 return; 983 } 984 985 /* Do logging here before we modify sel based on endian */ 986 switch (sel) { 987 case 0: /* lxvw4x */ 988 PPC_WARN_EMULATED(lxvw4x, regs); 989 break; 990 case 1: /* lxvh8x */ 991 PPC_WARN_EMULATED(lxvh8x, regs); 992 break; 993 case 2: /* lxvd2x */ 994 PPC_WARN_EMULATED(lxvd2x, regs); 995 break; 996 case 3: /* lxvb16x */ 997 PPC_WARN_EMULATED(lxvb16x, regs); 998 break; 999 } 1000 1001 #ifdef __LITTLE_ENDIAN__ 1002 /* 1003 * An LE kernel stores the vector in the task struct as an LE 1004 * byte array (effectively swapping both the components and 1005 * the content of the components). Those instructions expect 1006 * the components to remain in ascending address order, so we 1007 * swap them back. 1008 * 1009 * If we are running a BE user space, the expectation is that 1010 * of a simple memcpy, so forcing the emulation to look like 1011 * a lxvb16x should do the trick. 1012 */ 1013 if (swap) 1014 sel = 3; 1015 1016 switch (sel) { 1017 case 0: /* lxvw4x */ 1018 for (i = 0; i < 4; i++) 1019 ((u32 *)vdst)[i] = ((u32 *)vbuf)[3-i]; 1020 break; 1021 case 1: /* lxvh8x */ 1022 for (i = 0; i < 8; i++) 1023 ((u16 *)vdst)[i] = ((u16 *)vbuf)[7-i]; 1024 break; 1025 case 2: /* lxvd2x */ 1026 for (i = 0; i < 2; i++) 1027 ((u64 *)vdst)[i] = ((u64 *)vbuf)[1-i]; 1028 break; 1029 case 3: /* lxvb16x */ 1030 for (i = 0; i < 16; i++) 1031 vdst[i] = vbuf[15-i]; 1032 break; 1033 } 1034 #else /* __LITTLE_ENDIAN__ */ 1035 /* On a big endian kernel, a BE userspace only needs a memcpy */ 1036 if (!swap) 1037 sel = 3; 1038 1039 /* Otherwise, we need to swap the content of the components */ 1040 switch (sel) { 1041 case 0: /* lxvw4x */ 1042 for (i = 0; i < 4; i++) 1043 ((u32 *)vdst)[i] = cpu_to_le32(((u32 *)vbuf)[i]); 1044 break; 1045 case 1: /* lxvh8x */ 1046 for (i = 0; i < 8; i++) 1047 ((u16 *)vdst)[i] = cpu_to_le16(((u16 *)vbuf)[i]); 1048 break; 1049 case 2: /* lxvd2x */ 1050 for (i = 0; i < 2; i++) 1051 ((u64 *)vdst)[i] = cpu_to_le64(((u64 *)vbuf)[i]); 1052 break; 1053 case 3: /* lxvb16x */ 1054 memcpy(vdst, vbuf, 16); 1055 break; 1056 } 1057 #endif /* !__LITTLE_ENDIAN__ */ 1058 1059 /* Go to next instruction */ 1060 regs->nip += 4; 1061 } 1062 #endif /* CONFIG_VSX */ 1063 1064 void handle_hmi_exception(struct pt_regs *regs) 1065 { 1066 struct pt_regs *old_regs; 1067 1068 old_regs = set_irq_regs(regs); 1069 irq_enter(); 1070 1071 #ifdef CONFIG_VSX 1072 /* Real mode flagged P9 special emu is needed */ 1073 if (local_paca->hmi_p9_special_emu) { 1074 local_paca->hmi_p9_special_emu = 0; 1075 1076 /* 1077 * We don't want to take page faults while doing the 1078 * emulation, we just replay the instruction if necessary. 1079 */ 1080 pagefault_disable(); 1081 p9_hmi_special_emu(regs); 1082 pagefault_enable(); 1083 } 1084 #endif /* CONFIG_VSX */ 1085 1086 if (ppc_md.handle_hmi_exception) 1087 ppc_md.handle_hmi_exception(regs); 1088 1089 irq_exit(); 1090 set_irq_regs(old_regs); 1091 } 1092 1093 void unknown_exception(struct pt_regs *regs) 1094 { 1095 enum ctx_state prev_state = exception_enter(); 1096 1097 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 1098 regs->nip, regs->msr, regs->trap); 1099 1100 _exception(SIGTRAP, regs, TRAP_UNK, 0); 1101 1102 exception_exit(prev_state); 1103 } 1104 1105 void instruction_breakpoint_exception(struct pt_regs *regs) 1106 { 1107 enum ctx_state prev_state = exception_enter(); 1108 1109 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, 1110 5, SIGTRAP) == NOTIFY_STOP) 1111 goto bail; 1112 if (debugger_iabr_match(regs)) 1113 goto bail; 1114 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1115 1116 bail: 1117 exception_exit(prev_state); 1118 } 1119 1120 void RunModeException(struct pt_regs *regs) 1121 { 1122 _exception(SIGTRAP, regs, TRAP_UNK, 0); 1123 } 1124 1125 void single_step_exception(struct pt_regs *regs) 1126 { 1127 enum ctx_state prev_state = exception_enter(); 1128 1129 clear_single_step(regs); 1130 clear_br_trace(regs); 1131 1132 if (kprobe_post_handler(regs)) 1133 return; 1134 1135 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 1136 5, SIGTRAP) == NOTIFY_STOP) 1137 goto bail; 1138 if (debugger_sstep(regs)) 1139 goto bail; 1140 1141 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 1142 1143 bail: 1144 exception_exit(prev_state); 1145 } 1146 NOKPROBE_SYMBOL(single_step_exception); 1147 1148 /* 1149 * After we have successfully emulated an instruction, we have to 1150 * check if the instruction was being single-stepped, and if so, 1151 * pretend we got a single-step exception. This was pointed out 1152 * by Kumar Gala. -- paulus 1153 */ 1154 static void emulate_single_step(struct pt_regs *regs) 1155 { 1156 if (single_stepping(regs)) 1157 single_step_exception(regs); 1158 } 1159 1160 static inline int __parse_fpscr(unsigned long fpscr) 1161 { 1162 int ret = FPE_FLTUNK; 1163 1164 /* Invalid operation */ 1165 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) 1166 ret = FPE_FLTINV; 1167 1168 /* Overflow */ 1169 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) 1170 ret = FPE_FLTOVF; 1171 1172 /* Underflow */ 1173 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) 1174 ret = FPE_FLTUND; 1175 1176 /* Divide by zero */ 1177 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) 1178 ret = FPE_FLTDIV; 1179 1180 /* Inexact result */ 1181 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) 1182 ret = FPE_FLTRES; 1183 1184 return ret; 1185 } 1186 1187 static void parse_fpe(struct pt_regs *regs) 1188 { 1189 int code = 0; 1190 1191 flush_fp_to_thread(current); 1192 1193 code = __parse_fpscr(current->thread.fp_state.fpscr); 1194 1195 _exception(SIGFPE, regs, code, regs->nip); 1196 } 1197 1198 /* 1199 * Illegal instruction emulation support. Originally written to 1200 * provide the PVR to user applications using the mfspr rd, PVR. 1201 * Return non-zero if we can't emulate, or -EFAULT if the associated 1202 * memory access caused an access fault. Return zero on success. 1203 * 1204 * There are a couple of ways to do this, either "decode" the instruction 1205 * or directly match lots of bits. In this case, matching lots of 1206 * bits is faster and easier. 1207 * 1208 */ 1209 static int emulate_string_inst(struct pt_regs *regs, u32 instword) 1210 { 1211 u8 rT = (instword >> 21) & 0x1f; 1212 u8 rA = (instword >> 16) & 0x1f; 1213 u8 NB_RB = (instword >> 11) & 0x1f; 1214 u32 num_bytes; 1215 unsigned long EA; 1216 int pos = 0; 1217 1218 /* Early out if we are an invalid form of lswx */ 1219 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) 1220 if ((rT == rA) || (rT == NB_RB)) 1221 return -EINVAL; 1222 1223 EA = (rA == 0) ? 0 : regs->gpr[rA]; 1224 1225 switch (instword & PPC_INST_STRING_MASK) { 1226 case PPC_INST_LSWX: 1227 case PPC_INST_STSWX: 1228 EA += NB_RB; 1229 num_bytes = regs->xer & 0x7f; 1230 break; 1231 case PPC_INST_LSWI: 1232 case PPC_INST_STSWI: 1233 num_bytes = (NB_RB == 0) ? 32 : NB_RB; 1234 break; 1235 default: 1236 return -EINVAL; 1237 } 1238 1239 while (num_bytes != 0) 1240 { 1241 u8 val; 1242 u32 shift = 8 * (3 - (pos & 0x3)); 1243 1244 /* if process is 32-bit, clear upper 32 bits of EA */ 1245 if ((regs->msr & MSR_64BIT) == 0) 1246 EA &= 0xFFFFFFFF; 1247 1248 switch ((instword & PPC_INST_STRING_MASK)) { 1249 case PPC_INST_LSWX: 1250 case PPC_INST_LSWI: 1251 if (get_user(val, (u8 __user *)EA)) 1252 return -EFAULT; 1253 /* first time updating this reg, 1254 * zero it out */ 1255 if (pos == 0) 1256 regs->gpr[rT] = 0; 1257 regs->gpr[rT] |= val << shift; 1258 break; 1259 case PPC_INST_STSWI: 1260 case PPC_INST_STSWX: 1261 val = regs->gpr[rT] >> shift; 1262 if (put_user(val, (u8 __user *)EA)) 1263 return -EFAULT; 1264 break; 1265 } 1266 /* move EA to next address */ 1267 EA += 1; 1268 num_bytes--; 1269 1270 /* manage our position within the register */ 1271 if (++pos == 4) { 1272 pos = 0; 1273 if (++rT == 32) 1274 rT = 0; 1275 } 1276 } 1277 1278 return 0; 1279 } 1280 1281 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) 1282 { 1283 u32 ra,rs; 1284 unsigned long tmp; 1285 1286 ra = (instword >> 16) & 0x1f; 1287 rs = (instword >> 21) & 0x1f; 1288 1289 tmp = regs->gpr[rs]; 1290 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); 1291 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); 1292 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; 1293 regs->gpr[ra] = tmp; 1294 1295 return 0; 1296 } 1297 1298 static int emulate_isel(struct pt_regs *regs, u32 instword) 1299 { 1300 u8 rT = (instword >> 21) & 0x1f; 1301 u8 rA = (instword >> 16) & 0x1f; 1302 u8 rB = (instword >> 11) & 0x1f; 1303 u8 BC = (instword >> 6) & 0x1f; 1304 u8 bit; 1305 unsigned long tmp; 1306 1307 tmp = (rA == 0) ? 0 : regs->gpr[rA]; 1308 bit = (regs->ccr >> (31 - BC)) & 0x1; 1309 1310 regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; 1311 1312 return 0; 1313 } 1314 1315 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1316 static inline bool tm_abort_check(struct pt_regs *regs, int cause) 1317 { 1318 /* If we're emulating a load/store in an active transaction, we cannot 1319 * emulate it as the kernel operates in transaction suspended context. 1320 * We need to abort the transaction. This creates a persistent TM 1321 * abort so tell the user what caused it with a new code. 1322 */ 1323 if (MSR_TM_TRANSACTIONAL(regs->msr)) { 1324 tm_enable(); 1325 tm_abort(cause); 1326 return true; 1327 } 1328 return false; 1329 } 1330 #else 1331 static inline bool tm_abort_check(struct pt_regs *regs, int reason) 1332 { 1333 return false; 1334 } 1335 #endif 1336 1337 static int emulate_instruction(struct pt_regs *regs) 1338 { 1339 u32 instword; 1340 u32 rd; 1341 1342 if (!user_mode(regs)) 1343 return -EINVAL; 1344 CHECK_FULL_REGS(regs); 1345 1346 if (get_user(instword, (u32 __user *)(regs->nip))) 1347 return -EFAULT; 1348 1349 /* Emulate the mfspr rD, PVR. */ 1350 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { 1351 PPC_WARN_EMULATED(mfpvr, regs); 1352 rd = (instword >> 21) & 0x1f; 1353 regs->gpr[rd] = mfspr(SPRN_PVR); 1354 return 0; 1355 } 1356 1357 /* Emulating the dcba insn is just a no-op. */ 1358 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { 1359 PPC_WARN_EMULATED(dcba, regs); 1360 return 0; 1361 } 1362 1363 /* Emulate the mcrxr insn. */ 1364 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { 1365 int shift = (instword >> 21) & 0x1c; 1366 unsigned long msk = 0xf0000000UL >> shift; 1367 1368 PPC_WARN_EMULATED(mcrxr, regs); 1369 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); 1370 regs->xer &= ~0xf0000000UL; 1371 return 0; 1372 } 1373 1374 /* Emulate load/store string insn. */ 1375 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { 1376 if (tm_abort_check(regs, 1377 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) 1378 return -EINVAL; 1379 PPC_WARN_EMULATED(string, regs); 1380 return emulate_string_inst(regs, instword); 1381 } 1382 1383 /* Emulate the popcntb (Population Count Bytes) instruction. */ 1384 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { 1385 PPC_WARN_EMULATED(popcntb, regs); 1386 return emulate_popcntb_inst(regs, instword); 1387 } 1388 1389 /* Emulate isel (Integer Select) instruction */ 1390 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { 1391 PPC_WARN_EMULATED(isel, regs); 1392 return emulate_isel(regs, instword); 1393 } 1394 1395 /* Emulate sync instruction variants */ 1396 if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) { 1397 PPC_WARN_EMULATED(sync, regs); 1398 asm volatile("sync"); 1399 return 0; 1400 } 1401 1402 #ifdef CONFIG_PPC64 1403 /* Emulate the mfspr rD, DSCR. */ 1404 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) == 1405 PPC_INST_MFSPR_DSCR_USER) || 1406 ((instword & PPC_INST_MFSPR_DSCR_MASK) == 1407 PPC_INST_MFSPR_DSCR)) && 1408 cpu_has_feature(CPU_FTR_DSCR)) { 1409 PPC_WARN_EMULATED(mfdscr, regs); 1410 rd = (instword >> 21) & 0x1f; 1411 regs->gpr[rd] = mfspr(SPRN_DSCR); 1412 return 0; 1413 } 1414 /* Emulate the mtspr DSCR, rD. */ 1415 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) == 1416 PPC_INST_MTSPR_DSCR_USER) || 1417 ((instword & PPC_INST_MTSPR_DSCR_MASK) == 1418 PPC_INST_MTSPR_DSCR)) && 1419 cpu_has_feature(CPU_FTR_DSCR)) { 1420 PPC_WARN_EMULATED(mtdscr, regs); 1421 rd = (instword >> 21) & 0x1f; 1422 current->thread.dscr = regs->gpr[rd]; 1423 current->thread.dscr_inherit = 1; 1424 mtspr(SPRN_DSCR, current->thread.dscr); 1425 return 0; 1426 } 1427 #endif 1428 1429 return -EINVAL; 1430 } 1431 1432 int is_valid_bugaddr(unsigned long addr) 1433 { 1434 return is_kernel_addr(addr); 1435 } 1436 1437 #ifdef CONFIG_MATH_EMULATION 1438 static int emulate_math(struct pt_regs *regs) 1439 { 1440 int ret; 1441 extern int do_mathemu(struct pt_regs *regs); 1442 1443 ret = do_mathemu(regs); 1444 if (ret >= 0) 1445 PPC_WARN_EMULATED(math, regs); 1446 1447 switch (ret) { 1448 case 0: 1449 emulate_single_step(regs); 1450 return 0; 1451 case 1: { 1452 int code = 0; 1453 code = __parse_fpscr(current->thread.fp_state.fpscr); 1454 _exception(SIGFPE, regs, code, regs->nip); 1455 return 0; 1456 } 1457 case -EFAULT: 1458 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1459 return 0; 1460 } 1461 1462 return -1; 1463 } 1464 #else 1465 static inline int emulate_math(struct pt_regs *regs) { return -1; } 1466 #endif 1467 1468 void program_check_exception(struct pt_regs *regs) 1469 { 1470 enum ctx_state prev_state = exception_enter(); 1471 unsigned int reason = get_reason(regs); 1472 1473 /* We can now get here via a FP Unavailable exception if the core 1474 * has no FPU, in that case the reason flags will be 0 */ 1475 1476 if (reason & REASON_FP) { 1477 /* IEEE FP exception */ 1478 parse_fpe(regs); 1479 goto bail; 1480 } 1481 if (reason & REASON_TRAP) { 1482 unsigned long bugaddr; 1483 /* Debugger is first in line to stop recursive faults in 1484 * rcu_lock, notify_die, or atomic_notifier_call_chain */ 1485 if (debugger_bpt(regs)) 1486 goto bail; 1487 1488 if (kprobe_handler(regs)) 1489 goto bail; 1490 1491 /* trap exception */ 1492 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) 1493 == NOTIFY_STOP) 1494 goto bail; 1495 1496 bugaddr = regs->nip; 1497 /* 1498 * Fixup bugaddr for BUG_ON() in real mode 1499 */ 1500 if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR)) 1501 bugaddr += PAGE_OFFSET; 1502 1503 if (!(regs->msr & MSR_PR) && /* not user-mode */ 1504 report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) { 1505 regs->nip += 4; 1506 goto bail; 1507 } 1508 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1509 goto bail; 1510 } 1511 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1512 if (reason & REASON_TM) { 1513 /* This is a TM "Bad Thing Exception" program check. 1514 * This occurs when: 1515 * - An rfid/hrfid/mtmsrd attempts to cause an illegal 1516 * transition in TM states. 1517 * - A trechkpt is attempted when transactional. 1518 * - A treclaim is attempted when non transactional. 1519 * - A tend is illegally attempted. 1520 * - writing a TM SPR when transactional. 1521 * 1522 * If usermode caused this, it's done something illegal and 1523 * gets a SIGILL slap on the wrist. We call it an illegal 1524 * operand to distinguish from the instruction just being bad 1525 * (e.g. executing a 'tend' on a CPU without TM!); it's an 1526 * illegal /placement/ of a valid instruction. 1527 */ 1528 if (user_mode(regs)) { 1529 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip); 1530 goto bail; 1531 } else { 1532 printk(KERN_EMERG "Unexpected TM Bad Thing exception " 1533 "at %lx (msr 0x%lx) tm_scratch=%llx\n", 1534 regs->nip, regs->msr, get_paca()->tm_scratch); 1535 die("Unrecoverable exception", regs, SIGABRT); 1536 } 1537 } 1538 #endif 1539 1540 /* 1541 * If we took the program check in the kernel skip down to sending a 1542 * SIGILL. The subsequent cases all relate to emulating instructions 1543 * which we should only do for userspace. We also do not want to enable 1544 * interrupts for kernel faults because that might lead to further 1545 * faults, and loose the context of the original exception. 1546 */ 1547 if (!user_mode(regs)) 1548 goto sigill; 1549 1550 /* We restore the interrupt state now */ 1551 if (!arch_irq_disabled_regs(regs)) 1552 local_irq_enable(); 1553 1554 /* (reason & REASON_ILLEGAL) would be the obvious thing here, 1555 * but there seems to be a hardware bug on the 405GP (RevD) 1556 * that means ESR is sometimes set incorrectly - either to 1557 * ESR_DST (!?) or 0. In the process of chasing this with the 1558 * hardware people - not sure if it can happen on any illegal 1559 * instruction or only on FP instructions, whether there is a 1560 * pattern to occurrences etc. -dgibson 31/Mar/2003 1561 */ 1562 if (!emulate_math(regs)) 1563 goto bail; 1564 1565 /* Try to emulate it if we should. */ 1566 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { 1567 switch (emulate_instruction(regs)) { 1568 case 0: 1569 regs->nip += 4; 1570 emulate_single_step(regs); 1571 goto bail; 1572 case -EFAULT: 1573 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1574 goto bail; 1575 } 1576 } 1577 1578 sigill: 1579 if (reason & REASON_PRIVILEGED) 1580 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 1581 else 1582 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1583 1584 bail: 1585 exception_exit(prev_state); 1586 } 1587 NOKPROBE_SYMBOL(program_check_exception); 1588 1589 /* 1590 * This occurs when running in hypervisor mode on POWER6 or later 1591 * and an illegal instruction is encountered. 1592 */ 1593 void emulation_assist_interrupt(struct pt_regs *regs) 1594 { 1595 regs->msr |= REASON_ILLEGAL; 1596 program_check_exception(regs); 1597 } 1598 NOKPROBE_SYMBOL(emulation_assist_interrupt); 1599 1600 void alignment_exception(struct pt_regs *regs) 1601 { 1602 enum ctx_state prev_state = exception_enter(); 1603 int sig, code, fixed = 0; 1604 unsigned long reason; 1605 1606 /* We restore the interrupt state now */ 1607 if (!arch_irq_disabled_regs(regs)) 1608 local_irq_enable(); 1609 1610 reason = get_reason(regs); 1611 1612 if (reason & REASON_BOUNDARY) { 1613 sig = SIGBUS; 1614 code = BUS_ADRALN; 1615 goto bad; 1616 } 1617 1618 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT)) 1619 goto bail; 1620 1621 /* we don't implement logging of alignment exceptions */ 1622 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) 1623 fixed = fix_alignment(regs); 1624 1625 if (fixed == 1) { 1626 /* skip over emulated instruction */ 1627 regs->nip += inst_length(reason); 1628 emulate_single_step(regs); 1629 goto bail; 1630 } 1631 1632 /* Operand address was bad */ 1633 if (fixed == -EFAULT) { 1634 sig = SIGSEGV; 1635 code = SEGV_ACCERR; 1636 } else { 1637 sig = SIGBUS; 1638 code = BUS_ADRALN; 1639 } 1640 bad: 1641 if (user_mode(regs)) 1642 _exception(sig, regs, code, regs->dar); 1643 else 1644 bad_page_fault(regs, regs->dar, sig); 1645 1646 bail: 1647 exception_exit(prev_state); 1648 } 1649 1650 void StackOverflow(struct pt_regs *regs) 1651 { 1652 pr_crit("Kernel stack overflow in process %s[%d], r1=%lx\n", 1653 current->comm, task_pid_nr(current), regs->gpr[1]); 1654 debugger(regs); 1655 show_regs(regs); 1656 panic("kernel stack overflow"); 1657 } 1658 1659 void stack_overflow_exception(struct pt_regs *regs) 1660 { 1661 enum ctx_state prev_state = exception_enter(); 1662 1663 die("Kernel stack overflow", regs, SIGSEGV); 1664 1665 exception_exit(prev_state); 1666 } 1667 1668 void kernel_fp_unavailable_exception(struct pt_regs *regs) 1669 { 1670 enum ctx_state prev_state = exception_enter(); 1671 1672 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " 1673 "%lx at %lx\n", regs->trap, regs->nip); 1674 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); 1675 1676 exception_exit(prev_state); 1677 } 1678 1679 void altivec_unavailable_exception(struct pt_regs *regs) 1680 { 1681 enum ctx_state prev_state = exception_enter(); 1682 1683 if (user_mode(regs)) { 1684 /* A user program has executed an altivec instruction, 1685 but this kernel doesn't support altivec. */ 1686 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1687 goto bail; 1688 } 1689 1690 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " 1691 "%lx at %lx\n", regs->trap, regs->nip); 1692 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); 1693 1694 bail: 1695 exception_exit(prev_state); 1696 } 1697 1698 void vsx_unavailable_exception(struct pt_regs *regs) 1699 { 1700 if (user_mode(regs)) { 1701 /* A user program has executed an vsx instruction, 1702 but this kernel doesn't support vsx. */ 1703 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1704 return; 1705 } 1706 1707 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " 1708 "%lx at %lx\n", regs->trap, regs->nip); 1709 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); 1710 } 1711 1712 #ifdef CONFIG_PPC64 1713 static void tm_unavailable(struct pt_regs *regs) 1714 { 1715 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1716 if (user_mode(regs)) { 1717 current->thread.load_tm++; 1718 regs->msr |= MSR_TM; 1719 tm_enable(); 1720 tm_restore_sprs(¤t->thread); 1721 return; 1722 } 1723 #endif 1724 pr_emerg("Unrecoverable TM Unavailable Exception " 1725 "%lx at %lx\n", regs->trap, regs->nip); 1726 die("Unrecoverable TM Unavailable Exception", regs, SIGABRT); 1727 } 1728 1729 void facility_unavailable_exception(struct pt_regs *regs) 1730 { 1731 static char *facility_strings[] = { 1732 [FSCR_FP_LG] = "FPU", 1733 [FSCR_VECVSX_LG] = "VMX/VSX", 1734 [FSCR_DSCR_LG] = "DSCR", 1735 [FSCR_PM_LG] = "PMU SPRs", 1736 [FSCR_BHRB_LG] = "BHRB", 1737 [FSCR_TM_LG] = "TM", 1738 [FSCR_EBB_LG] = "EBB", 1739 [FSCR_TAR_LG] = "TAR", 1740 [FSCR_MSGP_LG] = "MSGP", 1741 [FSCR_SCV_LG] = "SCV", 1742 [FSCR_PREFIX_LG] = "PREFIX", 1743 }; 1744 char *facility = "unknown"; 1745 u64 value; 1746 u32 instword, rd; 1747 u8 status; 1748 bool hv; 1749 1750 hv = (TRAP(regs) == 0xf80); 1751 if (hv) 1752 value = mfspr(SPRN_HFSCR); 1753 else 1754 value = mfspr(SPRN_FSCR); 1755 1756 status = value >> 56; 1757 if ((hv || status >= 2) && 1758 (status < ARRAY_SIZE(facility_strings)) && 1759 facility_strings[status]) 1760 facility = facility_strings[status]; 1761 1762 /* We should not have taken this interrupt in kernel */ 1763 if (!user_mode(regs)) { 1764 pr_emerg("Facility '%s' unavailable (%d) exception in kernel mode at %lx\n", 1765 facility, status, regs->nip); 1766 die("Unexpected facility unavailable exception", regs, SIGABRT); 1767 } 1768 1769 /* We restore the interrupt state now */ 1770 if (!arch_irq_disabled_regs(regs)) 1771 local_irq_enable(); 1772 1773 if (status == FSCR_DSCR_LG) { 1774 /* 1775 * User is accessing the DSCR register using the problem 1776 * state only SPR number (0x03) either through a mfspr or 1777 * a mtspr instruction. If it is a write attempt through 1778 * a mtspr, then we set the inherit bit. This also allows 1779 * the user to write or read the register directly in the 1780 * future by setting via the FSCR DSCR bit. But in case it 1781 * is a read DSCR attempt through a mfspr instruction, we 1782 * just emulate the instruction instead. This code path will 1783 * always emulate all the mfspr instructions till the user 1784 * has attempted at least one mtspr instruction. This way it 1785 * preserves the same behaviour when the user is accessing 1786 * the DSCR through privilege level only SPR number (0x11) 1787 * which is emulated through illegal instruction exception. 1788 * We always leave HFSCR DSCR set. 1789 */ 1790 if (get_user(instword, (u32 __user *)(regs->nip))) { 1791 pr_err("Failed to fetch the user instruction\n"); 1792 return; 1793 } 1794 1795 /* Write into DSCR (mtspr 0x03, RS) */ 1796 if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK) 1797 == PPC_INST_MTSPR_DSCR_USER) { 1798 rd = (instword >> 21) & 0x1f; 1799 current->thread.dscr = regs->gpr[rd]; 1800 current->thread.dscr_inherit = 1; 1801 current->thread.fscr |= FSCR_DSCR; 1802 mtspr(SPRN_FSCR, current->thread.fscr); 1803 } 1804 1805 /* Read from DSCR (mfspr RT, 0x03) */ 1806 if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK) 1807 == PPC_INST_MFSPR_DSCR_USER) { 1808 if (emulate_instruction(regs)) { 1809 pr_err("DSCR based mfspr emulation failed\n"); 1810 return; 1811 } 1812 regs->nip += 4; 1813 emulate_single_step(regs); 1814 } 1815 return; 1816 } 1817 1818 if (status == FSCR_TM_LG) { 1819 /* 1820 * If we're here then the hardware is TM aware because it 1821 * generated an exception with FSRM_TM set. 1822 * 1823 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware 1824 * told us not to do TM, or the kernel is not built with TM 1825 * support. 1826 * 1827 * If both of those things are true, then userspace can spam the 1828 * console by triggering the printk() below just by continually 1829 * doing tbegin (or any TM instruction). So in that case just 1830 * send the process a SIGILL immediately. 1831 */ 1832 if (!cpu_has_feature(CPU_FTR_TM)) 1833 goto out; 1834 1835 tm_unavailable(regs); 1836 return; 1837 } 1838 1839 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n", 1840 hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr); 1841 1842 out: 1843 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1844 } 1845 #endif 1846 1847 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1848 1849 void fp_unavailable_tm(struct pt_regs *regs) 1850 { 1851 /* Note: This does not handle any kind of FP laziness. */ 1852 1853 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n", 1854 regs->nip, regs->msr); 1855 1856 /* We can only have got here if the task started using FP after 1857 * beginning the transaction. So, the transactional regs are just a 1858 * copy of the checkpointed ones. But, we still need to recheckpoint 1859 * as we're enabling FP for the process; it will return, abort the 1860 * transaction, and probably retry but now with FP enabled. So the 1861 * checkpointed FP registers need to be loaded. 1862 */ 1863 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1864 1865 /* 1866 * Reclaim initially saved out bogus (lazy) FPRs to ckfp_state, and 1867 * then it was overwrite by the thr->fp_state by tm_reclaim_thread(). 1868 * 1869 * At this point, ck{fp,vr}_state contains the exact values we want to 1870 * recheckpoint. 1871 */ 1872 1873 /* Enable FP for the task: */ 1874 current->thread.load_fp = 1; 1875 1876 /* 1877 * Recheckpoint all the checkpointed ckpt, ck{fp, vr}_state registers. 1878 */ 1879 tm_recheckpoint(¤t->thread); 1880 } 1881 1882 void altivec_unavailable_tm(struct pt_regs *regs) 1883 { 1884 /* See the comments in fp_unavailable_tm(). This function operates 1885 * the same way. 1886 */ 1887 1888 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx," 1889 "MSR=%lx\n", 1890 regs->nip, regs->msr); 1891 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1892 current->thread.load_vec = 1; 1893 tm_recheckpoint(¤t->thread); 1894 current->thread.used_vr = 1; 1895 } 1896 1897 void vsx_unavailable_tm(struct pt_regs *regs) 1898 { 1899 /* See the comments in fp_unavailable_tm(). This works similarly, 1900 * though we're loading both FP and VEC registers in here. 1901 * 1902 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC 1903 * regs. Either way, set MSR_VSX. 1904 */ 1905 1906 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx," 1907 "MSR=%lx\n", 1908 regs->nip, regs->msr); 1909 1910 current->thread.used_vsr = 1; 1911 1912 /* This reclaims FP and/or VR regs if they're already enabled */ 1913 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1914 1915 current->thread.load_vec = 1; 1916 current->thread.load_fp = 1; 1917 1918 tm_recheckpoint(¤t->thread); 1919 } 1920 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1921 1922 void performance_monitor_exception(struct pt_regs *regs) 1923 { 1924 __this_cpu_inc(irq_stat.pmu_irqs); 1925 1926 perf_irq(regs); 1927 } 1928 1929 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1930 static void handle_debug(struct pt_regs *regs, unsigned long debug_status) 1931 { 1932 int changed = 0; 1933 /* 1934 * Determine the cause of the debug event, clear the 1935 * event flags and send a trap to the handler. Torez 1936 */ 1937 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { 1938 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); 1939 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1940 current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; 1941 #endif 1942 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, 1943 5); 1944 changed |= 0x01; 1945 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { 1946 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); 1947 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, 1948 6); 1949 changed |= 0x01; 1950 } else if (debug_status & DBSR_IAC1) { 1951 current->thread.debug.dbcr0 &= ~DBCR0_IAC1; 1952 dbcr_iac_range(current) &= ~DBCR_IAC12MODE; 1953 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, 1954 1); 1955 changed |= 0x01; 1956 } else if (debug_status & DBSR_IAC2) { 1957 current->thread.debug.dbcr0 &= ~DBCR0_IAC2; 1958 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, 1959 2); 1960 changed |= 0x01; 1961 } else if (debug_status & DBSR_IAC3) { 1962 current->thread.debug.dbcr0 &= ~DBCR0_IAC3; 1963 dbcr_iac_range(current) &= ~DBCR_IAC34MODE; 1964 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, 1965 3); 1966 changed |= 0x01; 1967 } else if (debug_status & DBSR_IAC4) { 1968 current->thread.debug.dbcr0 &= ~DBCR0_IAC4; 1969 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, 1970 4); 1971 changed |= 0x01; 1972 } 1973 /* 1974 * At the point this routine was called, the MSR(DE) was turned off. 1975 * Check all other debug flags and see if that bit needs to be turned 1976 * back on or not. 1977 */ 1978 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 1979 current->thread.debug.dbcr1)) 1980 regs->msr |= MSR_DE; 1981 else 1982 /* Make sure the IDM flag is off */ 1983 current->thread.debug.dbcr0 &= ~DBCR0_IDM; 1984 1985 if (changed & 0x01) 1986 mtspr(SPRN_DBCR0, current->thread.debug.dbcr0); 1987 } 1988 1989 void DebugException(struct pt_regs *regs, unsigned long debug_status) 1990 { 1991 current->thread.debug.dbsr = debug_status; 1992 1993 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while 1994 * on server, it stops on the target of the branch. In order to simulate 1995 * the server behaviour, we thus restart right away with a single step 1996 * instead of stopping here when hitting a BT 1997 */ 1998 if (debug_status & DBSR_BT) { 1999 regs->msr &= ~MSR_DE; 2000 2001 /* Disable BT */ 2002 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); 2003 /* Clear the BT event */ 2004 mtspr(SPRN_DBSR, DBSR_BT); 2005 2006 /* Do the single step trick only when coming from userspace */ 2007 if (user_mode(regs)) { 2008 current->thread.debug.dbcr0 &= ~DBCR0_BT; 2009 current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; 2010 regs->msr |= MSR_DE; 2011 return; 2012 } 2013 2014 if (kprobe_post_handler(regs)) 2015 return; 2016 2017 if (notify_die(DIE_SSTEP, "block_step", regs, 5, 2018 5, SIGTRAP) == NOTIFY_STOP) { 2019 return; 2020 } 2021 if (debugger_sstep(regs)) 2022 return; 2023 } else if (debug_status & DBSR_IC) { /* Instruction complete */ 2024 regs->msr &= ~MSR_DE; 2025 2026 /* Disable instruction completion */ 2027 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); 2028 /* Clear the instruction completion event */ 2029 mtspr(SPRN_DBSR, DBSR_IC); 2030 2031 if (kprobe_post_handler(regs)) 2032 return; 2033 2034 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 2035 5, SIGTRAP) == NOTIFY_STOP) { 2036 return; 2037 } 2038 2039 if (debugger_sstep(regs)) 2040 return; 2041 2042 if (user_mode(regs)) { 2043 current->thread.debug.dbcr0 &= ~DBCR0_IC; 2044 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 2045 current->thread.debug.dbcr1)) 2046 regs->msr |= MSR_DE; 2047 else 2048 /* Make sure the IDM bit is off */ 2049 current->thread.debug.dbcr0 &= ~DBCR0_IDM; 2050 } 2051 2052 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 2053 } else 2054 handle_debug(regs, debug_status); 2055 } 2056 NOKPROBE_SYMBOL(DebugException); 2057 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 2058 2059 #ifdef CONFIG_ALTIVEC 2060 void altivec_assist_exception(struct pt_regs *regs) 2061 { 2062 int err; 2063 2064 if (!user_mode(regs)) { 2065 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" 2066 " at %lx\n", regs->nip); 2067 die("Kernel VMX/Altivec assist exception", regs, SIGILL); 2068 } 2069 2070 flush_altivec_to_thread(current); 2071 2072 PPC_WARN_EMULATED(altivec, regs); 2073 err = emulate_altivec(regs); 2074 if (err == 0) { 2075 regs->nip += 4; /* skip emulated instruction */ 2076 emulate_single_step(regs); 2077 return; 2078 } 2079 2080 if (err == -EFAULT) { 2081 /* got an error reading the instruction */ 2082 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2083 } else { 2084 /* didn't recognize the instruction */ 2085 /* XXX quick hack for now: set the non-Java bit in the VSCR */ 2086 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " 2087 "in %s at %lx\n", current->comm, regs->nip); 2088 current->thread.vr_state.vscr.u[3] |= 0x10000; 2089 } 2090 } 2091 #endif /* CONFIG_ALTIVEC */ 2092 2093 #ifdef CONFIG_FSL_BOOKE 2094 void CacheLockingException(struct pt_regs *regs, unsigned long address, 2095 unsigned long error_code) 2096 { 2097 /* We treat cache locking instructions from the user 2098 * as priv ops, in the future we could try to do 2099 * something smarter 2100 */ 2101 if (error_code & (ESR_DLK|ESR_ILK)) 2102 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 2103 return; 2104 } 2105 #endif /* CONFIG_FSL_BOOKE */ 2106 2107 #ifdef CONFIG_SPE 2108 void SPEFloatingPointException(struct pt_regs *regs) 2109 { 2110 extern int do_spe_mathemu(struct pt_regs *regs); 2111 unsigned long spefscr; 2112 int fpexc_mode; 2113 int code = FPE_FLTUNK; 2114 int err; 2115 2116 /* We restore the interrupt state now */ 2117 if (!arch_irq_disabled_regs(regs)) 2118 local_irq_enable(); 2119 2120 flush_spe_to_thread(current); 2121 2122 spefscr = current->thread.spefscr; 2123 fpexc_mode = current->thread.fpexc_mode; 2124 2125 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { 2126 code = FPE_FLTOVF; 2127 } 2128 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { 2129 code = FPE_FLTUND; 2130 } 2131 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) 2132 code = FPE_FLTDIV; 2133 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { 2134 code = FPE_FLTINV; 2135 } 2136 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) 2137 code = FPE_FLTRES; 2138 2139 err = do_spe_mathemu(regs); 2140 if (err == 0) { 2141 regs->nip += 4; /* skip emulated instruction */ 2142 emulate_single_step(regs); 2143 return; 2144 } 2145 2146 if (err == -EFAULT) { 2147 /* got an error reading the instruction */ 2148 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2149 } else if (err == -EINVAL) { 2150 /* didn't recognize the instruction */ 2151 printk(KERN_ERR "unrecognized spe instruction " 2152 "in %s at %lx\n", current->comm, regs->nip); 2153 } else { 2154 _exception(SIGFPE, regs, code, regs->nip); 2155 } 2156 2157 return; 2158 } 2159 2160 void SPEFloatingPointRoundException(struct pt_regs *regs) 2161 { 2162 extern int speround_handler(struct pt_regs *regs); 2163 int err; 2164 2165 /* We restore the interrupt state now */ 2166 if (!arch_irq_disabled_regs(regs)) 2167 local_irq_enable(); 2168 2169 preempt_disable(); 2170 if (regs->msr & MSR_SPE) 2171 giveup_spe(current); 2172 preempt_enable(); 2173 2174 regs->nip -= 4; 2175 err = speround_handler(regs); 2176 if (err == 0) { 2177 regs->nip += 4; /* skip emulated instruction */ 2178 emulate_single_step(regs); 2179 return; 2180 } 2181 2182 if (err == -EFAULT) { 2183 /* got an error reading the instruction */ 2184 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2185 } else if (err == -EINVAL) { 2186 /* didn't recognize the instruction */ 2187 printk(KERN_ERR "unrecognized spe instruction " 2188 "in %s at %lx\n", current->comm, regs->nip); 2189 } else { 2190 _exception(SIGFPE, regs, FPE_FLTUNK, regs->nip); 2191 return; 2192 } 2193 } 2194 #endif 2195 2196 /* 2197 * We enter here if we get an unrecoverable exception, that is, one 2198 * that happened at a point where the RI (recoverable interrupt) bit 2199 * in the MSR is 0. This indicates that SRR0/1 are live, and that 2200 * we therefore lost state by taking this exception. 2201 */ 2202 void unrecoverable_exception(struct pt_regs *regs) 2203 { 2204 pr_emerg("Unrecoverable exception %lx at %lx (msr=%lx)\n", 2205 regs->trap, regs->nip, regs->msr); 2206 die("Unrecoverable exception", regs, SIGABRT); 2207 } 2208 NOKPROBE_SYMBOL(unrecoverable_exception); 2209 2210 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x) 2211 /* 2212 * Default handler for a Watchdog exception, 2213 * spins until a reboot occurs 2214 */ 2215 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) 2216 { 2217 /* Generic WatchdogHandler, implement your own */ 2218 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); 2219 return; 2220 } 2221 2222 void WatchdogException(struct pt_regs *regs) 2223 { 2224 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); 2225 WatchdogHandler(regs); 2226 } 2227 #endif 2228 2229 /* 2230 * We enter here if we discover during exception entry that we are 2231 * running in supervisor mode with a userspace value in the stack pointer. 2232 */ 2233 void kernel_bad_stack(struct pt_regs *regs) 2234 { 2235 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", 2236 regs->gpr[1], regs->nip); 2237 die("Bad kernel stack pointer", regs, SIGABRT); 2238 } 2239 NOKPROBE_SYMBOL(kernel_bad_stack); 2240 2241 void __init trap_init(void) 2242 { 2243 } 2244 2245 2246 #ifdef CONFIG_PPC_EMULATED_STATS 2247 2248 #define WARN_EMULATED_SETUP(type) .type = { .name = #type } 2249 2250 struct ppc_emulated ppc_emulated = { 2251 #ifdef CONFIG_ALTIVEC 2252 WARN_EMULATED_SETUP(altivec), 2253 #endif 2254 WARN_EMULATED_SETUP(dcba), 2255 WARN_EMULATED_SETUP(dcbz), 2256 WARN_EMULATED_SETUP(fp_pair), 2257 WARN_EMULATED_SETUP(isel), 2258 WARN_EMULATED_SETUP(mcrxr), 2259 WARN_EMULATED_SETUP(mfpvr), 2260 WARN_EMULATED_SETUP(multiple), 2261 WARN_EMULATED_SETUP(popcntb), 2262 WARN_EMULATED_SETUP(spe), 2263 WARN_EMULATED_SETUP(string), 2264 WARN_EMULATED_SETUP(sync), 2265 WARN_EMULATED_SETUP(unaligned), 2266 #ifdef CONFIG_MATH_EMULATION 2267 WARN_EMULATED_SETUP(math), 2268 #endif 2269 #ifdef CONFIG_VSX 2270 WARN_EMULATED_SETUP(vsx), 2271 #endif 2272 #ifdef CONFIG_PPC64 2273 WARN_EMULATED_SETUP(mfdscr), 2274 WARN_EMULATED_SETUP(mtdscr), 2275 WARN_EMULATED_SETUP(lq_stq), 2276 WARN_EMULATED_SETUP(lxvw4x), 2277 WARN_EMULATED_SETUP(lxvh8x), 2278 WARN_EMULATED_SETUP(lxvd2x), 2279 WARN_EMULATED_SETUP(lxvb16x), 2280 #endif 2281 }; 2282 2283 u32 ppc_warn_emulated; 2284 2285 void ppc_warn_emulated_print(const char *type) 2286 { 2287 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, 2288 type); 2289 } 2290 2291 static int __init ppc_warn_emulated_init(void) 2292 { 2293 struct dentry *dir; 2294 unsigned int i; 2295 struct ppc_emulated_entry *entries = (void *)&ppc_emulated; 2296 2297 dir = debugfs_create_dir("emulated_instructions", 2298 powerpc_debugfs_root); 2299 2300 debugfs_create_u32("do_warn", 0644, dir, &ppc_warn_emulated); 2301 2302 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) 2303 debugfs_create_u32(entries[i].name, 0644, dir, 2304 (u32 *)&entries[i].val.counter); 2305 2306 return 0; 2307 } 2308 2309 device_initcall(ppc_warn_emulated_init); 2310 2311 #endif /* CONFIG_PPC_EMULATED_STATS */ 2312