1 /* 2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 3 * Copyright 2007-2010 Freescale Semiconductor, Inc. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 * 10 * Modified by Cort Dougan (cort@cs.nmt.edu) 11 * and Paul Mackerras (paulus@samba.org) 12 */ 13 14 /* 15 * This file handles the architecture-dependent parts of hardware exceptions 16 */ 17 18 #include <linux/errno.h> 19 #include <linux/sched.h> 20 #include <linux/kernel.h> 21 #include <linux/mm.h> 22 #include <linux/stddef.h> 23 #include <linux/unistd.h> 24 #include <linux/ptrace.h> 25 #include <linux/user.h> 26 #include <linux/interrupt.h> 27 #include <linux/init.h> 28 #include <linux/module.h> 29 #include <linux/prctl.h> 30 #include <linux/delay.h> 31 #include <linux/kprobes.h> 32 #include <linux/kexec.h> 33 #include <linux/backlight.h> 34 #include <linux/bug.h> 35 #include <linux/kdebug.h> 36 #include <linux/debugfs.h> 37 #include <linux/ratelimit.h> 38 #include <linux/context_tracking.h> 39 40 #include <asm/emulated_ops.h> 41 #include <asm/pgtable.h> 42 #include <asm/uaccess.h> 43 #include <asm/io.h> 44 #include <asm/machdep.h> 45 #include <asm/rtas.h> 46 #include <asm/pmc.h> 47 #ifdef CONFIG_PPC32 48 #include <asm/reg.h> 49 #endif 50 #ifdef CONFIG_PMAC_BACKLIGHT 51 #include <asm/backlight.h> 52 #endif 53 #ifdef CONFIG_PPC64 54 #include <asm/firmware.h> 55 #include <asm/processor.h> 56 #endif 57 #include <asm/kexec.h> 58 #include <asm/ppc-opcode.h> 59 #include <asm/rio.h> 60 #include <asm/fadump.h> 61 #include <asm/switch_to.h> 62 #include <asm/tm.h> 63 #include <asm/debug.h> 64 65 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) 66 int (*__debugger)(struct pt_regs *regs) __read_mostly; 67 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; 68 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; 69 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; 70 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; 71 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly; 72 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; 73 74 EXPORT_SYMBOL(__debugger); 75 EXPORT_SYMBOL(__debugger_ipi); 76 EXPORT_SYMBOL(__debugger_bpt); 77 EXPORT_SYMBOL(__debugger_sstep); 78 EXPORT_SYMBOL(__debugger_iabr_match); 79 EXPORT_SYMBOL(__debugger_break_match); 80 EXPORT_SYMBOL(__debugger_fault_handler); 81 #endif 82 83 /* Transactional Memory trap debug */ 84 #ifdef TM_DEBUG_SW 85 #define TM_DEBUG(x...) printk(KERN_INFO x) 86 #else 87 #define TM_DEBUG(x...) do { } while(0) 88 #endif 89 90 /* 91 * Trap & Exception support 92 */ 93 94 #ifdef CONFIG_PMAC_BACKLIGHT 95 static void pmac_backlight_unblank(void) 96 { 97 mutex_lock(&pmac_backlight_mutex); 98 if (pmac_backlight) { 99 struct backlight_properties *props; 100 101 props = &pmac_backlight->props; 102 props->brightness = props->max_brightness; 103 props->power = FB_BLANK_UNBLANK; 104 backlight_update_status(pmac_backlight); 105 } 106 mutex_unlock(&pmac_backlight_mutex); 107 } 108 #else 109 static inline void pmac_backlight_unblank(void) { } 110 #endif 111 112 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; 113 static int die_owner = -1; 114 static unsigned int die_nest_count; 115 static int die_counter; 116 117 static unsigned __kprobes long oops_begin(struct pt_regs *regs) 118 { 119 int cpu; 120 unsigned long flags; 121 122 if (debugger(regs)) 123 return 1; 124 125 oops_enter(); 126 127 /* racy, but better than risking deadlock. */ 128 raw_local_irq_save(flags); 129 cpu = smp_processor_id(); 130 if (!arch_spin_trylock(&die_lock)) { 131 if (cpu == die_owner) 132 /* nested oops. should stop eventually */; 133 else 134 arch_spin_lock(&die_lock); 135 } 136 die_nest_count++; 137 die_owner = cpu; 138 console_verbose(); 139 bust_spinlocks(1); 140 if (machine_is(powermac)) 141 pmac_backlight_unblank(); 142 return flags; 143 } 144 145 static void __kprobes oops_end(unsigned long flags, struct pt_regs *regs, 146 int signr) 147 { 148 bust_spinlocks(0); 149 die_owner = -1; 150 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 151 die_nest_count--; 152 oops_exit(); 153 printk("\n"); 154 if (!die_nest_count) 155 /* Nest count reaches zero, release the lock. */ 156 arch_spin_unlock(&die_lock); 157 raw_local_irq_restore(flags); 158 159 crash_fadump(regs, "die oops"); 160 161 /* 162 * A system reset (0x100) is a request to dump, so we always send 163 * it through the crashdump code. 164 */ 165 if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) { 166 crash_kexec(regs); 167 168 /* 169 * We aren't the primary crash CPU. We need to send it 170 * to a holding pattern to avoid it ending up in the panic 171 * code. 172 */ 173 crash_kexec_secondary(regs); 174 } 175 176 if (!signr) 177 return; 178 179 /* 180 * While our oops output is serialised by a spinlock, output 181 * from panic() called below can race and corrupt it. If we 182 * know we are going to panic, delay for 1 second so we have a 183 * chance to get clean backtraces from all CPUs that are oopsing. 184 */ 185 if (in_interrupt() || panic_on_oops || !current->pid || 186 is_global_init(current)) { 187 mdelay(MSEC_PER_SEC); 188 } 189 190 if (in_interrupt()) 191 panic("Fatal exception in interrupt"); 192 if (panic_on_oops) 193 panic("Fatal exception"); 194 do_exit(signr); 195 } 196 197 static int __kprobes __die(const char *str, struct pt_regs *regs, long err) 198 { 199 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); 200 #ifdef CONFIG_PREEMPT 201 printk("PREEMPT "); 202 #endif 203 #ifdef CONFIG_SMP 204 printk("SMP NR_CPUS=%d ", NR_CPUS); 205 #endif 206 #ifdef CONFIG_DEBUG_PAGEALLOC 207 printk("DEBUG_PAGEALLOC "); 208 #endif 209 #ifdef CONFIG_NUMA 210 printk("NUMA "); 211 #endif 212 printk("%s\n", ppc_md.name ? ppc_md.name : ""); 213 214 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP) 215 return 1; 216 217 print_modules(); 218 show_regs(regs); 219 220 return 0; 221 } 222 223 void die(const char *str, struct pt_regs *regs, long err) 224 { 225 unsigned long flags = oops_begin(regs); 226 227 if (__die(str, regs, err)) 228 err = 0; 229 oops_end(flags, regs, err); 230 } 231 232 void user_single_step_siginfo(struct task_struct *tsk, 233 struct pt_regs *regs, siginfo_t *info) 234 { 235 memset(info, 0, sizeof(*info)); 236 info->si_signo = SIGTRAP; 237 info->si_code = TRAP_TRACE; 238 info->si_addr = (void __user *)regs->nip; 239 } 240 241 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) 242 { 243 siginfo_t info; 244 const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \ 245 "at %08lx nip %08lx lr %08lx code %x\n"; 246 const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \ 247 "at %016lx nip %016lx lr %016lx code %x\n"; 248 249 if (!user_mode(regs)) { 250 die("Exception in kernel mode", regs, signr); 251 return; 252 } 253 254 if (show_unhandled_signals && unhandled_signal(current, signr)) { 255 printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32, 256 current->comm, current->pid, signr, 257 addr, regs->nip, regs->link, code); 258 } 259 260 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs)) 261 local_irq_enable(); 262 263 current->thread.trap_nr = code; 264 memset(&info, 0, sizeof(info)); 265 info.si_signo = signr; 266 info.si_code = code; 267 info.si_addr = (void __user *) addr; 268 force_sig_info(signr, &info, current); 269 } 270 271 #ifdef CONFIG_PPC64 272 void system_reset_exception(struct pt_regs *regs) 273 { 274 /* See if any machine dependent calls */ 275 if (ppc_md.system_reset_exception) { 276 if (ppc_md.system_reset_exception(regs)) 277 return; 278 } 279 280 die("System Reset", regs, SIGABRT); 281 282 /* Must die if the interrupt is not recoverable */ 283 if (!(regs->msr & MSR_RI)) 284 panic("Unrecoverable System Reset"); 285 286 /* What should we do here? We could issue a shutdown or hard reset. */ 287 } 288 #endif 289 290 /* 291 * I/O accesses can cause machine checks on powermacs. 292 * Check if the NIP corresponds to the address of a sync 293 * instruction for which there is an entry in the exception 294 * table. 295 * Note that the 601 only takes a machine check on TEA 296 * (transfer error ack) signal assertion, and does not 297 * set any of the top 16 bits of SRR1. 298 * -- paulus. 299 */ 300 static inline int check_io_access(struct pt_regs *regs) 301 { 302 #ifdef CONFIG_PPC32 303 unsigned long msr = regs->msr; 304 const struct exception_table_entry *entry; 305 unsigned int *nip = (unsigned int *)regs->nip; 306 307 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) 308 && (entry = search_exception_tables(regs->nip)) != NULL) { 309 /* 310 * Check that it's a sync instruction, or somewhere 311 * in the twi; isync; nop sequence that inb/inw/inl uses. 312 * As the address is in the exception table 313 * we should be able to read the instr there. 314 * For the debug message, we look at the preceding 315 * load or store. 316 */ 317 if (*nip == 0x60000000) /* nop */ 318 nip -= 2; 319 else if (*nip == 0x4c00012c) /* isync */ 320 --nip; 321 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) { 322 /* sync or twi */ 323 unsigned int rb; 324 325 --nip; 326 rb = (*nip >> 11) & 0x1f; 327 printk(KERN_DEBUG "%s bad port %lx at %p\n", 328 (*nip & 0x100)? "OUT to": "IN from", 329 regs->gpr[rb] - _IO_BASE, nip); 330 regs->msr |= MSR_RI; 331 regs->nip = entry->fixup; 332 return 1; 333 } 334 } 335 #endif /* CONFIG_PPC32 */ 336 return 0; 337 } 338 339 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 340 /* On 4xx, the reason for the machine check or program exception 341 is in the ESR. */ 342 #define get_reason(regs) ((regs)->dsisr) 343 #ifndef CONFIG_FSL_BOOKE 344 #define get_mc_reason(regs) ((regs)->dsisr) 345 #else 346 #define get_mc_reason(regs) (mfspr(SPRN_MCSR)) 347 #endif 348 #define REASON_FP ESR_FP 349 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) 350 #define REASON_PRIVILEGED ESR_PPR 351 #define REASON_TRAP ESR_PTR 352 353 /* single-step stuff */ 354 #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) 355 #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) 356 357 #else 358 /* On non-4xx, the reason for the machine check or program 359 exception is in the MSR. */ 360 #define get_reason(regs) ((regs)->msr) 361 #define get_mc_reason(regs) ((regs)->msr) 362 #define REASON_TM 0x200000 363 #define REASON_FP 0x100000 364 #define REASON_ILLEGAL 0x80000 365 #define REASON_PRIVILEGED 0x40000 366 #define REASON_TRAP 0x20000 367 368 #define single_stepping(regs) ((regs)->msr & MSR_SE) 369 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) 370 #endif 371 372 #if defined(CONFIG_4xx) 373 int machine_check_4xx(struct pt_regs *regs) 374 { 375 unsigned long reason = get_mc_reason(regs); 376 377 if (reason & ESR_IMCP) { 378 printk("Instruction"); 379 mtspr(SPRN_ESR, reason & ~ESR_IMCP); 380 } else 381 printk("Data"); 382 printk(" machine check in kernel mode.\n"); 383 384 return 0; 385 } 386 387 int machine_check_440A(struct pt_regs *regs) 388 { 389 unsigned long reason = get_mc_reason(regs); 390 391 printk("Machine check in kernel mode.\n"); 392 if (reason & ESR_IMCP){ 393 printk("Instruction Synchronous Machine Check exception\n"); 394 mtspr(SPRN_ESR, reason & ~ESR_IMCP); 395 } 396 else { 397 u32 mcsr = mfspr(SPRN_MCSR); 398 if (mcsr & MCSR_IB) 399 printk("Instruction Read PLB Error\n"); 400 if (mcsr & MCSR_DRB) 401 printk("Data Read PLB Error\n"); 402 if (mcsr & MCSR_DWB) 403 printk("Data Write PLB Error\n"); 404 if (mcsr & MCSR_TLBP) 405 printk("TLB Parity Error\n"); 406 if (mcsr & MCSR_ICP){ 407 flush_instruction_cache(); 408 printk("I-Cache Parity Error\n"); 409 } 410 if (mcsr & MCSR_DCSP) 411 printk("D-Cache Search Parity Error\n"); 412 if (mcsr & MCSR_DCFP) 413 printk("D-Cache Flush Parity Error\n"); 414 if (mcsr & MCSR_IMPE) 415 printk("Machine Check exception is imprecise\n"); 416 417 /* Clear MCSR */ 418 mtspr(SPRN_MCSR, mcsr); 419 } 420 return 0; 421 } 422 423 int machine_check_47x(struct pt_regs *regs) 424 { 425 unsigned long reason = get_mc_reason(regs); 426 u32 mcsr; 427 428 printk(KERN_ERR "Machine check in kernel mode.\n"); 429 if (reason & ESR_IMCP) { 430 printk(KERN_ERR 431 "Instruction Synchronous Machine Check exception\n"); 432 mtspr(SPRN_ESR, reason & ~ESR_IMCP); 433 return 0; 434 } 435 mcsr = mfspr(SPRN_MCSR); 436 if (mcsr & MCSR_IB) 437 printk(KERN_ERR "Instruction Read PLB Error\n"); 438 if (mcsr & MCSR_DRB) 439 printk(KERN_ERR "Data Read PLB Error\n"); 440 if (mcsr & MCSR_DWB) 441 printk(KERN_ERR "Data Write PLB Error\n"); 442 if (mcsr & MCSR_TLBP) 443 printk(KERN_ERR "TLB Parity Error\n"); 444 if (mcsr & MCSR_ICP) { 445 flush_instruction_cache(); 446 printk(KERN_ERR "I-Cache Parity Error\n"); 447 } 448 if (mcsr & MCSR_DCSP) 449 printk(KERN_ERR "D-Cache Search Parity Error\n"); 450 if (mcsr & PPC47x_MCSR_GPR) 451 printk(KERN_ERR "GPR Parity Error\n"); 452 if (mcsr & PPC47x_MCSR_FPR) 453 printk(KERN_ERR "FPR Parity Error\n"); 454 if (mcsr & PPC47x_MCSR_IPR) 455 printk(KERN_ERR "Machine Check exception is imprecise\n"); 456 457 /* Clear MCSR */ 458 mtspr(SPRN_MCSR, mcsr); 459 460 return 0; 461 } 462 #elif defined(CONFIG_E500) 463 int machine_check_e500mc(struct pt_regs *regs) 464 { 465 unsigned long mcsr = mfspr(SPRN_MCSR); 466 unsigned long reason = mcsr; 467 int recoverable = 1; 468 469 if (reason & MCSR_LD) { 470 recoverable = fsl_rio_mcheck_exception(regs); 471 if (recoverable == 1) 472 goto silent_out; 473 } 474 475 printk("Machine check in kernel mode.\n"); 476 printk("Caused by (from MCSR=%lx): ", reason); 477 478 if (reason & MCSR_MCP) 479 printk("Machine Check Signal\n"); 480 481 if (reason & MCSR_ICPERR) { 482 printk("Instruction Cache Parity Error\n"); 483 484 /* 485 * This is recoverable by invalidating the i-cache. 486 */ 487 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); 488 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) 489 ; 490 491 /* 492 * This will generally be accompanied by an instruction 493 * fetch error report -- only treat MCSR_IF as fatal 494 * if it wasn't due to an L1 parity error. 495 */ 496 reason &= ~MCSR_IF; 497 } 498 499 if (reason & MCSR_DCPERR_MC) { 500 printk("Data Cache Parity Error\n"); 501 502 /* 503 * In write shadow mode we auto-recover from the error, but it 504 * may still get logged and cause a machine check. We should 505 * only treat the non-write shadow case as non-recoverable. 506 */ 507 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) 508 recoverable = 0; 509 } 510 511 if (reason & MCSR_L2MMU_MHIT) { 512 printk("Hit on multiple TLB entries\n"); 513 recoverable = 0; 514 } 515 516 if (reason & MCSR_NMI) 517 printk("Non-maskable interrupt\n"); 518 519 if (reason & MCSR_IF) { 520 printk("Instruction Fetch Error Report\n"); 521 recoverable = 0; 522 } 523 524 if (reason & MCSR_LD) { 525 printk("Load Error Report\n"); 526 recoverable = 0; 527 } 528 529 if (reason & MCSR_ST) { 530 printk("Store Error Report\n"); 531 recoverable = 0; 532 } 533 534 if (reason & MCSR_LDG) { 535 printk("Guarded Load Error Report\n"); 536 recoverable = 0; 537 } 538 539 if (reason & MCSR_TLBSYNC) 540 printk("Simultaneous tlbsync operations\n"); 541 542 if (reason & MCSR_BSL2_ERR) { 543 printk("Level 2 Cache Error\n"); 544 recoverable = 0; 545 } 546 547 if (reason & MCSR_MAV) { 548 u64 addr; 549 550 addr = mfspr(SPRN_MCAR); 551 addr |= (u64)mfspr(SPRN_MCARU) << 32; 552 553 printk("Machine Check %s Address: %#llx\n", 554 reason & MCSR_MEA ? "Effective" : "Physical", addr); 555 } 556 557 silent_out: 558 mtspr(SPRN_MCSR, mcsr); 559 return mfspr(SPRN_MCSR) == 0 && recoverable; 560 } 561 562 int machine_check_e500(struct pt_regs *regs) 563 { 564 unsigned long reason = get_mc_reason(regs); 565 566 if (reason & MCSR_BUS_RBERR) { 567 if (fsl_rio_mcheck_exception(regs)) 568 return 1; 569 } 570 571 printk("Machine check in kernel mode.\n"); 572 printk("Caused by (from MCSR=%lx): ", reason); 573 574 if (reason & MCSR_MCP) 575 printk("Machine Check Signal\n"); 576 if (reason & MCSR_ICPERR) 577 printk("Instruction Cache Parity Error\n"); 578 if (reason & MCSR_DCP_PERR) 579 printk("Data Cache Push Parity Error\n"); 580 if (reason & MCSR_DCPERR) 581 printk("Data Cache Parity Error\n"); 582 if (reason & MCSR_BUS_IAERR) 583 printk("Bus - Instruction Address Error\n"); 584 if (reason & MCSR_BUS_RAERR) 585 printk("Bus - Read Address Error\n"); 586 if (reason & MCSR_BUS_WAERR) 587 printk("Bus - Write Address Error\n"); 588 if (reason & MCSR_BUS_IBERR) 589 printk("Bus - Instruction Data Error\n"); 590 if (reason & MCSR_BUS_RBERR) 591 printk("Bus - Read Data Bus Error\n"); 592 if (reason & MCSR_BUS_WBERR) 593 printk("Bus - Read Data Bus Error\n"); 594 if (reason & MCSR_BUS_IPERR) 595 printk("Bus - Instruction Parity Error\n"); 596 if (reason & MCSR_BUS_RPERR) 597 printk("Bus - Read Parity Error\n"); 598 599 return 0; 600 } 601 602 int machine_check_generic(struct pt_regs *regs) 603 { 604 return 0; 605 } 606 #elif defined(CONFIG_E200) 607 int machine_check_e200(struct pt_regs *regs) 608 { 609 unsigned long reason = get_mc_reason(regs); 610 611 printk("Machine check in kernel mode.\n"); 612 printk("Caused by (from MCSR=%lx): ", reason); 613 614 if (reason & MCSR_MCP) 615 printk("Machine Check Signal\n"); 616 if (reason & MCSR_CP_PERR) 617 printk("Cache Push Parity Error\n"); 618 if (reason & MCSR_CPERR) 619 printk("Cache Parity Error\n"); 620 if (reason & MCSR_EXCP_ERR) 621 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); 622 if (reason & MCSR_BUS_IRERR) 623 printk("Bus - Read Bus Error on instruction fetch\n"); 624 if (reason & MCSR_BUS_DRERR) 625 printk("Bus - Read Bus Error on data load\n"); 626 if (reason & MCSR_BUS_WRERR) 627 printk("Bus - Write Bus Error on buffered store or cache line push\n"); 628 629 return 0; 630 } 631 #else 632 int machine_check_generic(struct pt_regs *regs) 633 { 634 unsigned long reason = get_mc_reason(regs); 635 636 printk("Machine check in kernel mode.\n"); 637 printk("Caused by (from SRR1=%lx): ", reason); 638 switch (reason & 0x601F0000) { 639 case 0x80000: 640 printk("Machine check signal\n"); 641 break; 642 case 0: /* for 601 */ 643 case 0x40000: 644 case 0x140000: /* 7450 MSS error and TEA */ 645 printk("Transfer error ack signal\n"); 646 break; 647 case 0x20000: 648 printk("Data parity error signal\n"); 649 break; 650 case 0x10000: 651 printk("Address parity error signal\n"); 652 break; 653 case 0x20000000: 654 printk("L1 Data Cache error\n"); 655 break; 656 case 0x40000000: 657 printk("L1 Instruction Cache error\n"); 658 break; 659 case 0x00100000: 660 printk("L2 data cache parity error\n"); 661 break; 662 default: 663 printk("Unknown values in msr\n"); 664 } 665 return 0; 666 } 667 #endif /* everything else */ 668 669 void machine_check_exception(struct pt_regs *regs) 670 { 671 enum ctx_state prev_state = exception_enter(); 672 int recover = 0; 673 674 __get_cpu_var(irq_stat).mce_exceptions++; 675 676 /* See if any machine dependent calls. In theory, we would want 677 * to call the CPU first, and call the ppc_md. one if the CPU 678 * one returns a positive number. However there is existing code 679 * that assumes the board gets a first chance, so let's keep it 680 * that way for now and fix things later. --BenH. 681 */ 682 if (ppc_md.machine_check_exception) 683 recover = ppc_md.machine_check_exception(regs); 684 else if (cur_cpu_spec->machine_check) 685 recover = cur_cpu_spec->machine_check(regs); 686 687 if (recover > 0) 688 goto bail; 689 690 #if defined(CONFIG_8xx) && defined(CONFIG_PCI) 691 /* the qspan pci read routines can cause machine checks -- Cort 692 * 693 * yuck !!! that totally needs to go away ! There are better ways 694 * to deal with that than having a wart in the mcheck handler. 695 * -- BenH 696 */ 697 bad_page_fault(regs, regs->dar, SIGBUS); 698 goto bail; 699 #endif 700 701 if (debugger_fault_handler(regs)) 702 goto bail; 703 704 if (check_io_access(regs)) 705 goto bail; 706 707 die("Machine check", regs, SIGBUS); 708 709 /* Must die if the interrupt is not recoverable */ 710 if (!(regs->msr & MSR_RI)) 711 panic("Unrecoverable Machine check"); 712 713 bail: 714 exception_exit(prev_state); 715 } 716 717 void SMIException(struct pt_regs *regs) 718 { 719 die("System Management Interrupt", regs, SIGABRT); 720 } 721 722 void unknown_exception(struct pt_regs *regs) 723 { 724 enum ctx_state prev_state = exception_enter(); 725 726 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 727 regs->nip, regs->msr, regs->trap); 728 729 _exception(SIGTRAP, regs, 0, 0); 730 731 exception_exit(prev_state); 732 } 733 734 void instruction_breakpoint_exception(struct pt_regs *regs) 735 { 736 enum ctx_state prev_state = exception_enter(); 737 738 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, 739 5, SIGTRAP) == NOTIFY_STOP) 740 goto bail; 741 if (debugger_iabr_match(regs)) 742 goto bail; 743 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 744 745 bail: 746 exception_exit(prev_state); 747 } 748 749 void RunModeException(struct pt_regs *regs) 750 { 751 _exception(SIGTRAP, regs, 0, 0); 752 } 753 754 void __kprobes single_step_exception(struct pt_regs *regs) 755 { 756 enum ctx_state prev_state = exception_enter(); 757 758 clear_single_step(regs); 759 760 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 761 5, SIGTRAP) == NOTIFY_STOP) 762 goto bail; 763 if (debugger_sstep(regs)) 764 goto bail; 765 766 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 767 768 bail: 769 exception_exit(prev_state); 770 } 771 772 /* 773 * After we have successfully emulated an instruction, we have to 774 * check if the instruction was being single-stepped, and if so, 775 * pretend we got a single-step exception. This was pointed out 776 * by Kumar Gala. -- paulus 777 */ 778 static void emulate_single_step(struct pt_regs *regs) 779 { 780 if (single_stepping(regs)) 781 single_step_exception(regs); 782 } 783 784 static inline int __parse_fpscr(unsigned long fpscr) 785 { 786 int ret = 0; 787 788 /* Invalid operation */ 789 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) 790 ret = FPE_FLTINV; 791 792 /* Overflow */ 793 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) 794 ret = FPE_FLTOVF; 795 796 /* Underflow */ 797 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) 798 ret = FPE_FLTUND; 799 800 /* Divide by zero */ 801 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) 802 ret = FPE_FLTDIV; 803 804 /* Inexact result */ 805 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) 806 ret = FPE_FLTRES; 807 808 return ret; 809 } 810 811 static void parse_fpe(struct pt_regs *regs) 812 { 813 int code = 0; 814 815 flush_fp_to_thread(current); 816 817 code = __parse_fpscr(current->thread.fpscr.val); 818 819 _exception(SIGFPE, regs, code, regs->nip); 820 } 821 822 /* 823 * Illegal instruction emulation support. Originally written to 824 * provide the PVR to user applications using the mfspr rd, PVR. 825 * Return non-zero if we can't emulate, or -EFAULT if the associated 826 * memory access caused an access fault. Return zero on success. 827 * 828 * There are a couple of ways to do this, either "decode" the instruction 829 * or directly match lots of bits. In this case, matching lots of 830 * bits is faster and easier. 831 * 832 */ 833 static int emulate_string_inst(struct pt_regs *regs, u32 instword) 834 { 835 u8 rT = (instword >> 21) & 0x1f; 836 u8 rA = (instword >> 16) & 0x1f; 837 u8 NB_RB = (instword >> 11) & 0x1f; 838 u32 num_bytes; 839 unsigned long EA; 840 int pos = 0; 841 842 /* Early out if we are an invalid form of lswx */ 843 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) 844 if ((rT == rA) || (rT == NB_RB)) 845 return -EINVAL; 846 847 EA = (rA == 0) ? 0 : regs->gpr[rA]; 848 849 switch (instword & PPC_INST_STRING_MASK) { 850 case PPC_INST_LSWX: 851 case PPC_INST_STSWX: 852 EA += NB_RB; 853 num_bytes = regs->xer & 0x7f; 854 break; 855 case PPC_INST_LSWI: 856 case PPC_INST_STSWI: 857 num_bytes = (NB_RB == 0) ? 32 : NB_RB; 858 break; 859 default: 860 return -EINVAL; 861 } 862 863 while (num_bytes != 0) 864 { 865 u8 val; 866 u32 shift = 8 * (3 - (pos & 0x3)); 867 868 switch ((instword & PPC_INST_STRING_MASK)) { 869 case PPC_INST_LSWX: 870 case PPC_INST_LSWI: 871 if (get_user(val, (u8 __user *)EA)) 872 return -EFAULT; 873 /* first time updating this reg, 874 * zero it out */ 875 if (pos == 0) 876 regs->gpr[rT] = 0; 877 regs->gpr[rT] |= val << shift; 878 break; 879 case PPC_INST_STSWI: 880 case PPC_INST_STSWX: 881 val = regs->gpr[rT] >> shift; 882 if (put_user(val, (u8 __user *)EA)) 883 return -EFAULT; 884 break; 885 } 886 /* move EA to next address */ 887 EA += 1; 888 num_bytes--; 889 890 /* manage our position within the register */ 891 if (++pos == 4) { 892 pos = 0; 893 if (++rT == 32) 894 rT = 0; 895 } 896 } 897 898 return 0; 899 } 900 901 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) 902 { 903 u32 ra,rs; 904 unsigned long tmp; 905 906 ra = (instword >> 16) & 0x1f; 907 rs = (instword >> 21) & 0x1f; 908 909 tmp = regs->gpr[rs]; 910 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); 911 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); 912 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; 913 regs->gpr[ra] = tmp; 914 915 return 0; 916 } 917 918 static int emulate_isel(struct pt_regs *regs, u32 instword) 919 { 920 u8 rT = (instword >> 21) & 0x1f; 921 u8 rA = (instword >> 16) & 0x1f; 922 u8 rB = (instword >> 11) & 0x1f; 923 u8 BC = (instword >> 6) & 0x1f; 924 u8 bit; 925 unsigned long tmp; 926 927 tmp = (rA == 0) ? 0 : regs->gpr[rA]; 928 bit = (regs->ccr >> (31 - BC)) & 0x1; 929 930 regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; 931 932 return 0; 933 } 934 935 static int emulate_instruction(struct pt_regs *regs) 936 { 937 u32 instword; 938 u32 rd; 939 940 if (!user_mode(regs) || (regs->msr & MSR_LE)) 941 return -EINVAL; 942 CHECK_FULL_REGS(regs); 943 944 if (get_user(instword, (u32 __user *)(regs->nip))) 945 return -EFAULT; 946 947 /* Emulate the mfspr rD, PVR. */ 948 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { 949 PPC_WARN_EMULATED(mfpvr, regs); 950 rd = (instword >> 21) & 0x1f; 951 regs->gpr[rd] = mfspr(SPRN_PVR); 952 return 0; 953 } 954 955 /* Emulating the dcba insn is just a no-op. */ 956 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { 957 PPC_WARN_EMULATED(dcba, regs); 958 return 0; 959 } 960 961 /* Emulate the mcrxr insn. */ 962 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { 963 int shift = (instword >> 21) & 0x1c; 964 unsigned long msk = 0xf0000000UL >> shift; 965 966 PPC_WARN_EMULATED(mcrxr, regs); 967 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); 968 regs->xer &= ~0xf0000000UL; 969 return 0; 970 } 971 972 /* Emulate load/store string insn. */ 973 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { 974 PPC_WARN_EMULATED(string, regs); 975 return emulate_string_inst(regs, instword); 976 } 977 978 /* Emulate the popcntb (Population Count Bytes) instruction. */ 979 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { 980 PPC_WARN_EMULATED(popcntb, regs); 981 return emulate_popcntb_inst(regs, instword); 982 } 983 984 /* Emulate isel (Integer Select) instruction */ 985 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { 986 PPC_WARN_EMULATED(isel, regs); 987 return emulate_isel(regs, instword); 988 } 989 990 #ifdef CONFIG_PPC64 991 /* Emulate the mfspr rD, DSCR. */ 992 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) == 993 PPC_INST_MFSPR_DSCR_USER) || 994 ((instword & PPC_INST_MFSPR_DSCR_MASK) == 995 PPC_INST_MFSPR_DSCR)) && 996 cpu_has_feature(CPU_FTR_DSCR)) { 997 PPC_WARN_EMULATED(mfdscr, regs); 998 rd = (instword >> 21) & 0x1f; 999 regs->gpr[rd] = mfspr(SPRN_DSCR); 1000 return 0; 1001 } 1002 /* Emulate the mtspr DSCR, rD. */ 1003 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) == 1004 PPC_INST_MTSPR_DSCR_USER) || 1005 ((instword & PPC_INST_MTSPR_DSCR_MASK) == 1006 PPC_INST_MTSPR_DSCR)) && 1007 cpu_has_feature(CPU_FTR_DSCR)) { 1008 PPC_WARN_EMULATED(mtdscr, regs); 1009 rd = (instword >> 21) & 0x1f; 1010 current->thread.dscr = regs->gpr[rd]; 1011 current->thread.dscr_inherit = 1; 1012 mtspr(SPRN_DSCR, current->thread.dscr); 1013 return 0; 1014 } 1015 #endif 1016 1017 return -EINVAL; 1018 } 1019 1020 int is_valid_bugaddr(unsigned long addr) 1021 { 1022 return is_kernel_addr(addr); 1023 } 1024 1025 void __kprobes program_check_exception(struct pt_regs *regs) 1026 { 1027 enum ctx_state prev_state = exception_enter(); 1028 unsigned int reason = get_reason(regs); 1029 extern int do_mathemu(struct pt_regs *regs); 1030 1031 /* We can now get here via a FP Unavailable exception if the core 1032 * has no FPU, in that case the reason flags will be 0 */ 1033 1034 if (reason & REASON_FP) { 1035 /* IEEE FP exception */ 1036 parse_fpe(regs); 1037 goto bail; 1038 } 1039 if (reason & REASON_TRAP) { 1040 /* Debugger is first in line to stop recursive faults in 1041 * rcu_lock, notify_die, or atomic_notifier_call_chain */ 1042 if (debugger_bpt(regs)) 1043 goto bail; 1044 1045 /* trap exception */ 1046 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) 1047 == NOTIFY_STOP) 1048 goto bail; 1049 1050 if (!(regs->msr & MSR_PR) && /* not user-mode */ 1051 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { 1052 regs->nip += 4; 1053 goto bail; 1054 } 1055 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1056 goto bail; 1057 } 1058 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1059 if (reason & REASON_TM) { 1060 /* This is a TM "Bad Thing Exception" program check. 1061 * This occurs when: 1062 * - An rfid/hrfid/mtmsrd attempts to cause an illegal 1063 * transition in TM states. 1064 * - A trechkpt is attempted when transactional. 1065 * - A treclaim is attempted when non transactional. 1066 * - A tend is illegally attempted. 1067 * - writing a TM SPR when transactional. 1068 */ 1069 if (!user_mode(regs) && 1070 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { 1071 regs->nip += 4; 1072 goto bail; 1073 } 1074 /* If usermode caused this, it's done something illegal and 1075 * gets a SIGILL slap on the wrist. We call it an illegal 1076 * operand to distinguish from the instruction just being bad 1077 * (e.g. executing a 'tend' on a CPU without TM!); it's an 1078 * illegal /placement/ of a valid instruction. 1079 */ 1080 if (user_mode(regs)) { 1081 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip); 1082 goto bail; 1083 } else { 1084 printk(KERN_EMERG "Unexpected TM Bad Thing exception " 1085 "at %lx (msr 0x%x)\n", regs->nip, reason); 1086 die("Unrecoverable exception", regs, SIGABRT); 1087 } 1088 } 1089 #endif 1090 1091 /* We restore the interrupt state now */ 1092 if (!arch_irq_disabled_regs(regs)) 1093 local_irq_enable(); 1094 1095 #ifdef CONFIG_MATH_EMULATION 1096 /* (reason & REASON_ILLEGAL) would be the obvious thing here, 1097 * but there seems to be a hardware bug on the 405GP (RevD) 1098 * that means ESR is sometimes set incorrectly - either to 1099 * ESR_DST (!?) or 0. In the process of chasing this with the 1100 * hardware people - not sure if it can happen on any illegal 1101 * instruction or only on FP instructions, whether there is a 1102 * pattern to occurrences etc. -dgibson 31/Mar/2003 */ 1103 switch (do_mathemu(regs)) { 1104 case 0: 1105 emulate_single_step(regs); 1106 goto bail; 1107 case 1: { 1108 int code = 0; 1109 code = __parse_fpscr(current->thread.fpscr.val); 1110 _exception(SIGFPE, regs, code, regs->nip); 1111 goto bail; 1112 } 1113 case -EFAULT: 1114 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1115 goto bail; 1116 } 1117 /* fall through on any other errors */ 1118 #endif /* CONFIG_MATH_EMULATION */ 1119 1120 /* Try to emulate it if we should. */ 1121 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { 1122 switch (emulate_instruction(regs)) { 1123 case 0: 1124 regs->nip += 4; 1125 emulate_single_step(regs); 1126 goto bail; 1127 case -EFAULT: 1128 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1129 goto bail; 1130 } 1131 } 1132 1133 if (reason & REASON_PRIVILEGED) 1134 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 1135 else 1136 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1137 1138 bail: 1139 exception_exit(prev_state); 1140 } 1141 1142 void alignment_exception(struct pt_regs *regs) 1143 { 1144 enum ctx_state prev_state = exception_enter(); 1145 int sig, code, fixed = 0; 1146 1147 /* We restore the interrupt state now */ 1148 if (!arch_irq_disabled_regs(regs)) 1149 local_irq_enable(); 1150 1151 /* we don't implement logging of alignment exceptions */ 1152 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) 1153 fixed = fix_alignment(regs); 1154 1155 if (fixed == 1) { 1156 regs->nip += 4; /* skip over emulated instruction */ 1157 emulate_single_step(regs); 1158 goto bail; 1159 } 1160 1161 /* Operand address was bad */ 1162 if (fixed == -EFAULT) { 1163 sig = SIGSEGV; 1164 code = SEGV_ACCERR; 1165 } else { 1166 sig = SIGBUS; 1167 code = BUS_ADRALN; 1168 } 1169 if (user_mode(regs)) 1170 _exception(sig, regs, code, regs->dar); 1171 else 1172 bad_page_fault(regs, regs->dar, sig); 1173 1174 bail: 1175 exception_exit(prev_state); 1176 } 1177 1178 void StackOverflow(struct pt_regs *regs) 1179 { 1180 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", 1181 current, regs->gpr[1]); 1182 debugger(regs); 1183 show_regs(regs); 1184 panic("kernel stack overflow"); 1185 } 1186 1187 void nonrecoverable_exception(struct pt_regs *regs) 1188 { 1189 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", 1190 regs->nip, regs->msr); 1191 debugger(regs); 1192 die("nonrecoverable exception", regs, SIGKILL); 1193 } 1194 1195 void trace_syscall(struct pt_regs *regs) 1196 { 1197 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", 1198 current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0], 1199 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); 1200 } 1201 1202 void kernel_fp_unavailable_exception(struct pt_regs *regs) 1203 { 1204 enum ctx_state prev_state = exception_enter(); 1205 1206 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " 1207 "%lx at %lx\n", regs->trap, regs->nip); 1208 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); 1209 1210 exception_exit(prev_state); 1211 } 1212 1213 void altivec_unavailable_exception(struct pt_regs *regs) 1214 { 1215 enum ctx_state prev_state = exception_enter(); 1216 1217 if (user_mode(regs)) { 1218 /* A user program has executed an altivec instruction, 1219 but this kernel doesn't support altivec. */ 1220 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1221 goto bail; 1222 } 1223 1224 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " 1225 "%lx at %lx\n", regs->trap, regs->nip); 1226 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); 1227 1228 bail: 1229 exception_exit(prev_state); 1230 } 1231 1232 void vsx_unavailable_exception(struct pt_regs *regs) 1233 { 1234 if (user_mode(regs)) { 1235 /* A user program has executed an vsx instruction, 1236 but this kernel doesn't support vsx. */ 1237 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1238 return; 1239 } 1240 1241 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " 1242 "%lx at %lx\n", regs->trap, regs->nip); 1243 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); 1244 } 1245 1246 void tm_unavailable_exception(struct pt_regs *regs) 1247 { 1248 /* We restore the interrupt state now */ 1249 if (!arch_irq_disabled_regs(regs)) 1250 local_irq_enable(); 1251 1252 /* Currently we never expect a TMU exception. Catch 1253 * this and kill the process! 1254 */ 1255 printk(KERN_EMERG "Unexpected TM unavailable exception at %lx " 1256 "(msr %lx)\n", 1257 regs->nip, regs->msr); 1258 1259 if (user_mode(regs)) { 1260 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1261 return; 1262 } 1263 1264 die("Unexpected TM unavailable exception", regs, SIGABRT); 1265 } 1266 1267 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1268 1269 extern void do_load_up_fpu(struct pt_regs *regs); 1270 1271 void fp_unavailable_tm(struct pt_regs *regs) 1272 { 1273 /* Note: This does not handle any kind of FP laziness. */ 1274 1275 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n", 1276 regs->nip, regs->msr); 1277 tm_enable(); 1278 1279 /* We can only have got here if the task started using FP after 1280 * beginning the transaction. So, the transactional regs are just a 1281 * copy of the checkpointed ones. But, we still need to recheckpoint 1282 * as we're enabling FP for the process; it will return, abort the 1283 * transaction, and probably retry but now with FP enabled. So the 1284 * checkpointed FP registers need to be loaded. 1285 */ 1286 tm_reclaim(¤t->thread, current->thread.regs->msr, 1287 TM_CAUSE_FAC_UNAV); 1288 /* Reclaim didn't save out any FPRs to transact_fprs. */ 1289 1290 /* Enable FP for the task: */ 1291 regs->msr |= (MSR_FP | current->thread.fpexc_mode); 1292 1293 /* This loads and recheckpoints the FP registers from 1294 * thread.fpr[]. They will remain in registers after the 1295 * checkpoint so we don't need to reload them after. 1296 */ 1297 tm_recheckpoint(¤t->thread, regs->msr); 1298 } 1299 1300 #ifdef CONFIG_ALTIVEC 1301 extern void do_load_up_altivec(struct pt_regs *regs); 1302 1303 void altivec_unavailable_tm(struct pt_regs *regs) 1304 { 1305 /* See the comments in fp_unavailable_tm(). This function operates 1306 * the same way. 1307 */ 1308 1309 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx," 1310 "MSR=%lx\n", 1311 regs->nip, regs->msr); 1312 tm_enable(); 1313 tm_reclaim(¤t->thread, current->thread.regs->msr, 1314 TM_CAUSE_FAC_UNAV); 1315 regs->msr |= MSR_VEC; 1316 tm_recheckpoint(¤t->thread, regs->msr); 1317 current->thread.used_vr = 1; 1318 } 1319 #endif 1320 1321 #ifdef CONFIG_VSX 1322 void vsx_unavailable_tm(struct pt_regs *regs) 1323 { 1324 /* See the comments in fp_unavailable_tm(). This works similarly, 1325 * though we're loading both FP and VEC registers in here. 1326 * 1327 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC 1328 * regs. Either way, set MSR_VSX. 1329 */ 1330 1331 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx," 1332 "MSR=%lx\n", 1333 regs->nip, regs->msr); 1334 1335 tm_enable(); 1336 /* This reclaims FP and/or VR regs if they're already enabled */ 1337 tm_reclaim(¤t->thread, current->thread.regs->msr, 1338 TM_CAUSE_FAC_UNAV); 1339 1340 regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode | 1341 MSR_VSX; 1342 /* This loads & recheckpoints FP and VRs. */ 1343 tm_recheckpoint(¤t->thread, regs->msr); 1344 current->thread.used_vsr = 1; 1345 } 1346 #endif 1347 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1348 1349 void performance_monitor_exception(struct pt_regs *regs) 1350 { 1351 __get_cpu_var(irq_stat).pmu_irqs++; 1352 1353 perf_irq(regs); 1354 } 1355 1356 #ifdef CONFIG_8xx 1357 void SoftwareEmulation(struct pt_regs *regs) 1358 { 1359 extern int do_mathemu(struct pt_regs *); 1360 extern int Soft_emulate_8xx(struct pt_regs *); 1361 #if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU) 1362 int errcode; 1363 #endif 1364 1365 CHECK_FULL_REGS(regs); 1366 1367 if (!user_mode(regs)) { 1368 debugger(regs); 1369 die("Kernel Mode Software FPU Emulation", regs, SIGFPE); 1370 } 1371 1372 #ifdef CONFIG_MATH_EMULATION 1373 errcode = do_mathemu(regs); 1374 if (errcode >= 0) 1375 PPC_WARN_EMULATED(math, regs); 1376 1377 switch (errcode) { 1378 case 0: 1379 emulate_single_step(regs); 1380 return; 1381 case 1: { 1382 int code = 0; 1383 code = __parse_fpscr(current->thread.fpscr.val); 1384 _exception(SIGFPE, regs, code, regs->nip); 1385 return; 1386 } 1387 case -EFAULT: 1388 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1389 return; 1390 default: 1391 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1392 return; 1393 } 1394 1395 #elif defined(CONFIG_8XX_MINIMAL_FPEMU) 1396 errcode = Soft_emulate_8xx(regs); 1397 if (errcode >= 0) 1398 PPC_WARN_EMULATED(8xx, regs); 1399 1400 switch (errcode) { 1401 case 0: 1402 emulate_single_step(regs); 1403 return; 1404 case 1: 1405 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1406 return; 1407 case -EFAULT: 1408 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1409 return; 1410 } 1411 #else 1412 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1413 #endif 1414 } 1415 #endif /* CONFIG_8xx */ 1416 1417 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1418 static void handle_debug(struct pt_regs *regs, unsigned long debug_status) 1419 { 1420 int changed = 0; 1421 /* 1422 * Determine the cause of the debug event, clear the 1423 * event flags and send a trap to the handler. Torez 1424 */ 1425 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { 1426 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); 1427 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1428 current->thread.dbcr2 &= ~DBCR2_DAC12MODE; 1429 #endif 1430 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT, 1431 5); 1432 changed |= 0x01; 1433 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { 1434 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); 1435 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT, 1436 6); 1437 changed |= 0x01; 1438 } else if (debug_status & DBSR_IAC1) { 1439 current->thread.dbcr0 &= ~DBCR0_IAC1; 1440 dbcr_iac_range(current) &= ~DBCR_IAC12MODE; 1441 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT, 1442 1); 1443 changed |= 0x01; 1444 } else if (debug_status & DBSR_IAC2) { 1445 current->thread.dbcr0 &= ~DBCR0_IAC2; 1446 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT, 1447 2); 1448 changed |= 0x01; 1449 } else if (debug_status & DBSR_IAC3) { 1450 current->thread.dbcr0 &= ~DBCR0_IAC3; 1451 dbcr_iac_range(current) &= ~DBCR_IAC34MODE; 1452 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT, 1453 3); 1454 changed |= 0x01; 1455 } else if (debug_status & DBSR_IAC4) { 1456 current->thread.dbcr0 &= ~DBCR0_IAC4; 1457 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT, 1458 4); 1459 changed |= 0x01; 1460 } 1461 /* 1462 * At the point this routine was called, the MSR(DE) was turned off. 1463 * Check all other debug flags and see if that bit needs to be turned 1464 * back on or not. 1465 */ 1466 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1)) 1467 regs->msr |= MSR_DE; 1468 else 1469 /* Make sure the IDM flag is off */ 1470 current->thread.dbcr0 &= ~DBCR0_IDM; 1471 1472 if (changed & 0x01) 1473 mtspr(SPRN_DBCR0, current->thread.dbcr0); 1474 } 1475 1476 void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status) 1477 { 1478 current->thread.dbsr = debug_status; 1479 1480 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while 1481 * on server, it stops on the target of the branch. In order to simulate 1482 * the server behaviour, we thus restart right away with a single step 1483 * instead of stopping here when hitting a BT 1484 */ 1485 if (debug_status & DBSR_BT) { 1486 regs->msr &= ~MSR_DE; 1487 1488 /* Disable BT */ 1489 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); 1490 /* Clear the BT event */ 1491 mtspr(SPRN_DBSR, DBSR_BT); 1492 1493 /* Do the single step trick only when coming from userspace */ 1494 if (user_mode(regs)) { 1495 current->thread.dbcr0 &= ~DBCR0_BT; 1496 current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC; 1497 regs->msr |= MSR_DE; 1498 return; 1499 } 1500 1501 if (notify_die(DIE_SSTEP, "block_step", regs, 5, 1502 5, SIGTRAP) == NOTIFY_STOP) { 1503 return; 1504 } 1505 if (debugger_sstep(regs)) 1506 return; 1507 } else if (debug_status & DBSR_IC) { /* Instruction complete */ 1508 regs->msr &= ~MSR_DE; 1509 1510 /* Disable instruction completion */ 1511 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); 1512 /* Clear the instruction completion event */ 1513 mtspr(SPRN_DBSR, DBSR_IC); 1514 1515 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 1516 5, SIGTRAP) == NOTIFY_STOP) { 1517 return; 1518 } 1519 1520 if (debugger_sstep(regs)) 1521 return; 1522 1523 if (user_mode(regs)) { 1524 current->thread.dbcr0 &= ~DBCR0_IC; 1525 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, 1526 current->thread.dbcr1)) 1527 regs->msr |= MSR_DE; 1528 else 1529 /* Make sure the IDM bit is off */ 1530 current->thread.dbcr0 &= ~DBCR0_IDM; 1531 } 1532 1533 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 1534 } else 1535 handle_debug(regs, debug_status); 1536 } 1537 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 1538 1539 #if !defined(CONFIG_TAU_INT) 1540 void TAUException(struct pt_regs *regs) 1541 { 1542 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", 1543 regs->nip, regs->msr, regs->trap, print_tainted()); 1544 } 1545 #endif /* CONFIG_INT_TAU */ 1546 1547 #ifdef CONFIG_ALTIVEC 1548 void altivec_assist_exception(struct pt_regs *regs) 1549 { 1550 int err; 1551 1552 if (!user_mode(regs)) { 1553 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" 1554 " at %lx\n", regs->nip); 1555 die("Kernel VMX/Altivec assist exception", regs, SIGILL); 1556 } 1557 1558 flush_altivec_to_thread(current); 1559 1560 PPC_WARN_EMULATED(altivec, regs); 1561 err = emulate_altivec(regs); 1562 if (err == 0) { 1563 regs->nip += 4; /* skip emulated instruction */ 1564 emulate_single_step(regs); 1565 return; 1566 } 1567 1568 if (err == -EFAULT) { 1569 /* got an error reading the instruction */ 1570 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 1571 } else { 1572 /* didn't recognize the instruction */ 1573 /* XXX quick hack for now: set the non-Java bit in the VSCR */ 1574 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " 1575 "in %s at %lx\n", current->comm, regs->nip); 1576 current->thread.vscr.u[3] |= 0x10000; 1577 } 1578 } 1579 #endif /* CONFIG_ALTIVEC */ 1580 1581 #ifdef CONFIG_VSX 1582 void vsx_assist_exception(struct pt_regs *regs) 1583 { 1584 if (!user_mode(regs)) { 1585 printk(KERN_EMERG "VSX assist exception in kernel mode" 1586 " at %lx\n", regs->nip); 1587 die("Kernel VSX assist exception", regs, SIGILL); 1588 } 1589 1590 flush_vsx_to_thread(current); 1591 printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip); 1592 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1593 } 1594 #endif /* CONFIG_VSX */ 1595 1596 #ifdef CONFIG_FSL_BOOKE 1597 void CacheLockingException(struct pt_regs *regs, unsigned long address, 1598 unsigned long error_code) 1599 { 1600 /* We treat cache locking instructions from the user 1601 * as priv ops, in the future we could try to do 1602 * something smarter 1603 */ 1604 if (error_code & (ESR_DLK|ESR_ILK)) 1605 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 1606 return; 1607 } 1608 #endif /* CONFIG_FSL_BOOKE */ 1609 1610 #ifdef CONFIG_SPE 1611 void SPEFloatingPointException(struct pt_regs *regs) 1612 { 1613 extern int do_spe_mathemu(struct pt_regs *regs); 1614 unsigned long spefscr; 1615 int fpexc_mode; 1616 int code = 0; 1617 int err; 1618 1619 flush_spe_to_thread(current); 1620 1621 spefscr = current->thread.spefscr; 1622 fpexc_mode = current->thread.fpexc_mode; 1623 1624 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { 1625 code = FPE_FLTOVF; 1626 } 1627 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { 1628 code = FPE_FLTUND; 1629 } 1630 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) 1631 code = FPE_FLTDIV; 1632 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { 1633 code = FPE_FLTINV; 1634 } 1635 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) 1636 code = FPE_FLTRES; 1637 1638 err = do_spe_mathemu(regs); 1639 if (err == 0) { 1640 regs->nip += 4; /* skip emulated instruction */ 1641 emulate_single_step(regs); 1642 return; 1643 } 1644 1645 if (err == -EFAULT) { 1646 /* got an error reading the instruction */ 1647 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 1648 } else if (err == -EINVAL) { 1649 /* didn't recognize the instruction */ 1650 printk(KERN_ERR "unrecognized spe instruction " 1651 "in %s at %lx\n", current->comm, regs->nip); 1652 } else { 1653 _exception(SIGFPE, regs, code, regs->nip); 1654 } 1655 1656 return; 1657 } 1658 1659 void SPEFloatingPointRoundException(struct pt_regs *regs) 1660 { 1661 extern int speround_handler(struct pt_regs *regs); 1662 int err; 1663 1664 preempt_disable(); 1665 if (regs->msr & MSR_SPE) 1666 giveup_spe(current); 1667 preempt_enable(); 1668 1669 regs->nip -= 4; 1670 err = speround_handler(regs); 1671 if (err == 0) { 1672 regs->nip += 4; /* skip emulated instruction */ 1673 emulate_single_step(regs); 1674 return; 1675 } 1676 1677 if (err == -EFAULT) { 1678 /* got an error reading the instruction */ 1679 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 1680 } else if (err == -EINVAL) { 1681 /* didn't recognize the instruction */ 1682 printk(KERN_ERR "unrecognized spe instruction " 1683 "in %s at %lx\n", current->comm, regs->nip); 1684 } else { 1685 _exception(SIGFPE, regs, 0, regs->nip); 1686 return; 1687 } 1688 } 1689 #endif 1690 1691 /* 1692 * We enter here if we get an unrecoverable exception, that is, one 1693 * that happened at a point where the RI (recoverable interrupt) bit 1694 * in the MSR is 0. This indicates that SRR0/1 are live, and that 1695 * we therefore lost state by taking this exception. 1696 */ 1697 void unrecoverable_exception(struct pt_regs *regs) 1698 { 1699 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", 1700 regs->trap, regs->nip); 1701 die("Unrecoverable exception", regs, SIGABRT); 1702 } 1703 1704 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x) 1705 /* 1706 * Default handler for a Watchdog exception, 1707 * spins until a reboot occurs 1708 */ 1709 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) 1710 { 1711 /* Generic WatchdogHandler, implement your own */ 1712 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); 1713 return; 1714 } 1715 1716 void WatchdogException(struct pt_regs *regs) 1717 { 1718 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); 1719 WatchdogHandler(regs); 1720 } 1721 #endif 1722 1723 /* 1724 * We enter here if we discover during exception entry that we are 1725 * running in supervisor mode with a userspace value in the stack pointer. 1726 */ 1727 void kernel_bad_stack(struct pt_regs *regs) 1728 { 1729 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", 1730 regs->gpr[1], regs->nip); 1731 die("Bad kernel stack pointer", regs, SIGABRT); 1732 } 1733 1734 void __init trap_init(void) 1735 { 1736 } 1737 1738 1739 #ifdef CONFIG_PPC_EMULATED_STATS 1740 1741 #define WARN_EMULATED_SETUP(type) .type = { .name = #type } 1742 1743 struct ppc_emulated ppc_emulated = { 1744 #ifdef CONFIG_ALTIVEC 1745 WARN_EMULATED_SETUP(altivec), 1746 #endif 1747 WARN_EMULATED_SETUP(dcba), 1748 WARN_EMULATED_SETUP(dcbz), 1749 WARN_EMULATED_SETUP(fp_pair), 1750 WARN_EMULATED_SETUP(isel), 1751 WARN_EMULATED_SETUP(mcrxr), 1752 WARN_EMULATED_SETUP(mfpvr), 1753 WARN_EMULATED_SETUP(multiple), 1754 WARN_EMULATED_SETUP(popcntb), 1755 WARN_EMULATED_SETUP(spe), 1756 WARN_EMULATED_SETUP(string), 1757 WARN_EMULATED_SETUP(unaligned), 1758 #ifdef CONFIG_MATH_EMULATION 1759 WARN_EMULATED_SETUP(math), 1760 #elif defined(CONFIG_8XX_MINIMAL_FPEMU) 1761 WARN_EMULATED_SETUP(8xx), 1762 #endif 1763 #ifdef CONFIG_VSX 1764 WARN_EMULATED_SETUP(vsx), 1765 #endif 1766 #ifdef CONFIG_PPC64 1767 WARN_EMULATED_SETUP(mfdscr), 1768 WARN_EMULATED_SETUP(mtdscr), 1769 #endif 1770 }; 1771 1772 u32 ppc_warn_emulated; 1773 1774 void ppc_warn_emulated_print(const char *type) 1775 { 1776 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, 1777 type); 1778 } 1779 1780 static int __init ppc_warn_emulated_init(void) 1781 { 1782 struct dentry *dir, *d; 1783 unsigned int i; 1784 struct ppc_emulated_entry *entries = (void *)&ppc_emulated; 1785 1786 if (!powerpc_debugfs_root) 1787 return -ENODEV; 1788 1789 dir = debugfs_create_dir("emulated_instructions", 1790 powerpc_debugfs_root); 1791 if (!dir) 1792 return -ENOMEM; 1793 1794 d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir, 1795 &ppc_warn_emulated); 1796 if (!d) 1797 goto fail; 1798 1799 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { 1800 d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir, 1801 (u32 *)&entries[i].val.counter); 1802 if (!d) 1803 goto fail; 1804 } 1805 1806 return 0; 1807 1808 fail: 1809 debugfs_remove_recursive(dir); 1810 return -ENOMEM; 1811 } 1812 1813 device_initcall(ppc_warn_emulated_init); 1814 1815 #endif /* CONFIG_PPC_EMULATED_STATS */ 1816