1 /* 2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 3 * Copyright 2007-2010 Freescale Semiconductor, Inc. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 * 10 * Modified by Cort Dougan (cort@cs.nmt.edu) 11 * and Paul Mackerras (paulus@samba.org) 12 */ 13 14 /* 15 * This file handles the architecture-dependent parts of hardware exceptions 16 */ 17 18 #include <linux/errno.h> 19 #include <linux/sched.h> 20 #include <linux/kernel.h> 21 #include <linux/mm.h> 22 #include <linux/stddef.h> 23 #include <linux/unistd.h> 24 #include <linux/ptrace.h> 25 #include <linux/user.h> 26 #include <linux/interrupt.h> 27 #include <linux/init.h> 28 #include <linux/module.h> 29 #include <linux/prctl.h> 30 #include <linux/delay.h> 31 #include <linux/kprobes.h> 32 #include <linux/kexec.h> 33 #include <linux/backlight.h> 34 #include <linux/bug.h> 35 #include <linux/kdebug.h> 36 #include <linux/debugfs.h> 37 #include <linux/ratelimit.h> 38 #include <linux/context_tracking.h> 39 40 #include <asm/emulated_ops.h> 41 #include <asm/pgtable.h> 42 #include <asm/uaccess.h> 43 #include <asm/io.h> 44 #include <asm/machdep.h> 45 #include <asm/rtas.h> 46 #include <asm/pmc.h> 47 #include <asm/reg.h> 48 #ifdef CONFIG_PMAC_BACKLIGHT 49 #include <asm/backlight.h> 50 #endif 51 #ifdef CONFIG_PPC64 52 #include <asm/firmware.h> 53 #include <asm/processor.h> 54 #include <asm/tm.h> 55 #endif 56 #include <asm/kexec.h> 57 #include <asm/ppc-opcode.h> 58 #include <asm/rio.h> 59 #include <asm/fadump.h> 60 #include <asm/switch_to.h> 61 #include <asm/tm.h> 62 #include <asm/debug.h> 63 64 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) 65 int (*__debugger)(struct pt_regs *regs) __read_mostly; 66 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; 67 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; 68 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; 69 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; 70 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly; 71 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; 72 73 EXPORT_SYMBOL(__debugger); 74 EXPORT_SYMBOL(__debugger_ipi); 75 EXPORT_SYMBOL(__debugger_bpt); 76 EXPORT_SYMBOL(__debugger_sstep); 77 EXPORT_SYMBOL(__debugger_iabr_match); 78 EXPORT_SYMBOL(__debugger_break_match); 79 EXPORT_SYMBOL(__debugger_fault_handler); 80 #endif 81 82 /* Transactional Memory trap debug */ 83 #ifdef TM_DEBUG_SW 84 #define TM_DEBUG(x...) printk(KERN_INFO x) 85 #else 86 #define TM_DEBUG(x...) do { } while(0) 87 #endif 88 89 /* 90 * Trap & Exception support 91 */ 92 93 #ifdef CONFIG_PMAC_BACKLIGHT 94 static void pmac_backlight_unblank(void) 95 { 96 mutex_lock(&pmac_backlight_mutex); 97 if (pmac_backlight) { 98 struct backlight_properties *props; 99 100 props = &pmac_backlight->props; 101 props->brightness = props->max_brightness; 102 props->power = FB_BLANK_UNBLANK; 103 backlight_update_status(pmac_backlight); 104 } 105 mutex_unlock(&pmac_backlight_mutex); 106 } 107 #else 108 static inline void pmac_backlight_unblank(void) { } 109 #endif 110 111 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; 112 static int die_owner = -1; 113 static unsigned int die_nest_count; 114 static int die_counter; 115 116 static unsigned __kprobes long oops_begin(struct pt_regs *regs) 117 { 118 int cpu; 119 unsigned long flags; 120 121 if (debugger(regs)) 122 return 1; 123 124 oops_enter(); 125 126 /* racy, but better than risking deadlock. */ 127 raw_local_irq_save(flags); 128 cpu = smp_processor_id(); 129 if (!arch_spin_trylock(&die_lock)) { 130 if (cpu == die_owner) 131 /* nested oops. should stop eventually */; 132 else 133 arch_spin_lock(&die_lock); 134 } 135 die_nest_count++; 136 die_owner = cpu; 137 console_verbose(); 138 bust_spinlocks(1); 139 if (machine_is(powermac)) 140 pmac_backlight_unblank(); 141 return flags; 142 } 143 144 static void __kprobes oops_end(unsigned long flags, struct pt_regs *regs, 145 int signr) 146 { 147 bust_spinlocks(0); 148 die_owner = -1; 149 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 150 die_nest_count--; 151 oops_exit(); 152 printk("\n"); 153 if (!die_nest_count) 154 /* Nest count reaches zero, release the lock. */ 155 arch_spin_unlock(&die_lock); 156 raw_local_irq_restore(flags); 157 158 crash_fadump(regs, "die oops"); 159 160 /* 161 * A system reset (0x100) is a request to dump, so we always send 162 * it through the crashdump code. 163 */ 164 if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) { 165 crash_kexec(regs); 166 167 /* 168 * We aren't the primary crash CPU. We need to send it 169 * to a holding pattern to avoid it ending up in the panic 170 * code. 171 */ 172 crash_kexec_secondary(regs); 173 } 174 175 if (!signr) 176 return; 177 178 /* 179 * While our oops output is serialised by a spinlock, output 180 * from panic() called below can race and corrupt it. If we 181 * know we are going to panic, delay for 1 second so we have a 182 * chance to get clean backtraces from all CPUs that are oopsing. 183 */ 184 if (in_interrupt() || panic_on_oops || !current->pid || 185 is_global_init(current)) { 186 mdelay(MSEC_PER_SEC); 187 } 188 189 if (in_interrupt()) 190 panic("Fatal exception in interrupt"); 191 if (panic_on_oops) 192 panic("Fatal exception"); 193 do_exit(signr); 194 } 195 196 static int __kprobes __die(const char *str, struct pt_regs *regs, long err) 197 { 198 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); 199 #ifdef CONFIG_PREEMPT 200 printk("PREEMPT "); 201 #endif 202 #ifdef CONFIG_SMP 203 printk("SMP NR_CPUS=%d ", NR_CPUS); 204 #endif 205 #ifdef CONFIG_DEBUG_PAGEALLOC 206 printk("DEBUG_PAGEALLOC "); 207 #endif 208 #ifdef CONFIG_NUMA 209 printk("NUMA "); 210 #endif 211 printk("%s\n", ppc_md.name ? ppc_md.name : ""); 212 213 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP) 214 return 1; 215 216 print_modules(); 217 show_regs(regs); 218 219 return 0; 220 } 221 222 void die(const char *str, struct pt_regs *regs, long err) 223 { 224 unsigned long flags = oops_begin(regs); 225 226 if (__die(str, regs, err)) 227 err = 0; 228 oops_end(flags, regs, err); 229 } 230 231 void user_single_step_siginfo(struct task_struct *tsk, 232 struct pt_regs *regs, siginfo_t *info) 233 { 234 memset(info, 0, sizeof(*info)); 235 info->si_signo = SIGTRAP; 236 info->si_code = TRAP_TRACE; 237 info->si_addr = (void __user *)regs->nip; 238 } 239 240 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) 241 { 242 siginfo_t info; 243 const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \ 244 "at %08lx nip %08lx lr %08lx code %x\n"; 245 const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \ 246 "at %016lx nip %016lx lr %016lx code %x\n"; 247 248 if (!user_mode(regs)) { 249 die("Exception in kernel mode", regs, signr); 250 return; 251 } 252 253 if (show_unhandled_signals && unhandled_signal(current, signr)) { 254 printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32, 255 current->comm, current->pid, signr, 256 addr, regs->nip, regs->link, code); 257 } 258 259 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs)) 260 local_irq_enable(); 261 262 current->thread.trap_nr = code; 263 memset(&info, 0, sizeof(info)); 264 info.si_signo = signr; 265 info.si_code = code; 266 info.si_addr = (void __user *) addr; 267 force_sig_info(signr, &info, current); 268 } 269 270 #ifdef CONFIG_PPC64 271 void system_reset_exception(struct pt_regs *regs) 272 { 273 /* See if any machine dependent calls */ 274 if (ppc_md.system_reset_exception) { 275 if (ppc_md.system_reset_exception(regs)) 276 return; 277 } 278 279 die("System Reset", regs, SIGABRT); 280 281 /* Must die if the interrupt is not recoverable */ 282 if (!(regs->msr & MSR_RI)) 283 panic("Unrecoverable System Reset"); 284 285 /* What should we do here? We could issue a shutdown or hard reset. */ 286 } 287 #endif 288 289 /* 290 * I/O accesses can cause machine checks on powermacs. 291 * Check if the NIP corresponds to the address of a sync 292 * instruction for which there is an entry in the exception 293 * table. 294 * Note that the 601 only takes a machine check on TEA 295 * (transfer error ack) signal assertion, and does not 296 * set any of the top 16 bits of SRR1. 297 * -- paulus. 298 */ 299 static inline int check_io_access(struct pt_regs *regs) 300 { 301 #ifdef CONFIG_PPC32 302 unsigned long msr = regs->msr; 303 const struct exception_table_entry *entry; 304 unsigned int *nip = (unsigned int *)regs->nip; 305 306 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) 307 && (entry = search_exception_tables(regs->nip)) != NULL) { 308 /* 309 * Check that it's a sync instruction, or somewhere 310 * in the twi; isync; nop sequence that inb/inw/inl uses. 311 * As the address is in the exception table 312 * we should be able to read the instr there. 313 * For the debug message, we look at the preceding 314 * load or store. 315 */ 316 if (*nip == 0x60000000) /* nop */ 317 nip -= 2; 318 else if (*nip == 0x4c00012c) /* isync */ 319 --nip; 320 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) { 321 /* sync or twi */ 322 unsigned int rb; 323 324 --nip; 325 rb = (*nip >> 11) & 0x1f; 326 printk(KERN_DEBUG "%s bad port %lx at %p\n", 327 (*nip & 0x100)? "OUT to": "IN from", 328 regs->gpr[rb] - _IO_BASE, nip); 329 regs->msr |= MSR_RI; 330 regs->nip = entry->fixup; 331 return 1; 332 } 333 } 334 #endif /* CONFIG_PPC32 */ 335 return 0; 336 } 337 338 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 339 /* On 4xx, the reason for the machine check or program exception 340 is in the ESR. */ 341 #define get_reason(regs) ((regs)->dsisr) 342 #ifndef CONFIG_FSL_BOOKE 343 #define get_mc_reason(regs) ((regs)->dsisr) 344 #else 345 #define get_mc_reason(regs) (mfspr(SPRN_MCSR)) 346 #endif 347 #define REASON_FP ESR_FP 348 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) 349 #define REASON_PRIVILEGED ESR_PPR 350 #define REASON_TRAP ESR_PTR 351 352 /* single-step stuff */ 353 #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) 354 #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) 355 356 #else 357 /* On non-4xx, the reason for the machine check or program 358 exception is in the MSR. */ 359 #define get_reason(regs) ((regs)->msr) 360 #define get_mc_reason(regs) ((regs)->msr) 361 #define REASON_TM 0x200000 362 #define REASON_FP 0x100000 363 #define REASON_ILLEGAL 0x80000 364 #define REASON_PRIVILEGED 0x40000 365 #define REASON_TRAP 0x20000 366 367 #define single_stepping(regs) ((regs)->msr & MSR_SE) 368 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) 369 #endif 370 371 #if defined(CONFIG_4xx) 372 int machine_check_4xx(struct pt_regs *regs) 373 { 374 unsigned long reason = get_mc_reason(regs); 375 376 if (reason & ESR_IMCP) { 377 printk("Instruction"); 378 mtspr(SPRN_ESR, reason & ~ESR_IMCP); 379 } else 380 printk("Data"); 381 printk(" machine check in kernel mode.\n"); 382 383 return 0; 384 } 385 386 int machine_check_440A(struct pt_regs *regs) 387 { 388 unsigned long reason = get_mc_reason(regs); 389 390 printk("Machine check in kernel mode.\n"); 391 if (reason & ESR_IMCP){ 392 printk("Instruction Synchronous Machine Check exception\n"); 393 mtspr(SPRN_ESR, reason & ~ESR_IMCP); 394 } 395 else { 396 u32 mcsr = mfspr(SPRN_MCSR); 397 if (mcsr & MCSR_IB) 398 printk("Instruction Read PLB Error\n"); 399 if (mcsr & MCSR_DRB) 400 printk("Data Read PLB Error\n"); 401 if (mcsr & MCSR_DWB) 402 printk("Data Write PLB Error\n"); 403 if (mcsr & MCSR_TLBP) 404 printk("TLB Parity Error\n"); 405 if (mcsr & MCSR_ICP){ 406 flush_instruction_cache(); 407 printk("I-Cache Parity Error\n"); 408 } 409 if (mcsr & MCSR_DCSP) 410 printk("D-Cache Search Parity Error\n"); 411 if (mcsr & MCSR_DCFP) 412 printk("D-Cache Flush Parity Error\n"); 413 if (mcsr & MCSR_IMPE) 414 printk("Machine Check exception is imprecise\n"); 415 416 /* Clear MCSR */ 417 mtspr(SPRN_MCSR, mcsr); 418 } 419 return 0; 420 } 421 422 int machine_check_47x(struct pt_regs *regs) 423 { 424 unsigned long reason = get_mc_reason(regs); 425 u32 mcsr; 426 427 printk(KERN_ERR "Machine check in kernel mode.\n"); 428 if (reason & ESR_IMCP) { 429 printk(KERN_ERR 430 "Instruction Synchronous Machine Check exception\n"); 431 mtspr(SPRN_ESR, reason & ~ESR_IMCP); 432 return 0; 433 } 434 mcsr = mfspr(SPRN_MCSR); 435 if (mcsr & MCSR_IB) 436 printk(KERN_ERR "Instruction Read PLB Error\n"); 437 if (mcsr & MCSR_DRB) 438 printk(KERN_ERR "Data Read PLB Error\n"); 439 if (mcsr & MCSR_DWB) 440 printk(KERN_ERR "Data Write PLB Error\n"); 441 if (mcsr & MCSR_TLBP) 442 printk(KERN_ERR "TLB Parity Error\n"); 443 if (mcsr & MCSR_ICP) { 444 flush_instruction_cache(); 445 printk(KERN_ERR "I-Cache Parity Error\n"); 446 } 447 if (mcsr & MCSR_DCSP) 448 printk(KERN_ERR "D-Cache Search Parity Error\n"); 449 if (mcsr & PPC47x_MCSR_GPR) 450 printk(KERN_ERR "GPR Parity Error\n"); 451 if (mcsr & PPC47x_MCSR_FPR) 452 printk(KERN_ERR "FPR Parity Error\n"); 453 if (mcsr & PPC47x_MCSR_IPR) 454 printk(KERN_ERR "Machine Check exception is imprecise\n"); 455 456 /* Clear MCSR */ 457 mtspr(SPRN_MCSR, mcsr); 458 459 return 0; 460 } 461 #elif defined(CONFIG_E500) 462 int machine_check_e500mc(struct pt_regs *regs) 463 { 464 unsigned long mcsr = mfspr(SPRN_MCSR); 465 unsigned long reason = mcsr; 466 int recoverable = 1; 467 468 if (reason & MCSR_LD) { 469 recoverable = fsl_rio_mcheck_exception(regs); 470 if (recoverable == 1) 471 goto silent_out; 472 } 473 474 printk("Machine check in kernel mode.\n"); 475 printk("Caused by (from MCSR=%lx): ", reason); 476 477 if (reason & MCSR_MCP) 478 printk("Machine Check Signal\n"); 479 480 if (reason & MCSR_ICPERR) { 481 printk("Instruction Cache Parity Error\n"); 482 483 /* 484 * This is recoverable by invalidating the i-cache. 485 */ 486 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); 487 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) 488 ; 489 490 /* 491 * This will generally be accompanied by an instruction 492 * fetch error report -- only treat MCSR_IF as fatal 493 * if it wasn't due to an L1 parity error. 494 */ 495 reason &= ~MCSR_IF; 496 } 497 498 if (reason & MCSR_DCPERR_MC) { 499 printk("Data Cache Parity Error\n"); 500 501 /* 502 * In write shadow mode we auto-recover from the error, but it 503 * may still get logged and cause a machine check. We should 504 * only treat the non-write shadow case as non-recoverable. 505 */ 506 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) 507 recoverable = 0; 508 } 509 510 if (reason & MCSR_L2MMU_MHIT) { 511 printk("Hit on multiple TLB entries\n"); 512 recoverable = 0; 513 } 514 515 if (reason & MCSR_NMI) 516 printk("Non-maskable interrupt\n"); 517 518 if (reason & MCSR_IF) { 519 printk("Instruction Fetch Error Report\n"); 520 recoverable = 0; 521 } 522 523 if (reason & MCSR_LD) { 524 printk("Load Error Report\n"); 525 recoverable = 0; 526 } 527 528 if (reason & MCSR_ST) { 529 printk("Store Error Report\n"); 530 recoverable = 0; 531 } 532 533 if (reason & MCSR_LDG) { 534 printk("Guarded Load Error Report\n"); 535 recoverable = 0; 536 } 537 538 if (reason & MCSR_TLBSYNC) 539 printk("Simultaneous tlbsync operations\n"); 540 541 if (reason & MCSR_BSL2_ERR) { 542 printk("Level 2 Cache Error\n"); 543 recoverable = 0; 544 } 545 546 if (reason & MCSR_MAV) { 547 u64 addr; 548 549 addr = mfspr(SPRN_MCAR); 550 addr |= (u64)mfspr(SPRN_MCARU) << 32; 551 552 printk("Machine Check %s Address: %#llx\n", 553 reason & MCSR_MEA ? "Effective" : "Physical", addr); 554 } 555 556 silent_out: 557 mtspr(SPRN_MCSR, mcsr); 558 return mfspr(SPRN_MCSR) == 0 && recoverable; 559 } 560 561 int machine_check_e500(struct pt_regs *regs) 562 { 563 unsigned long reason = get_mc_reason(regs); 564 565 if (reason & MCSR_BUS_RBERR) { 566 if (fsl_rio_mcheck_exception(regs)) 567 return 1; 568 } 569 570 printk("Machine check in kernel mode.\n"); 571 printk("Caused by (from MCSR=%lx): ", reason); 572 573 if (reason & MCSR_MCP) 574 printk("Machine Check Signal\n"); 575 if (reason & MCSR_ICPERR) 576 printk("Instruction Cache Parity Error\n"); 577 if (reason & MCSR_DCP_PERR) 578 printk("Data Cache Push Parity Error\n"); 579 if (reason & MCSR_DCPERR) 580 printk("Data Cache Parity Error\n"); 581 if (reason & MCSR_BUS_IAERR) 582 printk("Bus - Instruction Address Error\n"); 583 if (reason & MCSR_BUS_RAERR) 584 printk("Bus - Read Address Error\n"); 585 if (reason & MCSR_BUS_WAERR) 586 printk("Bus - Write Address Error\n"); 587 if (reason & MCSR_BUS_IBERR) 588 printk("Bus - Instruction Data Error\n"); 589 if (reason & MCSR_BUS_RBERR) 590 printk("Bus - Read Data Bus Error\n"); 591 if (reason & MCSR_BUS_WBERR) 592 printk("Bus - Read Data Bus Error\n"); 593 if (reason & MCSR_BUS_IPERR) 594 printk("Bus - Instruction Parity Error\n"); 595 if (reason & MCSR_BUS_RPERR) 596 printk("Bus - Read Parity Error\n"); 597 598 return 0; 599 } 600 601 int machine_check_generic(struct pt_regs *regs) 602 { 603 return 0; 604 } 605 #elif defined(CONFIG_E200) 606 int machine_check_e200(struct pt_regs *regs) 607 { 608 unsigned long reason = get_mc_reason(regs); 609 610 printk("Machine check in kernel mode.\n"); 611 printk("Caused by (from MCSR=%lx): ", reason); 612 613 if (reason & MCSR_MCP) 614 printk("Machine Check Signal\n"); 615 if (reason & MCSR_CP_PERR) 616 printk("Cache Push Parity Error\n"); 617 if (reason & MCSR_CPERR) 618 printk("Cache Parity Error\n"); 619 if (reason & MCSR_EXCP_ERR) 620 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); 621 if (reason & MCSR_BUS_IRERR) 622 printk("Bus - Read Bus Error on instruction fetch\n"); 623 if (reason & MCSR_BUS_DRERR) 624 printk("Bus - Read Bus Error on data load\n"); 625 if (reason & MCSR_BUS_WRERR) 626 printk("Bus - Write Bus Error on buffered store or cache line push\n"); 627 628 return 0; 629 } 630 #else 631 int machine_check_generic(struct pt_regs *regs) 632 { 633 unsigned long reason = get_mc_reason(regs); 634 635 printk("Machine check in kernel mode.\n"); 636 printk("Caused by (from SRR1=%lx): ", reason); 637 switch (reason & 0x601F0000) { 638 case 0x80000: 639 printk("Machine check signal\n"); 640 break; 641 case 0: /* for 601 */ 642 case 0x40000: 643 case 0x140000: /* 7450 MSS error and TEA */ 644 printk("Transfer error ack signal\n"); 645 break; 646 case 0x20000: 647 printk("Data parity error signal\n"); 648 break; 649 case 0x10000: 650 printk("Address parity error signal\n"); 651 break; 652 case 0x20000000: 653 printk("L1 Data Cache error\n"); 654 break; 655 case 0x40000000: 656 printk("L1 Instruction Cache error\n"); 657 break; 658 case 0x00100000: 659 printk("L2 data cache parity error\n"); 660 break; 661 default: 662 printk("Unknown values in msr\n"); 663 } 664 return 0; 665 } 666 #endif /* everything else */ 667 668 void machine_check_exception(struct pt_regs *regs) 669 { 670 enum ctx_state prev_state = exception_enter(); 671 int recover = 0; 672 673 __get_cpu_var(irq_stat).mce_exceptions++; 674 675 /* See if any machine dependent calls. In theory, we would want 676 * to call the CPU first, and call the ppc_md. one if the CPU 677 * one returns a positive number. However there is existing code 678 * that assumes the board gets a first chance, so let's keep it 679 * that way for now and fix things later. --BenH. 680 */ 681 if (ppc_md.machine_check_exception) 682 recover = ppc_md.machine_check_exception(regs); 683 else if (cur_cpu_spec->machine_check) 684 recover = cur_cpu_spec->machine_check(regs); 685 686 if (recover > 0) 687 goto bail; 688 689 #if defined(CONFIG_8xx) && defined(CONFIG_PCI) 690 /* the qspan pci read routines can cause machine checks -- Cort 691 * 692 * yuck !!! that totally needs to go away ! There are better ways 693 * to deal with that than having a wart in the mcheck handler. 694 * -- BenH 695 */ 696 bad_page_fault(regs, regs->dar, SIGBUS); 697 goto bail; 698 #endif 699 700 if (debugger_fault_handler(regs)) 701 goto bail; 702 703 if (check_io_access(regs)) 704 goto bail; 705 706 die("Machine check", regs, SIGBUS); 707 708 /* Must die if the interrupt is not recoverable */ 709 if (!(regs->msr & MSR_RI)) 710 panic("Unrecoverable Machine check"); 711 712 bail: 713 exception_exit(prev_state); 714 } 715 716 void SMIException(struct pt_regs *regs) 717 { 718 die("System Management Interrupt", regs, SIGABRT); 719 } 720 721 void unknown_exception(struct pt_regs *regs) 722 { 723 enum ctx_state prev_state = exception_enter(); 724 725 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 726 regs->nip, regs->msr, regs->trap); 727 728 _exception(SIGTRAP, regs, 0, 0); 729 730 exception_exit(prev_state); 731 } 732 733 void instruction_breakpoint_exception(struct pt_regs *regs) 734 { 735 enum ctx_state prev_state = exception_enter(); 736 737 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, 738 5, SIGTRAP) == NOTIFY_STOP) 739 goto bail; 740 if (debugger_iabr_match(regs)) 741 goto bail; 742 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 743 744 bail: 745 exception_exit(prev_state); 746 } 747 748 void RunModeException(struct pt_regs *regs) 749 { 750 _exception(SIGTRAP, regs, 0, 0); 751 } 752 753 void __kprobes single_step_exception(struct pt_regs *regs) 754 { 755 enum ctx_state prev_state = exception_enter(); 756 757 clear_single_step(regs); 758 759 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 760 5, SIGTRAP) == NOTIFY_STOP) 761 goto bail; 762 if (debugger_sstep(regs)) 763 goto bail; 764 765 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 766 767 bail: 768 exception_exit(prev_state); 769 } 770 771 /* 772 * After we have successfully emulated an instruction, we have to 773 * check if the instruction was being single-stepped, and if so, 774 * pretend we got a single-step exception. This was pointed out 775 * by Kumar Gala. -- paulus 776 */ 777 static void emulate_single_step(struct pt_regs *regs) 778 { 779 if (single_stepping(regs)) 780 single_step_exception(regs); 781 } 782 783 static inline int __parse_fpscr(unsigned long fpscr) 784 { 785 int ret = 0; 786 787 /* Invalid operation */ 788 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) 789 ret = FPE_FLTINV; 790 791 /* Overflow */ 792 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) 793 ret = FPE_FLTOVF; 794 795 /* Underflow */ 796 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) 797 ret = FPE_FLTUND; 798 799 /* Divide by zero */ 800 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) 801 ret = FPE_FLTDIV; 802 803 /* Inexact result */ 804 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) 805 ret = FPE_FLTRES; 806 807 return ret; 808 } 809 810 static void parse_fpe(struct pt_regs *regs) 811 { 812 int code = 0; 813 814 flush_fp_to_thread(current); 815 816 code = __parse_fpscr(current->thread.fpscr.val); 817 818 _exception(SIGFPE, regs, code, regs->nip); 819 } 820 821 /* 822 * Illegal instruction emulation support. Originally written to 823 * provide the PVR to user applications using the mfspr rd, PVR. 824 * Return non-zero if we can't emulate, or -EFAULT if the associated 825 * memory access caused an access fault. Return zero on success. 826 * 827 * There are a couple of ways to do this, either "decode" the instruction 828 * or directly match lots of bits. In this case, matching lots of 829 * bits is faster and easier. 830 * 831 */ 832 static int emulate_string_inst(struct pt_regs *regs, u32 instword) 833 { 834 u8 rT = (instword >> 21) & 0x1f; 835 u8 rA = (instword >> 16) & 0x1f; 836 u8 NB_RB = (instword >> 11) & 0x1f; 837 u32 num_bytes; 838 unsigned long EA; 839 int pos = 0; 840 841 /* Early out if we are an invalid form of lswx */ 842 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) 843 if ((rT == rA) || (rT == NB_RB)) 844 return -EINVAL; 845 846 EA = (rA == 0) ? 0 : regs->gpr[rA]; 847 848 switch (instword & PPC_INST_STRING_MASK) { 849 case PPC_INST_LSWX: 850 case PPC_INST_STSWX: 851 EA += NB_RB; 852 num_bytes = regs->xer & 0x7f; 853 break; 854 case PPC_INST_LSWI: 855 case PPC_INST_STSWI: 856 num_bytes = (NB_RB == 0) ? 32 : NB_RB; 857 break; 858 default: 859 return -EINVAL; 860 } 861 862 while (num_bytes != 0) 863 { 864 u8 val; 865 u32 shift = 8 * (3 - (pos & 0x3)); 866 867 /* if process is 32-bit, clear upper 32 bits of EA */ 868 if ((regs->msr & MSR_64BIT) == 0) 869 EA &= 0xFFFFFFFF; 870 871 switch ((instword & PPC_INST_STRING_MASK)) { 872 case PPC_INST_LSWX: 873 case PPC_INST_LSWI: 874 if (get_user(val, (u8 __user *)EA)) 875 return -EFAULT; 876 /* first time updating this reg, 877 * zero it out */ 878 if (pos == 0) 879 regs->gpr[rT] = 0; 880 regs->gpr[rT] |= val << shift; 881 break; 882 case PPC_INST_STSWI: 883 case PPC_INST_STSWX: 884 val = regs->gpr[rT] >> shift; 885 if (put_user(val, (u8 __user *)EA)) 886 return -EFAULT; 887 break; 888 } 889 /* move EA to next address */ 890 EA += 1; 891 num_bytes--; 892 893 /* manage our position within the register */ 894 if (++pos == 4) { 895 pos = 0; 896 if (++rT == 32) 897 rT = 0; 898 } 899 } 900 901 return 0; 902 } 903 904 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) 905 { 906 u32 ra,rs; 907 unsigned long tmp; 908 909 ra = (instword >> 16) & 0x1f; 910 rs = (instword >> 21) & 0x1f; 911 912 tmp = regs->gpr[rs]; 913 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); 914 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); 915 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; 916 regs->gpr[ra] = tmp; 917 918 return 0; 919 } 920 921 static int emulate_isel(struct pt_regs *regs, u32 instword) 922 { 923 u8 rT = (instword >> 21) & 0x1f; 924 u8 rA = (instword >> 16) & 0x1f; 925 u8 rB = (instword >> 11) & 0x1f; 926 u8 BC = (instword >> 6) & 0x1f; 927 u8 bit; 928 unsigned long tmp; 929 930 tmp = (rA == 0) ? 0 : regs->gpr[rA]; 931 bit = (regs->ccr >> (31 - BC)) & 0x1; 932 933 regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; 934 935 return 0; 936 } 937 938 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 939 static inline bool tm_abort_check(struct pt_regs *regs, int cause) 940 { 941 /* If we're emulating a load/store in an active transaction, we cannot 942 * emulate it as the kernel operates in transaction suspended context. 943 * We need to abort the transaction. This creates a persistent TM 944 * abort so tell the user what caused it with a new code. 945 */ 946 if (MSR_TM_TRANSACTIONAL(regs->msr)) { 947 tm_enable(); 948 tm_abort(cause); 949 return true; 950 } 951 return false; 952 } 953 #else 954 static inline bool tm_abort_check(struct pt_regs *regs, int reason) 955 { 956 return false; 957 } 958 #endif 959 960 static int emulate_instruction(struct pt_regs *regs) 961 { 962 u32 instword; 963 u32 rd; 964 965 if (!user_mode(regs) || (regs->msr & MSR_LE)) 966 return -EINVAL; 967 CHECK_FULL_REGS(regs); 968 969 if (get_user(instword, (u32 __user *)(regs->nip))) 970 return -EFAULT; 971 972 /* Emulate the mfspr rD, PVR. */ 973 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { 974 PPC_WARN_EMULATED(mfpvr, regs); 975 rd = (instword >> 21) & 0x1f; 976 regs->gpr[rd] = mfspr(SPRN_PVR); 977 return 0; 978 } 979 980 /* Emulating the dcba insn is just a no-op. */ 981 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { 982 PPC_WARN_EMULATED(dcba, regs); 983 return 0; 984 } 985 986 /* Emulate the mcrxr insn. */ 987 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { 988 int shift = (instword >> 21) & 0x1c; 989 unsigned long msk = 0xf0000000UL >> shift; 990 991 PPC_WARN_EMULATED(mcrxr, regs); 992 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); 993 regs->xer &= ~0xf0000000UL; 994 return 0; 995 } 996 997 /* Emulate load/store string insn. */ 998 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { 999 if (tm_abort_check(regs, 1000 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) 1001 return -EINVAL; 1002 PPC_WARN_EMULATED(string, regs); 1003 return emulate_string_inst(regs, instword); 1004 } 1005 1006 /* Emulate the popcntb (Population Count Bytes) instruction. */ 1007 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { 1008 PPC_WARN_EMULATED(popcntb, regs); 1009 return emulate_popcntb_inst(regs, instword); 1010 } 1011 1012 /* Emulate isel (Integer Select) instruction */ 1013 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { 1014 PPC_WARN_EMULATED(isel, regs); 1015 return emulate_isel(regs, instword); 1016 } 1017 1018 #ifdef CONFIG_PPC64 1019 /* Emulate the mfspr rD, DSCR. */ 1020 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) == 1021 PPC_INST_MFSPR_DSCR_USER) || 1022 ((instword & PPC_INST_MFSPR_DSCR_MASK) == 1023 PPC_INST_MFSPR_DSCR)) && 1024 cpu_has_feature(CPU_FTR_DSCR)) { 1025 PPC_WARN_EMULATED(mfdscr, regs); 1026 rd = (instword >> 21) & 0x1f; 1027 regs->gpr[rd] = mfspr(SPRN_DSCR); 1028 return 0; 1029 } 1030 /* Emulate the mtspr DSCR, rD. */ 1031 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) == 1032 PPC_INST_MTSPR_DSCR_USER) || 1033 ((instword & PPC_INST_MTSPR_DSCR_MASK) == 1034 PPC_INST_MTSPR_DSCR)) && 1035 cpu_has_feature(CPU_FTR_DSCR)) { 1036 PPC_WARN_EMULATED(mtdscr, regs); 1037 rd = (instword >> 21) & 0x1f; 1038 current->thread.dscr = regs->gpr[rd]; 1039 current->thread.dscr_inherit = 1; 1040 mtspr(SPRN_DSCR, current->thread.dscr); 1041 return 0; 1042 } 1043 #endif 1044 1045 return -EINVAL; 1046 } 1047 1048 int is_valid_bugaddr(unsigned long addr) 1049 { 1050 return is_kernel_addr(addr); 1051 } 1052 1053 void __kprobes program_check_exception(struct pt_regs *regs) 1054 { 1055 enum ctx_state prev_state = exception_enter(); 1056 unsigned int reason = get_reason(regs); 1057 extern int do_mathemu(struct pt_regs *regs); 1058 1059 /* We can now get here via a FP Unavailable exception if the core 1060 * has no FPU, in that case the reason flags will be 0 */ 1061 1062 if (reason & REASON_FP) { 1063 /* IEEE FP exception */ 1064 parse_fpe(regs); 1065 goto bail; 1066 } 1067 if (reason & REASON_TRAP) { 1068 /* Debugger is first in line to stop recursive faults in 1069 * rcu_lock, notify_die, or atomic_notifier_call_chain */ 1070 if (debugger_bpt(regs)) 1071 goto bail; 1072 1073 /* trap exception */ 1074 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) 1075 == NOTIFY_STOP) 1076 goto bail; 1077 1078 if (!(regs->msr & MSR_PR) && /* not user-mode */ 1079 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { 1080 regs->nip += 4; 1081 goto bail; 1082 } 1083 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1084 goto bail; 1085 } 1086 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1087 if (reason & REASON_TM) { 1088 /* This is a TM "Bad Thing Exception" program check. 1089 * This occurs when: 1090 * - An rfid/hrfid/mtmsrd attempts to cause an illegal 1091 * transition in TM states. 1092 * - A trechkpt is attempted when transactional. 1093 * - A treclaim is attempted when non transactional. 1094 * - A tend is illegally attempted. 1095 * - writing a TM SPR when transactional. 1096 */ 1097 if (!user_mode(regs) && 1098 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { 1099 regs->nip += 4; 1100 goto bail; 1101 } 1102 /* If usermode caused this, it's done something illegal and 1103 * gets a SIGILL slap on the wrist. We call it an illegal 1104 * operand to distinguish from the instruction just being bad 1105 * (e.g. executing a 'tend' on a CPU without TM!); it's an 1106 * illegal /placement/ of a valid instruction. 1107 */ 1108 if (user_mode(regs)) { 1109 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip); 1110 goto bail; 1111 } else { 1112 printk(KERN_EMERG "Unexpected TM Bad Thing exception " 1113 "at %lx (msr 0x%x)\n", regs->nip, reason); 1114 die("Unrecoverable exception", regs, SIGABRT); 1115 } 1116 } 1117 #endif 1118 1119 /* We restore the interrupt state now */ 1120 if (!arch_irq_disabled_regs(regs)) 1121 local_irq_enable(); 1122 1123 #ifdef CONFIG_MATH_EMULATION 1124 /* (reason & REASON_ILLEGAL) would be the obvious thing here, 1125 * but there seems to be a hardware bug on the 405GP (RevD) 1126 * that means ESR is sometimes set incorrectly - either to 1127 * ESR_DST (!?) or 0. In the process of chasing this with the 1128 * hardware people - not sure if it can happen on any illegal 1129 * instruction or only on FP instructions, whether there is a 1130 * pattern to occurrences etc. -dgibson 31/Mar/2003 1131 */ 1132 1133 /* 1134 * If we support a HW FPU, we need to ensure the FP state 1135 * if flushed into the thread_struct before attempting 1136 * emulation 1137 */ 1138 #ifdef CONFIG_PPC_FPU 1139 flush_fp_to_thread(current); 1140 #endif 1141 switch (do_mathemu(regs)) { 1142 case 0: 1143 emulate_single_step(regs); 1144 goto bail; 1145 case 1: { 1146 int code = 0; 1147 code = __parse_fpscr(current->thread.fpscr.val); 1148 _exception(SIGFPE, regs, code, regs->nip); 1149 goto bail; 1150 } 1151 case -EFAULT: 1152 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1153 goto bail; 1154 } 1155 /* fall through on any other errors */ 1156 #endif /* CONFIG_MATH_EMULATION */ 1157 1158 /* Try to emulate it if we should. */ 1159 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { 1160 switch (emulate_instruction(regs)) { 1161 case 0: 1162 regs->nip += 4; 1163 emulate_single_step(regs); 1164 goto bail; 1165 case -EFAULT: 1166 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1167 goto bail; 1168 } 1169 } 1170 1171 if (reason & REASON_PRIVILEGED) 1172 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 1173 else 1174 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1175 1176 bail: 1177 exception_exit(prev_state); 1178 } 1179 1180 /* 1181 * This occurs when running in hypervisor mode on POWER6 or later 1182 * and an illegal instruction is encountered. 1183 */ 1184 void __kprobes emulation_assist_interrupt(struct pt_regs *regs) 1185 { 1186 regs->msr |= REASON_ILLEGAL; 1187 program_check_exception(regs); 1188 } 1189 1190 void alignment_exception(struct pt_regs *regs) 1191 { 1192 enum ctx_state prev_state = exception_enter(); 1193 int sig, code, fixed = 0; 1194 1195 /* We restore the interrupt state now */ 1196 if (!arch_irq_disabled_regs(regs)) 1197 local_irq_enable(); 1198 1199 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT)) 1200 goto bail; 1201 1202 /* we don't implement logging of alignment exceptions */ 1203 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) 1204 fixed = fix_alignment(regs); 1205 1206 if (fixed == 1) { 1207 regs->nip += 4; /* skip over emulated instruction */ 1208 emulate_single_step(regs); 1209 goto bail; 1210 } 1211 1212 /* Operand address was bad */ 1213 if (fixed == -EFAULT) { 1214 sig = SIGSEGV; 1215 code = SEGV_ACCERR; 1216 } else { 1217 sig = SIGBUS; 1218 code = BUS_ADRALN; 1219 } 1220 if (user_mode(regs)) 1221 _exception(sig, regs, code, regs->dar); 1222 else 1223 bad_page_fault(regs, regs->dar, sig); 1224 1225 bail: 1226 exception_exit(prev_state); 1227 } 1228 1229 void StackOverflow(struct pt_regs *regs) 1230 { 1231 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", 1232 current, regs->gpr[1]); 1233 debugger(regs); 1234 show_regs(regs); 1235 panic("kernel stack overflow"); 1236 } 1237 1238 void nonrecoverable_exception(struct pt_regs *regs) 1239 { 1240 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", 1241 regs->nip, regs->msr); 1242 debugger(regs); 1243 die("nonrecoverable exception", regs, SIGKILL); 1244 } 1245 1246 void trace_syscall(struct pt_regs *regs) 1247 { 1248 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", 1249 current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0], 1250 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); 1251 } 1252 1253 void kernel_fp_unavailable_exception(struct pt_regs *regs) 1254 { 1255 enum ctx_state prev_state = exception_enter(); 1256 1257 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " 1258 "%lx at %lx\n", regs->trap, regs->nip); 1259 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); 1260 1261 exception_exit(prev_state); 1262 } 1263 1264 void altivec_unavailable_exception(struct pt_regs *regs) 1265 { 1266 enum ctx_state prev_state = exception_enter(); 1267 1268 if (user_mode(regs)) { 1269 /* A user program has executed an altivec instruction, 1270 but this kernel doesn't support altivec. */ 1271 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1272 goto bail; 1273 } 1274 1275 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " 1276 "%lx at %lx\n", regs->trap, regs->nip); 1277 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); 1278 1279 bail: 1280 exception_exit(prev_state); 1281 } 1282 1283 void vsx_unavailable_exception(struct pt_regs *regs) 1284 { 1285 if (user_mode(regs)) { 1286 /* A user program has executed an vsx instruction, 1287 but this kernel doesn't support vsx. */ 1288 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1289 return; 1290 } 1291 1292 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " 1293 "%lx at %lx\n", regs->trap, regs->nip); 1294 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); 1295 } 1296 1297 #ifdef CONFIG_PPC64 1298 void facility_unavailable_exception(struct pt_regs *regs) 1299 { 1300 static char *facility_strings[] = { 1301 [FSCR_FP_LG] = "FPU", 1302 [FSCR_VECVSX_LG] = "VMX/VSX", 1303 [FSCR_DSCR_LG] = "DSCR", 1304 [FSCR_PM_LG] = "PMU SPRs", 1305 [FSCR_BHRB_LG] = "BHRB", 1306 [FSCR_TM_LG] = "TM", 1307 [FSCR_EBB_LG] = "EBB", 1308 [FSCR_TAR_LG] = "TAR", 1309 }; 1310 char *facility = "unknown"; 1311 u64 value; 1312 u8 status; 1313 bool hv; 1314 1315 hv = (regs->trap == 0xf80); 1316 if (hv) 1317 value = mfspr(SPRN_HFSCR); 1318 else 1319 value = mfspr(SPRN_FSCR); 1320 1321 status = value >> 56; 1322 if (status == FSCR_DSCR_LG) { 1323 /* User is acessing the DSCR. Set the inherit bit and allow 1324 * the user to set it directly in future by setting via the 1325 * H/FSCR DSCR bit. 1326 */ 1327 current->thread.dscr_inherit = 1; 1328 if (hv) 1329 mtspr(SPRN_HFSCR, value | HFSCR_DSCR); 1330 else 1331 mtspr(SPRN_FSCR, value | FSCR_DSCR); 1332 return; 1333 } 1334 1335 if ((status < ARRAY_SIZE(facility_strings)) && 1336 facility_strings[status]) 1337 facility = facility_strings[status]; 1338 1339 /* We restore the interrupt state now */ 1340 if (!arch_irq_disabled_regs(regs)) 1341 local_irq_enable(); 1342 1343 pr_err("%sFacility '%s' unavailable, exception at 0x%lx, MSR=%lx\n", 1344 hv ? "Hypervisor " : "", facility, regs->nip, regs->msr); 1345 1346 if (user_mode(regs)) { 1347 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1348 return; 1349 } 1350 1351 die("Unexpected facility unavailable exception", regs, SIGABRT); 1352 } 1353 #endif 1354 1355 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1356 1357 extern void do_load_up_fpu(struct pt_regs *regs); 1358 1359 void fp_unavailable_tm(struct pt_regs *regs) 1360 { 1361 /* Note: This does not handle any kind of FP laziness. */ 1362 1363 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n", 1364 regs->nip, regs->msr); 1365 tm_enable(); 1366 1367 /* We can only have got here if the task started using FP after 1368 * beginning the transaction. So, the transactional regs are just a 1369 * copy of the checkpointed ones. But, we still need to recheckpoint 1370 * as we're enabling FP for the process; it will return, abort the 1371 * transaction, and probably retry but now with FP enabled. So the 1372 * checkpointed FP registers need to be loaded. 1373 */ 1374 tm_reclaim(¤t->thread, current->thread.regs->msr, 1375 TM_CAUSE_FAC_UNAV); 1376 /* Reclaim didn't save out any FPRs to transact_fprs. */ 1377 1378 /* Enable FP for the task: */ 1379 regs->msr |= (MSR_FP | current->thread.fpexc_mode); 1380 1381 /* This loads and recheckpoints the FP registers from 1382 * thread.fpr[]. They will remain in registers after the 1383 * checkpoint so we don't need to reload them after. 1384 */ 1385 tm_recheckpoint(¤t->thread, regs->msr); 1386 } 1387 1388 #ifdef CONFIG_ALTIVEC 1389 extern void do_load_up_altivec(struct pt_regs *regs); 1390 1391 void altivec_unavailable_tm(struct pt_regs *regs) 1392 { 1393 /* See the comments in fp_unavailable_tm(). This function operates 1394 * the same way. 1395 */ 1396 1397 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx," 1398 "MSR=%lx\n", 1399 regs->nip, regs->msr); 1400 tm_enable(); 1401 tm_reclaim(¤t->thread, current->thread.regs->msr, 1402 TM_CAUSE_FAC_UNAV); 1403 regs->msr |= MSR_VEC; 1404 tm_recheckpoint(¤t->thread, regs->msr); 1405 current->thread.used_vr = 1; 1406 } 1407 #endif 1408 1409 #ifdef CONFIG_VSX 1410 void vsx_unavailable_tm(struct pt_regs *regs) 1411 { 1412 /* See the comments in fp_unavailable_tm(). This works similarly, 1413 * though we're loading both FP and VEC registers in here. 1414 * 1415 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC 1416 * regs. Either way, set MSR_VSX. 1417 */ 1418 1419 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx," 1420 "MSR=%lx\n", 1421 regs->nip, regs->msr); 1422 1423 tm_enable(); 1424 /* This reclaims FP and/or VR regs if they're already enabled */ 1425 tm_reclaim(¤t->thread, current->thread.regs->msr, 1426 TM_CAUSE_FAC_UNAV); 1427 1428 regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode | 1429 MSR_VSX; 1430 /* This loads & recheckpoints FP and VRs. */ 1431 tm_recheckpoint(¤t->thread, regs->msr); 1432 current->thread.used_vsr = 1; 1433 } 1434 #endif 1435 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1436 1437 void performance_monitor_exception(struct pt_regs *regs) 1438 { 1439 __get_cpu_var(irq_stat).pmu_irqs++; 1440 1441 perf_irq(regs); 1442 } 1443 1444 #ifdef CONFIG_8xx 1445 void SoftwareEmulation(struct pt_regs *regs) 1446 { 1447 extern int do_mathemu(struct pt_regs *); 1448 #if defined(CONFIG_MATH_EMULATION) 1449 int errcode; 1450 #endif 1451 1452 CHECK_FULL_REGS(regs); 1453 1454 if (!user_mode(regs)) { 1455 debugger(regs); 1456 die("Kernel Mode Software FPU Emulation", regs, SIGFPE); 1457 } 1458 1459 #ifdef CONFIG_MATH_EMULATION 1460 errcode = do_mathemu(regs); 1461 if (errcode >= 0) 1462 PPC_WARN_EMULATED(math, regs); 1463 1464 switch (errcode) { 1465 case 0: 1466 emulate_single_step(regs); 1467 return; 1468 case 1: { 1469 int code = 0; 1470 code = __parse_fpscr(current->thread.fpscr.val); 1471 _exception(SIGFPE, regs, code, regs->nip); 1472 return; 1473 } 1474 case -EFAULT: 1475 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1476 return; 1477 default: 1478 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1479 return; 1480 } 1481 #else 1482 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1483 #endif 1484 } 1485 #endif /* CONFIG_8xx */ 1486 1487 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1488 static void handle_debug(struct pt_regs *regs, unsigned long debug_status) 1489 { 1490 int changed = 0; 1491 /* 1492 * Determine the cause of the debug event, clear the 1493 * event flags and send a trap to the handler. Torez 1494 */ 1495 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { 1496 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); 1497 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1498 current->thread.dbcr2 &= ~DBCR2_DAC12MODE; 1499 #endif 1500 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT, 1501 5); 1502 changed |= 0x01; 1503 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { 1504 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); 1505 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT, 1506 6); 1507 changed |= 0x01; 1508 } else if (debug_status & DBSR_IAC1) { 1509 current->thread.dbcr0 &= ~DBCR0_IAC1; 1510 dbcr_iac_range(current) &= ~DBCR_IAC12MODE; 1511 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT, 1512 1); 1513 changed |= 0x01; 1514 } else if (debug_status & DBSR_IAC2) { 1515 current->thread.dbcr0 &= ~DBCR0_IAC2; 1516 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT, 1517 2); 1518 changed |= 0x01; 1519 } else if (debug_status & DBSR_IAC3) { 1520 current->thread.dbcr0 &= ~DBCR0_IAC3; 1521 dbcr_iac_range(current) &= ~DBCR_IAC34MODE; 1522 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT, 1523 3); 1524 changed |= 0x01; 1525 } else if (debug_status & DBSR_IAC4) { 1526 current->thread.dbcr0 &= ~DBCR0_IAC4; 1527 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT, 1528 4); 1529 changed |= 0x01; 1530 } 1531 /* 1532 * At the point this routine was called, the MSR(DE) was turned off. 1533 * Check all other debug flags and see if that bit needs to be turned 1534 * back on or not. 1535 */ 1536 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1)) 1537 regs->msr |= MSR_DE; 1538 else 1539 /* Make sure the IDM flag is off */ 1540 current->thread.dbcr0 &= ~DBCR0_IDM; 1541 1542 if (changed & 0x01) 1543 mtspr(SPRN_DBCR0, current->thread.dbcr0); 1544 } 1545 1546 void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status) 1547 { 1548 current->thread.dbsr = debug_status; 1549 1550 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while 1551 * on server, it stops on the target of the branch. In order to simulate 1552 * the server behaviour, we thus restart right away with a single step 1553 * instead of stopping here when hitting a BT 1554 */ 1555 if (debug_status & DBSR_BT) { 1556 regs->msr &= ~MSR_DE; 1557 1558 /* Disable BT */ 1559 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); 1560 /* Clear the BT event */ 1561 mtspr(SPRN_DBSR, DBSR_BT); 1562 1563 /* Do the single step trick only when coming from userspace */ 1564 if (user_mode(regs)) { 1565 current->thread.dbcr0 &= ~DBCR0_BT; 1566 current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC; 1567 regs->msr |= MSR_DE; 1568 return; 1569 } 1570 1571 if (notify_die(DIE_SSTEP, "block_step", regs, 5, 1572 5, SIGTRAP) == NOTIFY_STOP) { 1573 return; 1574 } 1575 if (debugger_sstep(regs)) 1576 return; 1577 } else if (debug_status & DBSR_IC) { /* Instruction complete */ 1578 regs->msr &= ~MSR_DE; 1579 1580 /* Disable instruction completion */ 1581 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); 1582 /* Clear the instruction completion event */ 1583 mtspr(SPRN_DBSR, DBSR_IC); 1584 1585 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 1586 5, SIGTRAP) == NOTIFY_STOP) { 1587 return; 1588 } 1589 1590 if (debugger_sstep(regs)) 1591 return; 1592 1593 if (user_mode(regs)) { 1594 current->thread.dbcr0 &= ~DBCR0_IC; 1595 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, 1596 current->thread.dbcr1)) 1597 regs->msr |= MSR_DE; 1598 else 1599 /* Make sure the IDM bit is off */ 1600 current->thread.dbcr0 &= ~DBCR0_IDM; 1601 } 1602 1603 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 1604 } else 1605 handle_debug(regs, debug_status); 1606 } 1607 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 1608 1609 #if !defined(CONFIG_TAU_INT) 1610 void TAUException(struct pt_regs *regs) 1611 { 1612 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", 1613 regs->nip, regs->msr, regs->trap, print_tainted()); 1614 } 1615 #endif /* CONFIG_INT_TAU */ 1616 1617 #ifdef CONFIG_ALTIVEC 1618 void altivec_assist_exception(struct pt_regs *regs) 1619 { 1620 int err; 1621 1622 if (!user_mode(regs)) { 1623 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" 1624 " at %lx\n", regs->nip); 1625 die("Kernel VMX/Altivec assist exception", regs, SIGILL); 1626 } 1627 1628 flush_altivec_to_thread(current); 1629 1630 PPC_WARN_EMULATED(altivec, regs); 1631 err = emulate_altivec(regs); 1632 if (err == 0) { 1633 regs->nip += 4; /* skip emulated instruction */ 1634 emulate_single_step(regs); 1635 return; 1636 } 1637 1638 if (err == -EFAULT) { 1639 /* got an error reading the instruction */ 1640 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 1641 } else { 1642 /* didn't recognize the instruction */ 1643 /* XXX quick hack for now: set the non-Java bit in the VSCR */ 1644 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " 1645 "in %s at %lx\n", current->comm, regs->nip); 1646 current->thread.vscr.u[3] |= 0x10000; 1647 } 1648 } 1649 #endif /* CONFIG_ALTIVEC */ 1650 1651 #ifdef CONFIG_VSX 1652 void vsx_assist_exception(struct pt_regs *regs) 1653 { 1654 if (!user_mode(regs)) { 1655 printk(KERN_EMERG "VSX assist exception in kernel mode" 1656 " at %lx\n", regs->nip); 1657 die("Kernel VSX assist exception", regs, SIGILL); 1658 } 1659 1660 flush_vsx_to_thread(current); 1661 printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip); 1662 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1663 } 1664 #endif /* CONFIG_VSX */ 1665 1666 #ifdef CONFIG_FSL_BOOKE 1667 void CacheLockingException(struct pt_regs *regs, unsigned long address, 1668 unsigned long error_code) 1669 { 1670 /* We treat cache locking instructions from the user 1671 * as priv ops, in the future we could try to do 1672 * something smarter 1673 */ 1674 if (error_code & (ESR_DLK|ESR_ILK)) 1675 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 1676 return; 1677 } 1678 #endif /* CONFIG_FSL_BOOKE */ 1679 1680 #ifdef CONFIG_SPE 1681 void SPEFloatingPointException(struct pt_regs *regs) 1682 { 1683 extern int do_spe_mathemu(struct pt_regs *regs); 1684 unsigned long spefscr; 1685 int fpexc_mode; 1686 int code = 0; 1687 int err; 1688 1689 flush_spe_to_thread(current); 1690 1691 spefscr = current->thread.spefscr; 1692 fpexc_mode = current->thread.fpexc_mode; 1693 1694 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { 1695 code = FPE_FLTOVF; 1696 } 1697 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { 1698 code = FPE_FLTUND; 1699 } 1700 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) 1701 code = FPE_FLTDIV; 1702 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { 1703 code = FPE_FLTINV; 1704 } 1705 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) 1706 code = FPE_FLTRES; 1707 1708 err = do_spe_mathemu(regs); 1709 if (err == 0) { 1710 regs->nip += 4; /* skip emulated instruction */ 1711 emulate_single_step(regs); 1712 return; 1713 } 1714 1715 if (err == -EFAULT) { 1716 /* got an error reading the instruction */ 1717 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 1718 } else if (err == -EINVAL) { 1719 /* didn't recognize the instruction */ 1720 printk(KERN_ERR "unrecognized spe instruction " 1721 "in %s at %lx\n", current->comm, regs->nip); 1722 } else { 1723 _exception(SIGFPE, regs, code, regs->nip); 1724 } 1725 1726 return; 1727 } 1728 1729 void SPEFloatingPointRoundException(struct pt_regs *regs) 1730 { 1731 extern int speround_handler(struct pt_regs *regs); 1732 int err; 1733 1734 preempt_disable(); 1735 if (regs->msr & MSR_SPE) 1736 giveup_spe(current); 1737 preempt_enable(); 1738 1739 regs->nip -= 4; 1740 err = speround_handler(regs); 1741 if (err == 0) { 1742 regs->nip += 4; /* skip emulated instruction */ 1743 emulate_single_step(regs); 1744 return; 1745 } 1746 1747 if (err == -EFAULT) { 1748 /* got an error reading the instruction */ 1749 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 1750 } else if (err == -EINVAL) { 1751 /* didn't recognize the instruction */ 1752 printk(KERN_ERR "unrecognized spe instruction " 1753 "in %s at %lx\n", current->comm, regs->nip); 1754 } else { 1755 _exception(SIGFPE, regs, 0, regs->nip); 1756 return; 1757 } 1758 } 1759 #endif 1760 1761 /* 1762 * We enter here if we get an unrecoverable exception, that is, one 1763 * that happened at a point where the RI (recoverable interrupt) bit 1764 * in the MSR is 0. This indicates that SRR0/1 are live, and that 1765 * we therefore lost state by taking this exception. 1766 */ 1767 void unrecoverable_exception(struct pt_regs *regs) 1768 { 1769 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", 1770 regs->trap, regs->nip); 1771 die("Unrecoverable exception", regs, SIGABRT); 1772 } 1773 1774 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x) 1775 /* 1776 * Default handler for a Watchdog exception, 1777 * spins until a reboot occurs 1778 */ 1779 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) 1780 { 1781 /* Generic WatchdogHandler, implement your own */ 1782 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); 1783 return; 1784 } 1785 1786 void WatchdogException(struct pt_regs *regs) 1787 { 1788 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); 1789 WatchdogHandler(regs); 1790 } 1791 #endif 1792 1793 /* 1794 * We enter here if we discover during exception entry that we are 1795 * running in supervisor mode with a userspace value in the stack pointer. 1796 */ 1797 void kernel_bad_stack(struct pt_regs *regs) 1798 { 1799 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", 1800 regs->gpr[1], regs->nip); 1801 die("Bad kernel stack pointer", regs, SIGABRT); 1802 } 1803 1804 void __init trap_init(void) 1805 { 1806 } 1807 1808 1809 #ifdef CONFIG_PPC_EMULATED_STATS 1810 1811 #define WARN_EMULATED_SETUP(type) .type = { .name = #type } 1812 1813 struct ppc_emulated ppc_emulated = { 1814 #ifdef CONFIG_ALTIVEC 1815 WARN_EMULATED_SETUP(altivec), 1816 #endif 1817 WARN_EMULATED_SETUP(dcba), 1818 WARN_EMULATED_SETUP(dcbz), 1819 WARN_EMULATED_SETUP(fp_pair), 1820 WARN_EMULATED_SETUP(isel), 1821 WARN_EMULATED_SETUP(mcrxr), 1822 WARN_EMULATED_SETUP(mfpvr), 1823 WARN_EMULATED_SETUP(multiple), 1824 WARN_EMULATED_SETUP(popcntb), 1825 WARN_EMULATED_SETUP(spe), 1826 WARN_EMULATED_SETUP(string), 1827 WARN_EMULATED_SETUP(unaligned), 1828 #ifdef CONFIG_MATH_EMULATION 1829 WARN_EMULATED_SETUP(math), 1830 #endif 1831 #ifdef CONFIG_VSX 1832 WARN_EMULATED_SETUP(vsx), 1833 #endif 1834 #ifdef CONFIG_PPC64 1835 WARN_EMULATED_SETUP(mfdscr), 1836 WARN_EMULATED_SETUP(mtdscr), 1837 #endif 1838 }; 1839 1840 u32 ppc_warn_emulated; 1841 1842 void ppc_warn_emulated_print(const char *type) 1843 { 1844 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, 1845 type); 1846 } 1847 1848 static int __init ppc_warn_emulated_init(void) 1849 { 1850 struct dentry *dir, *d; 1851 unsigned int i; 1852 struct ppc_emulated_entry *entries = (void *)&ppc_emulated; 1853 1854 if (!powerpc_debugfs_root) 1855 return -ENODEV; 1856 1857 dir = debugfs_create_dir("emulated_instructions", 1858 powerpc_debugfs_root); 1859 if (!dir) 1860 return -ENOMEM; 1861 1862 d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir, 1863 &ppc_warn_emulated); 1864 if (!d) 1865 goto fail; 1866 1867 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { 1868 d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir, 1869 (u32 *)&entries[i].val.counter); 1870 if (!d) 1871 goto fail; 1872 } 1873 1874 return 0; 1875 1876 fail: 1877 debugfs_remove_recursive(dir); 1878 return -ENOMEM; 1879 } 1880 1881 device_initcall(ppc_warn_emulated_init); 1882 1883 #endif /* CONFIG_PPC_EMULATED_STATS */ 1884