1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * Copyright 2007-2010 Freescale Semiconductor, Inc. 5 * 6 * Modified by Cort Dougan (cort@cs.nmt.edu) 7 * and Paul Mackerras (paulus@samba.org) 8 */ 9 10 /* 11 * This file handles the architecture-dependent parts of hardware exceptions 12 */ 13 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/sched/debug.h> 17 #include <linux/kernel.h> 18 #include <linux/mm.h> 19 #include <linux/pkeys.h> 20 #include <linux/stddef.h> 21 #include <linux/unistd.h> 22 #include <linux/ptrace.h> 23 #include <linux/user.h> 24 #include <linux/interrupt.h> 25 #include <linux/init.h> 26 #include <linux/extable.h> 27 #include <linux/module.h> /* print_modules */ 28 #include <linux/prctl.h> 29 #include <linux/delay.h> 30 #include <linux/kprobes.h> 31 #include <linux/kexec.h> 32 #include <linux/backlight.h> 33 #include <linux/bug.h> 34 #include <linux/kdebug.h> 35 #include <linux/ratelimit.h> 36 #include <linux/context_tracking.h> 37 #include <linux/smp.h> 38 #include <linux/console.h> 39 #include <linux/kmsg_dump.h> 40 #include <linux/debugfs.h> 41 42 #include <asm/emulated_ops.h> 43 #include <linux/uaccess.h> 44 #include <asm/interrupt.h> 45 #include <asm/io.h> 46 #include <asm/machdep.h> 47 #include <asm/rtas.h> 48 #include <asm/pmc.h> 49 #include <asm/reg.h> 50 #ifdef CONFIG_PMAC_BACKLIGHT 51 #include <asm/backlight.h> 52 #endif 53 #ifdef CONFIG_PPC64 54 #include <asm/firmware.h> 55 #include <asm/processor.h> 56 #endif 57 #include <asm/kexec.h> 58 #include <asm/ppc-opcode.h> 59 #include <asm/rio.h> 60 #include <asm/fadump.h> 61 #include <asm/switch_to.h> 62 #include <asm/tm.h> 63 #include <asm/debug.h> 64 #include <asm/asm-prototypes.h> 65 #include <asm/hmi.h> 66 #include <sysdev/fsl_pci.h> 67 #include <asm/kprobes.h> 68 #include <asm/stacktrace.h> 69 #include <asm/nmi.h> 70 #include <asm/disassemble.h> 71 72 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE) 73 int (*__debugger)(struct pt_regs *regs) __read_mostly; 74 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; 75 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; 76 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; 77 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; 78 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly; 79 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; 80 81 EXPORT_SYMBOL(__debugger); 82 EXPORT_SYMBOL(__debugger_ipi); 83 EXPORT_SYMBOL(__debugger_bpt); 84 EXPORT_SYMBOL(__debugger_sstep); 85 EXPORT_SYMBOL(__debugger_iabr_match); 86 EXPORT_SYMBOL(__debugger_break_match); 87 EXPORT_SYMBOL(__debugger_fault_handler); 88 #endif 89 90 /* Transactional Memory trap debug */ 91 #ifdef TM_DEBUG_SW 92 #define TM_DEBUG(x...) printk(KERN_INFO x) 93 #else 94 #define TM_DEBUG(x...) do { } while(0) 95 #endif 96 97 static const char *signame(int signr) 98 { 99 switch (signr) { 100 case SIGBUS: return "bus error"; 101 case SIGFPE: return "floating point exception"; 102 case SIGILL: return "illegal instruction"; 103 case SIGSEGV: return "segfault"; 104 case SIGTRAP: return "unhandled trap"; 105 } 106 107 return "unknown signal"; 108 } 109 110 /* 111 * Trap & Exception support 112 */ 113 114 #ifdef CONFIG_PMAC_BACKLIGHT 115 static void pmac_backlight_unblank(void) 116 { 117 mutex_lock(&pmac_backlight_mutex); 118 if (pmac_backlight) { 119 struct backlight_properties *props; 120 121 props = &pmac_backlight->props; 122 props->brightness = props->max_brightness; 123 props->power = FB_BLANK_UNBLANK; 124 backlight_update_status(pmac_backlight); 125 } 126 mutex_unlock(&pmac_backlight_mutex); 127 } 128 #else 129 static inline void pmac_backlight_unblank(void) { } 130 #endif 131 132 /* 133 * If oops/die is expected to crash the machine, return true here. 134 * 135 * This should not be expected to be 100% accurate, there may be 136 * notifiers registered or other unexpected conditions that may bring 137 * down the kernel. Or if the current process in the kernel is holding 138 * locks or has other critical state, the kernel may become effectively 139 * unusable anyway. 140 */ 141 bool die_will_crash(void) 142 { 143 if (should_fadump_crash()) 144 return true; 145 if (kexec_should_crash(current)) 146 return true; 147 if (in_interrupt() || panic_on_oops || 148 !current->pid || is_global_init(current)) 149 return true; 150 151 return false; 152 } 153 154 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; 155 static int die_owner = -1; 156 static unsigned int die_nest_count; 157 static int die_counter; 158 159 extern void panic_flush_kmsg_start(void) 160 { 161 /* 162 * These are mostly taken from kernel/panic.c, but tries to do 163 * relatively minimal work. Don't use delay functions (TB may 164 * be broken), don't crash dump (need to set a firmware log), 165 * don't run notifiers. We do want to get some information to 166 * Linux console. 167 */ 168 console_verbose(); 169 bust_spinlocks(1); 170 } 171 172 extern void panic_flush_kmsg_end(void) 173 { 174 kmsg_dump(KMSG_DUMP_PANIC); 175 bust_spinlocks(0); 176 debug_locks_off(); 177 console_flush_on_panic(CONSOLE_FLUSH_PENDING); 178 } 179 180 static unsigned long oops_begin(struct pt_regs *regs) 181 { 182 int cpu; 183 unsigned long flags; 184 185 oops_enter(); 186 187 /* racy, but better than risking deadlock. */ 188 raw_local_irq_save(flags); 189 cpu = smp_processor_id(); 190 if (!arch_spin_trylock(&die_lock)) { 191 if (cpu == die_owner) 192 /* nested oops. should stop eventually */; 193 else 194 arch_spin_lock(&die_lock); 195 } 196 die_nest_count++; 197 die_owner = cpu; 198 console_verbose(); 199 bust_spinlocks(1); 200 if (machine_is(powermac)) 201 pmac_backlight_unblank(); 202 return flags; 203 } 204 NOKPROBE_SYMBOL(oops_begin); 205 206 static void oops_end(unsigned long flags, struct pt_regs *regs, 207 int signr) 208 { 209 bust_spinlocks(0); 210 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 211 die_nest_count--; 212 oops_exit(); 213 printk("\n"); 214 if (!die_nest_count) { 215 /* Nest count reaches zero, release the lock. */ 216 die_owner = -1; 217 arch_spin_unlock(&die_lock); 218 } 219 raw_local_irq_restore(flags); 220 221 /* 222 * system_reset_excption handles debugger, crash dump, panic, for 0x100 223 */ 224 if (TRAP(regs) == INTERRUPT_SYSTEM_RESET) 225 return; 226 227 crash_fadump(regs, "die oops"); 228 229 if (kexec_should_crash(current)) 230 crash_kexec(regs); 231 232 if (!signr) 233 return; 234 235 /* 236 * While our oops output is serialised by a spinlock, output 237 * from panic() called below can race and corrupt it. If we 238 * know we are going to panic, delay for 1 second so we have a 239 * chance to get clean backtraces from all CPUs that are oopsing. 240 */ 241 if (in_interrupt() || panic_on_oops || !current->pid || 242 is_global_init(current)) { 243 mdelay(MSEC_PER_SEC); 244 } 245 246 if (panic_on_oops) 247 panic("Fatal exception"); 248 do_exit(signr); 249 } 250 NOKPROBE_SYMBOL(oops_end); 251 252 static char *get_mmu_str(void) 253 { 254 if (early_radix_enabled()) 255 return " MMU=Radix"; 256 if (early_mmu_has_feature(MMU_FTR_HPTE_TABLE)) 257 return " MMU=Hash"; 258 return ""; 259 } 260 261 static int __die(const char *str, struct pt_regs *regs, long err) 262 { 263 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); 264 265 printk("%s PAGE_SIZE=%luK%s%s%s%s%s%s %s\n", 266 IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN) ? "LE" : "BE", 267 PAGE_SIZE / 1024, get_mmu_str(), 268 IS_ENABLED(CONFIG_PREEMPT) ? " PREEMPT" : "", 269 IS_ENABLED(CONFIG_SMP) ? " SMP" : "", 270 IS_ENABLED(CONFIG_SMP) ? (" NR_CPUS=" __stringify(NR_CPUS)) : "", 271 debug_pagealloc_enabled() ? " DEBUG_PAGEALLOC" : "", 272 IS_ENABLED(CONFIG_NUMA) ? " NUMA" : "", 273 ppc_md.name ? ppc_md.name : ""); 274 275 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP) 276 return 1; 277 278 print_modules(); 279 show_regs(regs); 280 281 return 0; 282 } 283 NOKPROBE_SYMBOL(__die); 284 285 void die(const char *str, struct pt_regs *regs, long err) 286 { 287 unsigned long flags; 288 289 /* 290 * system_reset_excption handles debugger, crash dump, panic, for 0x100 291 */ 292 if (TRAP(regs) != INTERRUPT_SYSTEM_RESET) { 293 if (debugger(regs)) 294 return; 295 } 296 297 flags = oops_begin(regs); 298 if (__die(str, regs, err)) 299 err = 0; 300 oops_end(flags, regs, err); 301 } 302 NOKPROBE_SYMBOL(die); 303 304 void user_single_step_report(struct pt_regs *regs) 305 { 306 force_sig_fault(SIGTRAP, TRAP_TRACE, (void __user *)regs->nip); 307 } 308 309 static void show_signal_msg(int signr, struct pt_regs *regs, int code, 310 unsigned long addr) 311 { 312 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, 313 DEFAULT_RATELIMIT_BURST); 314 315 if (!show_unhandled_signals) 316 return; 317 318 if (!unhandled_signal(current, signr)) 319 return; 320 321 if (!__ratelimit(&rs)) 322 return; 323 324 pr_info("%s[%d]: %s (%d) at %lx nip %lx lr %lx code %x", 325 current->comm, current->pid, signame(signr), signr, 326 addr, regs->nip, regs->link, code); 327 328 print_vma_addr(KERN_CONT " in ", regs->nip); 329 330 pr_cont("\n"); 331 332 show_user_instructions(regs); 333 } 334 335 static bool exception_common(int signr, struct pt_regs *regs, int code, 336 unsigned long addr) 337 { 338 if (!user_mode(regs)) { 339 die("Exception in kernel mode", regs, signr); 340 return false; 341 } 342 343 /* 344 * Must not enable interrupts even for user-mode exception, because 345 * this can be called from machine check, which may be a NMI or IRQ 346 * which don't like interrupts being enabled. Could check for 347 * in_hardirq || in_nmi perhaps, but there doesn't seem to be a good 348 * reason why _exception() should enable irqs for an exception handler, 349 * the handlers themselves do that directly. 350 */ 351 352 show_signal_msg(signr, regs, code, addr); 353 354 current->thread.trap_nr = code; 355 356 return true; 357 } 358 359 void _exception_pkey(struct pt_regs *regs, unsigned long addr, int key) 360 { 361 if (!exception_common(SIGSEGV, regs, SEGV_PKUERR, addr)) 362 return; 363 364 force_sig_pkuerr((void __user *) addr, key); 365 } 366 367 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) 368 { 369 if (!exception_common(signr, regs, code, addr)) 370 return; 371 372 force_sig_fault(signr, code, (void __user *)addr); 373 } 374 375 /* 376 * The interrupt architecture has a quirk in that the HV interrupts excluding 377 * the NMIs (0x100 and 0x200) do not clear MSR[RI] at entry. The first thing 378 * that an interrupt handler must do is save off a GPR into a scratch register, 379 * and all interrupts on POWERNV (HV=1) use the HSPRG1 register as scratch. 380 * Therefore an NMI can clobber an HV interrupt's live HSPRG1 without noticing 381 * that it is non-reentrant, which leads to random data corruption. 382 * 383 * The solution is for NMI interrupts in HV mode to check if they originated 384 * from these critical HV interrupt regions. If so, then mark them not 385 * recoverable. 386 * 387 * An alternative would be for HV NMIs to use SPRG for scratch to avoid the 388 * HSPRG1 clobber, however this would cause guest SPRG to be clobbered. Linux 389 * guests should always have MSR[RI]=0 when its scratch SPRG is in use, so 390 * that would work. However any other guest OS that may have the SPRG live 391 * and MSR[RI]=1 could encounter silent corruption. 392 * 393 * Builds that do not support KVM could take this second option to increase 394 * the recoverability of NMIs. 395 */ 396 void hv_nmi_check_nonrecoverable(struct pt_regs *regs) 397 { 398 #ifdef CONFIG_PPC_POWERNV 399 unsigned long kbase = (unsigned long)_stext; 400 unsigned long nip = regs->nip; 401 402 if (!(regs->msr & MSR_RI)) 403 return; 404 if (!(regs->msr & MSR_HV)) 405 return; 406 if (regs->msr & MSR_PR) 407 return; 408 409 /* 410 * Now test if the interrupt has hit a range that may be using 411 * HSPRG1 without having RI=0 (i.e., an HSRR interrupt). The 412 * problem ranges all run un-relocated. Test real and virt modes 413 * at the same time by dropping the high bit of the nip (virt mode 414 * entry points still have the +0x4000 offset). 415 */ 416 nip &= ~0xc000000000000000ULL; 417 if ((nip >= 0x500 && nip < 0x600) || (nip >= 0x4500 && nip < 0x4600)) 418 goto nonrecoverable; 419 if ((nip >= 0x980 && nip < 0xa00) || (nip >= 0x4980 && nip < 0x4a00)) 420 goto nonrecoverable; 421 if ((nip >= 0xe00 && nip < 0xec0) || (nip >= 0x4e00 && nip < 0x4ec0)) 422 goto nonrecoverable; 423 if ((nip >= 0xf80 && nip < 0xfa0) || (nip >= 0x4f80 && nip < 0x4fa0)) 424 goto nonrecoverable; 425 426 /* Trampoline code runs un-relocated so subtract kbase. */ 427 if (nip >= (unsigned long)(start_real_trampolines - kbase) && 428 nip < (unsigned long)(end_real_trampolines - kbase)) 429 goto nonrecoverable; 430 if (nip >= (unsigned long)(start_virt_trampolines - kbase) && 431 nip < (unsigned long)(end_virt_trampolines - kbase)) 432 goto nonrecoverable; 433 return; 434 435 nonrecoverable: 436 regs_set_unrecoverable(regs); 437 #endif 438 } 439 DEFINE_INTERRUPT_HANDLER_NMI(system_reset_exception) 440 { 441 unsigned long hsrr0, hsrr1; 442 bool saved_hsrrs = false; 443 444 /* 445 * System reset can interrupt code where HSRRs are live and MSR[RI]=1. 446 * The system reset interrupt itself may clobber HSRRs (e.g., to call 447 * OPAL), so save them here and restore them before returning. 448 * 449 * Machine checks don't need to save HSRRs, as the real mode handler 450 * is careful to avoid them, and the regular handler is not delivered 451 * as an NMI. 452 */ 453 if (cpu_has_feature(CPU_FTR_HVMODE)) { 454 hsrr0 = mfspr(SPRN_HSRR0); 455 hsrr1 = mfspr(SPRN_HSRR1); 456 saved_hsrrs = true; 457 } 458 459 hv_nmi_check_nonrecoverable(regs); 460 461 __this_cpu_inc(irq_stat.sreset_irqs); 462 463 /* See if any machine dependent calls */ 464 if (ppc_md.system_reset_exception) { 465 if (ppc_md.system_reset_exception(regs)) 466 goto out; 467 } 468 469 if (debugger(regs)) 470 goto out; 471 472 kmsg_dump(KMSG_DUMP_OOPS); 473 /* 474 * A system reset is a request to dump, so we always send 475 * it through the crashdump code (if fadump or kdump are 476 * registered). 477 */ 478 crash_fadump(regs, "System Reset"); 479 480 crash_kexec(regs); 481 482 /* 483 * We aren't the primary crash CPU. We need to send it 484 * to a holding pattern to avoid it ending up in the panic 485 * code. 486 */ 487 crash_kexec_secondary(regs); 488 489 /* 490 * No debugger or crash dump registered, print logs then 491 * panic. 492 */ 493 die("System Reset", regs, SIGABRT); 494 495 mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */ 496 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 497 nmi_panic(regs, "System Reset"); 498 499 out: 500 #ifdef CONFIG_PPC_BOOK3S_64 501 BUG_ON(get_paca()->in_nmi == 0); 502 if (get_paca()->in_nmi > 1) 503 die("Unrecoverable nested System Reset", regs, SIGABRT); 504 #endif 505 /* Must die if the interrupt is not recoverable */ 506 if (regs_is_unrecoverable(regs)) { 507 /* For the reason explained in die_mce, nmi_exit before die */ 508 nmi_exit(); 509 die("Unrecoverable System Reset", regs, SIGABRT); 510 } 511 512 if (saved_hsrrs) { 513 mtspr(SPRN_HSRR0, hsrr0); 514 mtspr(SPRN_HSRR1, hsrr1); 515 } 516 517 /* What should we do here? We could issue a shutdown or hard reset. */ 518 519 return 0; 520 } 521 522 /* 523 * I/O accesses can cause machine checks on powermacs. 524 * Check if the NIP corresponds to the address of a sync 525 * instruction for which there is an entry in the exception 526 * table. 527 * -- paulus. 528 */ 529 static inline int check_io_access(struct pt_regs *regs) 530 { 531 #ifdef CONFIG_PPC32 532 unsigned long msr = regs->msr; 533 const struct exception_table_entry *entry; 534 unsigned int *nip = (unsigned int *)regs->nip; 535 536 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) 537 && (entry = search_exception_tables(regs->nip)) != NULL) { 538 /* 539 * Check that it's a sync instruction, or somewhere 540 * in the twi; isync; nop sequence that inb/inw/inl uses. 541 * As the address is in the exception table 542 * we should be able to read the instr there. 543 * For the debug message, we look at the preceding 544 * load or store. 545 */ 546 if (*nip == PPC_RAW_NOP()) 547 nip -= 2; 548 else if (*nip == PPC_RAW_ISYNC()) 549 --nip; 550 if (*nip == PPC_RAW_SYNC() || get_op(*nip) == OP_TRAP) { 551 unsigned int rb; 552 553 --nip; 554 rb = (*nip >> 11) & 0x1f; 555 printk(KERN_DEBUG "%s bad port %lx at %p\n", 556 (*nip & 0x100)? "OUT to": "IN from", 557 regs->gpr[rb] - _IO_BASE, nip); 558 regs_set_recoverable(regs); 559 regs_set_return_ip(regs, extable_fixup(entry)); 560 return 1; 561 } 562 } 563 #endif /* CONFIG_PPC32 */ 564 return 0; 565 } 566 567 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 568 /* On 4xx, the reason for the machine check or program exception 569 is in the ESR. */ 570 #define get_reason(regs) ((regs)->esr) 571 #define REASON_FP ESR_FP 572 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) 573 #define REASON_PRIVILEGED ESR_PPR 574 #define REASON_TRAP ESR_PTR 575 #define REASON_PREFIXED 0 576 #define REASON_BOUNDARY 0 577 578 /* single-step stuff */ 579 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC) 580 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC) 581 #define clear_br_trace(regs) do {} while(0) 582 #else 583 /* On non-4xx, the reason for the machine check or program 584 exception is in the MSR. */ 585 #define get_reason(regs) ((regs)->msr) 586 #define REASON_TM SRR1_PROGTM 587 #define REASON_FP SRR1_PROGFPE 588 #define REASON_ILLEGAL SRR1_PROGILL 589 #define REASON_PRIVILEGED SRR1_PROGPRIV 590 #define REASON_TRAP SRR1_PROGTRAP 591 #define REASON_PREFIXED SRR1_PREFIXED 592 #define REASON_BOUNDARY SRR1_BOUNDARY 593 594 #define single_stepping(regs) ((regs)->msr & MSR_SE) 595 #define clear_single_step(regs) (regs_set_return_msr((regs), (regs)->msr & ~MSR_SE)) 596 #define clear_br_trace(regs) (regs_set_return_msr((regs), (regs)->msr & ~MSR_BE)) 597 #endif 598 599 #define inst_length(reason) (((reason) & REASON_PREFIXED) ? 8 : 4) 600 601 #if defined(CONFIG_E500) 602 int machine_check_e500mc(struct pt_regs *regs) 603 { 604 unsigned long mcsr = mfspr(SPRN_MCSR); 605 unsigned long pvr = mfspr(SPRN_PVR); 606 unsigned long reason = mcsr; 607 int recoverable = 1; 608 609 if (reason & MCSR_LD) { 610 recoverable = fsl_rio_mcheck_exception(regs); 611 if (recoverable == 1) 612 goto silent_out; 613 } 614 615 printk("Machine check in kernel mode.\n"); 616 printk("Caused by (from MCSR=%lx): ", reason); 617 618 if (reason & MCSR_MCP) 619 pr_cont("Machine Check Signal\n"); 620 621 if (reason & MCSR_ICPERR) { 622 pr_cont("Instruction Cache Parity Error\n"); 623 624 /* 625 * This is recoverable by invalidating the i-cache. 626 */ 627 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); 628 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) 629 ; 630 631 /* 632 * This will generally be accompanied by an instruction 633 * fetch error report -- only treat MCSR_IF as fatal 634 * if it wasn't due to an L1 parity error. 635 */ 636 reason &= ~MCSR_IF; 637 } 638 639 if (reason & MCSR_DCPERR_MC) { 640 pr_cont("Data Cache Parity Error\n"); 641 642 /* 643 * In write shadow mode we auto-recover from the error, but it 644 * may still get logged and cause a machine check. We should 645 * only treat the non-write shadow case as non-recoverable. 646 */ 647 /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit 648 * is not implemented but L1 data cache always runs in write 649 * shadow mode. Hence on data cache parity errors HW will 650 * automatically invalidate the L1 Data Cache. 651 */ 652 if (PVR_VER(pvr) != PVR_VER_E6500) { 653 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) 654 recoverable = 0; 655 } 656 } 657 658 if (reason & MCSR_L2MMU_MHIT) { 659 pr_cont("Hit on multiple TLB entries\n"); 660 recoverable = 0; 661 } 662 663 if (reason & MCSR_NMI) 664 pr_cont("Non-maskable interrupt\n"); 665 666 if (reason & MCSR_IF) { 667 pr_cont("Instruction Fetch Error Report\n"); 668 recoverable = 0; 669 } 670 671 if (reason & MCSR_LD) { 672 pr_cont("Load Error Report\n"); 673 recoverable = 0; 674 } 675 676 if (reason & MCSR_ST) { 677 pr_cont("Store Error Report\n"); 678 recoverable = 0; 679 } 680 681 if (reason & MCSR_LDG) { 682 pr_cont("Guarded Load Error Report\n"); 683 recoverable = 0; 684 } 685 686 if (reason & MCSR_TLBSYNC) 687 pr_cont("Simultaneous tlbsync operations\n"); 688 689 if (reason & MCSR_BSL2_ERR) { 690 pr_cont("Level 2 Cache Error\n"); 691 recoverable = 0; 692 } 693 694 if (reason & MCSR_MAV) { 695 u64 addr; 696 697 addr = mfspr(SPRN_MCAR); 698 addr |= (u64)mfspr(SPRN_MCARU) << 32; 699 700 pr_cont("Machine Check %s Address: %#llx\n", 701 reason & MCSR_MEA ? "Effective" : "Physical", addr); 702 } 703 704 silent_out: 705 mtspr(SPRN_MCSR, mcsr); 706 return mfspr(SPRN_MCSR) == 0 && recoverable; 707 } 708 709 int machine_check_e500(struct pt_regs *regs) 710 { 711 unsigned long reason = mfspr(SPRN_MCSR); 712 713 if (reason & MCSR_BUS_RBERR) { 714 if (fsl_rio_mcheck_exception(regs)) 715 return 1; 716 if (fsl_pci_mcheck_exception(regs)) 717 return 1; 718 } 719 720 printk("Machine check in kernel mode.\n"); 721 printk("Caused by (from MCSR=%lx): ", reason); 722 723 if (reason & MCSR_MCP) 724 pr_cont("Machine Check Signal\n"); 725 if (reason & MCSR_ICPERR) 726 pr_cont("Instruction Cache Parity Error\n"); 727 if (reason & MCSR_DCP_PERR) 728 pr_cont("Data Cache Push Parity Error\n"); 729 if (reason & MCSR_DCPERR) 730 pr_cont("Data Cache Parity Error\n"); 731 if (reason & MCSR_BUS_IAERR) 732 pr_cont("Bus - Instruction Address Error\n"); 733 if (reason & MCSR_BUS_RAERR) 734 pr_cont("Bus - Read Address Error\n"); 735 if (reason & MCSR_BUS_WAERR) 736 pr_cont("Bus - Write Address Error\n"); 737 if (reason & MCSR_BUS_IBERR) 738 pr_cont("Bus - Instruction Data Error\n"); 739 if (reason & MCSR_BUS_RBERR) 740 pr_cont("Bus - Read Data Bus Error\n"); 741 if (reason & MCSR_BUS_WBERR) 742 pr_cont("Bus - Write Data Bus Error\n"); 743 if (reason & MCSR_BUS_IPERR) 744 pr_cont("Bus - Instruction Parity Error\n"); 745 if (reason & MCSR_BUS_RPERR) 746 pr_cont("Bus - Read Parity Error\n"); 747 748 return 0; 749 } 750 751 int machine_check_generic(struct pt_regs *regs) 752 { 753 return 0; 754 } 755 #elif defined(CONFIG_PPC32) 756 int machine_check_generic(struct pt_regs *regs) 757 { 758 unsigned long reason = regs->msr; 759 760 printk("Machine check in kernel mode.\n"); 761 printk("Caused by (from SRR1=%lx): ", reason); 762 switch (reason & 0x601F0000) { 763 case 0x80000: 764 pr_cont("Machine check signal\n"); 765 break; 766 case 0x40000: 767 case 0x140000: /* 7450 MSS error and TEA */ 768 pr_cont("Transfer error ack signal\n"); 769 break; 770 case 0x20000: 771 pr_cont("Data parity error signal\n"); 772 break; 773 case 0x10000: 774 pr_cont("Address parity error signal\n"); 775 break; 776 case 0x20000000: 777 pr_cont("L1 Data Cache error\n"); 778 break; 779 case 0x40000000: 780 pr_cont("L1 Instruction Cache error\n"); 781 break; 782 case 0x00100000: 783 pr_cont("L2 data cache parity error\n"); 784 break; 785 default: 786 pr_cont("Unknown values in msr\n"); 787 } 788 return 0; 789 } 790 #endif /* everything else */ 791 792 void die_mce(const char *str, struct pt_regs *regs, long err) 793 { 794 /* 795 * The machine check wants to kill the interrupted context, but 796 * do_exit() checks for in_interrupt() and panics in that case, so 797 * exit the irq/nmi before calling die. 798 */ 799 if (in_nmi()) 800 nmi_exit(); 801 else 802 irq_exit(); 803 die(str, regs, err); 804 } 805 806 /* 807 * BOOK3S_64 does not usually call this handler as a non-maskable interrupt 808 * (it uses its own early real-mode handler to handle the MCE proper 809 * and then raises irq_work to call this handler when interrupts are 810 * enabled). The only time when this is not true is if the early handler 811 * is unrecoverable, then it does call this directly to try to get a 812 * message out. 813 */ 814 static void __machine_check_exception(struct pt_regs *regs) 815 { 816 int recover = 0; 817 818 __this_cpu_inc(irq_stat.mce_exceptions); 819 820 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 821 822 /* See if any machine dependent calls. In theory, we would want 823 * to call the CPU first, and call the ppc_md. one if the CPU 824 * one returns a positive number. However there is existing code 825 * that assumes the board gets a first chance, so let's keep it 826 * that way for now and fix things later. --BenH. 827 */ 828 if (ppc_md.machine_check_exception) 829 recover = ppc_md.machine_check_exception(regs); 830 else if (cur_cpu_spec->machine_check) 831 recover = cur_cpu_spec->machine_check(regs); 832 833 if (recover > 0) 834 goto bail; 835 836 if (debugger_fault_handler(regs)) 837 goto bail; 838 839 if (check_io_access(regs)) 840 goto bail; 841 842 die_mce("Machine check", regs, SIGBUS); 843 844 bail: 845 /* Must die if the interrupt is not recoverable */ 846 if (regs_is_unrecoverable(regs)) 847 die_mce("Unrecoverable Machine check", regs, SIGBUS); 848 } 849 850 #ifdef CONFIG_PPC_BOOK3S_64 851 DEFINE_INTERRUPT_HANDLER_ASYNC(machine_check_exception_async) 852 { 853 __machine_check_exception(regs); 854 } 855 #endif 856 DEFINE_INTERRUPT_HANDLER_NMI(machine_check_exception) 857 { 858 __machine_check_exception(regs); 859 860 return 0; 861 } 862 863 DEFINE_INTERRUPT_HANDLER(SMIException) /* async? */ 864 { 865 die("System Management Interrupt", regs, SIGABRT); 866 } 867 868 #ifdef CONFIG_VSX 869 static void p9_hmi_special_emu(struct pt_regs *regs) 870 { 871 unsigned int ra, rb, t, i, sel, instr, rc; 872 const void __user *addr; 873 u8 vbuf[16] __aligned(16), *vdst; 874 unsigned long ea, msr, msr_mask; 875 bool swap; 876 877 if (__get_user(instr, (unsigned int __user *)regs->nip)) 878 return; 879 880 /* 881 * lxvb16x opcode: 0x7c0006d8 882 * lxvd2x opcode: 0x7c000698 883 * lxvh8x opcode: 0x7c000658 884 * lxvw4x opcode: 0x7c000618 885 */ 886 if ((instr & 0xfc00073e) != 0x7c000618) { 887 pr_devel("HMI vec emu: not vector CI %i:%s[%d] nip=%016lx" 888 " instr=%08x\n", 889 smp_processor_id(), current->comm, current->pid, 890 regs->nip, instr); 891 return; 892 } 893 894 /* Grab vector registers into the task struct */ 895 msr = regs->msr; /* Grab msr before we flush the bits */ 896 flush_vsx_to_thread(current); 897 enable_kernel_altivec(); 898 899 /* 900 * Is userspace running with a different endian (this is rare but 901 * not impossible) 902 */ 903 swap = (msr & MSR_LE) != (MSR_KERNEL & MSR_LE); 904 905 /* Decode the instruction */ 906 ra = (instr >> 16) & 0x1f; 907 rb = (instr >> 11) & 0x1f; 908 t = (instr >> 21) & 0x1f; 909 if (instr & 1) 910 vdst = (u8 *)¤t->thread.vr_state.vr[t]; 911 else 912 vdst = (u8 *)¤t->thread.fp_state.fpr[t][0]; 913 914 /* Grab the vector address */ 915 ea = regs->gpr[rb] + (ra ? regs->gpr[ra] : 0); 916 if (is_32bit_task()) 917 ea &= 0xfffffffful; 918 addr = (__force const void __user *)ea; 919 920 /* Check it */ 921 if (!access_ok(addr, 16)) { 922 pr_devel("HMI vec emu: bad access %i:%s[%d] nip=%016lx" 923 " instr=%08x addr=%016lx\n", 924 smp_processor_id(), current->comm, current->pid, 925 regs->nip, instr, (unsigned long)addr); 926 return; 927 } 928 929 /* Read the vector */ 930 rc = 0; 931 if ((unsigned long)addr & 0xfUL) 932 /* unaligned case */ 933 rc = __copy_from_user_inatomic(vbuf, addr, 16); 934 else 935 __get_user_atomic_128_aligned(vbuf, addr, rc); 936 if (rc) { 937 pr_devel("HMI vec emu: page fault %i:%s[%d] nip=%016lx" 938 " instr=%08x addr=%016lx\n", 939 smp_processor_id(), current->comm, current->pid, 940 regs->nip, instr, (unsigned long)addr); 941 return; 942 } 943 944 pr_devel("HMI vec emu: emulated vector CI %i:%s[%d] nip=%016lx" 945 " instr=%08x addr=%016lx\n", 946 smp_processor_id(), current->comm, current->pid, regs->nip, 947 instr, (unsigned long) addr); 948 949 /* Grab instruction "selector" */ 950 sel = (instr >> 6) & 3; 951 952 /* 953 * Check to make sure the facility is actually enabled. This 954 * could happen if we get a false positive hit. 955 * 956 * lxvd2x/lxvw4x always check MSR VSX sel = 0,2 957 * lxvh8x/lxvb16x check MSR VSX or VEC depending on VSR used sel = 1,3 958 */ 959 msr_mask = MSR_VSX; 960 if ((sel & 1) && (instr & 1)) /* lxvh8x & lxvb16x + VSR >= 32 */ 961 msr_mask = MSR_VEC; 962 if (!(msr & msr_mask)) { 963 pr_devel("HMI vec emu: MSR fac clear %i:%s[%d] nip=%016lx" 964 " instr=%08x msr:%016lx\n", 965 smp_processor_id(), current->comm, current->pid, 966 regs->nip, instr, msr); 967 return; 968 } 969 970 /* Do logging here before we modify sel based on endian */ 971 switch (sel) { 972 case 0: /* lxvw4x */ 973 PPC_WARN_EMULATED(lxvw4x, regs); 974 break; 975 case 1: /* lxvh8x */ 976 PPC_WARN_EMULATED(lxvh8x, regs); 977 break; 978 case 2: /* lxvd2x */ 979 PPC_WARN_EMULATED(lxvd2x, regs); 980 break; 981 case 3: /* lxvb16x */ 982 PPC_WARN_EMULATED(lxvb16x, regs); 983 break; 984 } 985 986 #ifdef __LITTLE_ENDIAN__ 987 /* 988 * An LE kernel stores the vector in the task struct as an LE 989 * byte array (effectively swapping both the components and 990 * the content of the components). Those instructions expect 991 * the components to remain in ascending address order, so we 992 * swap them back. 993 * 994 * If we are running a BE user space, the expectation is that 995 * of a simple memcpy, so forcing the emulation to look like 996 * a lxvb16x should do the trick. 997 */ 998 if (swap) 999 sel = 3; 1000 1001 switch (sel) { 1002 case 0: /* lxvw4x */ 1003 for (i = 0; i < 4; i++) 1004 ((u32 *)vdst)[i] = ((u32 *)vbuf)[3-i]; 1005 break; 1006 case 1: /* lxvh8x */ 1007 for (i = 0; i < 8; i++) 1008 ((u16 *)vdst)[i] = ((u16 *)vbuf)[7-i]; 1009 break; 1010 case 2: /* lxvd2x */ 1011 for (i = 0; i < 2; i++) 1012 ((u64 *)vdst)[i] = ((u64 *)vbuf)[1-i]; 1013 break; 1014 case 3: /* lxvb16x */ 1015 for (i = 0; i < 16; i++) 1016 vdst[i] = vbuf[15-i]; 1017 break; 1018 } 1019 #else /* __LITTLE_ENDIAN__ */ 1020 /* On a big endian kernel, a BE userspace only needs a memcpy */ 1021 if (!swap) 1022 sel = 3; 1023 1024 /* Otherwise, we need to swap the content of the components */ 1025 switch (sel) { 1026 case 0: /* lxvw4x */ 1027 for (i = 0; i < 4; i++) 1028 ((u32 *)vdst)[i] = cpu_to_le32(((u32 *)vbuf)[i]); 1029 break; 1030 case 1: /* lxvh8x */ 1031 for (i = 0; i < 8; i++) 1032 ((u16 *)vdst)[i] = cpu_to_le16(((u16 *)vbuf)[i]); 1033 break; 1034 case 2: /* lxvd2x */ 1035 for (i = 0; i < 2; i++) 1036 ((u64 *)vdst)[i] = cpu_to_le64(((u64 *)vbuf)[i]); 1037 break; 1038 case 3: /* lxvb16x */ 1039 memcpy(vdst, vbuf, 16); 1040 break; 1041 } 1042 #endif /* !__LITTLE_ENDIAN__ */ 1043 1044 /* Go to next instruction */ 1045 regs_add_return_ip(regs, 4); 1046 } 1047 #endif /* CONFIG_VSX */ 1048 1049 DEFINE_INTERRUPT_HANDLER_ASYNC(handle_hmi_exception) 1050 { 1051 struct pt_regs *old_regs; 1052 1053 old_regs = set_irq_regs(regs); 1054 1055 #ifdef CONFIG_VSX 1056 /* Real mode flagged P9 special emu is needed */ 1057 if (local_paca->hmi_p9_special_emu) { 1058 local_paca->hmi_p9_special_emu = 0; 1059 1060 /* 1061 * We don't want to take page faults while doing the 1062 * emulation, we just replay the instruction if necessary. 1063 */ 1064 pagefault_disable(); 1065 p9_hmi_special_emu(regs); 1066 pagefault_enable(); 1067 } 1068 #endif /* CONFIG_VSX */ 1069 1070 if (ppc_md.handle_hmi_exception) 1071 ppc_md.handle_hmi_exception(regs); 1072 1073 set_irq_regs(old_regs); 1074 } 1075 1076 DEFINE_INTERRUPT_HANDLER(unknown_exception) 1077 { 1078 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 1079 regs->nip, regs->msr, regs->trap); 1080 1081 _exception(SIGTRAP, regs, TRAP_UNK, 0); 1082 } 1083 1084 DEFINE_INTERRUPT_HANDLER_ASYNC(unknown_async_exception) 1085 { 1086 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 1087 regs->nip, regs->msr, regs->trap); 1088 1089 _exception(SIGTRAP, regs, TRAP_UNK, 0); 1090 } 1091 1092 DEFINE_INTERRUPT_HANDLER_NMI(unknown_nmi_exception) 1093 { 1094 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 1095 regs->nip, regs->msr, regs->trap); 1096 1097 _exception(SIGTRAP, regs, TRAP_UNK, 0); 1098 1099 return 0; 1100 } 1101 1102 DEFINE_INTERRUPT_HANDLER(instruction_breakpoint_exception) 1103 { 1104 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, 1105 5, SIGTRAP) == NOTIFY_STOP) 1106 return; 1107 if (debugger_iabr_match(regs)) 1108 return; 1109 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1110 } 1111 1112 DEFINE_INTERRUPT_HANDLER(RunModeException) 1113 { 1114 _exception(SIGTRAP, regs, TRAP_UNK, 0); 1115 } 1116 1117 static void __single_step_exception(struct pt_regs *regs) 1118 { 1119 clear_single_step(regs); 1120 clear_br_trace(regs); 1121 1122 if (kprobe_post_handler(regs)) 1123 return; 1124 1125 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 1126 5, SIGTRAP) == NOTIFY_STOP) 1127 return; 1128 if (debugger_sstep(regs)) 1129 return; 1130 1131 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 1132 } 1133 1134 DEFINE_INTERRUPT_HANDLER(single_step_exception) 1135 { 1136 __single_step_exception(regs); 1137 } 1138 1139 /* 1140 * After we have successfully emulated an instruction, we have to 1141 * check if the instruction was being single-stepped, and if so, 1142 * pretend we got a single-step exception. This was pointed out 1143 * by Kumar Gala. -- paulus 1144 */ 1145 static void emulate_single_step(struct pt_regs *regs) 1146 { 1147 if (single_stepping(regs)) 1148 __single_step_exception(regs); 1149 } 1150 1151 static inline int __parse_fpscr(unsigned long fpscr) 1152 { 1153 int ret = FPE_FLTUNK; 1154 1155 /* Invalid operation */ 1156 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) 1157 ret = FPE_FLTINV; 1158 1159 /* Overflow */ 1160 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) 1161 ret = FPE_FLTOVF; 1162 1163 /* Underflow */ 1164 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) 1165 ret = FPE_FLTUND; 1166 1167 /* Divide by zero */ 1168 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) 1169 ret = FPE_FLTDIV; 1170 1171 /* Inexact result */ 1172 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) 1173 ret = FPE_FLTRES; 1174 1175 return ret; 1176 } 1177 1178 static void parse_fpe(struct pt_regs *regs) 1179 { 1180 int code = 0; 1181 1182 flush_fp_to_thread(current); 1183 1184 #ifdef CONFIG_PPC_FPU_REGS 1185 code = __parse_fpscr(current->thread.fp_state.fpscr); 1186 #endif 1187 1188 _exception(SIGFPE, regs, code, regs->nip); 1189 } 1190 1191 /* 1192 * Illegal instruction emulation support. Originally written to 1193 * provide the PVR to user applications using the mfspr rd, PVR. 1194 * Return non-zero if we can't emulate, or -EFAULT if the associated 1195 * memory access caused an access fault. Return zero on success. 1196 * 1197 * There are a couple of ways to do this, either "decode" the instruction 1198 * or directly match lots of bits. In this case, matching lots of 1199 * bits is faster and easier. 1200 * 1201 */ 1202 static int emulate_string_inst(struct pt_regs *regs, u32 instword) 1203 { 1204 u8 rT = (instword >> 21) & 0x1f; 1205 u8 rA = (instword >> 16) & 0x1f; 1206 u8 NB_RB = (instword >> 11) & 0x1f; 1207 u32 num_bytes; 1208 unsigned long EA; 1209 int pos = 0; 1210 1211 /* Early out if we are an invalid form of lswx */ 1212 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) 1213 if ((rT == rA) || (rT == NB_RB)) 1214 return -EINVAL; 1215 1216 EA = (rA == 0) ? 0 : regs->gpr[rA]; 1217 1218 switch (instword & PPC_INST_STRING_MASK) { 1219 case PPC_INST_LSWX: 1220 case PPC_INST_STSWX: 1221 EA += NB_RB; 1222 num_bytes = regs->xer & 0x7f; 1223 break; 1224 case PPC_INST_LSWI: 1225 case PPC_INST_STSWI: 1226 num_bytes = (NB_RB == 0) ? 32 : NB_RB; 1227 break; 1228 default: 1229 return -EINVAL; 1230 } 1231 1232 while (num_bytes != 0) 1233 { 1234 u8 val; 1235 u32 shift = 8 * (3 - (pos & 0x3)); 1236 1237 /* if process is 32-bit, clear upper 32 bits of EA */ 1238 if ((regs->msr & MSR_64BIT) == 0) 1239 EA &= 0xFFFFFFFF; 1240 1241 switch ((instword & PPC_INST_STRING_MASK)) { 1242 case PPC_INST_LSWX: 1243 case PPC_INST_LSWI: 1244 if (get_user(val, (u8 __user *)EA)) 1245 return -EFAULT; 1246 /* first time updating this reg, 1247 * zero it out */ 1248 if (pos == 0) 1249 regs->gpr[rT] = 0; 1250 regs->gpr[rT] |= val << shift; 1251 break; 1252 case PPC_INST_STSWI: 1253 case PPC_INST_STSWX: 1254 val = regs->gpr[rT] >> shift; 1255 if (put_user(val, (u8 __user *)EA)) 1256 return -EFAULT; 1257 break; 1258 } 1259 /* move EA to next address */ 1260 EA += 1; 1261 num_bytes--; 1262 1263 /* manage our position within the register */ 1264 if (++pos == 4) { 1265 pos = 0; 1266 if (++rT == 32) 1267 rT = 0; 1268 } 1269 } 1270 1271 return 0; 1272 } 1273 1274 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) 1275 { 1276 u32 ra,rs; 1277 unsigned long tmp; 1278 1279 ra = (instword >> 16) & 0x1f; 1280 rs = (instword >> 21) & 0x1f; 1281 1282 tmp = regs->gpr[rs]; 1283 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); 1284 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); 1285 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; 1286 regs->gpr[ra] = tmp; 1287 1288 return 0; 1289 } 1290 1291 static int emulate_isel(struct pt_regs *regs, u32 instword) 1292 { 1293 u8 rT = (instword >> 21) & 0x1f; 1294 u8 rA = (instword >> 16) & 0x1f; 1295 u8 rB = (instword >> 11) & 0x1f; 1296 u8 BC = (instword >> 6) & 0x1f; 1297 u8 bit; 1298 unsigned long tmp; 1299 1300 tmp = (rA == 0) ? 0 : regs->gpr[rA]; 1301 bit = (regs->ccr >> (31 - BC)) & 0x1; 1302 1303 regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; 1304 1305 return 0; 1306 } 1307 1308 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1309 static inline bool tm_abort_check(struct pt_regs *regs, int cause) 1310 { 1311 /* If we're emulating a load/store in an active transaction, we cannot 1312 * emulate it as the kernel operates in transaction suspended context. 1313 * We need to abort the transaction. This creates a persistent TM 1314 * abort so tell the user what caused it with a new code. 1315 */ 1316 if (MSR_TM_TRANSACTIONAL(regs->msr)) { 1317 tm_enable(); 1318 tm_abort(cause); 1319 return true; 1320 } 1321 return false; 1322 } 1323 #else 1324 static inline bool tm_abort_check(struct pt_regs *regs, int reason) 1325 { 1326 return false; 1327 } 1328 #endif 1329 1330 static int emulate_instruction(struct pt_regs *regs) 1331 { 1332 u32 instword; 1333 u32 rd; 1334 1335 if (!user_mode(regs)) 1336 return -EINVAL; 1337 1338 if (get_user(instword, (u32 __user *)(regs->nip))) 1339 return -EFAULT; 1340 1341 /* Emulate the mfspr rD, PVR. */ 1342 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { 1343 PPC_WARN_EMULATED(mfpvr, regs); 1344 rd = (instword >> 21) & 0x1f; 1345 regs->gpr[rd] = mfspr(SPRN_PVR); 1346 return 0; 1347 } 1348 1349 /* Emulating the dcba insn is just a no-op. */ 1350 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { 1351 PPC_WARN_EMULATED(dcba, regs); 1352 return 0; 1353 } 1354 1355 /* Emulate the mcrxr insn. */ 1356 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { 1357 int shift = (instword >> 21) & 0x1c; 1358 unsigned long msk = 0xf0000000UL >> shift; 1359 1360 PPC_WARN_EMULATED(mcrxr, regs); 1361 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); 1362 regs->xer &= ~0xf0000000UL; 1363 return 0; 1364 } 1365 1366 /* Emulate load/store string insn. */ 1367 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { 1368 if (tm_abort_check(regs, 1369 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) 1370 return -EINVAL; 1371 PPC_WARN_EMULATED(string, regs); 1372 return emulate_string_inst(regs, instword); 1373 } 1374 1375 /* Emulate the popcntb (Population Count Bytes) instruction. */ 1376 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { 1377 PPC_WARN_EMULATED(popcntb, regs); 1378 return emulate_popcntb_inst(regs, instword); 1379 } 1380 1381 /* Emulate isel (Integer Select) instruction */ 1382 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { 1383 PPC_WARN_EMULATED(isel, regs); 1384 return emulate_isel(regs, instword); 1385 } 1386 1387 /* Emulate sync instruction variants */ 1388 if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) { 1389 PPC_WARN_EMULATED(sync, regs); 1390 asm volatile("sync"); 1391 return 0; 1392 } 1393 1394 #ifdef CONFIG_PPC64 1395 /* Emulate the mfspr rD, DSCR. */ 1396 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) == 1397 PPC_INST_MFSPR_DSCR_USER) || 1398 ((instword & PPC_INST_MFSPR_DSCR_MASK) == 1399 PPC_INST_MFSPR_DSCR)) && 1400 cpu_has_feature(CPU_FTR_DSCR)) { 1401 PPC_WARN_EMULATED(mfdscr, regs); 1402 rd = (instword >> 21) & 0x1f; 1403 regs->gpr[rd] = mfspr(SPRN_DSCR); 1404 return 0; 1405 } 1406 /* Emulate the mtspr DSCR, rD. */ 1407 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) == 1408 PPC_INST_MTSPR_DSCR_USER) || 1409 ((instword & PPC_INST_MTSPR_DSCR_MASK) == 1410 PPC_INST_MTSPR_DSCR)) && 1411 cpu_has_feature(CPU_FTR_DSCR)) { 1412 PPC_WARN_EMULATED(mtdscr, regs); 1413 rd = (instword >> 21) & 0x1f; 1414 current->thread.dscr = regs->gpr[rd]; 1415 current->thread.dscr_inherit = 1; 1416 mtspr(SPRN_DSCR, current->thread.dscr); 1417 return 0; 1418 } 1419 #endif 1420 1421 return -EINVAL; 1422 } 1423 1424 int is_valid_bugaddr(unsigned long addr) 1425 { 1426 return is_kernel_addr(addr); 1427 } 1428 1429 #ifdef CONFIG_MATH_EMULATION 1430 static int emulate_math(struct pt_regs *regs) 1431 { 1432 int ret; 1433 1434 ret = do_mathemu(regs); 1435 if (ret >= 0) 1436 PPC_WARN_EMULATED(math, regs); 1437 1438 switch (ret) { 1439 case 0: 1440 emulate_single_step(regs); 1441 return 0; 1442 case 1: { 1443 int code = 0; 1444 code = __parse_fpscr(current->thread.fp_state.fpscr); 1445 _exception(SIGFPE, regs, code, regs->nip); 1446 return 0; 1447 } 1448 case -EFAULT: 1449 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1450 return 0; 1451 } 1452 1453 return -1; 1454 } 1455 #else 1456 static inline int emulate_math(struct pt_regs *regs) { return -1; } 1457 #endif 1458 1459 static void do_program_check(struct pt_regs *regs) 1460 { 1461 unsigned int reason = get_reason(regs); 1462 1463 /* We can now get here via a FP Unavailable exception if the core 1464 * has no FPU, in that case the reason flags will be 0 */ 1465 1466 if (reason & REASON_FP) { 1467 /* IEEE FP exception */ 1468 parse_fpe(regs); 1469 return; 1470 } 1471 if (reason & REASON_TRAP) { 1472 unsigned long bugaddr; 1473 /* Debugger is first in line to stop recursive faults in 1474 * rcu_lock, notify_die, or atomic_notifier_call_chain */ 1475 if (debugger_bpt(regs)) 1476 return; 1477 1478 if (kprobe_handler(regs)) 1479 return; 1480 1481 /* trap exception */ 1482 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) 1483 == NOTIFY_STOP) 1484 return; 1485 1486 bugaddr = regs->nip; 1487 /* 1488 * Fixup bugaddr for BUG_ON() in real mode 1489 */ 1490 if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR)) 1491 bugaddr += PAGE_OFFSET; 1492 1493 if (!(regs->msr & MSR_PR) && /* not user-mode */ 1494 report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) { 1495 const struct exception_table_entry *entry; 1496 1497 entry = search_exception_tables(bugaddr); 1498 if (entry) { 1499 regs_set_return_ip(regs, extable_fixup(entry) + regs->nip - bugaddr); 1500 return; 1501 } 1502 } 1503 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1504 return; 1505 } 1506 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1507 if (reason & REASON_TM) { 1508 /* This is a TM "Bad Thing Exception" program check. 1509 * This occurs when: 1510 * - An rfid/hrfid/mtmsrd attempts to cause an illegal 1511 * transition in TM states. 1512 * - A trechkpt is attempted when transactional. 1513 * - A treclaim is attempted when non transactional. 1514 * - A tend is illegally attempted. 1515 * - writing a TM SPR when transactional. 1516 * 1517 * If usermode caused this, it's done something illegal and 1518 * gets a SIGILL slap on the wrist. We call it an illegal 1519 * operand to distinguish from the instruction just being bad 1520 * (e.g. executing a 'tend' on a CPU without TM!); it's an 1521 * illegal /placement/ of a valid instruction. 1522 */ 1523 if (user_mode(regs)) { 1524 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip); 1525 return; 1526 } else { 1527 printk(KERN_EMERG "Unexpected TM Bad Thing exception " 1528 "at %lx (msr 0x%lx) tm_scratch=%llx\n", 1529 regs->nip, regs->msr, get_paca()->tm_scratch); 1530 die("Unrecoverable exception", regs, SIGABRT); 1531 } 1532 } 1533 #endif 1534 1535 /* 1536 * If we took the program check in the kernel skip down to sending a 1537 * SIGILL. The subsequent cases all relate to emulating instructions 1538 * which we should only do for userspace. We also do not want to enable 1539 * interrupts for kernel faults because that might lead to further 1540 * faults, and loose the context of the original exception. 1541 */ 1542 if (!user_mode(regs)) 1543 goto sigill; 1544 1545 interrupt_cond_local_irq_enable(regs); 1546 1547 /* (reason & REASON_ILLEGAL) would be the obvious thing here, 1548 * but there seems to be a hardware bug on the 405GP (RevD) 1549 * that means ESR is sometimes set incorrectly - either to 1550 * ESR_DST (!?) or 0. In the process of chasing this with the 1551 * hardware people - not sure if it can happen on any illegal 1552 * instruction or only on FP instructions, whether there is a 1553 * pattern to occurrences etc. -dgibson 31/Mar/2003 1554 */ 1555 if (!emulate_math(regs)) 1556 return; 1557 1558 /* Try to emulate it if we should. */ 1559 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { 1560 switch (emulate_instruction(regs)) { 1561 case 0: 1562 regs_add_return_ip(regs, 4); 1563 emulate_single_step(regs); 1564 return; 1565 case -EFAULT: 1566 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1567 return; 1568 } 1569 } 1570 1571 sigill: 1572 if (reason & REASON_PRIVILEGED) 1573 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 1574 else 1575 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1576 1577 } 1578 1579 DEFINE_INTERRUPT_HANDLER(program_check_exception) 1580 { 1581 do_program_check(regs); 1582 } 1583 1584 /* 1585 * This occurs when running in hypervisor mode on POWER6 or later 1586 * and an illegal instruction is encountered. 1587 */ 1588 DEFINE_INTERRUPT_HANDLER(emulation_assist_interrupt) 1589 { 1590 regs_set_return_msr(regs, regs->msr | REASON_ILLEGAL); 1591 do_program_check(regs); 1592 } 1593 1594 DEFINE_INTERRUPT_HANDLER(alignment_exception) 1595 { 1596 int sig, code, fixed = 0; 1597 unsigned long reason; 1598 1599 interrupt_cond_local_irq_enable(regs); 1600 1601 reason = get_reason(regs); 1602 if (reason & REASON_BOUNDARY) { 1603 sig = SIGBUS; 1604 code = BUS_ADRALN; 1605 goto bad; 1606 } 1607 1608 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT)) 1609 return; 1610 1611 /* we don't implement logging of alignment exceptions */ 1612 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) 1613 fixed = fix_alignment(regs); 1614 1615 if (fixed == 1) { 1616 /* skip over emulated instruction */ 1617 regs_add_return_ip(regs, inst_length(reason)); 1618 emulate_single_step(regs); 1619 return; 1620 } 1621 1622 /* Operand address was bad */ 1623 if (fixed == -EFAULT) { 1624 sig = SIGSEGV; 1625 code = SEGV_ACCERR; 1626 } else { 1627 sig = SIGBUS; 1628 code = BUS_ADRALN; 1629 } 1630 bad: 1631 if (user_mode(regs)) 1632 _exception(sig, regs, code, regs->dar); 1633 else 1634 bad_page_fault(regs, sig); 1635 } 1636 1637 DEFINE_INTERRUPT_HANDLER(stack_overflow_exception) 1638 { 1639 die("Kernel stack overflow", regs, SIGSEGV); 1640 } 1641 1642 DEFINE_INTERRUPT_HANDLER(kernel_fp_unavailable_exception) 1643 { 1644 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " 1645 "%lx at %lx\n", regs->trap, regs->nip); 1646 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); 1647 } 1648 1649 DEFINE_INTERRUPT_HANDLER(altivec_unavailable_exception) 1650 { 1651 if (user_mode(regs)) { 1652 /* A user program has executed an altivec instruction, 1653 but this kernel doesn't support altivec. */ 1654 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1655 return; 1656 } 1657 1658 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " 1659 "%lx at %lx\n", regs->trap, regs->nip); 1660 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); 1661 } 1662 1663 DEFINE_INTERRUPT_HANDLER(vsx_unavailable_exception) 1664 { 1665 if (user_mode(regs)) { 1666 /* A user program has executed an vsx instruction, 1667 but this kernel doesn't support vsx. */ 1668 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1669 return; 1670 } 1671 1672 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " 1673 "%lx at %lx\n", regs->trap, regs->nip); 1674 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); 1675 } 1676 1677 #ifdef CONFIG_PPC64 1678 static void tm_unavailable(struct pt_regs *regs) 1679 { 1680 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1681 if (user_mode(regs)) { 1682 current->thread.load_tm++; 1683 regs_set_return_msr(regs, regs->msr | MSR_TM); 1684 tm_enable(); 1685 tm_restore_sprs(¤t->thread); 1686 return; 1687 } 1688 #endif 1689 pr_emerg("Unrecoverable TM Unavailable Exception " 1690 "%lx at %lx\n", regs->trap, regs->nip); 1691 die("Unrecoverable TM Unavailable Exception", regs, SIGABRT); 1692 } 1693 1694 DEFINE_INTERRUPT_HANDLER(facility_unavailable_exception) 1695 { 1696 static char *facility_strings[] = { 1697 [FSCR_FP_LG] = "FPU", 1698 [FSCR_VECVSX_LG] = "VMX/VSX", 1699 [FSCR_DSCR_LG] = "DSCR", 1700 [FSCR_PM_LG] = "PMU SPRs", 1701 [FSCR_BHRB_LG] = "BHRB", 1702 [FSCR_TM_LG] = "TM", 1703 [FSCR_EBB_LG] = "EBB", 1704 [FSCR_TAR_LG] = "TAR", 1705 [FSCR_MSGP_LG] = "MSGP", 1706 [FSCR_SCV_LG] = "SCV", 1707 [FSCR_PREFIX_LG] = "PREFIX", 1708 }; 1709 char *facility = "unknown"; 1710 u64 value; 1711 u32 instword, rd; 1712 u8 status; 1713 bool hv; 1714 1715 hv = (TRAP(regs) == INTERRUPT_H_FAC_UNAVAIL); 1716 if (hv) 1717 value = mfspr(SPRN_HFSCR); 1718 else 1719 value = mfspr(SPRN_FSCR); 1720 1721 status = value >> 56; 1722 if ((hv || status >= 2) && 1723 (status < ARRAY_SIZE(facility_strings)) && 1724 facility_strings[status]) 1725 facility = facility_strings[status]; 1726 1727 /* We should not have taken this interrupt in kernel */ 1728 if (!user_mode(regs)) { 1729 pr_emerg("Facility '%s' unavailable (%d) exception in kernel mode at %lx\n", 1730 facility, status, regs->nip); 1731 die("Unexpected facility unavailable exception", regs, SIGABRT); 1732 } 1733 1734 interrupt_cond_local_irq_enable(regs); 1735 1736 if (status == FSCR_DSCR_LG) { 1737 /* 1738 * User is accessing the DSCR register using the problem 1739 * state only SPR number (0x03) either through a mfspr or 1740 * a mtspr instruction. If it is a write attempt through 1741 * a mtspr, then we set the inherit bit. This also allows 1742 * the user to write or read the register directly in the 1743 * future by setting via the FSCR DSCR bit. But in case it 1744 * is a read DSCR attempt through a mfspr instruction, we 1745 * just emulate the instruction instead. This code path will 1746 * always emulate all the mfspr instructions till the user 1747 * has attempted at least one mtspr instruction. This way it 1748 * preserves the same behaviour when the user is accessing 1749 * the DSCR through privilege level only SPR number (0x11) 1750 * which is emulated through illegal instruction exception. 1751 * We always leave HFSCR DSCR set. 1752 */ 1753 if (get_user(instword, (u32 __user *)(regs->nip))) { 1754 pr_err("Failed to fetch the user instruction\n"); 1755 return; 1756 } 1757 1758 /* Write into DSCR (mtspr 0x03, RS) */ 1759 if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK) 1760 == PPC_INST_MTSPR_DSCR_USER) { 1761 rd = (instword >> 21) & 0x1f; 1762 current->thread.dscr = regs->gpr[rd]; 1763 current->thread.dscr_inherit = 1; 1764 current->thread.fscr |= FSCR_DSCR; 1765 mtspr(SPRN_FSCR, current->thread.fscr); 1766 } 1767 1768 /* Read from DSCR (mfspr RT, 0x03) */ 1769 if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK) 1770 == PPC_INST_MFSPR_DSCR_USER) { 1771 if (emulate_instruction(regs)) { 1772 pr_err("DSCR based mfspr emulation failed\n"); 1773 return; 1774 } 1775 regs_add_return_ip(regs, 4); 1776 emulate_single_step(regs); 1777 } 1778 return; 1779 } 1780 1781 if (status == FSCR_TM_LG) { 1782 /* 1783 * If we're here then the hardware is TM aware because it 1784 * generated an exception with FSRM_TM set. 1785 * 1786 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware 1787 * told us not to do TM, or the kernel is not built with TM 1788 * support. 1789 * 1790 * If both of those things are true, then userspace can spam the 1791 * console by triggering the printk() below just by continually 1792 * doing tbegin (or any TM instruction). So in that case just 1793 * send the process a SIGILL immediately. 1794 */ 1795 if (!cpu_has_feature(CPU_FTR_TM)) 1796 goto out; 1797 1798 tm_unavailable(regs); 1799 return; 1800 } 1801 1802 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n", 1803 hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr); 1804 1805 out: 1806 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1807 } 1808 #endif 1809 1810 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1811 1812 DEFINE_INTERRUPT_HANDLER(fp_unavailable_tm) 1813 { 1814 /* Note: This does not handle any kind of FP laziness. */ 1815 1816 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n", 1817 regs->nip, regs->msr); 1818 1819 /* We can only have got here if the task started using FP after 1820 * beginning the transaction. So, the transactional regs are just a 1821 * copy of the checkpointed ones. But, we still need to recheckpoint 1822 * as we're enabling FP for the process; it will return, abort the 1823 * transaction, and probably retry but now with FP enabled. So the 1824 * checkpointed FP registers need to be loaded. 1825 */ 1826 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1827 1828 /* 1829 * Reclaim initially saved out bogus (lazy) FPRs to ckfp_state, and 1830 * then it was overwrite by the thr->fp_state by tm_reclaim_thread(). 1831 * 1832 * At this point, ck{fp,vr}_state contains the exact values we want to 1833 * recheckpoint. 1834 */ 1835 1836 /* Enable FP for the task: */ 1837 current->thread.load_fp = 1; 1838 1839 /* 1840 * Recheckpoint all the checkpointed ckpt, ck{fp, vr}_state registers. 1841 */ 1842 tm_recheckpoint(¤t->thread); 1843 } 1844 1845 DEFINE_INTERRUPT_HANDLER(altivec_unavailable_tm) 1846 { 1847 /* See the comments in fp_unavailable_tm(). This function operates 1848 * the same way. 1849 */ 1850 1851 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx," 1852 "MSR=%lx\n", 1853 regs->nip, regs->msr); 1854 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1855 current->thread.load_vec = 1; 1856 tm_recheckpoint(¤t->thread); 1857 current->thread.used_vr = 1; 1858 } 1859 1860 DEFINE_INTERRUPT_HANDLER(vsx_unavailable_tm) 1861 { 1862 /* See the comments in fp_unavailable_tm(). This works similarly, 1863 * though we're loading both FP and VEC registers in here. 1864 * 1865 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC 1866 * regs. Either way, set MSR_VSX. 1867 */ 1868 1869 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx," 1870 "MSR=%lx\n", 1871 regs->nip, regs->msr); 1872 1873 current->thread.used_vsr = 1; 1874 1875 /* This reclaims FP and/or VR regs if they're already enabled */ 1876 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1877 1878 current->thread.load_vec = 1; 1879 current->thread.load_fp = 1; 1880 1881 tm_recheckpoint(¤t->thread); 1882 } 1883 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1884 1885 #ifdef CONFIG_PPC64 1886 DECLARE_INTERRUPT_HANDLER_NMI(performance_monitor_exception_nmi); 1887 DEFINE_INTERRUPT_HANDLER_NMI(performance_monitor_exception_nmi) 1888 { 1889 __this_cpu_inc(irq_stat.pmu_irqs); 1890 1891 perf_irq(regs); 1892 1893 return 0; 1894 } 1895 #endif 1896 1897 DECLARE_INTERRUPT_HANDLER_ASYNC(performance_monitor_exception_async); 1898 DEFINE_INTERRUPT_HANDLER_ASYNC(performance_monitor_exception_async) 1899 { 1900 __this_cpu_inc(irq_stat.pmu_irqs); 1901 1902 perf_irq(regs); 1903 } 1904 1905 DEFINE_INTERRUPT_HANDLER_RAW(performance_monitor_exception) 1906 { 1907 /* 1908 * On 64-bit, if perf interrupts hit in a local_irq_disable 1909 * (soft-masked) region, we consider them as NMIs. This is required to 1910 * prevent hash faults on user addresses when reading callchains (and 1911 * looks better from an irq tracing perspective). 1912 */ 1913 if (IS_ENABLED(CONFIG_PPC64) && unlikely(arch_irq_disabled_regs(regs))) 1914 performance_monitor_exception_nmi(regs); 1915 else 1916 performance_monitor_exception_async(regs); 1917 1918 return 0; 1919 } 1920 1921 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1922 static void handle_debug(struct pt_regs *regs, unsigned long debug_status) 1923 { 1924 int changed = 0; 1925 /* 1926 * Determine the cause of the debug event, clear the 1927 * event flags and send a trap to the handler. Torez 1928 */ 1929 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { 1930 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); 1931 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1932 current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; 1933 #endif 1934 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, 1935 5); 1936 changed |= 0x01; 1937 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { 1938 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); 1939 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, 1940 6); 1941 changed |= 0x01; 1942 } else if (debug_status & DBSR_IAC1) { 1943 current->thread.debug.dbcr0 &= ~DBCR0_IAC1; 1944 dbcr_iac_range(current) &= ~DBCR_IAC12MODE; 1945 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, 1946 1); 1947 changed |= 0x01; 1948 } else if (debug_status & DBSR_IAC2) { 1949 current->thread.debug.dbcr0 &= ~DBCR0_IAC2; 1950 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, 1951 2); 1952 changed |= 0x01; 1953 } else if (debug_status & DBSR_IAC3) { 1954 current->thread.debug.dbcr0 &= ~DBCR0_IAC3; 1955 dbcr_iac_range(current) &= ~DBCR_IAC34MODE; 1956 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, 1957 3); 1958 changed |= 0x01; 1959 } else if (debug_status & DBSR_IAC4) { 1960 current->thread.debug.dbcr0 &= ~DBCR0_IAC4; 1961 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, 1962 4); 1963 changed |= 0x01; 1964 } 1965 /* 1966 * At the point this routine was called, the MSR(DE) was turned off. 1967 * Check all other debug flags and see if that bit needs to be turned 1968 * back on or not. 1969 */ 1970 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 1971 current->thread.debug.dbcr1)) 1972 regs_set_return_msr(regs, regs->msr | MSR_DE); 1973 else 1974 /* Make sure the IDM flag is off */ 1975 current->thread.debug.dbcr0 &= ~DBCR0_IDM; 1976 1977 if (changed & 0x01) 1978 mtspr(SPRN_DBCR0, current->thread.debug.dbcr0); 1979 } 1980 1981 DEFINE_INTERRUPT_HANDLER(DebugException) 1982 { 1983 unsigned long debug_status = regs->dsisr; 1984 1985 current->thread.debug.dbsr = debug_status; 1986 1987 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while 1988 * on server, it stops on the target of the branch. In order to simulate 1989 * the server behaviour, we thus restart right away with a single step 1990 * instead of stopping here when hitting a BT 1991 */ 1992 if (debug_status & DBSR_BT) { 1993 regs_set_return_msr(regs, regs->msr & ~MSR_DE); 1994 1995 /* Disable BT */ 1996 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); 1997 /* Clear the BT event */ 1998 mtspr(SPRN_DBSR, DBSR_BT); 1999 2000 /* Do the single step trick only when coming from userspace */ 2001 if (user_mode(regs)) { 2002 current->thread.debug.dbcr0 &= ~DBCR0_BT; 2003 current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; 2004 regs_set_return_msr(regs, regs->msr | MSR_DE); 2005 return; 2006 } 2007 2008 if (kprobe_post_handler(regs)) 2009 return; 2010 2011 if (notify_die(DIE_SSTEP, "block_step", regs, 5, 2012 5, SIGTRAP) == NOTIFY_STOP) { 2013 return; 2014 } 2015 if (debugger_sstep(regs)) 2016 return; 2017 } else if (debug_status & DBSR_IC) { /* Instruction complete */ 2018 regs_set_return_msr(regs, regs->msr & ~MSR_DE); 2019 2020 /* Disable instruction completion */ 2021 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); 2022 /* Clear the instruction completion event */ 2023 mtspr(SPRN_DBSR, DBSR_IC); 2024 2025 if (kprobe_post_handler(regs)) 2026 return; 2027 2028 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 2029 5, SIGTRAP) == NOTIFY_STOP) { 2030 return; 2031 } 2032 2033 if (debugger_sstep(regs)) 2034 return; 2035 2036 if (user_mode(regs)) { 2037 current->thread.debug.dbcr0 &= ~DBCR0_IC; 2038 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 2039 current->thread.debug.dbcr1)) 2040 regs_set_return_msr(regs, regs->msr | MSR_DE); 2041 else 2042 /* Make sure the IDM bit is off */ 2043 current->thread.debug.dbcr0 &= ~DBCR0_IDM; 2044 } 2045 2046 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 2047 } else 2048 handle_debug(regs, debug_status); 2049 } 2050 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 2051 2052 #ifdef CONFIG_ALTIVEC 2053 DEFINE_INTERRUPT_HANDLER(altivec_assist_exception) 2054 { 2055 int err; 2056 2057 if (!user_mode(regs)) { 2058 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" 2059 " at %lx\n", regs->nip); 2060 die("Kernel VMX/Altivec assist exception", regs, SIGILL); 2061 } 2062 2063 flush_altivec_to_thread(current); 2064 2065 PPC_WARN_EMULATED(altivec, regs); 2066 err = emulate_altivec(regs); 2067 if (err == 0) { 2068 regs_add_return_ip(regs, 4); /* skip emulated instruction */ 2069 emulate_single_step(regs); 2070 return; 2071 } 2072 2073 if (err == -EFAULT) { 2074 /* got an error reading the instruction */ 2075 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2076 } else { 2077 /* didn't recognize the instruction */ 2078 /* XXX quick hack for now: set the non-Java bit in the VSCR */ 2079 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " 2080 "in %s at %lx\n", current->comm, regs->nip); 2081 current->thread.vr_state.vscr.u[3] |= 0x10000; 2082 } 2083 } 2084 #endif /* CONFIG_ALTIVEC */ 2085 2086 #ifdef CONFIG_FSL_BOOKE 2087 DEFINE_INTERRUPT_HANDLER(CacheLockingException) 2088 { 2089 unsigned long error_code = regs->dsisr; 2090 2091 /* We treat cache locking instructions from the user 2092 * as priv ops, in the future we could try to do 2093 * something smarter 2094 */ 2095 if (error_code & (ESR_DLK|ESR_ILK)) 2096 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 2097 return; 2098 } 2099 #endif /* CONFIG_FSL_BOOKE */ 2100 2101 #ifdef CONFIG_SPE 2102 DEFINE_INTERRUPT_HANDLER(SPEFloatingPointException) 2103 { 2104 extern int do_spe_mathemu(struct pt_regs *regs); 2105 unsigned long spefscr; 2106 int fpexc_mode; 2107 int code = FPE_FLTUNK; 2108 int err; 2109 2110 interrupt_cond_local_irq_enable(regs); 2111 2112 flush_spe_to_thread(current); 2113 2114 spefscr = current->thread.spefscr; 2115 fpexc_mode = current->thread.fpexc_mode; 2116 2117 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { 2118 code = FPE_FLTOVF; 2119 } 2120 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { 2121 code = FPE_FLTUND; 2122 } 2123 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) 2124 code = FPE_FLTDIV; 2125 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { 2126 code = FPE_FLTINV; 2127 } 2128 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) 2129 code = FPE_FLTRES; 2130 2131 err = do_spe_mathemu(regs); 2132 if (err == 0) { 2133 regs_add_return_ip(regs, 4); /* skip emulated instruction */ 2134 emulate_single_step(regs); 2135 return; 2136 } 2137 2138 if (err == -EFAULT) { 2139 /* got an error reading the instruction */ 2140 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2141 } else if (err == -EINVAL) { 2142 /* didn't recognize the instruction */ 2143 printk(KERN_ERR "unrecognized spe instruction " 2144 "in %s at %lx\n", current->comm, regs->nip); 2145 } else { 2146 _exception(SIGFPE, regs, code, regs->nip); 2147 } 2148 2149 return; 2150 } 2151 2152 DEFINE_INTERRUPT_HANDLER(SPEFloatingPointRoundException) 2153 { 2154 extern int speround_handler(struct pt_regs *regs); 2155 int err; 2156 2157 interrupt_cond_local_irq_enable(regs); 2158 2159 preempt_disable(); 2160 if (regs->msr & MSR_SPE) 2161 giveup_spe(current); 2162 preempt_enable(); 2163 2164 regs_add_return_ip(regs, -4); 2165 err = speround_handler(regs); 2166 if (err == 0) { 2167 regs_add_return_ip(regs, 4); /* skip emulated instruction */ 2168 emulate_single_step(regs); 2169 return; 2170 } 2171 2172 if (err == -EFAULT) { 2173 /* got an error reading the instruction */ 2174 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2175 } else if (err == -EINVAL) { 2176 /* didn't recognize the instruction */ 2177 printk(KERN_ERR "unrecognized spe instruction " 2178 "in %s at %lx\n", current->comm, regs->nip); 2179 } else { 2180 _exception(SIGFPE, regs, FPE_FLTUNK, regs->nip); 2181 return; 2182 } 2183 } 2184 #endif 2185 2186 /* 2187 * We enter here if we get an unrecoverable exception, that is, one 2188 * that happened at a point where the RI (recoverable interrupt) bit 2189 * in the MSR is 0. This indicates that SRR0/1 are live, and that 2190 * we therefore lost state by taking this exception. 2191 */ 2192 void __noreturn unrecoverable_exception(struct pt_regs *regs) 2193 { 2194 pr_emerg("Unrecoverable exception %lx at %lx (msr=%lx)\n", 2195 regs->trap, regs->nip, regs->msr); 2196 die("Unrecoverable exception", regs, SIGABRT); 2197 /* die() should not return */ 2198 for (;;) 2199 ; 2200 } 2201 2202 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x) 2203 /* 2204 * Default handler for a Watchdog exception, 2205 * spins until a reboot occurs 2206 */ 2207 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) 2208 { 2209 /* Generic WatchdogHandler, implement your own */ 2210 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); 2211 return; 2212 } 2213 2214 DEFINE_INTERRUPT_HANDLER_NMI(WatchdogException) 2215 { 2216 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); 2217 WatchdogHandler(regs); 2218 return 0; 2219 } 2220 #endif 2221 2222 /* 2223 * We enter here if we discover during exception entry that we are 2224 * running in supervisor mode with a userspace value in the stack pointer. 2225 */ 2226 DEFINE_INTERRUPT_HANDLER(kernel_bad_stack) 2227 { 2228 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", 2229 regs->gpr[1], regs->nip); 2230 die("Bad kernel stack pointer", regs, SIGABRT); 2231 } 2232 2233 #ifdef CONFIG_PPC_EMULATED_STATS 2234 2235 #define WARN_EMULATED_SETUP(type) .type = { .name = #type } 2236 2237 struct ppc_emulated ppc_emulated = { 2238 #ifdef CONFIG_ALTIVEC 2239 WARN_EMULATED_SETUP(altivec), 2240 #endif 2241 WARN_EMULATED_SETUP(dcba), 2242 WARN_EMULATED_SETUP(dcbz), 2243 WARN_EMULATED_SETUP(fp_pair), 2244 WARN_EMULATED_SETUP(isel), 2245 WARN_EMULATED_SETUP(mcrxr), 2246 WARN_EMULATED_SETUP(mfpvr), 2247 WARN_EMULATED_SETUP(multiple), 2248 WARN_EMULATED_SETUP(popcntb), 2249 WARN_EMULATED_SETUP(spe), 2250 WARN_EMULATED_SETUP(string), 2251 WARN_EMULATED_SETUP(sync), 2252 WARN_EMULATED_SETUP(unaligned), 2253 #ifdef CONFIG_MATH_EMULATION 2254 WARN_EMULATED_SETUP(math), 2255 #endif 2256 #ifdef CONFIG_VSX 2257 WARN_EMULATED_SETUP(vsx), 2258 #endif 2259 #ifdef CONFIG_PPC64 2260 WARN_EMULATED_SETUP(mfdscr), 2261 WARN_EMULATED_SETUP(mtdscr), 2262 WARN_EMULATED_SETUP(lq_stq), 2263 WARN_EMULATED_SETUP(lxvw4x), 2264 WARN_EMULATED_SETUP(lxvh8x), 2265 WARN_EMULATED_SETUP(lxvd2x), 2266 WARN_EMULATED_SETUP(lxvb16x), 2267 #endif 2268 }; 2269 2270 u32 ppc_warn_emulated; 2271 2272 void ppc_warn_emulated_print(const char *type) 2273 { 2274 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, 2275 type); 2276 } 2277 2278 static int __init ppc_warn_emulated_init(void) 2279 { 2280 struct dentry *dir; 2281 unsigned int i; 2282 struct ppc_emulated_entry *entries = (void *)&ppc_emulated; 2283 2284 dir = debugfs_create_dir("emulated_instructions", 2285 arch_debugfs_dir); 2286 2287 debugfs_create_u32("do_warn", 0644, dir, &ppc_warn_emulated); 2288 2289 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) 2290 debugfs_create_u32(entries[i].name, 0644, dir, 2291 (u32 *)&entries[i].val.counter); 2292 2293 return 0; 2294 } 2295 2296 device_initcall(ppc_warn_emulated_init); 2297 2298 #endif /* CONFIG_PPC_EMULATED_STATS */ 2299