1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * Copyright 2007-2010 Freescale Semiconductor, Inc. 5 * 6 * Modified by Cort Dougan (cort@cs.nmt.edu) 7 * and Paul Mackerras (paulus@samba.org) 8 */ 9 10 /* 11 * This file handles the architecture-dependent parts of hardware exceptions 12 */ 13 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/sched/debug.h> 17 #include <linux/kernel.h> 18 #include <linux/mm.h> 19 #include <linux/pkeys.h> 20 #include <linux/stddef.h> 21 #include <linux/unistd.h> 22 #include <linux/ptrace.h> 23 #include <linux/user.h> 24 #include <linux/interrupt.h> 25 #include <linux/init.h> 26 #include <linux/extable.h> 27 #include <linux/module.h> /* print_modules */ 28 #include <linux/prctl.h> 29 #include <linux/delay.h> 30 #include <linux/kprobes.h> 31 #include <linux/kexec.h> 32 #include <linux/backlight.h> 33 #include <linux/bug.h> 34 #include <linux/kdebug.h> 35 #include <linux/ratelimit.h> 36 #include <linux/context_tracking.h> 37 #include <linux/smp.h> 38 #include <linux/console.h> 39 #include <linux/kmsg_dump.h> 40 41 #include <asm/emulated_ops.h> 42 #include <asm/pgtable.h> 43 #include <linux/uaccess.h> 44 #include <asm/debugfs.h> 45 #include <asm/io.h> 46 #include <asm/machdep.h> 47 #include <asm/rtas.h> 48 #include <asm/pmc.h> 49 #include <asm/reg.h> 50 #ifdef CONFIG_PMAC_BACKLIGHT 51 #include <asm/backlight.h> 52 #endif 53 #ifdef CONFIG_PPC64 54 #include <asm/firmware.h> 55 #include <asm/processor.h> 56 #include <asm/tm.h> 57 #endif 58 #include <asm/kexec.h> 59 #include <asm/ppc-opcode.h> 60 #include <asm/rio.h> 61 #include <asm/fadump.h> 62 #include <asm/switch_to.h> 63 #include <asm/tm.h> 64 #include <asm/debug.h> 65 #include <asm/asm-prototypes.h> 66 #include <asm/hmi.h> 67 #include <sysdev/fsl_pci.h> 68 #include <asm/kprobes.h> 69 #include <asm/stacktrace.h> 70 #include <asm/nmi.h> 71 72 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE) 73 int (*__debugger)(struct pt_regs *regs) __read_mostly; 74 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; 75 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; 76 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; 77 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; 78 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly; 79 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; 80 81 EXPORT_SYMBOL(__debugger); 82 EXPORT_SYMBOL(__debugger_ipi); 83 EXPORT_SYMBOL(__debugger_bpt); 84 EXPORT_SYMBOL(__debugger_sstep); 85 EXPORT_SYMBOL(__debugger_iabr_match); 86 EXPORT_SYMBOL(__debugger_break_match); 87 EXPORT_SYMBOL(__debugger_fault_handler); 88 #endif 89 90 /* Transactional Memory trap debug */ 91 #ifdef TM_DEBUG_SW 92 #define TM_DEBUG(x...) printk(KERN_INFO x) 93 #else 94 #define TM_DEBUG(x...) do { } while(0) 95 #endif 96 97 static const char *signame(int signr) 98 { 99 switch (signr) { 100 case SIGBUS: return "bus error"; 101 case SIGFPE: return "floating point exception"; 102 case SIGILL: return "illegal instruction"; 103 case SIGSEGV: return "segfault"; 104 case SIGTRAP: return "unhandled trap"; 105 } 106 107 return "unknown signal"; 108 } 109 110 /* 111 * Trap & Exception support 112 */ 113 114 #ifdef CONFIG_PMAC_BACKLIGHT 115 static void pmac_backlight_unblank(void) 116 { 117 mutex_lock(&pmac_backlight_mutex); 118 if (pmac_backlight) { 119 struct backlight_properties *props; 120 121 props = &pmac_backlight->props; 122 props->brightness = props->max_brightness; 123 props->power = FB_BLANK_UNBLANK; 124 backlight_update_status(pmac_backlight); 125 } 126 mutex_unlock(&pmac_backlight_mutex); 127 } 128 #else 129 static inline void pmac_backlight_unblank(void) { } 130 #endif 131 132 /* 133 * If oops/die is expected to crash the machine, return true here. 134 * 135 * This should not be expected to be 100% accurate, there may be 136 * notifiers registered or other unexpected conditions that may bring 137 * down the kernel. Or if the current process in the kernel is holding 138 * locks or has other critical state, the kernel may become effectively 139 * unusable anyway. 140 */ 141 bool die_will_crash(void) 142 { 143 if (should_fadump_crash()) 144 return true; 145 if (kexec_should_crash(current)) 146 return true; 147 if (in_interrupt() || panic_on_oops || 148 !current->pid || is_global_init(current)) 149 return true; 150 151 return false; 152 } 153 154 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; 155 static int die_owner = -1; 156 static unsigned int die_nest_count; 157 static int die_counter; 158 159 extern void panic_flush_kmsg_start(void) 160 { 161 /* 162 * These are mostly taken from kernel/panic.c, but tries to do 163 * relatively minimal work. Don't use delay functions (TB may 164 * be broken), don't crash dump (need to set a firmware log), 165 * don't run notifiers. We do want to get some information to 166 * Linux console. 167 */ 168 console_verbose(); 169 bust_spinlocks(1); 170 } 171 172 extern void panic_flush_kmsg_end(void) 173 { 174 printk_safe_flush_on_panic(); 175 kmsg_dump(KMSG_DUMP_PANIC); 176 bust_spinlocks(0); 177 debug_locks_off(); 178 console_flush_on_panic(CONSOLE_FLUSH_PENDING); 179 } 180 181 static unsigned long oops_begin(struct pt_regs *regs) 182 { 183 int cpu; 184 unsigned long flags; 185 186 oops_enter(); 187 188 /* racy, but better than risking deadlock. */ 189 raw_local_irq_save(flags); 190 cpu = smp_processor_id(); 191 if (!arch_spin_trylock(&die_lock)) { 192 if (cpu == die_owner) 193 /* nested oops. should stop eventually */; 194 else 195 arch_spin_lock(&die_lock); 196 } 197 die_nest_count++; 198 die_owner = cpu; 199 console_verbose(); 200 bust_spinlocks(1); 201 if (machine_is(powermac)) 202 pmac_backlight_unblank(); 203 return flags; 204 } 205 NOKPROBE_SYMBOL(oops_begin); 206 207 static void oops_end(unsigned long flags, struct pt_regs *regs, 208 int signr) 209 { 210 bust_spinlocks(0); 211 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 212 die_nest_count--; 213 oops_exit(); 214 printk("\n"); 215 if (!die_nest_count) { 216 /* Nest count reaches zero, release the lock. */ 217 die_owner = -1; 218 arch_spin_unlock(&die_lock); 219 } 220 raw_local_irq_restore(flags); 221 222 /* 223 * system_reset_excption handles debugger, crash dump, panic, for 0x100 224 */ 225 if (TRAP(regs) == 0x100) 226 return; 227 228 crash_fadump(regs, "die oops"); 229 230 if (kexec_should_crash(current)) 231 crash_kexec(regs); 232 233 if (!signr) 234 return; 235 236 /* 237 * While our oops output is serialised by a spinlock, output 238 * from panic() called below can race and corrupt it. If we 239 * know we are going to panic, delay for 1 second so we have a 240 * chance to get clean backtraces from all CPUs that are oopsing. 241 */ 242 if (in_interrupt() || panic_on_oops || !current->pid || 243 is_global_init(current)) { 244 mdelay(MSEC_PER_SEC); 245 } 246 247 if (panic_on_oops) 248 panic("Fatal exception"); 249 do_exit(signr); 250 } 251 NOKPROBE_SYMBOL(oops_end); 252 253 static int __die(const char *str, struct pt_regs *regs, long err) 254 { 255 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); 256 257 printk("%s PAGE_SIZE=%luK%s%s%s%s%s%s%s %s\n", 258 IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN) ? "LE" : "BE", 259 PAGE_SIZE / 1024, 260 early_radix_enabled() ? " MMU=Radix" : "", 261 early_mmu_has_feature(MMU_FTR_HPTE_TABLE) ? " MMU=Hash" : "", 262 IS_ENABLED(CONFIG_PREEMPT) ? " PREEMPT" : "", 263 IS_ENABLED(CONFIG_SMP) ? " SMP" : "", 264 IS_ENABLED(CONFIG_SMP) ? (" NR_CPUS=" __stringify(NR_CPUS)) : "", 265 debug_pagealloc_enabled() ? " DEBUG_PAGEALLOC" : "", 266 IS_ENABLED(CONFIG_NUMA) ? " NUMA" : "", 267 ppc_md.name ? ppc_md.name : ""); 268 269 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP) 270 return 1; 271 272 print_modules(); 273 show_regs(regs); 274 275 return 0; 276 } 277 NOKPROBE_SYMBOL(__die); 278 279 void die(const char *str, struct pt_regs *regs, long err) 280 { 281 unsigned long flags; 282 283 /* 284 * system_reset_excption handles debugger, crash dump, panic, for 0x100 285 */ 286 if (TRAP(regs) != 0x100) { 287 if (debugger(regs)) 288 return; 289 } 290 291 flags = oops_begin(regs); 292 if (__die(str, regs, err)) 293 err = 0; 294 oops_end(flags, regs, err); 295 } 296 NOKPROBE_SYMBOL(die); 297 298 void user_single_step_report(struct pt_regs *regs) 299 { 300 force_sig_fault(SIGTRAP, TRAP_TRACE, (void __user *)regs->nip, current); 301 } 302 303 static void show_signal_msg(int signr, struct pt_regs *regs, int code, 304 unsigned long addr) 305 { 306 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, 307 DEFAULT_RATELIMIT_BURST); 308 309 if (!show_unhandled_signals) 310 return; 311 312 if (!unhandled_signal(current, signr)) 313 return; 314 315 if (!__ratelimit(&rs)) 316 return; 317 318 pr_info("%s[%d]: %s (%d) at %lx nip %lx lr %lx code %x", 319 current->comm, current->pid, signame(signr), signr, 320 addr, regs->nip, regs->link, code); 321 322 print_vma_addr(KERN_CONT " in ", regs->nip); 323 324 pr_cont("\n"); 325 326 show_user_instructions(regs); 327 } 328 329 static bool exception_common(int signr, struct pt_regs *regs, int code, 330 unsigned long addr) 331 { 332 if (!user_mode(regs)) { 333 die("Exception in kernel mode", regs, signr); 334 return false; 335 } 336 337 show_signal_msg(signr, regs, code, addr); 338 339 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs)) 340 local_irq_enable(); 341 342 current->thread.trap_nr = code; 343 344 /* 345 * Save all the pkey registers AMR/IAMR/UAMOR. Eg: Core dumps need 346 * to capture the content, if the task gets killed. 347 */ 348 thread_pkey_regs_save(¤t->thread); 349 350 return true; 351 } 352 353 void _exception_pkey(struct pt_regs *regs, unsigned long addr, int key) 354 { 355 if (!exception_common(SIGSEGV, regs, SEGV_PKUERR, addr)) 356 return; 357 358 force_sig_pkuerr((void __user *) addr, key); 359 } 360 361 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) 362 { 363 if (!exception_common(signr, regs, code, addr)) 364 return; 365 366 force_sig_fault(signr, code, (void __user *)addr, current); 367 } 368 369 /* 370 * The interrupt architecture has a quirk in that the HV interrupts excluding 371 * the NMIs (0x100 and 0x200) do not clear MSR[RI] at entry. The first thing 372 * that an interrupt handler must do is save off a GPR into a scratch register, 373 * and all interrupts on POWERNV (HV=1) use the HSPRG1 register as scratch. 374 * Therefore an NMI can clobber an HV interrupt's live HSPRG1 without noticing 375 * that it is non-reentrant, which leads to random data corruption. 376 * 377 * The solution is for NMI interrupts in HV mode to check if they originated 378 * from these critical HV interrupt regions. If so, then mark them not 379 * recoverable. 380 * 381 * An alternative would be for HV NMIs to use SPRG for scratch to avoid the 382 * HSPRG1 clobber, however this would cause guest SPRG to be clobbered. Linux 383 * guests should always have MSR[RI]=0 when its scratch SPRG is in use, so 384 * that would work. However any other guest OS that may have the SPRG live 385 * and MSR[RI]=1 could encounter silent corruption. 386 * 387 * Builds that do not support KVM could take this second option to increase 388 * the recoverability of NMIs. 389 */ 390 void hv_nmi_check_nonrecoverable(struct pt_regs *regs) 391 { 392 #ifdef CONFIG_PPC_POWERNV 393 unsigned long kbase = (unsigned long)_stext; 394 unsigned long nip = regs->nip; 395 396 if (!(regs->msr & MSR_RI)) 397 return; 398 if (!(regs->msr & MSR_HV)) 399 return; 400 if (regs->msr & MSR_PR) 401 return; 402 403 /* 404 * Now test if the interrupt has hit a range that may be using 405 * HSPRG1 without having RI=0 (i.e., an HSRR interrupt). The 406 * problem ranges all run un-relocated. Test real and virt modes 407 * at the same time by droping the high bit of the nip (virt mode 408 * entry points still have the +0x4000 offset). 409 */ 410 nip &= ~0xc000000000000000ULL; 411 if ((nip >= 0x500 && nip < 0x600) || (nip >= 0x4500 && nip < 0x4600)) 412 goto nonrecoverable; 413 if ((nip >= 0x980 && nip < 0xa00) || (nip >= 0x4980 && nip < 0x4a00)) 414 goto nonrecoverable; 415 if ((nip >= 0xe00 && nip < 0xec0) || (nip >= 0x4e00 && nip < 0x4ec0)) 416 goto nonrecoverable; 417 if ((nip >= 0xf80 && nip < 0xfa0) || (nip >= 0x4f80 && nip < 0x4fa0)) 418 goto nonrecoverable; 419 420 /* Trampoline code runs un-relocated so subtract kbase. */ 421 if (nip >= (unsigned long)(start_real_trampolines - kbase) && 422 nip < (unsigned long)(end_real_trampolines - kbase)) 423 goto nonrecoverable; 424 if (nip >= (unsigned long)(start_virt_trampolines - kbase) && 425 nip < (unsigned long)(end_virt_trampolines - kbase)) 426 goto nonrecoverable; 427 return; 428 429 nonrecoverable: 430 regs->msr &= ~MSR_RI; 431 #endif 432 } 433 434 void system_reset_exception(struct pt_regs *regs) 435 { 436 unsigned long hsrr0, hsrr1; 437 bool nested = in_nmi(); 438 bool saved_hsrrs = false; 439 440 /* 441 * Avoid crashes in case of nested NMI exceptions. Recoverability 442 * is determined by RI and in_nmi 443 */ 444 if (!nested) 445 nmi_enter(); 446 447 /* 448 * System reset can interrupt code where HSRRs are live and MSR[RI]=1. 449 * The system reset interrupt itself may clobber HSRRs (e.g., to call 450 * OPAL), so save them here and restore them before returning. 451 * 452 * Machine checks don't need to save HSRRs, as the real mode handler 453 * is careful to avoid them, and the regular handler is not delivered 454 * as an NMI. 455 */ 456 if (cpu_has_feature(CPU_FTR_HVMODE)) { 457 hsrr0 = mfspr(SPRN_HSRR0); 458 hsrr1 = mfspr(SPRN_HSRR1); 459 saved_hsrrs = true; 460 } 461 462 hv_nmi_check_nonrecoverable(regs); 463 464 __this_cpu_inc(irq_stat.sreset_irqs); 465 466 /* See if any machine dependent calls */ 467 if (ppc_md.system_reset_exception) { 468 if (ppc_md.system_reset_exception(regs)) 469 goto out; 470 } 471 472 if (debugger(regs)) 473 goto out; 474 475 /* 476 * A system reset is a request to dump, so we always send 477 * it through the crashdump code (if fadump or kdump are 478 * registered). 479 */ 480 crash_fadump(regs, "System Reset"); 481 482 crash_kexec(regs); 483 484 /* 485 * We aren't the primary crash CPU. We need to send it 486 * to a holding pattern to avoid it ending up in the panic 487 * code. 488 */ 489 crash_kexec_secondary(regs); 490 491 /* 492 * No debugger or crash dump registered, print logs then 493 * panic. 494 */ 495 die("System Reset", regs, SIGABRT); 496 497 mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */ 498 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 499 nmi_panic(regs, "System Reset"); 500 501 out: 502 #ifdef CONFIG_PPC_BOOK3S_64 503 BUG_ON(get_paca()->in_nmi == 0); 504 if (get_paca()->in_nmi > 1) 505 nmi_panic(regs, "Unrecoverable nested System Reset"); 506 #endif 507 /* Must die if the interrupt is not recoverable */ 508 if (!(regs->msr & MSR_RI)) 509 nmi_panic(regs, "Unrecoverable System Reset"); 510 511 if (saved_hsrrs) { 512 mtspr(SPRN_HSRR0, hsrr0); 513 mtspr(SPRN_HSRR1, hsrr1); 514 } 515 516 if (!nested) 517 nmi_exit(); 518 519 /* What should we do here? We could issue a shutdown or hard reset. */ 520 } 521 522 /* 523 * I/O accesses can cause machine checks on powermacs. 524 * Check if the NIP corresponds to the address of a sync 525 * instruction for which there is an entry in the exception 526 * table. 527 * Note that the 601 only takes a machine check on TEA 528 * (transfer error ack) signal assertion, and does not 529 * set any of the top 16 bits of SRR1. 530 * -- paulus. 531 */ 532 static inline int check_io_access(struct pt_regs *regs) 533 { 534 #ifdef CONFIG_PPC32 535 unsigned long msr = regs->msr; 536 const struct exception_table_entry *entry; 537 unsigned int *nip = (unsigned int *)regs->nip; 538 539 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) 540 && (entry = search_exception_tables(regs->nip)) != NULL) { 541 /* 542 * Check that it's a sync instruction, or somewhere 543 * in the twi; isync; nop sequence that inb/inw/inl uses. 544 * As the address is in the exception table 545 * we should be able to read the instr there. 546 * For the debug message, we look at the preceding 547 * load or store. 548 */ 549 if (*nip == PPC_INST_NOP) 550 nip -= 2; 551 else if (*nip == PPC_INST_ISYNC) 552 --nip; 553 if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) { 554 unsigned int rb; 555 556 --nip; 557 rb = (*nip >> 11) & 0x1f; 558 printk(KERN_DEBUG "%s bad port %lx at %p\n", 559 (*nip & 0x100)? "OUT to": "IN from", 560 regs->gpr[rb] - _IO_BASE, nip); 561 regs->msr |= MSR_RI; 562 regs->nip = extable_fixup(entry); 563 return 1; 564 } 565 } 566 #endif /* CONFIG_PPC32 */ 567 return 0; 568 } 569 570 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 571 /* On 4xx, the reason for the machine check or program exception 572 is in the ESR. */ 573 #define get_reason(regs) ((regs)->dsisr) 574 #define REASON_FP ESR_FP 575 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) 576 #define REASON_PRIVILEGED ESR_PPR 577 #define REASON_TRAP ESR_PTR 578 579 /* single-step stuff */ 580 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC) 581 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC) 582 #define clear_br_trace(regs) do {} while(0) 583 #else 584 /* On non-4xx, the reason for the machine check or program 585 exception is in the MSR. */ 586 #define get_reason(regs) ((regs)->msr) 587 #define REASON_TM SRR1_PROGTM 588 #define REASON_FP SRR1_PROGFPE 589 #define REASON_ILLEGAL SRR1_PROGILL 590 #define REASON_PRIVILEGED SRR1_PROGPRIV 591 #define REASON_TRAP SRR1_PROGTRAP 592 593 #define single_stepping(regs) ((regs)->msr & MSR_SE) 594 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) 595 #define clear_br_trace(regs) ((regs)->msr &= ~MSR_BE) 596 #endif 597 598 #if defined(CONFIG_E500) 599 int machine_check_e500mc(struct pt_regs *regs) 600 { 601 unsigned long mcsr = mfspr(SPRN_MCSR); 602 unsigned long pvr = mfspr(SPRN_PVR); 603 unsigned long reason = mcsr; 604 int recoverable = 1; 605 606 if (reason & MCSR_LD) { 607 recoverable = fsl_rio_mcheck_exception(regs); 608 if (recoverable == 1) 609 goto silent_out; 610 } 611 612 printk("Machine check in kernel mode.\n"); 613 printk("Caused by (from MCSR=%lx): ", reason); 614 615 if (reason & MCSR_MCP) 616 pr_cont("Machine Check Signal\n"); 617 618 if (reason & MCSR_ICPERR) { 619 pr_cont("Instruction Cache Parity Error\n"); 620 621 /* 622 * This is recoverable by invalidating the i-cache. 623 */ 624 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); 625 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) 626 ; 627 628 /* 629 * This will generally be accompanied by an instruction 630 * fetch error report -- only treat MCSR_IF as fatal 631 * if it wasn't due to an L1 parity error. 632 */ 633 reason &= ~MCSR_IF; 634 } 635 636 if (reason & MCSR_DCPERR_MC) { 637 pr_cont("Data Cache Parity Error\n"); 638 639 /* 640 * In write shadow mode we auto-recover from the error, but it 641 * may still get logged and cause a machine check. We should 642 * only treat the non-write shadow case as non-recoverable. 643 */ 644 /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit 645 * is not implemented but L1 data cache always runs in write 646 * shadow mode. Hence on data cache parity errors HW will 647 * automatically invalidate the L1 Data Cache. 648 */ 649 if (PVR_VER(pvr) != PVR_VER_E6500) { 650 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) 651 recoverable = 0; 652 } 653 } 654 655 if (reason & MCSR_L2MMU_MHIT) { 656 pr_cont("Hit on multiple TLB entries\n"); 657 recoverable = 0; 658 } 659 660 if (reason & MCSR_NMI) 661 pr_cont("Non-maskable interrupt\n"); 662 663 if (reason & MCSR_IF) { 664 pr_cont("Instruction Fetch Error Report\n"); 665 recoverable = 0; 666 } 667 668 if (reason & MCSR_LD) { 669 pr_cont("Load Error Report\n"); 670 recoverable = 0; 671 } 672 673 if (reason & MCSR_ST) { 674 pr_cont("Store Error Report\n"); 675 recoverable = 0; 676 } 677 678 if (reason & MCSR_LDG) { 679 pr_cont("Guarded Load Error Report\n"); 680 recoverable = 0; 681 } 682 683 if (reason & MCSR_TLBSYNC) 684 pr_cont("Simultaneous tlbsync operations\n"); 685 686 if (reason & MCSR_BSL2_ERR) { 687 pr_cont("Level 2 Cache Error\n"); 688 recoverable = 0; 689 } 690 691 if (reason & MCSR_MAV) { 692 u64 addr; 693 694 addr = mfspr(SPRN_MCAR); 695 addr |= (u64)mfspr(SPRN_MCARU) << 32; 696 697 pr_cont("Machine Check %s Address: %#llx\n", 698 reason & MCSR_MEA ? "Effective" : "Physical", addr); 699 } 700 701 silent_out: 702 mtspr(SPRN_MCSR, mcsr); 703 return mfspr(SPRN_MCSR) == 0 && recoverable; 704 } 705 706 int machine_check_e500(struct pt_regs *regs) 707 { 708 unsigned long reason = mfspr(SPRN_MCSR); 709 710 if (reason & MCSR_BUS_RBERR) { 711 if (fsl_rio_mcheck_exception(regs)) 712 return 1; 713 if (fsl_pci_mcheck_exception(regs)) 714 return 1; 715 } 716 717 printk("Machine check in kernel mode.\n"); 718 printk("Caused by (from MCSR=%lx): ", reason); 719 720 if (reason & MCSR_MCP) 721 pr_cont("Machine Check Signal\n"); 722 if (reason & MCSR_ICPERR) 723 pr_cont("Instruction Cache Parity Error\n"); 724 if (reason & MCSR_DCP_PERR) 725 pr_cont("Data Cache Push Parity Error\n"); 726 if (reason & MCSR_DCPERR) 727 pr_cont("Data Cache Parity Error\n"); 728 if (reason & MCSR_BUS_IAERR) 729 pr_cont("Bus - Instruction Address Error\n"); 730 if (reason & MCSR_BUS_RAERR) 731 pr_cont("Bus - Read Address Error\n"); 732 if (reason & MCSR_BUS_WAERR) 733 pr_cont("Bus - Write Address Error\n"); 734 if (reason & MCSR_BUS_IBERR) 735 pr_cont("Bus - Instruction Data Error\n"); 736 if (reason & MCSR_BUS_RBERR) 737 pr_cont("Bus - Read Data Bus Error\n"); 738 if (reason & MCSR_BUS_WBERR) 739 pr_cont("Bus - Write Data Bus Error\n"); 740 if (reason & MCSR_BUS_IPERR) 741 pr_cont("Bus - Instruction Parity Error\n"); 742 if (reason & MCSR_BUS_RPERR) 743 pr_cont("Bus - Read Parity Error\n"); 744 745 return 0; 746 } 747 748 int machine_check_generic(struct pt_regs *regs) 749 { 750 return 0; 751 } 752 #elif defined(CONFIG_E200) 753 int machine_check_e200(struct pt_regs *regs) 754 { 755 unsigned long reason = mfspr(SPRN_MCSR); 756 757 printk("Machine check in kernel mode.\n"); 758 printk("Caused by (from MCSR=%lx): ", reason); 759 760 if (reason & MCSR_MCP) 761 pr_cont("Machine Check Signal\n"); 762 if (reason & MCSR_CP_PERR) 763 pr_cont("Cache Push Parity Error\n"); 764 if (reason & MCSR_CPERR) 765 pr_cont("Cache Parity Error\n"); 766 if (reason & MCSR_EXCP_ERR) 767 pr_cont("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); 768 if (reason & MCSR_BUS_IRERR) 769 pr_cont("Bus - Read Bus Error on instruction fetch\n"); 770 if (reason & MCSR_BUS_DRERR) 771 pr_cont("Bus - Read Bus Error on data load\n"); 772 if (reason & MCSR_BUS_WRERR) 773 pr_cont("Bus - Write Bus Error on buffered store or cache line push\n"); 774 775 return 0; 776 } 777 #elif defined(CONFIG_PPC32) 778 int machine_check_generic(struct pt_regs *regs) 779 { 780 unsigned long reason = regs->msr; 781 782 printk("Machine check in kernel mode.\n"); 783 printk("Caused by (from SRR1=%lx): ", reason); 784 switch (reason & 0x601F0000) { 785 case 0x80000: 786 pr_cont("Machine check signal\n"); 787 break; 788 case 0: /* for 601 */ 789 case 0x40000: 790 case 0x140000: /* 7450 MSS error and TEA */ 791 pr_cont("Transfer error ack signal\n"); 792 break; 793 case 0x20000: 794 pr_cont("Data parity error signal\n"); 795 break; 796 case 0x10000: 797 pr_cont("Address parity error signal\n"); 798 break; 799 case 0x20000000: 800 pr_cont("L1 Data Cache error\n"); 801 break; 802 case 0x40000000: 803 pr_cont("L1 Instruction Cache error\n"); 804 break; 805 case 0x00100000: 806 pr_cont("L2 data cache parity error\n"); 807 break; 808 default: 809 pr_cont("Unknown values in msr\n"); 810 } 811 return 0; 812 } 813 #endif /* everything else */ 814 815 void machine_check_exception(struct pt_regs *regs) 816 { 817 int recover = 0; 818 bool nested = in_nmi(); 819 if (!nested) 820 nmi_enter(); 821 822 __this_cpu_inc(irq_stat.mce_exceptions); 823 824 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 825 826 /* See if any machine dependent calls. In theory, we would want 827 * to call the CPU first, and call the ppc_md. one if the CPU 828 * one returns a positive number. However there is existing code 829 * that assumes the board gets a first chance, so let's keep it 830 * that way for now and fix things later. --BenH. 831 */ 832 if (ppc_md.machine_check_exception) 833 recover = ppc_md.machine_check_exception(regs); 834 else if (cur_cpu_spec->machine_check) 835 recover = cur_cpu_spec->machine_check(regs); 836 837 if (recover > 0) 838 goto bail; 839 840 if (debugger_fault_handler(regs)) 841 goto bail; 842 843 if (check_io_access(regs)) 844 goto bail; 845 846 if (!nested) 847 nmi_exit(); 848 849 die("Machine check", regs, SIGBUS); 850 851 /* Must die if the interrupt is not recoverable */ 852 if (!(regs->msr & MSR_RI)) 853 nmi_panic(regs, "Unrecoverable Machine check"); 854 855 return; 856 857 bail: 858 if (!nested) 859 nmi_exit(); 860 } 861 862 void SMIException(struct pt_regs *regs) 863 { 864 die("System Management Interrupt", regs, SIGABRT); 865 } 866 867 #ifdef CONFIG_VSX 868 static void p9_hmi_special_emu(struct pt_regs *regs) 869 { 870 unsigned int ra, rb, t, i, sel, instr, rc; 871 const void __user *addr; 872 u8 vbuf[16], *vdst; 873 unsigned long ea, msr, msr_mask; 874 bool swap; 875 876 if (__get_user_inatomic(instr, (unsigned int __user *)regs->nip)) 877 return; 878 879 /* 880 * lxvb16x opcode: 0x7c0006d8 881 * lxvd2x opcode: 0x7c000698 882 * lxvh8x opcode: 0x7c000658 883 * lxvw4x opcode: 0x7c000618 884 */ 885 if ((instr & 0xfc00073e) != 0x7c000618) { 886 pr_devel("HMI vec emu: not vector CI %i:%s[%d] nip=%016lx" 887 " instr=%08x\n", 888 smp_processor_id(), current->comm, current->pid, 889 regs->nip, instr); 890 return; 891 } 892 893 /* Grab vector registers into the task struct */ 894 msr = regs->msr; /* Grab msr before we flush the bits */ 895 flush_vsx_to_thread(current); 896 enable_kernel_altivec(); 897 898 /* 899 * Is userspace running with a different endian (this is rare but 900 * not impossible) 901 */ 902 swap = (msr & MSR_LE) != (MSR_KERNEL & MSR_LE); 903 904 /* Decode the instruction */ 905 ra = (instr >> 16) & 0x1f; 906 rb = (instr >> 11) & 0x1f; 907 t = (instr >> 21) & 0x1f; 908 if (instr & 1) 909 vdst = (u8 *)¤t->thread.vr_state.vr[t]; 910 else 911 vdst = (u8 *)¤t->thread.fp_state.fpr[t][0]; 912 913 /* Grab the vector address */ 914 ea = regs->gpr[rb] + (ra ? regs->gpr[ra] : 0); 915 if (is_32bit_task()) 916 ea &= 0xfffffffful; 917 addr = (__force const void __user *)ea; 918 919 /* Check it */ 920 if (!access_ok(addr, 16)) { 921 pr_devel("HMI vec emu: bad access %i:%s[%d] nip=%016lx" 922 " instr=%08x addr=%016lx\n", 923 smp_processor_id(), current->comm, current->pid, 924 regs->nip, instr, (unsigned long)addr); 925 return; 926 } 927 928 /* Read the vector */ 929 rc = 0; 930 if ((unsigned long)addr & 0xfUL) 931 /* unaligned case */ 932 rc = __copy_from_user_inatomic(vbuf, addr, 16); 933 else 934 __get_user_atomic_128_aligned(vbuf, addr, rc); 935 if (rc) { 936 pr_devel("HMI vec emu: page fault %i:%s[%d] nip=%016lx" 937 " instr=%08x addr=%016lx\n", 938 smp_processor_id(), current->comm, current->pid, 939 regs->nip, instr, (unsigned long)addr); 940 return; 941 } 942 943 pr_devel("HMI vec emu: emulated vector CI %i:%s[%d] nip=%016lx" 944 " instr=%08x addr=%016lx\n", 945 smp_processor_id(), current->comm, current->pid, regs->nip, 946 instr, (unsigned long) addr); 947 948 /* Grab instruction "selector" */ 949 sel = (instr >> 6) & 3; 950 951 /* 952 * Check to make sure the facility is actually enabled. This 953 * could happen if we get a false positive hit. 954 * 955 * lxvd2x/lxvw4x always check MSR VSX sel = 0,2 956 * lxvh8x/lxvb16x check MSR VSX or VEC depending on VSR used sel = 1,3 957 */ 958 msr_mask = MSR_VSX; 959 if ((sel & 1) && (instr & 1)) /* lxvh8x & lxvb16x + VSR >= 32 */ 960 msr_mask = MSR_VEC; 961 if (!(msr & msr_mask)) { 962 pr_devel("HMI vec emu: MSR fac clear %i:%s[%d] nip=%016lx" 963 " instr=%08x msr:%016lx\n", 964 smp_processor_id(), current->comm, current->pid, 965 regs->nip, instr, msr); 966 return; 967 } 968 969 /* Do logging here before we modify sel based on endian */ 970 switch (sel) { 971 case 0: /* lxvw4x */ 972 PPC_WARN_EMULATED(lxvw4x, regs); 973 break; 974 case 1: /* lxvh8x */ 975 PPC_WARN_EMULATED(lxvh8x, regs); 976 break; 977 case 2: /* lxvd2x */ 978 PPC_WARN_EMULATED(lxvd2x, regs); 979 break; 980 case 3: /* lxvb16x */ 981 PPC_WARN_EMULATED(lxvb16x, regs); 982 break; 983 } 984 985 #ifdef __LITTLE_ENDIAN__ 986 /* 987 * An LE kernel stores the vector in the task struct as an LE 988 * byte array (effectively swapping both the components and 989 * the content of the components). Those instructions expect 990 * the components to remain in ascending address order, so we 991 * swap them back. 992 * 993 * If we are running a BE user space, the expectation is that 994 * of a simple memcpy, so forcing the emulation to look like 995 * a lxvb16x should do the trick. 996 */ 997 if (swap) 998 sel = 3; 999 1000 switch (sel) { 1001 case 0: /* lxvw4x */ 1002 for (i = 0; i < 4; i++) 1003 ((u32 *)vdst)[i] = ((u32 *)vbuf)[3-i]; 1004 break; 1005 case 1: /* lxvh8x */ 1006 for (i = 0; i < 8; i++) 1007 ((u16 *)vdst)[i] = ((u16 *)vbuf)[7-i]; 1008 break; 1009 case 2: /* lxvd2x */ 1010 for (i = 0; i < 2; i++) 1011 ((u64 *)vdst)[i] = ((u64 *)vbuf)[1-i]; 1012 break; 1013 case 3: /* lxvb16x */ 1014 for (i = 0; i < 16; i++) 1015 vdst[i] = vbuf[15-i]; 1016 break; 1017 } 1018 #else /* __LITTLE_ENDIAN__ */ 1019 /* On a big endian kernel, a BE userspace only needs a memcpy */ 1020 if (!swap) 1021 sel = 3; 1022 1023 /* Otherwise, we need to swap the content of the components */ 1024 switch (sel) { 1025 case 0: /* lxvw4x */ 1026 for (i = 0; i < 4; i++) 1027 ((u32 *)vdst)[i] = cpu_to_le32(((u32 *)vbuf)[i]); 1028 break; 1029 case 1: /* lxvh8x */ 1030 for (i = 0; i < 8; i++) 1031 ((u16 *)vdst)[i] = cpu_to_le16(((u16 *)vbuf)[i]); 1032 break; 1033 case 2: /* lxvd2x */ 1034 for (i = 0; i < 2; i++) 1035 ((u64 *)vdst)[i] = cpu_to_le64(((u64 *)vbuf)[i]); 1036 break; 1037 case 3: /* lxvb16x */ 1038 memcpy(vdst, vbuf, 16); 1039 break; 1040 } 1041 #endif /* !__LITTLE_ENDIAN__ */ 1042 1043 /* Go to next instruction */ 1044 regs->nip += 4; 1045 } 1046 #endif /* CONFIG_VSX */ 1047 1048 void handle_hmi_exception(struct pt_regs *regs) 1049 { 1050 struct pt_regs *old_regs; 1051 1052 old_regs = set_irq_regs(regs); 1053 irq_enter(); 1054 1055 #ifdef CONFIG_VSX 1056 /* Real mode flagged P9 special emu is needed */ 1057 if (local_paca->hmi_p9_special_emu) { 1058 local_paca->hmi_p9_special_emu = 0; 1059 1060 /* 1061 * We don't want to take page faults while doing the 1062 * emulation, we just replay the instruction if necessary. 1063 */ 1064 pagefault_disable(); 1065 p9_hmi_special_emu(regs); 1066 pagefault_enable(); 1067 } 1068 #endif /* CONFIG_VSX */ 1069 1070 if (ppc_md.handle_hmi_exception) 1071 ppc_md.handle_hmi_exception(regs); 1072 1073 irq_exit(); 1074 set_irq_regs(old_regs); 1075 } 1076 1077 void unknown_exception(struct pt_regs *regs) 1078 { 1079 enum ctx_state prev_state = exception_enter(); 1080 1081 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 1082 regs->nip, regs->msr, regs->trap); 1083 1084 _exception(SIGTRAP, regs, TRAP_UNK, 0); 1085 1086 exception_exit(prev_state); 1087 } 1088 1089 void instruction_breakpoint_exception(struct pt_regs *regs) 1090 { 1091 enum ctx_state prev_state = exception_enter(); 1092 1093 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, 1094 5, SIGTRAP) == NOTIFY_STOP) 1095 goto bail; 1096 if (debugger_iabr_match(regs)) 1097 goto bail; 1098 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1099 1100 bail: 1101 exception_exit(prev_state); 1102 } 1103 1104 void RunModeException(struct pt_regs *regs) 1105 { 1106 _exception(SIGTRAP, regs, TRAP_UNK, 0); 1107 } 1108 1109 void single_step_exception(struct pt_regs *regs) 1110 { 1111 enum ctx_state prev_state = exception_enter(); 1112 1113 clear_single_step(regs); 1114 clear_br_trace(regs); 1115 1116 if (kprobe_post_handler(regs)) 1117 return; 1118 1119 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 1120 5, SIGTRAP) == NOTIFY_STOP) 1121 goto bail; 1122 if (debugger_sstep(regs)) 1123 goto bail; 1124 1125 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 1126 1127 bail: 1128 exception_exit(prev_state); 1129 } 1130 NOKPROBE_SYMBOL(single_step_exception); 1131 1132 /* 1133 * After we have successfully emulated an instruction, we have to 1134 * check if the instruction was being single-stepped, and if so, 1135 * pretend we got a single-step exception. This was pointed out 1136 * by Kumar Gala. -- paulus 1137 */ 1138 static void emulate_single_step(struct pt_regs *regs) 1139 { 1140 if (single_stepping(regs)) 1141 single_step_exception(regs); 1142 } 1143 1144 static inline int __parse_fpscr(unsigned long fpscr) 1145 { 1146 int ret = FPE_FLTUNK; 1147 1148 /* Invalid operation */ 1149 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) 1150 ret = FPE_FLTINV; 1151 1152 /* Overflow */ 1153 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) 1154 ret = FPE_FLTOVF; 1155 1156 /* Underflow */ 1157 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) 1158 ret = FPE_FLTUND; 1159 1160 /* Divide by zero */ 1161 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) 1162 ret = FPE_FLTDIV; 1163 1164 /* Inexact result */ 1165 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) 1166 ret = FPE_FLTRES; 1167 1168 return ret; 1169 } 1170 1171 static void parse_fpe(struct pt_regs *regs) 1172 { 1173 int code = 0; 1174 1175 flush_fp_to_thread(current); 1176 1177 code = __parse_fpscr(current->thread.fp_state.fpscr); 1178 1179 _exception(SIGFPE, regs, code, regs->nip); 1180 } 1181 1182 /* 1183 * Illegal instruction emulation support. Originally written to 1184 * provide the PVR to user applications using the mfspr rd, PVR. 1185 * Return non-zero if we can't emulate, or -EFAULT if the associated 1186 * memory access caused an access fault. Return zero on success. 1187 * 1188 * There are a couple of ways to do this, either "decode" the instruction 1189 * or directly match lots of bits. In this case, matching lots of 1190 * bits is faster and easier. 1191 * 1192 */ 1193 static int emulate_string_inst(struct pt_regs *regs, u32 instword) 1194 { 1195 u8 rT = (instword >> 21) & 0x1f; 1196 u8 rA = (instword >> 16) & 0x1f; 1197 u8 NB_RB = (instword >> 11) & 0x1f; 1198 u32 num_bytes; 1199 unsigned long EA; 1200 int pos = 0; 1201 1202 /* Early out if we are an invalid form of lswx */ 1203 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) 1204 if ((rT == rA) || (rT == NB_RB)) 1205 return -EINVAL; 1206 1207 EA = (rA == 0) ? 0 : regs->gpr[rA]; 1208 1209 switch (instword & PPC_INST_STRING_MASK) { 1210 case PPC_INST_LSWX: 1211 case PPC_INST_STSWX: 1212 EA += NB_RB; 1213 num_bytes = regs->xer & 0x7f; 1214 break; 1215 case PPC_INST_LSWI: 1216 case PPC_INST_STSWI: 1217 num_bytes = (NB_RB == 0) ? 32 : NB_RB; 1218 break; 1219 default: 1220 return -EINVAL; 1221 } 1222 1223 while (num_bytes != 0) 1224 { 1225 u8 val; 1226 u32 shift = 8 * (3 - (pos & 0x3)); 1227 1228 /* if process is 32-bit, clear upper 32 bits of EA */ 1229 if ((regs->msr & MSR_64BIT) == 0) 1230 EA &= 0xFFFFFFFF; 1231 1232 switch ((instword & PPC_INST_STRING_MASK)) { 1233 case PPC_INST_LSWX: 1234 case PPC_INST_LSWI: 1235 if (get_user(val, (u8 __user *)EA)) 1236 return -EFAULT; 1237 /* first time updating this reg, 1238 * zero it out */ 1239 if (pos == 0) 1240 regs->gpr[rT] = 0; 1241 regs->gpr[rT] |= val << shift; 1242 break; 1243 case PPC_INST_STSWI: 1244 case PPC_INST_STSWX: 1245 val = regs->gpr[rT] >> shift; 1246 if (put_user(val, (u8 __user *)EA)) 1247 return -EFAULT; 1248 break; 1249 } 1250 /* move EA to next address */ 1251 EA += 1; 1252 num_bytes--; 1253 1254 /* manage our position within the register */ 1255 if (++pos == 4) { 1256 pos = 0; 1257 if (++rT == 32) 1258 rT = 0; 1259 } 1260 } 1261 1262 return 0; 1263 } 1264 1265 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) 1266 { 1267 u32 ra,rs; 1268 unsigned long tmp; 1269 1270 ra = (instword >> 16) & 0x1f; 1271 rs = (instword >> 21) & 0x1f; 1272 1273 tmp = regs->gpr[rs]; 1274 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); 1275 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); 1276 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; 1277 regs->gpr[ra] = tmp; 1278 1279 return 0; 1280 } 1281 1282 static int emulate_isel(struct pt_regs *regs, u32 instword) 1283 { 1284 u8 rT = (instword >> 21) & 0x1f; 1285 u8 rA = (instword >> 16) & 0x1f; 1286 u8 rB = (instword >> 11) & 0x1f; 1287 u8 BC = (instword >> 6) & 0x1f; 1288 u8 bit; 1289 unsigned long tmp; 1290 1291 tmp = (rA == 0) ? 0 : regs->gpr[rA]; 1292 bit = (regs->ccr >> (31 - BC)) & 0x1; 1293 1294 regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; 1295 1296 return 0; 1297 } 1298 1299 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1300 static inline bool tm_abort_check(struct pt_regs *regs, int cause) 1301 { 1302 /* If we're emulating a load/store in an active transaction, we cannot 1303 * emulate it as the kernel operates in transaction suspended context. 1304 * We need to abort the transaction. This creates a persistent TM 1305 * abort so tell the user what caused it with a new code. 1306 */ 1307 if (MSR_TM_TRANSACTIONAL(regs->msr)) { 1308 tm_enable(); 1309 tm_abort(cause); 1310 return true; 1311 } 1312 return false; 1313 } 1314 #else 1315 static inline bool tm_abort_check(struct pt_regs *regs, int reason) 1316 { 1317 return false; 1318 } 1319 #endif 1320 1321 static int emulate_instruction(struct pt_regs *regs) 1322 { 1323 u32 instword; 1324 u32 rd; 1325 1326 if (!user_mode(regs)) 1327 return -EINVAL; 1328 CHECK_FULL_REGS(regs); 1329 1330 if (get_user(instword, (u32 __user *)(regs->nip))) 1331 return -EFAULT; 1332 1333 /* Emulate the mfspr rD, PVR. */ 1334 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { 1335 PPC_WARN_EMULATED(mfpvr, regs); 1336 rd = (instword >> 21) & 0x1f; 1337 regs->gpr[rd] = mfspr(SPRN_PVR); 1338 return 0; 1339 } 1340 1341 /* Emulating the dcba insn is just a no-op. */ 1342 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { 1343 PPC_WARN_EMULATED(dcba, regs); 1344 return 0; 1345 } 1346 1347 /* Emulate the mcrxr insn. */ 1348 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { 1349 int shift = (instword >> 21) & 0x1c; 1350 unsigned long msk = 0xf0000000UL >> shift; 1351 1352 PPC_WARN_EMULATED(mcrxr, regs); 1353 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); 1354 regs->xer &= ~0xf0000000UL; 1355 return 0; 1356 } 1357 1358 /* Emulate load/store string insn. */ 1359 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { 1360 if (tm_abort_check(regs, 1361 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) 1362 return -EINVAL; 1363 PPC_WARN_EMULATED(string, regs); 1364 return emulate_string_inst(regs, instword); 1365 } 1366 1367 /* Emulate the popcntb (Population Count Bytes) instruction. */ 1368 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { 1369 PPC_WARN_EMULATED(popcntb, regs); 1370 return emulate_popcntb_inst(regs, instword); 1371 } 1372 1373 /* Emulate isel (Integer Select) instruction */ 1374 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { 1375 PPC_WARN_EMULATED(isel, regs); 1376 return emulate_isel(regs, instword); 1377 } 1378 1379 /* Emulate sync instruction variants */ 1380 if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) { 1381 PPC_WARN_EMULATED(sync, regs); 1382 asm volatile("sync"); 1383 return 0; 1384 } 1385 1386 #ifdef CONFIG_PPC64 1387 /* Emulate the mfspr rD, DSCR. */ 1388 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) == 1389 PPC_INST_MFSPR_DSCR_USER) || 1390 ((instword & PPC_INST_MFSPR_DSCR_MASK) == 1391 PPC_INST_MFSPR_DSCR)) && 1392 cpu_has_feature(CPU_FTR_DSCR)) { 1393 PPC_WARN_EMULATED(mfdscr, regs); 1394 rd = (instword >> 21) & 0x1f; 1395 regs->gpr[rd] = mfspr(SPRN_DSCR); 1396 return 0; 1397 } 1398 /* Emulate the mtspr DSCR, rD. */ 1399 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) == 1400 PPC_INST_MTSPR_DSCR_USER) || 1401 ((instword & PPC_INST_MTSPR_DSCR_MASK) == 1402 PPC_INST_MTSPR_DSCR)) && 1403 cpu_has_feature(CPU_FTR_DSCR)) { 1404 PPC_WARN_EMULATED(mtdscr, regs); 1405 rd = (instword >> 21) & 0x1f; 1406 current->thread.dscr = regs->gpr[rd]; 1407 current->thread.dscr_inherit = 1; 1408 mtspr(SPRN_DSCR, current->thread.dscr); 1409 return 0; 1410 } 1411 #endif 1412 1413 return -EINVAL; 1414 } 1415 1416 int is_valid_bugaddr(unsigned long addr) 1417 { 1418 return is_kernel_addr(addr); 1419 } 1420 1421 #ifdef CONFIG_MATH_EMULATION 1422 static int emulate_math(struct pt_regs *regs) 1423 { 1424 int ret; 1425 extern int do_mathemu(struct pt_regs *regs); 1426 1427 ret = do_mathemu(regs); 1428 if (ret >= 0) 1429 PPC_WARN_EMULATED(math, regs); 1430 1431 switch (ret) { 1432 case 0: 1433 emulate_single_step(regs); 1434 return 0; 1435 case 1: { 1436 int code = 0; 1437 code = __parse_fpscr(current->thread.fp_state.fpscr); 1438 _exception(SIGFPE, regs, code, regs->nip); 1439 return 0; 1440 } 1441 case -EFAULT: 1442 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1443 return 0; 1444 } 1445 1446 return -1; 1447 } 1448 #else 1449 static inline int emulate_math(struct pt_regs *regs) { return -1; } 1450 #endif 1451 1452 void program_check_exception(struct pt_regs *regs) 1453 { 1454 enum ctx_state prev_state = exception_enter(); 1455 unsigned int reason = get_reason(regs); 1456 1457 /* We can now get here via a FP Unavailable exception if the core 1458 * has no FPU, in that case the reason flags will be 0 */ 1459 1460 if (reason & REASON_FP) { 1461 /* IEEE FP exception */ 1462 parse_fpe(regs); 1463 goto bail; 1464 } 1465 if (reason & REASON_TRAP) { 1466 unsigned long bugaddr; 1467 /* Debugger is first in line to stop recursive faults in 1468 * rcu_lock, notify_die, or atomic_notifier_call_chain */ 1469 if (debugger_bpt(regs)) 1470 goto bail; 1471 1472 if (kprobe_handler(regs)) 1473 goto bail; 1474 1475 /* trap exception */ 1476 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) 1477 == NOTIFY_STOP) 1478 goto bail; 1479 1480 bugaddr = regs->nip; 1481 /* 1482 * Fixup bugaddr for BUG_ON() in real mode 1483 */ 1484 if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR)) 1485 bugaddr += PAGE_OFFSET; 1486 1487 if (!(regs->msr & MSR_PR) && /* not user-mode */ 1488 report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) { 1489 regs->nip += 4; 1490 goto bail; 1491 } 1492 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1493 goto bail; 1494 } 1495 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1496 if (reason & REASON_TM) { 1497 /* This is a TM "Bad Thing Exception" program check. 1498 * This occurs when: 1499 * - An rfid/hrfid/mtmsrd attempts to cause an illegal 1500 * transition in TM states. 1501 * - A trechkpt is attempted when transactional. 1502 * - A treclaim is attempted when non transactional. 1503 * - A tend is illegally attempted. 1504 * - writing a TM SPR when transactional. 1505 * 1506 * If usermode caused this, it's done something illegal and 1507 * gets a SIGILL slap on the wrist. We call it an illegal 1508 * operand to distinguish from the instruction just being bad 1509 * (e.g. executing a 'tend' on a CPU without TM!); it's an 1510 * illegal /placement/ of a valid instruction. 1511 */ 1512 if (user_mode(regs)) { 1513 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip); 1514 goto bail; 1515 } else { 1516 printk(KERN_EMERG "Unexpected TM Bad Thing exception " 1517 "at %lx (msr 0x%lx) tm_scratch=%llx\n", 1518 regs->nip, regs->msr, get_paca()->tm_scratch); 1519 die("Unrecoverable exception", regs, SIGABRT); 1520 } 1521 } 1522 #endif 1523 1524 /* 1525 * If we took the program check in the kernel skip down to sending a 1526 * SIGILL. The subsequent cases all relate to emulating instructions 1527 * which we should only do for userspace. We also do not want to enable 1528 * interrupts for kernel faults because that might lead to further 1529 * faults, and loose the context of the original exception. 1530 */ 1531 if (!user_mode(regs)) 1532 goto sigill; 1533 1534 /* We restore the interrupt state now */ 1535 if (!arch_irq_disabled_regs(regs)) 1536 local_irq_enable(); 1537 1538 /* (reason & REASON_ILLEGAL) would be the obvious thing here, 1539 * but there seems to be a hardware bug on the 405GP (RevD) 1540 * that means ESR is sometimes set incorrectly - either to 1541 * ESR_DST (!?) or 0. In the process of chasing this with the 1542 * hardware people - not sure if it can happen on any illegal 1543 * instruction or only on FP instructions, whether there is a 1544 * pattern to occurrences etc. -dgibson 31/Mar/2003 1545 */ 1546 if (!emulate_math(regs)) 1547 goto bail; 1548 1549 /* Try to emulate it if we should. */ 1550 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { 1551 switch (emulate_instruction(regs)) { 1552 case 0: 1553 regs->nip += 4; 1554 emulate_single_step(regs); 1555 goto bail; 1556 case -EFAULT: 1557 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1558 goto bail; 1559 } 1560 } 1561 1562 sigill: 1563 if (reason & REASON_PRIVILEGED) 1564 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 1565 else 1566 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1567 1568 bail: 1569 exception_exit(prev_state); 1570 } 1571 NOKPROBE_SYMBOL(program_check_exception); 1572 1573 /* 1574 * This occurs when running in hypervisor mode on POWER6 or later 1575 * and an illegal instruction is encountered. 1576 */ 1577 void emulation_assist_interrupt(struct pt_regs *regs) 1578 { 1579 regs->msr |= REASON_ILLEGAL; 1580 program_check_exception(regs); 1581 } 1582 NOKPROBE_SYMBOL(emulation_assist_interrupt); 1583 1584 void alignment_exception(struct pt_regs *regs) 1585 { 1586 enum ctx_state prev_state = exception_enter(); 1587 int sig, code, fixed = 0; 1588 1589 /* We restore the interrupt state now */ 1590 if (!arch_irq_disabled_regs(regs)) 1591 local_irq_enable(); 1592 1593 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT)) 1594 goto bail; 1595 1596 /* we don't implement logging of alignment exceptions */ 1597 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) 1598 fixed = fix_alignment(regs); 1599 1600 if (fixed == 1) { 1601 regs->nip += 4; /* skip over emulated instruction */ 1602 emulate_single_step(regs); 1603 goto bail; 1604 } 1605 1606 /* Operand address was bad */ 1607 if (fixed == -EFAULT) { 1608 sig = SIGSEGV; 1609 code = SEGV_ACCERR; 1610 } else { 1611 sig = SIGBUS; 1612 code = BUS_ADRALN; 1613 } 1614 if (user_mode(regs)) 1615 _exception(sig, regs, code, regs->dar); 1616 else 1617 bad_page_fault(regs, regs->dar, sig); 1618 1619 bail: 1620 exception_exit(prev_state); 1621 } 1622 1623 void StackOverflow(struct pt_regs *regs) 1624 { 1625 pr_crit("Kernel stack overflow in process %s[%d], r1=%lx\n", 1626 current->comm, task_pid_nr(current), regs->gpr[1]); 1627 debugger(regs); 1628 show_regs(regs); 1629 panic("kernel stack overflow"); 1630 } 1631 1632 void kernel_fp_unavailable_exception(struct pt_regs *regs) 1633 { 1634 enum ctx_state prev_state = exception_enter(); 1635 1636 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " 1637 "%lx at %lx\n", regs->trap, regs->nip); 1638 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); 1639 1640 exception_exit(prev_state); 1641 } 1642 1643 void altivec_unavailable_exception(struct pt_regs *regs) 1644 { 1645 enum ctx_state prev_state = exception_enter(); 1646 1647 if (user_mode(regs)) { 1648 /* A user program has executed an altivec instruction, 1649 but this kernel doesn't support altivec. */ 1650 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1651 goto bail; 1652 } 1653 1654 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " 1655 "%lx at %lx\n", regs->trap, regs->nip); 1656 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); 1657 1658 bail: 1659 exception_exit(prev_state); 1660 } 1661 1662 void vsx_unavailable_exception(struct pt_regs *regs) 1663 { 1664 if (user_mode(regs)) { 1665 /* A user program has executed an vsx instruction, 1666 but this kernel doesn't support vsx. */ 1667 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1668 return; 1669 } 1670 1671 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " 1672 "%lx at %lx\n", regs->trap, regs->nip); 1673 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); 1674 } 1675 1676 #ifdef CONFIG_PPC64 1677 static void tm_unavailable(struct pt_regs *regs) 1678 { 1679 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1680 if (user_mode(regs)) { 1681 current->thread.load_tm++; 1682 regs->msr |= MSR_TM; 1683 tm_enable(); 1684 tm_restore_sprs(¤t->thread); 1685 return; 1686 } 1687 #endif 1688 pr_emerg("Unrecoverable TM Unavailable Exception " 1689 "%lx at %lx\n", regs->trap, regs->nip); 1690 die("Unrecoverable TM Unavailable Exception", regs, SIGABRT); 1691 } 1692 1693 void facility_unavailable_exception(struct pt_regs *regs) 1694 { 1695 static char *facility_strings[] = { 1696 [FSCR_FP_LG] = "FPU", 1697 [FSCR_VECVSX_LG] = "VMX/VSX", 1698 [FSCR_DSCR_LG] = "DSCR", 1699 [FSCR_PM_LG] = "PMU SPRs", 1700 [FSCR_BHRB_LG] = "BHRB", 1701 [FSCR_TM_LG] = "TM", 1702 [FSCR_EBB_LG] = "EBB", 1703 [FSCR_TAR_LG] = "TAR", 1704 [FSCR_MSGP_LG] = "MSGP", 1705 [FSCR_SCV_LG] = "SCV", 1706 }; 1707 char *facility = "unknown"; 1708 u64 value; 1709 u32 instword, rd; 1710 u8 status; 1711 bool hv; 1712 1713 hv = (TRAP(regs) == 0xf80); 1714 if (hv) 1715 value = mfspr(SPRN_HFSCR); 1716 else 1717 value = mfspr(SPRN_FSCR); 1718 1719 status = value >> 56; 1720 if ((hv || status >= 2) && 1721 (status < ARRAY_SIZE(facility_strings)) && 1722 facility_strings[status]) 1723 facility = facility_strings[status]; 1724 1725 /* We should not have taken this interrupt in kernel */ 1726 if (!user_mode(regs)) { 1727 pr_emerg("Facility '%s' unavailable (%d) exception in kernel mode at %lx\n", 1728 facility, status, regs->nip); 1729 die("Unexpected facility unavailable exception", regs, SIGABRT); 1730 } 1731 1732 /* We restore the interrupt state now */ 1733 if (!arch_irq_disabled_regs(regs)) 1734 local_irq_enable(); 1735 1736 if (status == FSCR_DSCR_LG) { 1737 /* 1738 * User is accessing the DSCR register using the problem 1739 * state only SPR number (0x03) either through a mfspr or 1740 * a mtspr instruction. If it is a write attempt through 1741 * a mtspr, then we set the inherit bit. This also allows 1742 * the user to write or read the register directly in the 1743 * future by setting via the FSCR DSCR bit. But in case it 1744 * is a read DSCR attempt through a mfspr instruction, we 1745 * just emulate the instruction instead. This code path will 1746 * always emulate all the mfspr instructions till the user 1747 * has attempted at least one mtspr instruction. This way it 1748 * preserves the same behaviour when the user is accessing 1749 * the DSCR through privilege level only SPR number (0x11) 1750 * which is emulated through illegal instruction exception. 1751 * We always leave HFSCR DSCR set. 1752 */ 1753 if (get_user(instword, (u32 __user *)(regs->nip))) { 1754 pr_err("Failed to fetch the user instruction\n"); 1755 return; 1756 } 1757 1758 /* Write into DSCR (mtspr 0x03, RS) */ 1759 if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK) 1760 == PPC_INST_MTSPR_DSCR_USER) { 1761 rd = (instword >> 21) & 0x1f; 1762 current->thread.dscr = regs->gpr[rd]; 1763 current->thread.dscr_inherit = 1; 1764 current->thread.fscr |= FSCR_DSCR; 1765 mtspr(SPRN_FSCR, current->thread.fscr); 1766 } 1767 1768 /* Read from DSCR (mfspr RT, 0x03) */ 1769 if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK) 1770 == PPC_INST_MFSPR_DSCR_USER) { 1771 if (emulate_instruction(regs)) { 1772 pr_err("DSCR based mfspr emulation failed\n"); 1773 return; 1774 } 1775 regs->nip += 4; 1776 emulate_single_step(regs); 1777 } 1778 return; 1779 } 1780 1781 if (status == FSCR_TM_LG) { 1782 /* 1783 * If we're here then the hardware is TM aware because it 1784 * generated an exception with FSRM_TM set. 1785 * 1786 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware 1787 * told us not to do TM, or the kernel is not built with TM 1788 * support. 1789 * 1790 * If both of those things are true, then userspace can spam the 1791 * console by triggering the printk() below just by continually 1792 * doing tbegin (or any TM instruction). So in that case just 1793 * send the process a SIGILL immediately. 1794 */ 1795 if (!cpu_has_feature(CPU_FTR_TM)) 1796 goto out; 1797 1798 tm_unavailable(regs); 1799 return; 1800 } 1801 1802 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n", 1803 hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr); 1804 1805 out: 1806 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1807 } 1808 #endif 1809 1810 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1811 1812 void fp_unavailable_tm(struct pt_regs *regs) 1813 { 1814 /* Note: This does not handle any kind of FP laziness. */ 1815 1816 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n", 1817 regs->nip, regs->msr); 1818 1819 /* We can only have got here if the task started using FP after 1820 * beginning the transaction. So, the transactional regs are just a 1821 * copy of the checkpointed ones. But, we still need to recheckpoint 1822 * as we're enabling FP for the process; it will return, abort the 1823 * transaction, and probably retry but now with FP enabled. So the 1824 * checkpointed FP registers need to be loaded. 1825 */ 1826 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1827 1828 /* 1829 * Reclaim initially saved out bogus (lazy) FPRs to ckfp_state, and 1830 * then it was overwrite by the thr->fp_state by tm_reclaim_thread(). 1831 * 1832 * At this point, ck{fp,vr}_state contains the exact values we want to 1833 * recheckpoint. 1834 */ 1835 1836 /* Enable FP for the task: */ 1837 current->thread.load_fp = 1; 1838 1839 /* 1840 * Recheckpoint all the checkpointed ckpt, ck{fp, vr}_state registers. 1841 */ 1842 tm_recheckpoint(¤t->thread); 1843 } 1844 1845 void altivec_unavailable_tm(struct pt_regs *regs) 1846 { 1847 /* See the comments in fp_unavailable_tm(). This function operates 1848 * the same way. 1849 */ 1850 1851 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx," 1852 "MSR=%lx\n", 1853 regs->nip, regs->msr); 1854 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1855 current->thread.load_vec = 1; 1856 tm_recheckpoint(¤t->thread); 1857 current->thread.used_vr = 1; 1858 } 1859 1860 void vsx_unavailable_tm(struct pt_regs *regs) 1861 { 1862 /* See the comments in fp_unavailable_tm(). This works similarly, 1863 * though we're loading both FP and VEC registers in here. 1864 * 1865 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC 1866 * regs. Either way, set MSR_VSX. 1867 */ 1868 1869 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx," 1870 "MSR=%lx\n", 1871 regs->nip, regs->msr); 1872 1873 current->thread.used_vsr = 1; 1874 1875 /* This reclaims FP and/or VR regs if they're already enabled */ 1876 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1877 1878 current->thread.load_vec = 1; 1879 current->thread.load_fp = 1; 1880 1881 tm_recheckpoint(¤t->thread); 1882 } 1883 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1884 1885 void performance_monitor_exception(struct pt_regs *regs) 1886 { 1887 __this_cpu_inc(irq_stat.pmu_irqs); 1888 1889 perf_irq(regs); 1890 } 1891 1892 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1893 static void handle_debug(struct pt_regs *regs, unsigned long debug_status) 1894 { 1895 int changed = 0; 1896 /* 1897 * Determine the cause of the debug event, clear the 1898 * event flags and send a trap to the handler. Torez 1899 */ 1900 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { 1901 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); 1902 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1903 current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; 1904 #endif 1905 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, 1906 5); 1907 changed |= 0x01; 1908 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { 1909 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); 1910 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, 1911 6); 1912 changed |= 0x01; 1913 } else if (debug_status & DBSR_IAC1) { 1914 current->thread.debug.dbcr0 &= ~DBCR0_IAC1; 1915 dbcr_iac_range(current) &= ~DBCR_IAC12MODE; 1916 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, 1917 1); 1918 changed |= 0x01; 1919 } else if (debug_status & DBSR_IAC2) { 1920 current->thread.debug.dbcr0 &= ~DBCR0_IAC2; 1921 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, 1922 2); 1923 changed |= 0x01; 1924 } else if (debug_status & DBSR_IAC3) { 1925 current->thread.debug.dbcr0 &= ~DBCR0_IAC3; 1926 dbcr_iac_range(current) &= ~DBCR_IAC34MODE; 1927 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, 1928 3); 1929 changed |= 0x01; 1930 } else if (debug_status & DBSR_IAC4) { 1931 current->thread.debug.dbcr0 &= ~DBCR0_IAC4; 1932 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, 1933 4); 1934 changed |= 0x01; 1935 } 1936 /* 1937 * At the point this routine was called, the MSR(DE) was turned off. 1938 * Check all other debug flags and see if that bit needs to be turned 1939 * back on or not. 1940 */ 1941 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 1942 current->thread.debug.dbcr1)) 1943 regs->msr |= MSR_DE; 1944 else 1945 /* Make sure the IDM flag is off */ 1946 current->thread.debug.dbcr0 &= ~DBCR0_IDM; 1947 1948 if (changed & 0x01) 1949 mtspr(SPRN_DBCR0, current->thread.debug.dbcr0); 1950 } 1951 1952 void DebugException(struct pt_regs *regs, unsigned long debug_status) 1953 { 1954 current->thread.debug.dbsr = debug_status; 1955 1956 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while 1957 * on server, it stops on the target of the branch. In order to simulate 1958 * the server behaviour, we thus restart right away with a single step 1959 * instead of stopping here when hitting a BT 1960 */ 1961 if (debug_status & DBSR_BT) { 1962 regs->msr &= ~MSR_DE; 1963 1964 /* Disable BT */ 1965 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); 1966 /* Clear the BT event */ 1967 mtspr(SPRN_DBSR, DBSR_BT); 1968 1969 /* Do the single step trick only when coming from userspace */ 1970 if (user_mode(regs)) { 1971 current->thread.debug.dbcr0 &= ~DBCR0_BT; 1972 current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; 1973 regs->msr |= MSR_DE; 1974 return; 1975 } 1976 1977 if (kprobe_post_handler(regs)) 1978 return; 1979 1980 if (notify_die(DIE_SSTEP, "block_step", regs, 5, 1981 5, SIGTRAP) == NOTIFY_STOP) { 1982 return; 1983 } 1984 if (debugger_sstep(regs)) 1985 return; 1986 } else if (debug_status & DBSR_IC) { /* Instruction complete */ 1987 regs->msr &= ~MSR_DE; 1988 1989 /* Disable instruction completion */ 1990 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); 1991 /* Clear the instruction completion event */ 1992 mtspr(SPRN_DBSR, DBSR_IC); 1993 1994 if (kprobe_post_handler(regs)) 1995 return; 1996 1997 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 1998 5, SIGTRAP) == NOTIFY_STOP) { 1999 return; 2000 } 2001 2002 if (debugger_sstep(regs)) 2003 return; 2004 2005 if (user_mode(regs)) { 2006 current->thread.debug.dbcr0 &= ~DBCR0_IC; 2007 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 2008 current->thread.debug.dbcr1)) 2009 regs->msr |= MSR_DE; 2010 else 2011 /* Make sure the IDM bit is off */ 2012 current->thread.debug.dbcr0 &= ~DBCR0_IDM; 2013 } 2014 2015 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 2016 } else 2017 handle_debug(regs, debug_status); 2018 } 2019 NOKPROBE_SYMBOL(DebugException); 2020 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 2021 2022 #if !defined(CONFIG_TAU_INT) 2023 void TAUException(struct pt_regs *regs) 2024 { 2025 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", 2026 regs->nip, regs->msr, regs->trap, print_tainted()); 2027 } 2028 #endif /* CONFIG_INT_TAU */ 2029 2030 #ifdef CONFIG_ALTIVEC 2031 void altivec_assist_exception(struct pt_regs *regs) 2032 { 2033 int err; 2034 2035 if (!user_mode(regs)) { 2036 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" 2037 " at %lx\n", regs->nip); 2038 die("Kernel VMX/Altivec assist exception", regs, SIGILL); 2039 } 2040 2041 flush_altivec_to_thread(current); 2042 2043 PPC_WARN_EMULATED(altivec, regs); 2044 err = emulate_altivec(regs); 2045 if (err == 0) { 2046 regs->nip += 4; /* skip emulated instruction */ 2047 emulate_single_step(regs); 2048 return; 2049 } 2050 2051 if (err == -EFAULT) { 2052 /* got an error reading the instruction */ 2053 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2054 } else { 2055 /* didn't recognize the instruction */ 2056 /* XXX quick hack for now: set the non-Java bit in the VSCR */ 2057 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " 2058 "in %s at %lx\n", current->comm, regs->nip); 2059 current->thread.vr_state.vscr.u[3] |= 0x10000; 2060 } 2061 } 2062 #endif /* CONFIG_ALTIVEC */ 2063 2064 #ifdef CONFIG_FSL_BOOKE 2065 void CacheLockingException(struct pt_regs *regs, unsigned long address, 2066 unsigned long error_code) 2067 { 2068 /* We treat cache locking instructions from the user 2069 * as priv ops, in the future we could try to do 2070 * something smarter 2071 */ 2072 if (error_code & (ESR_DLK|ESR_ILK)) 2073 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 2074 return; 2075 } 2076 #endif /* CONFIG_FSL_BOOKE */ 2077 2078 #ifdef CONFIG_SPE 2079 void SPEFloatingPointException(struct pt_regs *regs) 2080 { 2081 extern int do_spe_mathemu(struct pt_regs *regs); 2082 unsigned long spefscr; 2083 int fpexc_mode; 2084 int code = FPE_FLTUNK; 2085 int err; 2086 2087 /* We restore the interrupt state now */ 2088 if (!arch_irq_disabled_regs(regs)) 2089 local_irq_enable(); 2090 2091 flush_spe_to_thread(current); 2092 2093 spefscr = current->thread.spefscr; 2094 fpexc_mode = current->thread.fpexc_mode; 2095 2096 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { 2097 code = FPE_FLTOVF; 2098 } 2099 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { 2100 code = FPE_FLTUND; 2101 } 2102 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) 2103 code = FPE_FLTDIV; 2104 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { 2105 code = FPE_FLTINV; 2106 } 2107 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) 2108 code = FPE_FLTRES; 2109 2110 err = do_spe_mathemu(regs); 2111 if (err == 0) { 2112 regs->nip += 4; /* skip emulated instruction */ 2113 emulate_single_step(regs); 2114 return; 2115 } 2116 2117 if (err == -EFAULT) { 2118 /* got an error reading the instruction */ 2119 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2120 } else if (err == -EINVAL) { 2121 /* didn't recognize the instruction */ 2122 printk(KERN_ERR "unrecognized spe instruction " 2123 "in %s at %lx\n", current->comm, regs->nip); 2124 } else { 2125 _exception(SIGFPE, regs, code, regs->nip); 2126 } 2127 2128 return; 2129 } 2130 2131 void SPEFloatingPointRoundException(struct pt_regs *regs) 2132 { 2133 extern int speround_handler(struct pt_regs *regs); 2134 int err; 2135 2136 /* We restore the interrupt state now */ 2137 if (!arch_irq_disabled_regs(regs)) 2138 local_irq_enable(); 2139 2140 preempt_disable(); 2141 if (regs->msr & MSR_SPE) 2142 giveup_spe(current); 2143 preempt_enable(); 2144 2145 regs->nip -= 4; 2146 err = speround_handler(regs); 2147 if (err == 0) { 2148 regs->nip += 4; /* skip emulated instruction */ 2149 emulate_single_step(regs); 2150 return; 2151 } 2152 2153 if (err == -EFAULT) { 2154 /* got an error reading the instruction */ 2155 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2156 } else if (err == -EINVAL) { 2157 /* didn't recognize the instruction */ 2158 printk(KERN_ERR "unrecognized spe instruction " 2159 "in %s at %lx\n", current->comm, regs->nip); 2160 } else { 2161 _exception(SIGFPE, regs, FPE_FLTUNK, regs->nip); 2162 return; 2163 } 2164 } 2165 #endif 2166 2167 /* 2168 * We enter here if we get an unrecoverable exception, that is, one 2169 * that happened at a point where the RI (recoverable interrupt) bit 2170 * in the MSR is 0. This indicates that SRR0/1 are live, and that 2171 * we therefore lost state by taking this exception. 2172 */ 2173 void unrecoverable_exception(struct pt_regs *regs) 2174 { 2175 pr_emerg("Unrecoverable exception %lx at %lx (msr=%lx)\n", 2176 regs->trap, regs->nip, regs->msr); 2177 die("Unrecoverable exception", regs, SIGABRT); 2178 } 2179 NOKPROBE_SYMBOL(unrecoverable_exception); 2180 2181 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x) 2182 /* 2183 * Default handler for a Watchdog exception, 2184 * spins until a reboot occurs 2185 */ 2186 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) 2187 { 2188 /* Generic WatchdogHandler, implement your own */ 2189 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); 2190 return; 2191 } 2192 2193 void WatchdogException(struct pt_regs *regs) 2194 { 2195 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); 2196 WatchdogHandler(regs); 2197 } 2198 #endif 2199 2200 /* 2201 * We enter here if we discover during exception entry that we are 2202 * running in supervisor mode with a userspace value in the stack pointer. 2203 */ 2204 void kernel_bad_stack(struct pt_regs *regs) 2205 { 2206 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", 2207 regs->gpr[1], regs->nip); 2208 die("Bad kernel stack pointer", regs, SIGABRT); 2209 } 2210 NOKPROBE_SYMBOL(kernel_bad_stack); 2211 2212 void __init trap_init(void) 2213 { 2214 } 2215 2216 2217 #ifdef CONFIG_PPC_EMULATED_STATS 2218 2219 #define WARN_EMULATED_SETUP(type) .type = { .name = #type } 2220 2221 struct ppc_emulated ppc_emulated = { 2222 #ifdef CONFIG_ALTIVEC 2223 WARN_EMULATED_SETUP(altivec), 2224 #endif 2225 WARN_EMULATED_SETUP(dcba), 2226 WARN_EMULATED_SETUP(dcbz), 2227 WARN_EMULATED_SETUP(fp_pair), 2228 WARN_EMULATED_SETUP(isel), 2229 WARN_EMULATED_SETUP(mcrxr), 2230 WARN_EMULATED_SETUP(mfpvr), 2231 WARN_EMULATED_SETUP(multiple), 2232 WARN_EMULATED_SETUP(popcntb), 2233 WARN_EMULATED_SETUP(spe), 2234 WARN_EMULATED_SETUP(string), 2235 WARN_EMULATED_SETUP(sync), 2236 WARN_EMULATED_SETUP(unaligned), 2237 #ifdef CONFIG_MATH_EMULATION 2238 WARN_EMULATED_SETUP(math), 2239 #endif 2240 #ifdef CONFIG_VSX 2241 WARN_EMULATED_SETUP(vsx), 2242 #endif 2243 #ifdef CONFIG_PPC64 2244 WARN_EMULATED_SETUP(mfdscr), 2245 WARN_EMULATED_SETUP(mtdscr), 2246 WARN_EMULATED_SETUP(lq_stq), 2247 WARN_EMULATED_SETUP(lxvw4x), 2248 WARN_EMULATED_SETUP(lxvh8x), 2249 WARN_EMULATED_SETUP(lxvd2x), 2250 WARN_EMULATED_SETUP(lxvb16x), 2251 #endif 2252 }; 2253 2254 u32 ppc_warn_emulated; 2255 2256 void ppc_warn_emulated_print(const char *type) 2257 { 2258 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, 2259 type); 2260 } 2261 2262 static int __init ppc_warn_emulated_init(void) 2263 { 2264 struct dentry *dir, *d; 2265 unsigned int i; 2266 struct ppc_emulated_entry *entries = (void *)&ppc_emulated; 2267 2268 if (!powerpc_debugfs_root) 2269 return -ENODEV; 2270 2271 dir = debugfs_create_dir("emulated_instructions", 2272 powerpc_debugfs_root); 2273 if (!dir) 2274 return -ENOMEM; 2275 2276 d = debugfs_create_u32("do_warn", 0644, dir, 2277 &ppc_warn_emulated); 2278 if (!d) 2279 goto fail; 2280 2281 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { 2282 d = debugfs_create_u32(entries[i].name, 0644, dir, 2283 (u32 *)&entries[i].val.counter); 2284 if (!d) 2285 goto fail; 2286 } 2287 2288 return 0; 2289 2290 fail: 2291 debugfs_remove_recursive(dir); 2292 return -ENOMEM; 2293 } 2294 2295 device_initcall(ppc_warn_emulated_init); 2296 2297 #endif /* CONFIG_PPC_EMULATED_STATS */ 2298