1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * Copyright 2007-2010 Freescale Semiconductor, Inc. 5 * 6 * Modified by Cort Dougan (cort@cs.nmt.edu) 7 * and Paul Mackerras (paulus@samba.org) 8 */ 9 10 /* 11 * This file handles the architecture-dependent parts of hardware exceptions 12 */ 13 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/sched/debug.h> 17 #include <linux/kernel.h> 18 #include <linux/mm.h> 19 #include <linux/pkeys.h> 20 #include <linux/stddef.h> 21 #include <linux/unistd.h> 22 #include <linux/ptrace.h> 23 #include <linux/user.h> 24 #include <linux/interrupt.h> 25 #include <linux/init.h> 26 #include <linux/extable.h> 27 #include <linux/module.h> /* print_modules */ 28 #include <linux/prctl.h> 29 #include <linux/delay.h> 30 #include <linux/kprobes.h> 31 #include <linux/kexec.h> 32 #include <linux/backlight.h> 33 #include <linux/bug.h> 34 #include <linux/kdebug.h> 35 #include <linux/ratelimit.h> 36 #include <linux/context_tracking.h> 37 #include <linux/smp.h> 38 #include <linux/console.h> 39 #include <linux/kmsg_dump.h> 40 41 #include <asm/emulated_ops.h> 42 #include <linux/uaccess.h> 43 #include <asm/debugfs.h> 44 #include <asm/io.h> 45 #include <asm/machdep.h> 46 #include <asm/rtas.h> 47 #include <asm/pmc.h> 48 #include <asm/reg.h> 49 #ifdef CONFIG_PMAC_BACKLIGHT 50 #include <asm/backlight.h> 51 #endif 52 #ifdef CONFIG_PPC64 53 #include <asm/firmware.h> 54 #include <asm/processor.h> 55 #include <asm/tm.h> 56 #endif 57 #include <asm/kexec.h> 58 #include <asm/ppc-opcode.h> 59 #include <asm/rio.h> 60 #include <asm/fadump.h> 61 #include <asm/switch_to.h> 62 #include <asm/tm.h> 63 #include <asm/debug.h> 64 #include <asm/asm-prototypes.h> 65 #include <asm/hmi.h> 66 #include <sysdev/fsl_pci.h> 67 #include <asm/kprobes.h> 68 #include <asm/stacktrace.h> 69 #include <asm/nmi.h> 70 71 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE) 72 int (*__debugger)(struct pt_regs *regs) __read_mostly; 73 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; 74 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; 75 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; 76 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; 77 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly; 78 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; 79 80 EXPORT_SYMBOL(__debugger); 81 EXPORT_SYMBOL(__debugger_ipi); 82 EXPORT_SYMBOL(__debugger_bpt); 83 EXPORT_SYMBOL(__debugger_sstep); 84 EXPORT_SYMBOL(__debugger_iabr_match); 85 EXPORT_SYMBOL(__debugger_break_match); 86 EXPORT_SYMBOL(__debugger_fault_handler); 87 #endif 88 89 /* Transactional Memory trap debug */ 90 #ifdef TM_DEBUG_SW 91 #define TM_DEBUG(x...) printk(KERN_INFO x) 92 #else 93 #define TM_DEBUG(x...) do { } while(0) 94 #endif 95 96 static const char *signame(int signr) 97 { 98 switch (signr) { 99 case SIGBUS: return "bus error"; 100 case SIGFPE: return "floating point exception"; 101 case SIGILL: return "illegal instruction"; 102 case SIGSEGV: return "segfault"; 103 case SIGTRAP: return "unhandled trap"; 104 } 105 106 return "unknown signal"; 107 } 108 109 /* 110 * Trap & Exception support 111 */ 112 113 #ifdef CONFIG_PMAC_BACKLIGHT 114 static void pmac_backlight_unblank(void) 115 { 116 mutex_lock(&pmac_backlight_mutex); 117 if (pmac_backlight) { 118 struct backlight_properties *props; 119 120 props = &pmac_backlight->props; 121 props->brightness = props->max_brightness; 122 props->power = FB_BLANK_UNBLANK; 123 backlight_update_status(pmac_backlight); 124 } 125 mutex_unlock(&pmac_backlight_mutex); 126 } 127 #else 128 static inline void pmac_backlight_unblank(void) { } 129 #endif 130 131 /* 132 * If oops/die is expected to crash the machine, return true here. 133 * 134 * This should not be expected to be 100% accurate, there may be 135 * notifiers registered or other unexpected conditions that may bring 136 * down the kernel. Or if the current process in the kernel is holding 137 * locks or has other critical state, the kernel may become effectively 138 * unusable anyway. 139 */ 140 bool die_will_crash(void) 141 { 142 if (should_fadump_crash()) 143 return true; 144 if (kexec_should_crash(current)) 145 return true; 146 if (in_interrupt() || panic_on_oops || 147 !current->pid || is_global_init(current)) 148 return true; 149 150 return false; 151 } 152 153 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; 154 static int die_owner = -1; 155 static unsigned int die_nest_count; 156 static int die_counter; 157 158 extern void panic_flush_kmsg_start(void) 159 { 160 /* 161 * These are mostly taken from kernel/panic.c, but tries to do 162 * relatively minimal work. Don't use delay functions (TB may 163 * be broken), don't crash dump (need to set a firmware log), 164 * don't run notifiers. We do want to get some information to 165 * Linux console. 166 */ 167 console_verbose(); 168 bust_spinlocks(1); 169 } 170 171 extern void panic_flush_kmsg_end(void) 172 { 173 printk_safe_flush_on_panic(); 174 kmsg_dump(KMSG_DUMP_PANIC); 175 bust_spinlocks(0); 176 debug_locks_off(); 177 console_flush_on_panic(CONSOLE_FLUSH_PENDING); 178 } 179 180 static unsigned long oops_begin(struct pt_regs *regs) 181 { 182 int cpu; 183 unsigned long flags; 184 185 oops_enter(); 186 187 /* racy, but better than risking deadlock. */ 188 raw_local_irq_save(flags); 189 cpu = smp_processor_id(); 190 if (!arch_spin_trylock(&die_lock)) { 191 if (cpu == die_owner) 192 /* nested oops. should stop eventually */; 193 else 194 arch_spin_lock(&die_lock); 195 } 196 die_nest_count++; 197 die_owner = cpu; 198 console_verbose(); 199 bust_spinlocks(1); 200 if (machine_is(powermac)) 201 pmac_backlight_unblank(); 202 return flags; 203 } 204 NOKPROBE_SYMBOL(oops_begin); 205 206 static void oops_end(unsigned long flags, struct pt_regs *regs, 207 int signr) 208 { 209 bust_spinlocks(0); 210 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 211 die_nest_count--; 212 oops_exit(); 213 printk("\n"); 214 if (!die_nest_count) { 215 /* Nest count reaches zero, release the lock. */ 216 die_owner = -1; 217 arch_spin_unlock(&die_lock); 218 } 219 raw_local_irq_restore(flags); 220 221 /* 222 * system_reset_excption handles debugger, crash dump, panic, for 0x100 223 */ 224 if (TRAP(regs) == 0x100) 225 return; 226 227 crash_fadump(regs, "die oops"); 228 229 if (kexec_should_crash(current)) 230 crash_kexec(regs); 231 232 if (!signr) 233 return; 234 235 /* 236 * While our oops output is serialised by a spinlock, output 237 * from panic() called below can race and corrupt it. If we 238 * know we are going to panic, delay for 1 second so we have a 239 * chance to get clean backtraces from all CPUs that are oopsing. 240 */ 241 if (in_interrupt() || panic_on_oops || !current->pid || 242 is_global_init(current)) { 243 mdelay(MSEC_PER_SEC); 244 } 245 246 if (panic_on_oops) 247 panic("Fatal exception"); 248 do_exit(signr); 249 } 250 NOKPROBE_SYMBOL(oops_end); 251 252 static char *get_mmu_str(void) 253 { 254 if (early_radix_enabled()) 255 return " MMU=Radix"; 256 if (early_mmu_has_feature(MMU_FTR_HPTE_TABLE)) 257 return " MMU=Hash"; 258 return ""; 259 } 260 261 static int __die(const char *str, struct pt_regs *regs, long err) 262 { 263 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); 264 265 printk("%s PAGE_SIZE=%luK%s%s%s%s%s%s %s\n", 266 IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN) ? "LE" : "BE", 267 PAGE_SIZE / 1024, get_mmu_str(), 268 IS_ENABLED(CONFIG_PREEMPT) ? " PREEMPT" : "", 269 IS_ENABLED(CONFIG_SMP) ? " SMP" : "", 270 IS_ENABLED(CONFIG_SMP) ? (" NR_CPUS=" __stringify(NR_CPUS)) : "", 271 debug_pagealloc_enabled() ? " DEBUG_PAGEALLOC" : "", 272 IS_ENABLED(CONFIG_NUMA) ? " NUMA" : "", 273 ppc_md.name ? ppc_md.name : ""); 274 275 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP) 276 return 1; 277 278 print_modules(); 279 show_regs(regs); 280 281 return 0; 282 } 283 NOKPROBE_SYMBOL(__die); 284 285 void die(const char *str, struct pt_regs *regs, long err) 286 { 287 unsigned long flags; 288 289 /* 290 * system_reset_excption handles debugger, crash dump, panic, for 0x100 291 */ 292 if (TRAP(regs) != 0x100) { 293 if (debugger(regs)) 294 return; 295 } 296 297 flags = oops_begin(regs); 298 if (__die(str, regs, err)) 299 err = 0; 300 oops_end(flags, regs, err); 301 } 302 NOKPROBE_SYMBOL(die); 303 304 void user_single_step_report(struct pt_regs *regs) 305 { 306 force_sig_fault(SIGTRAP, TRAP_TRACE, (void __user *)regs->nip); 307 } 308 309 static void show_signal_msg(int signr, struct pt_regs *regs, int code, 310 unsigned long addr) 311 { 312 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, 313 DEFAULT_RATELIMIT_BURST); 314 315 if (!show_unhandled_signals) 316 return; 317 318 if (!unhandled_signal(current, signr)) 319 return; 320 321 if (!__ratelimit(&rs)) 322 return; 323 324 pr_info("%s[%d]: %s (%d) at %lx nip %lx lr %lx code %x", 325 current->comm, current->pid, signame(signr), signr, 326 addr, regs->nip, regs->link, code); 327 328 print_vma_addr(KERN_CONT " in ", regs->nip); 329 330 pr_cont("\n"); 331 332 show_user_instructions(regs); 333 } 334 335 static bool exception_common(int signr, struct pt_regs *regs, int code, 336 unsigned long addr) 337 { 338 if (!user_mode(regs)) { 339 die("Exception in kernel mode", regs, signr); 340 return false; 341 } 342 343 show_signal_msg(signr, regs, code, addr); 344 345 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs)) 346 local_irq_enable(); 347 348 current->thread.trap_nr = code; 349 350 /* 351 * Save all the pkey registers AMR/IAMR/UAMOR. Eg: Core dumps need 352 * to capture the content, if the task gets killed. 353 */ 354 thread_pkey_regs_save(¤t->thread); 355 356 return true; 357 } 358 359 void _exception_pkey(struct pt_regs *regs, unsigned long addr, int key) 360 { 361 if (!exception_common(SIGSEGV, regs, SEGV_PKUERR, addr)) 362 return; 363 364 force_sig_pkuerr((void __user *) addr, key); 365 } 366 367 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) 368 { 369 if (!exception_common(signr, regs, code, addr)) 370 return; 371 372 force_sig_fault(signr, code, (void __user *)addr); 373 } 374 375 /* 376 * The interrupt architecture has a quirk in that the HV interrupts excluding 377 * the NMIs (0x100 and 0x200) do not clear MSR[RI] at entry. The first thing 378 * that an interrupt handler must do is save off a GPR into a scratch register, 379 * and all interrupts on POWERNV (HV=1) use the HSPRG1 register as scratch. 380 * Therefore an NMI can clobber an HV interrupt's live HSPRG1 without noticing 381 * that it is non-reentrant, which leads to random data corruption. 382 * 383 * The solution is for NMI interrupts in HV mode to check if they originated 384 * from these critical HV interrupt regions. If so, then mark them not 385 * recoverable. 386 * 387 * An alternative would be for HV NMIs to use SPRG for scratch to avoid the 388 * HSPRG1 clobber, however this would cause guest SPRG to be clobbered. Linux 389 * guests should always have MSR[RI]=0 when its scratch SPRG is in use, so 390 * that would work. However any other guest OS that may have the SPRG live 391 * and MSR[RI]=1 could encounter silent corruption. 392 * 393 * Builds that do not support KVM could take this second option to increase 394 * the recoverability of NMIs. 395 */ 396 void hv_nmi_check_nonrecoverable(struct pt_regs *regs) 397 { 398 #ifdef CONFIG_PPC_POWERNV 399 unsigned long kbase = (unsigned long)_stext; 400 unsigned long nip = regs->nip; 401 402 if (!(regs->msr & MSR_RI)) 403 return; 404 if (!(regs->msr & MSR_HV)) 405 return; 406 if (regs->msr & MSR_PR) 407 return; 408 409 /* 410 * Now test if the interrupt has hit a range that may be using 411 * HSPRG1 without having RI=0 (i.e., an HSRR interrupt). The 412 * problem ranges all run un-relocated. Test real and virt modes 413 * at the same time by droping the high bit of the nip (virt mode 414 * entry points still have the +0x4000 offset). 415 */ 416 nip &= ~0xc000000000000000ULL; 417 if ((nip >= 0x500 && nip < 0x600) || (nip >= 0x4500 && nip < 0x4600)) 418 goto nonrecoverable; 419 if ((nip >= 0x980 && nip < 0xa00) || (nip >= 0x4980 && nip < 0x4a00)) 420 goto nonrecoverable; 421 if ((nip >= 0xe00 && nip < 0xec0) || (nip >= 0x4e00 && nip < 0x4ec0)) 422 goto nonrecoverable; 423 if ((nip >= 0xf80 && nip < 0xfa0) || (nip >= 0x4f80 && nip < 0x4fa0)) 424 goto nonrecoverable; 425 426 /* Trampoline code runs un-relocated so subtract kbase. */ 427 if (nip >= (unsigned long)(start_real_trampolines - kbase) && 428 nip < (unsigned long)(end_real_trampolines - kbase)) 429 goto nonrecoverable; 430 if (nip >= (unsigned long)(start_virt_trampolines - kbase) && 431 nip < (unsigned long)(end_virt_trampolines - kbase)) 432 goto nonrecoverable; 433 return; 434 435 nonrecoverable: 436 regs->msr &= ~MSR_RI; 437 #endif 438 } 439 440 void system_reset_exception(struct pt_regs *regs) 441 { 442 unsigned long hsrr0, hsrr1; 443 bool saved_hsrrs = false; 444 u8 ftrace_enabled = this_cpu_get_ftrace_enabled(); 445 446 this_cpu_set_ftrace_enabled(0); 447 448 nmi_enter(); 449 450 /* 451 * System reset can interrupt code where HSRRs are live and MSR[RI]=1. 452 * The system reset interrupt itself may clobber HSRRs (e.g., to call 453 * OPAL), so save them here and restore them before returning. 454 * 455 * Machine checks don't need to save HSRRs, as the real mode handler 456 * is careful to avoid them, and the regular handler is not delivered 457 * as an NMI. 458 */ 459 if (cpu_has_feature(CPU_FTR_HVMODE)) { 460 hsrr0 = mfspr(SPRN_HSRR0); 461 hsrr1 = mfspr(SPRN_HSRR1); 462 saved_hsrrs = true; 463 } 464 465 hv_nmi_check_nonrecoverable(regs); 466 467 __this_cpu_inc(irq_stat.sreset_irqs); 468 469 /* See if any machine dependent calls */ 470 if (ppc_md.system_reset_exception) { 471 if (ppc_md.system_reset_exception(regs)) 472 goto out; 473 } 474 475 if (debugger(regs)) 476 goto out; 477 478 kmsg_dump(KMSG_DUMP_OOPS); 479 /* 480 * A system reset is a request to dump, so we always send 481 * it through the crashdump code (if fadump or kdump are 482 * registered). 483 */ 484 crash_fadump(regs, "System Reset"); 485 486 crash_kexec(regs); 487 488 /* 489 * We aren't the primary crash CPU. We need to send it 490 * to a holding pattern to avoid it ending up in the panic 491 * code. 492 */ 493 crash_kexec_secondary(regs); 494 495 /* 496 * No debugger or crash dump registered, print logs then 497 * panic. 498 */ 499 die("System Reset", regs, SIGABRT); 500 501 mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */ 502 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 503 nmi_panic(regs, "System Reset"); 504 505 out: 506 #ifdef CONFIG_PPC_BOOK3S_64 507 BUG_ON(get_paca()->in_nmi == 0); 508 if (get_paca()->in_nmi > 1) 509 die("Unrecoverable nested System Reset", regs, SIGABRT); 510 #endif 511 /* Must die if the interrupt is not recoverable */ 512 if (!(regs->msr & MSR_RI)) 513 die("Unrecoverable System Reset", regs, SIGABRT); 514 515 if (saved_hsrrs) { 516 mtspr(SPRN_HSRR0, hsrr0); 517 mtspr(SPRN_HSRR1, hsrr1); 518 } 519 520 nmi_exit(); 521 522 this_cpu_set_ftrace_enabled(ftrace_enabled); 523 524 /* What should we do here? We could issue a shutdown or hard reset. */ 525 } 526 527 /* 528 * I/O accesses can cause machine checks on powermacs. 529 * Check if the NIP corresponds to the address of a sync 530 * instruction for which there is an entry in the exception 531 * table. 532 * Note that the 601 only takes a machine check on TEA 533 * (transfer error ack) signal assertion, and does not 534 * set any of the top 16 bits of SRR1. 535 * -- paulus. 536 */ 537 static inline int check_io_access(struct pt_regs *regs) 538 { 539 #ifdef CONFIG_PPC32 540 unsigned long msr = regs->msr; 541 const struct exception_table_entry *entry; 542 unsigned int *nip = (unsigned int *)regs->nip; 543 544 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) 545 && (entry = search_exception_tables(regs->nip)) != NULL) { 546 /* 547 * Check that it's a sync instruction, or somewhere 548 * in the twi; isync; nop sequence that inb/inw/inl uses. 549 * As the address is in the exception table 550 * we should be able to read the instr there. 551 * For the debug message, we look at the preceding 552 * load or store. 553 */ 554 if (*nip == PPC_INST_NOP) 555 nip -= 2; 556 else if (*nip == PPC_INST_ISYNC) 557 --nip; 558 if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) { 559 unsigned int rb; 560 561 --nip; 562 rb = (*nip >> 11) & 0x1f; 563 printk(KERN_DEBUG "%s bad port %lx at %p\n", 564 (*nip & 0x100)? "OUT to": "IN from", 565 regs->gpr[rb] - _IO_BASE, nip); 566 regs->msr |= MSR_RI; 567 regs->nip = extable_fixup(entry); 568 return 1; 569 } 570 } 571 #endif /* CONFIG_PPC32 */ 572 return 0; 573 } 574 575 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 576 /* On 4xx, the reason for the machine check or program exception 577 is in the ESR. */ 578 #define get_reason(regs) ((regs)->dsisr) 579 #define REASON_FP ESR_FP 580 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) 581 #define REASON_PRIVILEGED ESR_PPR 582 #define REASON_TRAP ESR_PTR 583 #define REASON_PREFIXED 0 584 #define REASON_BOUNDARY 0 585 586 /* single-step stuff */ 587 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC) 588 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC) 589 #define clear_br_trace(regs) do {} while(0) 590 #else 591 /* On non-4xx, the reason for the machine check or program 592 exception is in the MSR. */ 593 #define get_reason(regs) ((regs)->msr) 594 #define REASON_TM SRR1_PROGTM 595 #define REASON_FP SRR1_PROGFPE 596 #define REASON_ILLEGAL SRR1_PROGILL 597 #define REASON_PRIVILEGED SRR1_PROGPRIV 598 #define REASON_TRAP SRR1_PROGTRAP 599 #define REASON_PREFIXED SRR1_PREFIXED 600 #define REASON_BOUNDARY SRR1_BOUNDARY 601 602 #define single_stepping(regs) ((regs)->msr & MSR_SE) 603 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) 604 #define clear_br_trace(regs) ((regs)->msr &= ~MSR_BE) 605 #endif 606 607 #define inst_length(reason) (((reason) & REASON_PREFIXED) ? 8 : 4) 608 609 #if defined(CONFIG_E500) 610 int machine_check_e500mc(struct pt_regs *regs) 611 { 612 unsigned long mcsr = mfspr(SPRN_MCSR); 613 unsigned long pvr = mfspr(SPRN_PVR); 614 unsigned long reason = mcsr; 615 int recoverable = 1; 616 617 if (reason & MCSR_LD) { 618 recoverable = fsl_rio_mcheck_exception(regs); 619 if (recoverable == 1) 620 goto silent_out; 621 } 622 623 printk("Machine check in kernel mode.\n"); 624 printk("Caused by (from MCSR=%lx): ", reason); 625 626 if (reason & MCSR_MCP) 627 pr_cont("Machine Check Signal\n"); 628 629 if (reason & MCSR_ICPERR) { 630 pr_cont("Instruction Cache Parity Error\n"); 631 632 /* 633 * This is recoverable by invalidating the i-cache. 634 */ 635 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); 636 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) 637 ; 638 639 /* 640 * This will generally be accompanied by an instruction 641 * fetch error report -- only treat MCSR_IF as fatal 642 * if it wasn't due to an L1 parity error. 643 */ 644 reason &= ~MCSR_IF; 645 } 646 647 if (reason & MCSR_DCPERR_MC) { 648 pr_cont("Data Cache Parity Error\n"); 649 650 /* 651 * In write shadow mode we auto-recover from the error, but it 652 * may still get logged and cause a machine check. We should 653 * only treat the non-write shadow case as non-recoverable. 654 */ 655 /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit 656 * is not implemented but L1 data cache always runs in write 657 * shadow mode. Hence on data cache parity errors HW will 658 * automatically invalidate the L1 Data Cache. 659 */ 660 if (PVR_VER(pvr) != PVR_VER_E6500) { 661 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) 662 recoverable = 0; 663 } 664 } 665 666 if (reason & MCSR_L2MMU_MHIT) { 667 pr_cont("Hit on multiple TLB entries\n"); 668 recoverable = 0; 669 } 670 671 if (reason & MCSR_NMI) 672 pr_cont("Non-maskable interrupt\n"); 673 674 if (reason & MCSR_IF) { 675 pr_cont("Instruction Fetch Error Report\n"); 676 recoverable = 0; 677 } 678 679 if (reason & MCSR_LD) { 680 pr_cont("Load Error Report\n"); 681 recoverable = 0; 682 } 683 684 if (reason & MCSR_ST) { 685 pr_cont("Store Error Report\n"); 686 recoverable = 0; 687 } 688 689 if (reason & MCSR_LDG) { 690 pr_cont("Guarded Load Error Report\n"); 691 recoverable = 0; 692 } 693 694 if (reason & MCSR_TLBSYNC) 695 pr_cont("Simultaneous tlbsync operations\n"); 696 697 if (reason & MCSR_BSL2_ERR) { 698 pr_cont("Level 2 Cache Error\n"); 699 recoverable = 0; 700 } 701 702 if (reason & MCSR_MAV) { 703 u64 addr; 704 705 addr = mfspr(SPRN_MCAR); 706 addr |= (u64)mfspr(SPRN_MCARU) << 32; 707 708 pr_cont("Machine Check %s Address: %#llx\n", 709 reason & MCSR_MEA ? "Effective" : "Physical", addr); 710 } 711 712 silent_out: 713 mtspr(SPRN_MCSR, mcsr); 714 return mfspr(SPRN_MCSR) == 0 && recoverable; 715 } 716 717 int machine_check_e500(struct pt_regs *regs) 718 { 719 unsigned long reason = mfspr(SPRN_MCSR); 720 721 if (reason & MCSR_BUS_RBERR) { 722 if (fsl_rio_mcheck_exception(regs)) 723 return 1; 724 if (fsl_pci_mcheck_exception(regs)) 725 return 1; 726 } 727 728 printk("Machine check in kernel mode.\n"); 729 printk("Caused by (from MCSR=%lx): ", reason); 730 731 if (reason & MCSR_MCP) 732 pr_cont("Machine Check Signal\n"); 733 if (reason & MCSR_ICPERR) 734 pr_cont("Instruction Cache Parity Error\n"); 735 if (reason & MCSR_DCP_PERR) 736 pr_cont("Data Cache Push Parity Error\n"); 737 if (reason & MCSR_DCPERR) 738 pr_cont("Data Cache Parity Error\n"); 739 if (reason & MCSR_BUS_IAERR) 740 pr_cont("Bus - Instruction Address Error\n"); 741 if (reason & MCSR_BUS_RAERR) 742 pr_cont("Bus - Read Address Error\n"); 743 if (reason & MCSR_BUS_WAERR) 744 pr_cont("Bus - Write Address Error\n"); 745 if (reason & MCSR_BUS_IBERR) 746 pr_cont("Bus - Instruction Data Error\n"); 747 if (reason & MCSR_BUS_RBERR) 748 pr_cont("Bus - Read Data Bus Error\n"); 749 if (reason & MCSR_BUS_WBERR) 750 pr_cont("Bus - Write Data Bus Error\n"); 751 if (reason & MCSR_BUS_IPERR) 752 pr_cont("Bus - Instruction Parity Error\n"); 753 if (reason & MCSR_BUS_RPERR) 754 pr_cont("Bus - Read Parity Error\n"); 755 756 return 0; 757 } 758 759 int machine_check_generic(struct pt_regs *regs) 760 { 761 return 0; 762 } 763 #elif defined(CONFIG_E200) 764 int machine_check_e200(struct pt_regs *regs) 765 { 766 unsigned long reason = mfspr(SPRN_MCSR); 767 768 printk("Machine check in kernel mode.\n"); 769 printk("Caused by (from MCSR=%lx): ", reason); 770 771 if (reason & MCSR_MCP) 772 pr_cont("Machine Check Signal\n"); 773 if (reason & MCSR_CP_PERR) 774 pr_cont("Cache Push Parity Error\n"); 775 if (reason & MCSR_CPERR) 776 pr_cont("Cache Parity Error\n"); 777 if (reason & MCSR_EXCP_ERR) 778 pr_cont("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); 779 if (reason & MCSR_BUS_IRERR) 780 pr_cont("Bus - Read Bus Error on instruction fetch\n"); 781 if (reason & MCSR_BUS_DRERR) 782 pr_cont("Bus - Read Bus Error on data load\n"); 783 if (reason & MCSR_BUS_WRERR) 784 pr_cont("Bus - Write Bus Error on buffered store or cache line push\n"); 785 786 return 0; 787 } 788 #elif defined(CONFIG_PPC32) 789 int machine_check_generic(struct pt_regs *regs) 790 { 791 unsigned long reason = regs->msr; 792 793 printk("Machine check in kernel mode.\n"); 794 printk("Caused by (from SRR1=%lx): ", reason); 795 switch (reason & 0x601F0000) { 796 case 0x80000: 797 pr_cont("Machine check signal\n"); 798 break; 799 case 0: /* for 601 */ 800 case 0x40000: 801 case 0x140000: /* 7450 MSS error and TEA */ 802 pr_cont("Transfer error ack signal\n"); 803 break; 804 case 0x20000: 805 pr_cont("Data parity error signal\n"); 806 break; 807 case 0x10000: 808 pr_cont("Address parity error signal\n"); 809 break; 810 case 0x20000000: 811 pr_cont("L1 Data Cache error\n"); 812 break; 813 case 0x40000000: 814 pr_cont("L1 Instruction Cache error\n"); 815 break; 816 case 0x00100000: 817 pr_cont("L2 data cache parity error\n"); 818 break; 819 default: 820 pr_cont("Unknown values in msr\n"); 821 } 822 return 0; 823 } 824 #endif /* everything else */ 825 826 void machine_check_exception(struct pt_regs *regs) 827 { 828 int recover = 0; 829 830 /* 831 * BOOK3S_64 does not call this handler as a non-maskable interrupt 832 * (it uses its own early real-mode handler to handle the MCE proper 833 * and then raises irq_work to call this handler when interrupts are 834 * enabled). 835 * 836 * This is silly. The BOOK3S_64 should just call a different function 837 * rather than expecting semantics to magically change. Something 838 * like 'non_nmi_machine_check_exception()', perhaps? 839 */ 840 const bool nmi = !IS_ENABLED(CONFIG_PPC_BOOK3S_64); 841 842 if (nmi) nmi_enter(); 843 844 __this_cpu_inc(irq_stat.mce_exceptions); 845 846 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 847 848 /* See if any machine dependent calls. In theory, we would want 849 * to call the CPU first, and call the ppc_md. one if the CPU 850 * one returns a positive number. However there is existing code 851 * that assumes the board gets a first chance, so let's keep it 852 * that way for now and fix things later. --BenH. 853 */ 854 if (ppc_md.machine_check_exception) 855 recover = ppc_md.machine_check_exception(regs); 856 else if (cur_cpu_spec->machine_check) 857 recover = cur_cpu_spec->machine_check(regs); 858 859 if (recover > 0) 860 goto bail; 861 862 if (debugger_fault_handler(regs)) 863 goto bail; 864 865 if (check_io_access(regs)) 866 goto bail; 867 868 if (nmi) nmi_exit(); 869 870 die("Machine check", regs, SIGBUS); 871 872 /* Must die if the interrupt is not recoverable */ 873 if (!(regs->msr & MSR_RI)) 874 die("Unrecoverable Machine check", regs, SIGBUS); 875 876 return; 877 878 bail: 879 if (nmi) nmi_exit(); 880 } 881 882 void SMIException(struct pt_regs *regs) 883 { 884 die("System Management Interrupt", regs, SIGABRT); 885 } 886 887 #ifdef CONFIG_VSX 888 static void p9_hmi_special_emu(struct pt_regs *regs) 889 { 890 unsigned int ra, rb, t, i, sel, instr, rc; 891 const void __user *addr; 892 u8 vbuf[16], *vdst; 893 unsigned long ea, msr, msr_mask; 894 bool swap; 895 896 if (__get_user_inatomic(instr, (unsigned int __user *)regs->nip)) 897 return; 898 899 /* 900 * lxvb16x opcode: 0x7c0006d8 901 * lxvd2x opcode: 0x7c000698 902 * lxvh8x opcode: 0x7c000658 903 * lxvw4x opcode: 0x7c000618 904 */ 905 if ((instr & 0xfc00073e) != 0x7c000618) { 906 pr_devel("HMI vec emu: not vector CI %i:%s[%d] nip=%016lx" 907 " instr=%08x\n", 908 smp_processor_id(), current->comm, current->pid, 909 regs->nip, instr); 910 return; 911 } 912 913 /* Grab vector registers into the task struct */ 914 msr = regs->msr; /* Grab msr before we flush the bits */ 915 flush_vsx_to_thread(current); 916 enable_kernel_altivec(); 917 918 /* 919 * Is userspace running with a different endian (this is rare but 920 * not impossible) 921 */ 922 swap = (msr & MSR_LE) != (MSR_KERNEL & MSR_LE); 923 924 /* Decode the instruction */ 925 ra = (instr >> 16) & 0x1f; 926 rb = (instr >> 11) & 0x1f; 927 t = (instr >> 21) & 0x1f; 928 if (instr & 1) 929 vdst = (u8 *)¤t->thread.vr_state.vr[t]; 930 else 931 vdst = (u8 *)¤t->thread.fp_state.fpr[t][0]; 932 933 /* Grab the vector address */ 934 ea = regs->gpr[rb] + (ra ? regs->gpr[ra] : 0); 935 if (is_32bit_task()) 936 ea &= 0xfffffffful; 937 addr = (__force const void __user *)ea; 938 939 /* Check it */ 940 if (!access_ok(addr, 16)) { 941 pr_devel("HMI vec emu: bad access %i:%s[%d] nip=%016lx" 942 " instr=%08x addr=%016lx\n", 943 smp_processor_id(), current->comm, current->pid, 944 regs->nip, instr, (unsigned long)addr); 945 return; 946 } 947 948 /* Read the vector */ 949 rc = 0; 950 if ((unsigned long)addr & 0xfUL) 951 /* unaligned case */ 952 rc = __copy_from_user_inatomic(vbuf, addr, 16); 953 else 954 __get_user_atomic_128_aligned(vbuf, addr, rc); 955 if (rc) { 956 pr_devel("HMI vec emu: page fault %i:%s[%d] nip=%016lx" 957 " instr=%08x addr=%016lx\n", 958 smp_processor_id(), current->comm, current->pid, 959 regs->nip, instr, (unsigned long)addr); 960 return; 961 } 962 963 pr_devel("HMI vec emu: emulated vector CI %i:%s[%d] nip=%016lx" 964 " instr=%08x addr=%016lx\n", 965 smp_processor_id(), current->comm, current->pid, regs->nip, 966 instr, (unsigned long) addr); 967 968 /* Grab instruction "selector" */ 969 sel = (instr >> 6) & 3; 970 971 /* 972 * Check to make sure the facility is actually enabled. This 973 * could happen if we get a false positive hit. 974 * 975 * lxvd2x/lxvw4x always check MSR VSX sel = 0,2 976 * lxvh8x/lxvb16x check MSR VSX or VEC depending on VSR used sel = 1,3 977 */ 978 msr_mask = MSR_VSX; 979 if ((sel & 1) && (instr & 1)) /* lxvh8x & lxvb16x + VSR >= 32 */ 980 msr_mask = MSR_VEC; 981 if (!(msr & msr_mask)) { 982 pr_devel("HMI vec emu: MSR fac clear %i:%s[%d] nip=%016lx" 983 " instr=%08x msr:%016lx\n", 984 smp_processor_id(), current->comm, current->pid, 985 regs->nip, instr, msr); 986 return; 987 } 988 989 /* Do logging here before we modify sel based on endian */ 990 switch (sel) { 991 case 0: /* lxvw4x */ 992 PPC_WARN_EMULATED(lxvw4x, regs); 993 break; 994 case 1: /* lxvh8x */ 995 PPC_WARN_EMULATED(lxvh8x, regs); 996 break; 997 case 2: /* lxvd2x */ 998 PPC_WARN_EMULATED(lxvd2x, regs); 999 break; 1000 case 3: /* lxvb16x */ 1001 PPC_WARN_EMULATED(lxvb16x, regs); 1002 break; 1003 } 1004 1005 #ifdef __LITTLE_ENDIAN__ 1006 /* 1007 * An LE kernel stores the vector in the task struct as an LE 1008 * byte array (effectively swapping both the components and 1009 * the content of the components). Those instructions expect 1010 * the components to remain in ascending address order, so we 1011 * swap them back. 1012 * 1013 * If we are running a BE user space, the expectation is that 1014 * of a simple memcpy, so forcing the emulation to look like 1015 * a lxvb16x should do the trick. 1016 */ 1017 if (swap) 1018 sel = 3; 1019 1020 switch (sel) { 1021 case 0: /* lxvw4x */ 1022 for (i = 0; i < 4; i++) 1023 ((u32 *)vdst)[i] = ((u32 *)vbuf)[3-i]; 1024 break; 1025 case 1: /* lxvh8x */ 1026 for (i = 0; i < 8; i++) 1027 ((u16 *)vdst)[i] = ((u16 *)vbuf)[7-i]; 1028 break; 1029 case 2: /* lxvd2x */ 1030 for (i = 0; i < 2; i++) 1031 ((u64 *)vdst)[i] = ((u64 *)vbuf)[1-i]; 1032 break; 1033 case 3: /* lxvb16x */ 1034 for (i = 0; i < 16; i++) 1035 vdst[i] = vbuf[15-i]; 1036 break; 1037 } 1038 #else /* __LITTLE_ENDIAN__ */ 1039 /* On a big endian kernel, a BE userspace only needs a memcpy */ 1040 if (!swap) 1041 sel = 3; 1042 1043 /* Otherwise, we need to swap the content of the components */ 1044 switch (sel) { 1045 case 0: /* lxvw4x */ 1046 for (i = 0; i < 4; i++) 1047 ((u32 *)vdst)[i] = cpu_to_le32(((u32 *)vbuf)[i]); 1048 break; 1049 case 1: /* lxvh8x */ 1050 for (i = 0; i < 8; i++) 1051 ((u16 *)vdst)[i] = cpu_to_le16(((u16 *)vbuf)[i]); 1052 break; 1053 case 2: /* lxvd2x */ 1054 for (i = 0; i < 2; i++) 1055 ((u64 *)vdst)[i] = cpu_to_le64(((u64 *)vbuf)[i]); 1056 break; 1057 case 3: /* lxvb16x */ 1058 memcpy(vdst, vbuf, 16); 1059 break; 1060 } 1061 #endif /* !__LITTLE_ENDIAN__ */ 1062 1063 /* Go to next instruction */ 1064 regs->nip += 4; 1065 } 1066 #endif /* CONFIG_VSX */ 1067 1068 void handle_hmi_exception(struct pt_regs *regs) 1069 { 1070 struct pt_regs *old_regs; 1071 1072 old_regs = set_irq_regs(regs); 1073 irq_enter(); 1074 1075 #ifdef CONFIG_VSX 1076 /* Real mode flagged P9 special emu is needed */ 1077 if (local_paca->hmi_p9_special_emu) { 1078 local_paca->hmi_p9_special_emu = 0; 1079 1080 /* 1081 * We don't want to take page faults while doing the 1082 * emulation, we just replay the instruction if necessary. 1083 */ 1084 pagefault_disable(); 1085 p9_hmi_special_emu(regs); 1086 pagefault_enable(); 1087 } 1088 #endif /* CONFIG_VSX */ 1089 1090 if (ppc_md.handle_hmi_exception) 1091 ppc_md.handle_hmi_exception(regs); 1092 1093 irq_exit(); 1094 set_irq_regs(old_regs); 1095 } 1096 1097 void unknown_exception(struct pt_regs *regs) 1098 { 1099 enum ctx_state prev_state = exception_enter(); 1100 1101 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 1102 regs->nip, regs->msr, regs->trap); 1103 1104 _exception(SIGTRAP, regs, TRAP_UNK, 0); 1105 1106 exception_exit(prev_state); 1107 } 1108 1109 void instruction_breakpoint_exception(struct pt_regs *regs) 1110 { 1111 enum ctx_state prev_state = exception_enter(); 1112 1113 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, 1114 5, SIGTRAP) == NOTIFY_STOP) 1115 goto bail; 1116 if (debugger_iabr_match(regs)) 1117 goto bail; 1118 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1119 1120 bail: 1121 exception_exit(prev_state); 1122 } 1123 1124 void RunModeException(struct pt_regs *regs) 1125 { 1126 _exception(SIGTRAP, regs, TRAP_UNK, 0); 1127 } 1128 1129 void single_step_exception(struct pt_regs *regs) 1130 { 1131 enum ctx_state prev_state = exception_enter(); 1132 1133 clear_single_step(regs); 1134 clear_br_trace(regs); 1135 1136 if (kprobe_post_handler(regs)) 1137 return; 1138 1139 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 1140 5, SIGTRAP) == NOTIFY_STOP) 1141 goto bail; 1142 if (debugger_sstep(regs)) 1143 goto bail; 1144 1145 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 1146 1147 bail: 1148 exception_exit(prev_state); 1149 } 1150 NOKPROBE_SYMBOL(single_step_exception); 1151 1152 /* 1153 * After we have successfully emulated an instruction, we have to 1154 * check if the instruction was being single-stepped, and if so, 1155 * pretend we got a single-step exception. This was pointed out 1156 * by Kumar Gala. -- paulus 1157 */ 1158 static void emulate_single_step(struct pt_regs *regs) 1159 { 1160 if (single_stepping(regs)) 1161 single_step_exception(regs); 1162 } 1163 1164 static inline int __parse_fpscr(unsigned long fpscr) 1165 { 1166 int ret = FPE_FLTUNK; 1167 1168 /* Invalid operation */ 1169 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) 1170 ret = FPE_FLTINV; 1171 1172 /* Overflow */ 1173 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) 1174 ret = FPE_FLTOVF; 1175 1176 /* Underflow */ 1177 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) 1178 ret = FPE_FLTUND; 1179 1180 /* Divide by zero */ 1181 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) 1182 ret = FPE_FLTDIV; 1183 1184 /* Inexact result */ 1185 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) 1186 ret = FPE_FLTRES; 1187 1188 return ret; 1189 } 1190 1191 static void parse_fpe(struct pt_regs *regs) 1192 { 1193 int code = 0; 1194 1195 flush_fp_to_thread(current); 1196 1197 code = __parse_fpscr(current->thread.fp_state.fpscr); 1198 1199 _exception(SIGFPE, regs, code, regs->nip); 1200 } 1201 1202 /* 1203 * Illegal instruction emulation support. Originally written to 1204 * provide the PVR to user applications using the mfspr rd, PVR. 1205 * Return non-zero if we can't emulate, or -EFAULT if the associated 1206 * memory access caused an access fault. Return zero on success. 1207 * 1208 * There are a couple of ways to do this, either "decode" the instruction 1209 * or directly match lots of bits. In this case, matching lots of 1210 * bits is faster and easier. 1211 * 1212 */ 1213 static int emulate_string_inst(struct pt_regs *regs, u32 instword) 1214 { 1215 u8 rT = (instword >> 21) & 0x1f; 1216 u8 rA = (instword >> 16) & 0x1f; 1217 u8 NB_RB = (instword >> 11) & 0x1f; 1218 u32 num_bytes; 1219 unsigned long EA; 1220 int pos = 0; 1221 1222 /* Early out if we are an invalid form of lswx */ 1223 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) 1224 if ((rT == rA) || (rT == NB_RB)) 1225 return -EINVAL; 1226 1227 EA = (rA == 0) ? 0 : regs->gpr[rA]; 1228 1229 switch (instword & PPC_INST_STRING_MASK) { 1230 case PPC_INST_LSWX: 1231 case PPC_INST_STSWX: 1232 EA += NB_RB; 1233 num_bytes = regs->xer & 0x7f; 1234 break; 1235 case PPC_INST_LSWI: 1236 case PPC_INST_STSWI: 1237 num_bytes = (NB_RB == 0) ? 32 : NB_RB; 1238 break; 1239 default: 1240 return -EINVAL; 1241 } 1242 1243 while (num_bytes != 0) 1244 { 1245 u8 val; 1246 u32 shift = 8 * (3 - (pos & 0x3)); 1247 1248 /* if process is 32-bit, clear upper 32 bits of EA */ 1249 if ((regs->msr & MSR_64BIT) == 0) 1250 EA &= 0xFFFFFFFF; 1251 1252 switch ((instword & PPC_INST_STRING_MASK)) { 1253 case PPC_INST_LSWX: 1254 case PPC_INST_LSWI: 1255 if (get_user(val, (u8 __user *)EA)) 1256 return -EFAULT; 1257 /* first time updating this reg, 1258 * zero it out */ 1259 if (pos == 0) 1260 regs->gpr[rT] = 0; 1261 regs->gpr[rT] |= val << shift; 1262 break; 1263 case PPC_INST_STSWI: 1264 case PPC_INST_STSWX: 1265 val = regs->gpr[rT] >> shift; 1266 if (put_user(val, (u8 __user *)EA)) 1267 return -EFAULT; 1268 break; 1269 } 1270 /* move EA to next address */ 1271 EA += 1; 1272 num_bytes--; 1273 1274 /* manage our position within the register */ 1275 if (++pos == 4) { 1276 pos = 0; 1277 if (++rT == 32) 1278 rT = 0; 1279 } 1280 } 1281 1282 return 0; 1283 } 1284 1285 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) 1286 { 1287 u32 ra,rs; 1288 unsigned long tmp; 1289 1290 ra = (instword >> 16) & 0x1f; 1291 rs = (instword >> 21) & 0x1f; 1292 1293 tmp = regs->gpr[rs]; 1294 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); 1295 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); 1296 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; 1297 regs->gpr[ra] = tmp; 1298 1299 return 0; 1300 } 1301 1302 static int emulate_isel(struct pt_regs *regs, u32 instword) 1303 { 1304 u8 rT = (instword >> 21) & 0x1f; 1305 u8 rA = (instword >> 16) & 0x1f; 1306 u8 rB = (instword >> 11) & 0x1f; 1307 u8 BC = (instword >> 6) & 0x1f; 1308 u8 bit; 1309 unsigned long tmp; 1310 1311 tmp = (rA == 0) ? 0 : regs->gpr[rA]; 1312 bit = (regs->ccr >> (31 - BC)) & 0x1; 1313 1314 regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; 1315 1316 return 0; 1317 } 1318 1319 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1320 static inline bool tm_abort_check(struct pt_regs *regs, int cause) 1321 { 1322 /* If we're emulating a load/store in an active transaction, we cannot 1323 * emulate it as the kernel operates in transaction suspended context. 1324 * We need to abort the transaction. This creates a persistent TM 1325 * abort so tell the user what caused it with a new code. 1326 */ 1327 if (MSR_TM_TRANSACTIONAL(regs->msr)) { 1328 tm_enable(); 1329 tm_abort(cause); 1330 return true; 1331 } 1332 return false; 1333 } 1334 #else 1335 static inline bool tm_abort_check(struct pt_regs *regs, int reason) 1336 { 1337 return false; 1338 } 1339 #endif 1340 1341 static int emulate_instruction(struct pt_regs *regs) 1342 { 1343 u32 instword; 1344 u32 rd; 1345 1346 if (!user_mode(regs)) 1347 return -EINVAL; 1348 CHECK_FULL_REGS(regs); 1349 1350 if (get_user(instword, (u32 __user *)(regs->nip))) 1351 return -EFAULT; 1352 1353 /* Emulate the mfspr rD, PVR. */ 1354 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { 1355 PPC_WARN_EMULATED(mfpvr, regs); 1356 rd = (instword >> 21) & 0x1f; 1357 regs->gpr[rd] = mfspr(SPRN_PVR); 1358 return 0; 1359 } 1360 1361 /* Emulating the dcba insn is just a no-op. */ 1362 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { 1363 PPC_WARN_EMULATED(dcba, regs); 1364 return 0; 1365 } 1366 1367 /* Emulate the mcrxr insn. */ 1368 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { 1369 int shift = (instword >> 21) & 0x1c; 1370 unsigned long msk = 0xf0000000UL >> shift; 1371 1372 PPC_WARN_EMULATED(mcrxr, regs); 1373 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); 1374 regs->xer &= ~0xf0000000UL; 1375 return 0; 1376 } 1377 1378 /* Emulate load/store string insn. */ 1379 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { 1380 if (tm_abort_check(regs, 1381 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) 1382 return -EINVAL; 1383 PPC_WARN_EMULATED(string, regs); 1384 return emulate_string_inst(regs, instword); 1385 } 1386 1387 /* Emulate the popcntb (Population Count Bytes) instruction. */ 1388 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { 1389 PPC_WARN_EMULATED(popcntb, regs); 1390 return emulate_popcntb_inst(regs, instword); 1391 } 1392 1393 /* Emulate isel (Integer Select) instruction */ 1394 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { 1395 PPC_WARN_EMULATED(isel, regs); 1396 return emulate_isel(regs, instword); 1397 } 1398 1399 /* Emulate sync instruction variants */ 1400 if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) { 1401 PPC_WARN_EMULATED(sync, regs); 1402 asm volatile("sync"); 1403 return 0; 1404 } 1405 1406 #ifdef CONFIG_PPC64 1407 /* Emulate the mfspr rD, DSCR. */ 1408 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) == 1409 PPC_INST_MFSPR_DSCR_USER) || 1410 ((instword & PPC_INST_MFSPR_DSCR_MASK) == 1411 PPC_INST_MFSPR_DSCR)) && 1412 cpu_has_feature(CPU_FTR_DSCR)) { 1413 PPC_WARN_EMULATED(mfdscr, regs); 1414 rd = (instword >> 21) & 0x1f; 1415 regs->gpr[rd] = mfspr(SPRN_DSCR); 1416 return 0; 1417 } 1418 /* Emulate the mtspr DSCR, rD. */ 1419 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) == 1420 PPC_INST_MTSPR_DSCR_USER) || 1421 ((instword & PPC_INST_MTSPR_DSCR_MASK) == 1422 PPC_INST_MTSPR_DSCR)) && 1423 cpu_has_feature(CPU_FTR_DSCR)) { 1424 PPC_WARN_EMULATED(mtdscr, regs); 1425 rd = (instword >> 21) & 0x1f; 1426 current->thread.dscr = regs->gpr[rd]; 1427 current->thread.dscr_inherit = 1; 1428 mtspr(SPRN_DSCR, current->thread.dscr); 1429 return 0; 1430 } 1431 #endif 1432 1433 return -EINVAL; 1434 } 1435 1436 int is_valid_bugaddr(unsigned long addr) 1437 { 1438 return is_kernel_addr(addr); 1439 } 1440 1441 #ifdef CONFIG_MATH_EMULATION 1442 static int emulate_math(struct pt_regs *regs) 1443 { 1444 int ret; 1445 extern int do_mathemu(struct pt_regs *regs); 1446 1447 ret = do_mathemu(regs); 1448 if (ret >= 0) 1449 PPC_WARN_EMULATED(math, regs); 1450 1451 switch (ret) { 1452 case 0: 1453 emulate_single_step(regs); 1454 return 0; 1455 case 1: { 1456 int code = 0; 1457 code = __parse_fpscr(current->thread.fp_state.fpscr); 1458 _exception(SIGFPE, regs, code, regs->nip); 1459 return 0; 1460 } 1461 case -EFAULT: 1462 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1463 return 0; 1464 } 1465 1466 return -1; 1467 } 1468 #else 1469 static inline int emulate_math(struct pt_regs *regs) { return -1; } 1470 #endif 1471 1472 void program_check_exception(struct pt_regs *regs) 1473 { 1474 enum ctx_state prev_state = exception_enter(); 1475 unsigned int reason = get_reason(regs); 1476 1477 /* We can now get here via a FP Unavailable exception if the core 1478 * has no FPU, in that case the reason flags will be 0 */ 1479 1480 if (reason & REASON_FP) { 1481 /* IEEE FP exception */ 1482 parse_fpe(regs); 1483 goto bail; 1484 } 1485 if (reason & REASON_TRAP) { 1486 unsigned long bugaddr; 1487 /* Debugger is first in line to stop recursive faults in 1488 * rcu_lock, notify_die, or atomic_notifier_call_chain */ 1489 if (debugger_bpt(regs)) 1490 goto bail; 1491 1492 if (kprobe_handler(regs)) 1493 goto bail; 1494 1495 /* trap exception */ 1496 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) 1497 == NOTIFY_STOP) 1498 goto bail; 1499 1500 bugaddr = regs->nip; 1501 /* 1502 * Fixup bugaddr for BUG_ON() in real mode 1503 */ 1504 if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR)) 1505 bugaddr += PAGE_OFFSET; 1506 1507 if (!(regs->msr & MSR_PR) && /* not user-mode */ 1508 report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) { 1509 regs->nip += 4; 1510 goto bail; 1511 } 1512 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1513 goto bail; 1514 } 1515 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1516 if (reason & REASON_TM) { 1517 /* This is a TM "Bad Thing Exception" program check. 1518 * This occurs when: 1519 * - An rfid/hrfid/mtmsrd attempts to cause an illegal 1520 * transition in TM states. 1521 * - A trechkpt is attempted when transactional. 1522 * - A treclaim is attempted when non transactional. 1523 * - A tend is illegally attempted. 1524 * - writing a TM SPR when transactional. 1525 * 1526 * If usermode caused this, it's done something illegal and 1527 * gets a SIGILL slap on the wrist. We call it an illegal 1528 * operand to distinguish from the instruction just being bad 1529 * (e.g. executing a 'tend' on a CPU without TM!); it's an 1530 * illegal /placement/ of a valid instruction. 1531 */ 1532 if (user_mode(regs)) { 1533 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip); 1534 goto bail; 1535 } else { 1536 printk(KERN_EMERG "Unexpected TM Bad Thing exception " 1537 "at %lx (msr 0x%lx) tm_scratch=%llx\n", 1538 regs->nip, regs->msr, get_paca()->tm_scratch); 1539 die("Unrecoverable exception", regs, SIGABRT); 1540 } 1541 } 1542 #endif 1543 1544 /* 1545 * If we took the program check in the kernel skip down to sending a 1546 * SIGILL. The subsequent cases all relate to emulating instructions 1547 * which we should only do for userspace. We also do not want to enable 1548 * interrupts for kernel faults because that might lead to further 1549 * faults, and loose the context of the original exception. 1550 */ 1551 if (!user_mode(regs)) 1552 goto sigill; 1553 1554 /* We restore the interrupt state now */ 1555 if (!arch_irq_disabled_regs(regs)) 1556 local_irq_enable(); 1557 1558 /* (reason & REASON_ILLEGAL) would be the obvious thing here, 1559 * but there seems to be a hardware bug on the 405GP (RevD) 1560 * that means ESR is sometimes set incorrectly - either to 1561 * ESR_DST (!?) or 0. In the process of chasing this with the 1562 * hardware people - not sure if it can happen on any illegal 1563 * instruction or only on FP instructions, whether there is a 1564 * pattern to occurrences etc. -dgibson 31/Mar/2003 1565 */ 1566 if (!emulate_math(regs)) 1567 goto bail; 1568 1569 /* Try to emulate it if we should. */ 1570 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { 1571 switch (emulate_instruction(regs)) { 1572 case 0: 1573 regs->nip += 4; 1574 emulate_single_step(regs); 1575 goto bail; 1576 case -EFAULT: 1577 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1578 goto bail; 1579 } 1580 } 1581 1582 sigill: 1583 if (reason & REASON_PRIVILEGED) 1584 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 1585 else 1586 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1587 1588 bail: 1589 exception_exit(prev_state); 1590 } 1591 NOKPROBE_SYMBOL(program_check_exception); 1592 1593 /* 1594 * This occurs when running in hypervisor mode on POWER6 or later 1595 * and an illegal instruction is encountered. 1596 */ 1597 void emulation_assist_interrupt(struct pt_regs *regs) 1598 { 1599 regs->msr |= REASON_ILLEGAL; 1600 program_check_exception(regs); 1601 } 1602 NOKPROBE_SYMBOL(emulation_assist_interrupt); 1603 1604 void alignment_exception(struct pt_regs *regs) 1605 { 1606 enum ctx_state prev_state = exception_enter(); 1607 int sig, code, fixed = 0; 1608 unsigned long reason; 1609 1610 /* We restore the interrupt state now */ 1611 if (!arch_irq_disabled_regs(regs)) 1612 local_irq_enable(); 1613 1614 reason = get_reason(regs); 1615 1616 if (reason & REASON_BOUNDARY) { 1617 sig = SIGBUS; 1618 code = BUS_ADRALN; 1619 goto bad; 1620 } 1621 1622 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT)) 1623 goto bail; 1624 1625 /* we don't implement logging of alignment exceptions */ 1626 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) 1627 fixed = fix_alignment(regs); 1628 1629 if (fixed == 1) { 1630 /* skip over emulated instruction */ 1631 regs->nip += inst_length(reason); 1632 emulate_single_step(regs); 1633 goto bail; 1634 } 1635 1636 /* Operand address was bad */ 1637 if (fixed == -EFAULT) { 1638 sig = SIGSEGV; 1639 code = SEGV_ACCERR; 1640 } else { 1641 sig = SIGBUS; 1642 code = BUS_ADRALN; 1643 } 1644 bad: 1645 if (user_mode(regs)) 1646 _exception(sig, regs, code, regs->dar); 1647 else 1648 bad_page_fault(regs, regs->dar, sig); 1649 1650 bail: 1651 exception_exit(prev_state); 1652 } 1653 1654 void StackOverflow(struct pt_regs *regs) 1655 { 1656 pr_crit("Kernel stack overflow in process %s[%d], r1=%lx\n", 1657 current->comm, task_pid_nr(current), regs->gpr[1]); 1658 debugger(regs); 1659 show_regs(regs); 1660 panic("kernel stack overflow"); 1661 } 1662 1663 void stack_overflow_exception(struct pt_regs *regs) 1664 { 1665 enum ctx_state prev_state = exception_enter(); 1666 1667 die("Kernel stack overflow", regs, SIGSEGV); 1668 1669 exception_exit(prev_state); 1670 } 1671 1672 void kernel_fp_unavailable_exception(struct pt_regs *regs) 1673 { 1674 enum ctx_state prev_state = exception_enter(); 1675 1676 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " 1677 "%lx at %lx\n", regs->trap, regs->nip); 1678 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); 1679 1680 exception_exit(prev_state); 1681 } 1682 1683 void altivec_unavailable_exception(struct pt_regs *regs) 1684 { 1685 enum ctx_state prev_state = exception_enter(); 1686 1687 if (user_mode(regs)) { 1688 /* A user program has executed an altivec instruction, 1689 but this kernel doesn't support altivec. */ 1690 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1691 goto bail; 1692 } 1693 1694 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " 1695 "%lx at %lx\n", regs->trap, regs->nip); 1696 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); 1697 1698 bail: 1699 exception_exit(prev_state); 1700 } 1701 1702 void vsx_unavailable_exception(struct pt_regs *regs) 1703 { 1704 if (user_mode(regs)) { 1705 /* A user program has executed an vsx instruction, 1706 but this kernel doesn't support vsx. */ 1707 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1708 return; 1709 } 1710 1711 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " 1712 "%lx at %lx\n", regs->trap, regs->nip); 1713 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); 1714 } 1715 1716 #ifdef CONFIG_PPC64 1717 static void tm_unavailable(struct pt_regs *regs) 1718 { 1719 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1720 if (user_mode(regs)) { 1721 current->thread.load_tm++; 1722 regs->msr |= MSR_TM; 1723 tm_enable(); 1724 tm_restore_sprs(¤t->thread); 1725 return; 1726 } 1727 #endif 1728 pr_emerg("Unrecoverable TM Unavailable Exception " 1729 "%lx at %lx\n", regs->trap, regs->nip); 1730 die("Unrecoverable TM Unavailable Exception", regs, SIGABRT); 1731 } 1732 1733 void facility_unavailable_exception(struct pt_regs *regs) 1734 { 1735 static char *facility_strings[] = { 1736 [FSCR_FP_LG] = "FPU", 1737 [FSCR_VECVSX_LG] = "VMX/VSX", 1738 [FSCR_DSCR_LG] = "DSCR", 1739 [FSCR_PM_LG] = "PMU SPRs", 1740 [FSCR_BHRB_LG] = "BHRB", 1741 [FSCR_TM_LG] = "TM", 1742 [FSCR_EBB_LG] = "EBB", 1743 [FSCR_TAR_LG] = "TAR", 1744 [FSCR_MSGP_LG] = "MSGP", 1745 [FSCR_SCV_LG] = "SCV", 1746 [FSCR_PREFIX_LG] = "PREFIX", 1747 }; 1748 char *facility = "unknown"; 1749 u64 value; 1750 u32 instword, rd; 1751 u8 status; 1752 bool hv; 1753 1754 hv = (TRAP(regs) == 0xf80); 1755 if (hv) 1756 value = mfspr(SPRN_HFSCR); 1757 else 1758 value = mfspr(SPRN_FSCR); 1759 1760 status = value >> 56; 1761 if ((hv || status >= 2) && 1762 (status < ARRAY_SIZE(facility_strings)) && 1763 facility_strings[status]) 1764 facility = facility_strings[status]; 1765 1766 /* We should not have taken this interrupt in kernel */ 1767 if (!user_mode(regs)) { 1768 pr_emerg("Facility '%s' unavailable (%d) exception in kernel mode at %lx\n", 1769 facility, status, regs->nip); 1770 die("Unexpected facility unavailable exception", regs, SIGABRT); 1771 } 1772 1773 /* We restore the interrupt state now */ 1774 if (!arch_irq_disabled_regs(regs)) 1775 local_irq_enable(); 1776 1777 if (status == FSCR_DSCR_LG) { 1778 /* 1779 * User is accessing the DSCR register using the problem 1780 * state only SPR number (0x03) either through a mfspr or 1781 * a mtspr instruction. If it is a write attempt through 1782 * a mtspr, then we set the inherit bit. This also allows 1783 * the user to write or read the register directly in the 1784 * future by setting via the FSCR DSCR bit. But in case it 1785 * is a read DSCR attempt through a mfspr instruction, we 1786 * just emulate the instruction instead. This code path will 1787 * always emulate all the mfspr instructions till the user 1788 * has attempted at least one mtspr instruction. This way it 1789 * preserves the same behaviour when the user is accessing 1790 * the DSCR through privilege level only SPR number (0x11) 1791 * which is emulated through illegal instruction exception. 1792 * We always leave HFSCR DSCR set. 1793 */ 1794 if (get_user(instword, (u32 __user *)(regs->nip))) { 1795 pr_err("Failed to fetch the user instruction\n"); 1796 return; 1797 } 1798 1799 /* Write into DSCR (mtspr 0x03, RS) */ 1800 if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK) 1801 == PPC_INST_MTSPR_DSCR_USER) { 1802 rd = (instword >> 21) & 0x1f; 1803 current->thread.dscr = regs->gpr[rd]; 1804 current->thread.dscr_inherit = 1; 1805 current->thread.fscr |= FSCR_DSCR; 1806 mtspr(SPRN_FSCR, current->thread.fscr); 1807 } 1808 1809 /* Read from DSCR (mfspr RT, 0x03) */ 1810 if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK) 1811 == PPC_INST_MFSPR_DSCR_USER) { 1812 if (emulate_instruction(regs)) { 1813 pr_err("DSCR based mfspr emulation failed\n"); 1814 return; 1815 } 1816 regs->nip += 4; 1817 emulate_single_step(regs); 1818 } 1819 return; 1820 } 1821 1822 if (status == FSCR_TM_LG) { 1823 /* 1824 * If we're here then the hardware is TM aware because it 1825 * generated an exception with FSRM_TM set. 1826 * 1827 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware 1828 * told us not to do TM, or the kernel is not built with TM 1829 * support. 1830 * 1831 * If both of those things are true, then userspace can spam the 1832 * console by triggering the printk() below just by continually 1833 * doing tbegin (or any TM instruction). So in that case just 1834 * send the process a SIGILL immediately. 1835 */ 1836 if (!cpu_has_feature(CPU_FTR_TM)) 1837 goto out; 1838 1839 tm_unavailable(regs); 1840 return; 1841 } 1842 1843 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n", 1844 hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr); 1845 1846 out: 1847 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1848 } 1849 #endif 1850 1851 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1852 1853 void fp_unavailable_tm(struct pt_regs *regs) 1854 { 1855 /* Note: This does not handle any kind of FP laziness. */ 1856 1857 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n", 1858 regs->nip, regs->msr); 1859 1860 /* We can only have got here if the task started using FP after 1861 * beginning the transaction. So, the transactional regs are just a 1862 * copy of the checkpointed ones. But, we still need to recheckpoint 1863 * as we're enabling FP for the process; it will return, abort the 1864 * transaction, and probably retry but now with FP enabled. So the 1865 * checkpointed FP registers need to be loaded. 1866 */ 1867 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1868 1869 /* 1870 * Reclaim initially saved out bogus (lazy) FPRs to ckfp_state, and 1871 * then it was overwrite by the thr->fp_state by tm_reclaim_thread(). 1872 * 1873 * At this point, ck{fp,vr}_state contains the exact values we want to 1874 * recheckpoint. 1875 */ 1876 1877 /* Enable FP for the task: */ 1878 current->thread.load_fp = 1; 1879 1880 /* 1881 * Recheckpoint all the checkpointed ckpt, ck{fp, vr}_state registers. 1882 */ 1883 tm_recheckpoint(¤t->thread); 1884 } 1885 1886 void altivec_unavailable_tm(struct pt_regs *regs) 1887 { 1888 /* See the comments in fp_unavailable_tm(). This function operates 1889 * the same way. 1890 */ 1891 1892 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx," 1893 "MSR=%lx\n", 1894 regs->nip, regs->msr); 1895 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1896 current->thread.load_vec = 1; 1897 tm_recheckpoint(¤t->thread); 1898 current->thread.used_vr = 1; 1899 } 1900 1901 void vsx_unavailable_tm(struct pt_regs *regs) 1902 { 1903 /* See the comments in fp_unavailable_tm(). This works similarly, 1904 * though we're loading both FP and VEC registers in here. 1905 * 1906 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC 1907 * regs. Either way, set MSR_VSX. 1908 */ 1909 1910 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx," 1911 "MSR=%lx\n", 1912 regs->nip, regs->msr); 1913 1914 current->thread.used_vsr = 1; 1915 1916 /* This reclaims FP and/or VR regs if they're already enabled */ 1917 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1918 1919 current->thread.load_vec = 1; 1920 current->thread.load_fp = 1; 1921 1922 tm_recheckpoint(¤t->thread); 1923 } 1924 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1925 1926 void performance_monitor_exception(struct pt_regs *regs) 1927 { 1928 __this_cpu_inc(irq_stat.pmu_irqs); 1929 1930 perf_irq(regs); 1931 } 1932 1933 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1934 static void handle_debug(struct pt_regs *regs, unsigned long debug_status) 1935 { 1936 int changed = 0; 1937 /* 1938 * Determine the cause of the debug event, clear the 1939 * event flags and send a trap to the handler. Torez 1940 */ 1941 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { 1942 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); 1943 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1944 current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; 1945 #endif 1946 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, 1947 5); 1948 changed |= 0x01; 1949 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { 1950 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); 1951 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, 1952 6); 1953 changed |= 0x01; 1954 } else if (debug_status & DBSR_IAC1) { 1955 current->thread.debug.dbcr0 &= ~DBCR0_IAC1; 1956 dbcr_iac_range(current) &= ~DBCR_IAC12MODE; 1957 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, 1958 1); 1959 changed |= 0x01; 1960 } else if (debug_status & DBSR_IAC2) { 1961 current->thread.debug.dbcr0 &= ~DBCR0_IAC2; 1962 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, 1963 2); 1964 changed |= 0x01; 1965 } else if (debug_status & DBSR_IAC3) { 1966 current->thread.debug.dbcr0 &= ~DBCR0_IAC3; 1967 dbcr_iac_range(current) &= ~DBCR_IAC34MODE; 1968 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, 1969 3); 1970 changed |= 0x01; 1971 } else if (debug_status & DBSR_IAC4) { 1972 current->thread.debug.dbcr0 &= ~DBCR0_IAC4; 1973 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, 1974 4); 1975 changed |= 0x01; 1976 } 1977 /* 1978 * At the point this routine was called, the MSR(DE) was turned off. 1979 * Check all other debug flags and see if that bit needs to be turned 1980 * back on or not. 1981 */ 1982 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 1983 current->thread.debug.dbcr1)) 1984 regs->msr |= MSR_DE; 1985 else 1986 /* Make sure the IDM flag is off */ 1987 current->thread.debug.dbcr0 &= ~DBCR0_IDM; 1988 1989 if (changed & 0x01) 1990 mtspr(SPRN_DBCR0, current->thread.debug.dbcr0); 1991 } 1992 1993 void DebugException(struct pt_regs *regs, unsigned long debug_status) 1994 { 1995 current->thread.debug.dbsr = debug_status; 1996 1997 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while 1998 * on server, it stops on the target of the branch. In order to simulate 1999 * the server behaviour, we thus restart right away with a single step 2000 * instead of stopping here when hitting a BT 2001 */ 2002 if (debug_status & DBSR_BT) { 2003 regs->msr &= ~MSR_DE; 2004 2005 /* Disable BT */ 2006 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); 2007 /* Clear the BT event */ 2008 mtspr(SPRN_DBSR, DBSR_BT); 2009 2010 /* Do the single step trick only when coming from userspace */ 2011 if (user_mode(regs)) { 2012 current->thread.debug.dbcr0 &= ~DBCR0_BT; 2013 current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; 2014 regs->msr |= MSR_DE; 2015 return; 2016 } 2017 2018 if (kprobe_post_handler(regs)) 2019 return; 2020 2021 if (notify_die(DIE_SSTEP, "block_step", regs, 5, 2022 5, SIGTRAP) == NOTIFY_STOP) { 2023 return; 2024 } 2025 if (debugger_sstep(regs)) 2026 return; 2027 } else if (debug_status & DBSR_IC) { /* Instruction complete */ 2028 regs->msr &= ~MSR_DE; 2029 2030 /* Disable instruction completion */ 2031 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); 2032 /* Clear the instruction completion event */ 2033 mtspr(SPRN_DBSR, DBSR_IC); 2034 2035 if (kprobe_post_handler(regs)) 2036 return; 2037 2038 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 2039 5, SIGTRAP) == NOTIFY_STOP) { 2040 return; 2041 } 2042 2043 if (debugger_sstep(regs)) 2044 return; 2045 2046 if (user_mode(regs)) { 2047 current->thread.debug.dbcr0 &= ~DBCR0_IC; 2048 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 2049 current->thread.debug.dbcr1)) 2050 regs->msr |= MSR_DE; 2051 else 2052 /* Make sure the IDM bit is off */ 2053 current->thread.debug.dbcr0 &= ~DBCR0_IDM; 2054 } 2055 2056 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 2057 } else 2058 handle_debug(regs, debug_status); 2059 } 2060 NOKPROBE_SYMBOL(DebugException); 2061 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 2062 2063 #if !defined(CONFIG_TAU_INT) 2064 void TAUException(struct pt_regs *regs) 2065 { 2066 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", 2067 regs->nip, regs->msr, regs->trap, print_tainted()); 2068 } 2069 #endif /* CONFIG_INT_TAU */ 2070 2071 #ifdef CONFIG_ALTIVEC 2072 void altivec_assist_exception(struct pt_regs *regs) 2073 { 2074 int err; 2075 2076 if (!user_mode(regs)) { 2077 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" 2078 " at %lx\n", regs->nip); 2079 die("Kernel VMX/Altivec assist exception", regs, SIGILL); 2080 } 2081 2082 flush_altivec_to_thread(current); 2083 2084 PPC_WARN_EMULATED(altivec, regs); 2085 err = emulate_altivec(regs); 2086 if (err == 0) { 2087 regs->nip += 4; /* skip emulated instruction */ 2088 emulate_single_step(regs); 2089 return; 2090 } 2091 2092 if (err == -EFAULT) { 2093 /* got an error reading the instruction */ 2094 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2095 } else { 2096 /* didn't recognize the instruction */ 2097 /* XXX quick hack for now: set the non-Java bit in the VSCR */ 2098 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " 2099 "in %s at %lx\n", current->comm, regs->nip); 2100 current->thread.vr_state.vscr.u[3] |= 0x10000; 2101 } 2102 } 2103 #endif /* CONFIG_ALTIVEC */ 2104 2105 #ifdef CONFIG_FSL_BOOKE 2106 void CacheLockingException(struct pt_regs *regs, unsigned long address, 2107 unsigned long error_code) 2108 { 2109 /* We treat cache locking instructions from the user 2110 * as priv ops, in the future we could try to do 2111 * something smarter 2112 */ 2113 if (error_code & (ESR_DLK|ESR_ILK)) 2114 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 2115 return; 2116 } 2117 #endif /* CONFIG_FSL_BOOKE */ 2118 2119 #ifdef CONFIG_SPE 2120 void SPEFloatingPointException(struct pt_regs *regs) 2121 { 2122 extern int do_spe_mathemu(struct pt_regs *regs); 2123 unsigned long spefscr; 2124 int fpexc_mode; 2125 int code = FPE_FLTUNK; 2126 int err; 2127 2128 /* We restore the interrupt state now */ 2129 if (!arch_irq_disabled_regs(regs)) 2130 local_irq_enable(); 2131 2132 flush_spe_to_thread(current); 2133 2134 spefscr = current->thread.spefscr; 2135 fpexc_mode = current->thread.fpexc_mode; 2136 2137 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { 2138 code = FPE_FLTOVF; 2139 } 2140 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { 2141 code = FPE_FLTUND; 2142 } 2143 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) 2144 code = FPE_FLTDIV; 2145 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { 2146 code = FPE_FLTINV; 2147 } 2148 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) 2149 code = FPE_FLTRES; 2150 2151 err = do_spe_mathemu(regs); 2152 if (err == 0) { 2153 regs->nip += 4; /* skip emulated instruction */ 2154 emulate_single_step(regs); 2155 return; 2156 } 2157 2158 if (err == -EFAULT) { 2159 /* got an error reading the instruction */ 2160 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2161 } else if (err == -EINVAL) { 2162 /* didn't recognize the instruction */ 2163 printk(KERN_ERR "unrecognized spe instruction " 2164 "in %s at %lx\n", current->comm, regs->nip); 2165 } else { 2166 _exception(SIGFPE, regs, code, regs->nip); 2167 } 2168 2169 return; 2170 } 2171 2172 void SPEFloatingPointRoundException(struct pt_regs *regs) 2173 { 2174 extern int speround_handler(struct pt_regs *regs); 2175 int err; 2176 2177 /* We restore the interrupt state now */ 2178 if (!arch_irq_disabled_regs(regs)) 2179 local_irq_enable(); 2180 2181 preempt_disable(); 2182 if (regs->msr & MSR_SPE) 2183 giveup_spe(current); 2184 preempt_enable(); 2185 2186 regs->nip -= 4; 2187 err = speround_handler(regs); 2188 if (err == 0) { 2189 regs->nip += 4; /* skip emulated instruction */ 2190 emulate_single_step(regs); 2191 return; 2192 } 2193 2194 if (err == -EFAULT) { 2195 /* got an error reading the instruction */ 2196 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2197 } else if (err == -EINVAL) { 2198 /* didn't recognize the instruction */ 2199 printk(KERN_ERR "unrecognized spe instruction " 2200 "in %s at %lx\n", current->comm, regs->nip); 2201 } else { 2202 _exception(SIGFPE, regs, FPE_FLTUNK, regs->nip); 2203 return; 2204 } 2205 } 2206 #endif 2207 2208 /* 2209 * We enter here if we get an unrecoverable exception, that is, one 2210 * that happened at a point where the RI (recoverable interrupt) bit 2211 * in the MSR is 0. This indicates that SRR0/1 are live, and that 2212 * we therefore lost state by taking this exception. 2213 */ 2214 void unrecoverable_exception(struct pt_regs *regs) 2215 { 2216 pr_emerg("Unrecoverable exception %lx at %lx (msr=%lx)\n", 2217 regs->trap, regs->nip, regs->msr); 2218 die("Unrecoverable exception", regs, SIGABRT); 2219 } 2220 NOKPROBE_SYMBOL(unrecoverable_exception); 2221 2222 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x) 2223 /* 2224 * Default handler for a Watchdog exception, 2225 * spins until a reboot occurs 2226 */ 2227 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) 2228 { 2229 /* Generic WatchdogHandler, implement your own */ 2230 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); 2231 return; 2232 } 2233 2234 void WatchdogException(struct pt_regs *regs) 2235 { 2236 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); 2237 WatchdogHandler(regs); 2238 } 2239 #endif 2240 2241 /* 2242 * We enter here if we discover during exception entry that we are 2243 * running in supervisor mode with a userspace value in the stack pointer. 2244 */ 2245 void kernel_bad_stack(struct pt_regs *regs) 2246 { 2247 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", 2248 regs->gpr[1], regs->nip); 2249 die("Bad kernel stack pointer", regs, SIGABRT); 2250 } 2251 NOKPROBE_SYMBOL(kernel_bad_stack); 2252 2253 void __init trap_init(void) 2254 { 2255 } 2256 2257 2258 #ifdef CONFIG_PPC_EMULATED_STATS 2259 2260 #define WARN_EMULATED_SETUP(type) .type = { .name = #type } 2261 2262 struct ppc_emulated ppc_emulated = { 2263 #ifdef CONFIG_ALTIVEC 2264 WARN_EMULATED_SETUP(altivec), 2265 #endif 2266 WARN_EMULATED_SETUP(dcba), 2267 WARN_EMULATED_SETUP(dcbz), 2268 WARN_EMULATED_SETUP(fp_pair), 2269 WARN_EMULATED_SETUP(isel), 2270 WARN_EMULATED_SETUP(mcrxr), 2271 WARN_EMULATED_SETUP(mfpvr), 2272 WARN_EMULATED_SETUP(multiple), 2273 WARN_EMULATED_SETUP(popcntb), 2274 WARN_EMULATED_SETUP(spe), 2275 WARN_EMULATED_SETUP(string), 2276 WARN_EMULATED_SETUP(sync), 2277 WARN_EMULATED_SETUP(unaligned), 2278 #ifdef CONFIG_MATH_EMULATION 2279 WARN_EMULATED_SETUP(math), 2280 #endif 2281 #ifdef CONFIG_VSX 2282 WARN_EMULATED_SETUP(vsx), 2283 #endif 2284 #ifdef CONFIG_PPC64 2285 WARN_EMULATED_SETUP(mfdscr), 2286 WARN_EMULATED_SETUP(mtdscr), 2287 WARN_EMULATED_SETUP(lq_stq), 2288 WARN_EMULATED_SETUP(lxvw4x), 2289 WARN_EMULATED_SETUP(lxvh8x), 2290 WARN_EMULATED_SETUP(lxvd2x), 2291 WARN_EMULATED_SETUP(lxvb16x), 2292 #endif 2293 }; 2294 2295 u32 ppc_warn_emulated; 2296 2297 void ppc_warn_emulated_print(const char *type) 2298 { 2299 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, 2300 type); 2301 } 2302 2303 static int __init ppc_warn_emulated_init(void) 2304 { 2305 struct dentry *dir; 2306 unsigned int i; 2307 struct ppc_emulated_entry *entries = (void *)&ppc_emulated; 2308 2309 dir = debugfs_create_dir("emulated_instructions", 2310 powerpc_debugfs_root); 2311 2312 debugfs_create_u32("do_warn", 0644, dir, &ppc_warn_emulated); 2313 2314 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) 2315 debugfs_create_u32(entries[i].name, 0644, dir, 2316 (u32 *)&entries[i].val.counter); 2317 2318 return 0; 2319 } 2320 2321 device_initcall(ppc_warn_emulated_init); 2322 2323 #endif /* CONFIG_PPC_EMULATED_STATS */ 2324