1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * Copyright 2007-2010 Freescale Semiconductor, Inc. 5 * 6 * Modified by Cort Dougan (cort@cs.nmt.edu) 7 * and Paul Mackerras (paulus@samba.org) 8 */ 9 10 /* 11 * This file handles the architecture-dependent parts of hardware exceptions 12 */ 13 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/sched/debug.h> 17 #include <linux/kernel.h> 18 #include <linux/mm.h> 19 #include <linux/pkeys.h> 20 #include <linux/stddef.h> 21 #include <linux/unistd.h> 22 #include <linux/ptrace.h> 23 #include <linux/user.h> 24 #include <linux/interrupt.h> 25 #include <linux/init.h> 26 #include <linux/extable.h> 27 #include <linux/module.h> /* print_modules */ 28 #include <linux/prctl.h> 29 #include <linux/delay.h> 30 #include <linux/kprobes.h> 31 #include <linux/kexec.h> 32 #include <linux/backlight.h> 33 #include <linux/bug.h> 34 #include <linux/kdebug.h> 35 #include <linux/ratelimit.h> 36 #include <linux/context_tracking.h> 37 #include <linux/smp.h> 38 #include <linux/console.h> 39 #include <linux/kmsg_dump.h> 40 41 #include <asm/emulated_ops.h> 42 #include <asm/pgtable.h> 43 #include <linux/uaccess.h> 44 #include <asm/debugfs.h> 45 #include <asm/io.h> 46 #include <asm/machdep.h> 47 #include <asm/rtas.h> 48 #include <asm/pmc.h> 49 #include <asm/reg.h> 50 #ifdef CONFIG_PMAC_BACKLIGHT 51 #include <asm/backlight.h> 52 #endif 53 #ifdef CONFIG_PPC64 54 #include <asm/firmware.h> 55 #include <asm/processor.h> 56 #include <asm/tm.h> 57 #endif 58 #include <asm/kexec.h> 59 #include <asm/ppc-opcode.h> 60 #include <asm/rio.h> 61 #include <asm/fadump.h> 62 #include <asm/switch_to.h> 63 #include <asm/tm.h> 64 #include <asm/debug.h> 65 #include <asm/asm-prototypes.h> 66 #include <asm/hmi.h> 67 #include <sysdev/fsl_pci.h> 68 #include <asm/kprobes.h> 69 #include <asm/stacktrace.h> 70 #include <asm/nmi.h> 71 72 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE) 73 int (*__debugger)(struct pt_regs *regs) __read_mostly; 74 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; 75 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; 76 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; 77 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; 78 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly; 79 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; 80 81 EXPORT_SYMBOL(__debugger); 82 EXPORT_SYMBOL(__debugger_ipi); 83 EXPORT_SYMBOL(__debugger_bpt); 84 EXPORT_SYMBOL(__debugger_sstep); 85 EXPORT_SYMBOL(__debugger_iabr_match); 86 EXPORT_SYMBOL(__debugger_break_match); 87 EXPORT_SYMBOL(__debugger_fault_handler); 88 #endif 89 90 /* Transactional Memory trap debug */ 91 #ifdef TM_DEBUG_SW 92 #define TM_DEBUG(x...) printk(KERN_INFO x) 93 #else 94 #define TM_DEBUG(x...) do { } while(0) 95 #endif 96 97 static const char *signame(int signr) 98 { 99 switch (signr) { 100 case SIGBUS: return "bus error"; 101 case SIGFPE: return "floating point exception"; 102 case SIGILL: return "illegal instruction"; 103 case SIGSEGV: return "segfault"; 104 case SIGTRAP: return "unhandled trap"; 105 } 106 107 return "unknown signal"; 108 } 109 110 /* 111 * Trap & Exception support 112 */ 113 114 #ifdef CONFIG_PMAC_BACKLIGHT 115 static void pmac_backlight_unblank(void) 116 { 117 mutex_lock(&pmac_backlight_mutex); 118 if (pmac_backlight) { 119 struct backlight_properties *props; 120 121 props = &pmac_backlight->props; 122 props->brightness = props->max_brightness; 123 props->power = FB_BLANK_UNBLANK; 124 backlight_update_status(pmac_backlight); 125 } 126 mutex_unlock(&pmac_backlight_mutex); 127 } 128 #else 129 static inline void pmac_backlight_unblank(void) { } 130 #endif 131 132 /* 133 * If oops/die is expected to crash the machine, return true here. 134 * 135 * This should not be expected to be 100% accurate, there may be 136 * notifiers registered or other unexpected conditions that may bring 137 * down the kernel. Or if the current process in the kernel is holding 138 * locks or has other critical state, the kernel may become effectively 139 * unusable anyway. 140 */ 141 bool die_will_crash(void) 142 { 143 if (should_fadump_crash()) 144 return true; 145 if (kexec_should_crash(current)) 146 return true; 147 if (in_interrupt() || panic_on_oops || 148 !current->pid || is_global_init(current)) 149 return true; 150 151 return false; 152 } 153 154 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; 155 static int die_owner = -1; 156 static unsigned int die_nest_count; 157 static int die_counter; 158 159 extern void panic_flush_kmsg_start(void) 160 { 161 /* 162 * These are mostly taken from kernel/panic.c, but tries to do 163 * relatively minimal work. Don't use delay functions (TB may 164 * be broken), don't crash dump (need to set a firmware log), 165 * don't run notifiers. We do want to get some information to 166 * Linux console. 167 */ 168 console_verbose(); 169 bust_spinlocks(1); 170 } 171 172 extern void panic_flush_kmsg_end(void) 173 { 174 printk_safe_flush_on_panic(); 175 kmsg_dump(KMSG_DUMP_PANIC); 176 bust_spinlocks(0); 177 debug_locks_off(); 178 console_flush_on_panic(CONSOLE_FLUSH_PENDING); 179 } 180 181 static unsigned long oops_begin(struct pt_regs *regs) 182 { 183 int cpu; 184 unsigned long flags; 185 186 oops_enter(); 187 188 /* racy, but better than risking deadlock. */ 189 raw_local_irq_save(flags); 190 cpu = smp_processor_id(); 191 if (!arch_spin_trylock(&die_lock)) { 192 if (cpu == die_owner) 193 /* nested oops. should stop eventually */; 194 else 195 arch_spin_lock(&die_lock); 196 } 197 die_nest_count++; 198 die_owner = cpu; 199 console_verbose(); 200 bust_spinlocks(1); 201 if (machine_is(powermac)) 202 pmac_backlight_unblank(); 203 return flags; 204 } 205 NOKPROBE_SYMBOL(oops_begin); 206 207 static void oops_end(unsigned long flags, struct pt_regs *regs, 208 int signr) 209 { 210 bust_spinlocks(0); 211 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 212 die_nest_count--; 213 oops_exit(); 214 printk("\n"); 215 if (!die_nest_count) { 216 /* Nest count reaches zero, release the lock. */ 217 die_owner = -1; 218 arch_spin_unlock(&die_lock); 219 } 220 raw_local_irq_restore(flags); 221 222 /* 223 * system_reset_excption handles debugger, crash dump, panic, for 0x100 224 */ 225 if (TRAP(regs) == 0x100) 226 return; 227 228 crash_fadump(regs, "die oops"); 229 230 if (kexec_should_crash(current)) 231 crash_kexec(regs); 232 233 if (!signr) 234 return; 235 236 /* 237 * While our oops output is serialised by a spinlock, output 238 * from panic() called below can race and corrupt it. If we 239 * know we are going to panic, delay for 1 second so we have a 240 * chance to get clean backtraces from all CPUs that are oopsing. 241 */ 242 if (in_interrupt() || panic_on_oops || !current->pid || 243 is_global_init(current)) { 244 mdelay(MSEC_PER_SEC); 245 } 246 247 if (panic_on_oops) 248 panic("Fatal exception"); 249 do_exit(signr); 250 } 251 NOKPROBE_SYMBOL(oops_end); 252 253 static char *get_mmu_str(void) 254 { 255 if (early_radix_enabled()) 256 return " MMU=Radix"; 257 if (early_mmu_has_feature(MMU_FTR_HPTE_TABLE)) 258 return " MMU=Hash"; 259 return ""; 260 } 261 262 static int __die(const char *str, struct pt_regs *regs, long err) 263 { 264 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); 265 266 printk("%s PAGE_SIZE=%luK%s%s%s%s%s%s %s\n", 267 IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN) ? "LE" : "BE", 268 PAGE_SIZE / 1024, get_mmu_str(), 269 IS_ENABLED(CONFIG_PREEMPT) ? " PREEMPT" : "", 270 IS_ENABLED(CONFIG_SMP) ? " SMP" : "", 271 IS_ENABLED(CONFIG_SMP) ? (" NR_CPUS=" __stringify(NR_CPUS)) : "", 272 debug_pagealloc_enabled() ? " DEBUG_PAGEALLOC" : "", 273 IS_ENABLED(CONFIG_NUMA) ? " NUMA" : "", 274 ppc_md.name ? ppc_md.name : ""); 275 276 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP) 277 return 1; 278 279 print_modules(); 280 show_regs(regs); 281 282 return 0; 283 } 284 NOKPROBE_SYMBOL(__die); 285 286 void die(const char *str, struct pt_regs *regs, long err) 287 { 288 unsigned long flags; 289 290 /* 291 * system_reset_excption handles debugger, crash dump, panic, for 0x100 292 */ 293 if (TRAP(regs) != 0x100) { 294 if (debugger(regs)) 295 return; 296 } 297 298 flags = oops_begin(regs); 299 if (__die(str, regs, err)) 300 err = 0; 301 oops_end(flags, regs, err); 302 } 303 NOKPROBE_SYMBOL(die); 304 305 void user_single_step_report(struct pt_regs *regs) 306 { 307 force_sig_fault(SIGTRAP, TRAP_TRACE, (void __user *)regs->nip); 308 } 309 310 static void show_signal_msg(int signr, struct pt_regs *regs, int code, 311 unsigned long addr) 312 { 313 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, 314 DEFAULT_RATELIMIT_BURST); 315 316 if (!show_unhandled_signals) 317 return; 318 319 if (!unhandled_signal(current, signr)) 320 return; 321 322 if (!__ratelimit(&rs)) 323 return; 324 325 pr_info("%s[%d]: %s (%d) at %lx nip %lx lr %lx code %x", 326 current->comm, current->pid, signame(signr), signr, 327 addr, regs->nip, regs->link, code); 328 329 print_vma_addr(KERN_CONT " in ", regs->nip); 330 331 pr_cont("\n"); 332 333 show_user_instructions(regs); 334 } 335 336 static bool exception_common(int signr, struct pt_regs *regs, int code, 337 unsigned long addr) 338 { 339 if (!user_mode(regs)) { 340 die("Exception in kernel mode", regs, signr); 341 return false; 342 } 343 344 show_signal_msg(signr, regs, code, addr); 345 346 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs)) 347 local_irq_enable(); 348 349 current->thread.trap_nr = code; 350 351 /* 352 * Save all the pkey registers AMR/IAMR/UAMOR. Eg: Core dumps need 353 * to capture the content, if the task gets killed. 354 */ 355 thread_pkey_regs_save(¤t->thread); 356 357 return true; 358 } 359 360 void _exception_pkey(struct pt_regs *regs, unsigned long addr, int key) 361 { 362 if (!exception_common(SIGSEGV, regs, SEGV_PKUERR, addr)) 363 return; 364 365 force_sig_pkuerr((void __user *) addr, key); 366 } 367 368 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) 369 { 370 if (!exception_common(signr, regs, code, addr)) 371 return; 372 373 force_sig_fault(signr, code, (void __user *)addr); 374 } 375 376 /* 377 * The interrupt architecture has a quirk in that the HV interrupts excluding 378 * the NMIs (0x100 and 0x200) do not clear MSR[RI] at entry. The first thing 379 * that an interrupt handler must do is save off a GPR into a scratch register, 380 * and all interrupts on POWERNV (HV=1) use the HSPRG1 register as scratch. 381 * Therefore an NMI can clobber an HV interrupt's live HSPRG1 without noticing 382 * that it is non-reentrant, which leads to random data corruption. 383 * 384 * The solution is for NMI interrupts in HV mode to check if they originated 385 * from these critical HV interrupt regions. If so, then mark them not 386 * recoverable. 387 * 388 * An alternative would be for HV NMIs to use SPRG for scratch to avoid the 389 * HSPRG1 clobber, however this would cause guest SPRG to be clobbered. Linux 390 * guests should always have MSR[RI]=0 when its scratch SPRG is in use, so 391 * that would work. However any other guest OS that may have the SPRG live 392 * and MSR[RI]=1 could encounter silent corruption. 393 * 394 * Builds that do not support KVM could take this second option to increase 395 * the recoverability of NMIs. 396 */ 397 void hv_nmi_check_nonrecoverable(struct pt_regs *regs) 398 { 399 #ifdef CONFIG_PPC_POWERNV 400 unsigned long kbase = (unsigned long)_stext; 401 unsigned long nip = regs->nip; 402 403 if (!(regs->msr & MSR_RI)) 404 return; 405 if (!(regs->msr & MSR_HV)) 406 return; 407 if (regs->msr & MSR_PR) 408 return; 409 410 /* 411 * Now test if the interrupt has hit a range that may be using 412 * HSPRG1 without having RI=0 (i.e., an HSRR interrupt). The 413 * problem ranges all run un-relocated. Test real and virt modes 414 * at the same time by droping the high bit of the nip (virt mode 415 * entry points still have the +0x4000 offset). 416 */ 417 nip &= ~0xc000000000000000ULL; 418 if ((nip >= 0x500 && nip < 0x600) || (nip >= 0x4500 && nip < 0x4600)) 419 goto nonrecoverable; 420 if ((nip >= 0x980 && nip < 0xa00) || (nip >= 0x4980 && nip < 0x4a00)) 421 goto nonrecoverable; 422 if ((nip >= 0xe00 && nip < 0xec0) || (nip >= 0x4e00 && nip < 0x4ec0)) 423 goto nonrecoverable; 424 if ((nip >= 0xf80 && nip < 0xfa0) || (nip >= 0x4f80 && nip < 0x4fa0)) 425 goto nonrecoverable; 426 427 /* Trampoline code runs un-relocated so subtract kbase. */ 428 if (nip >= (unsigned long)(start_real_trampolines - kbase) && 429 nip < (unsigned long)(end_real_trampolines - kbase)) 430 goto nonrecoverable; 431 if (nip >= (unsigned long)(start_virt_trampolines - kbase) && 432 nip < (unsigned long)(end_virt_trampolines - kbase)) 433 goto nonrecoverable; 434 return; 435 436 nonrecoverable: 437 regs->msr &= ~MSR_RI; 438 #endif 439 } 440 441 void system_reset_exception(struct pt_regs *regs) 442 { 443 unsigned long hsrr0, hsrr1; 444 bool saved_hsrrs = false; 445 446 nmi_enter(); 447 448 /* 449 * System reset can interrupt code where HSRRs are live and MSR[RI]=1. 450 * The system reset interrupt itself may clobber HSRRs (e.g., to call 451 * OPAL), so save them here and restore them before returning. 452 * 453 * Machine checks don't need to save HSRRs, as the real mode handler 454 * is careful to avoid them, and the regular handler is not delivered 455 * as an NMI. 456 */ 457 if (cpu_has_feature(CPU_FTR_HVMODE)) { 458 hsrr0 = mfspr(SPRN_HSRR0); 459 hsrr1 = mfspr(SPRN_HSRR1); 460 saved_hsrrs = true; 461 } 462 463 hv_nmi_check_nonrecoverable(regs); 464 465 __this_cpu_inc(irq_stat.sreset_irqs); 466 467 /* See if any machine dependent calls */ 468 if (ppc_md.system_reset_exception) { 469 if (ppc_md.system_reset_exception(regs)) 470 goto out; 471 } 472 473 if (debugger(regs)) 474 goto out; 475 476 kmsg_dump(KMSG_DUMP_OOPS); 477 /* 478 * A system reset is a request to dump, so we always send 479 * it through the crashdump code (if fadump or kdump are 480 * registered). 481 */ 482 crash_fadump(regs, "System Reset"); 483 484 crash_kexec(regs); 485 486 /* 487 * We aren't the primary crash CPU. We need to send it 488 * to a holding pattern to avoid it ending up in the panic 489 * code. 490 */ 491 crash_kexec_secondary(regs); 492 493 /* 494 * No debugger or crash dump registered, print logs then 495 * panic. 496 */ 497 die("System Reset", regs, SIGABRT); 498 499 mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */ 500 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 501 nmi_panic(regs, "System Reset"); 502 503 out: 504 #ifdef CONFIG_PPC_BOOK3S_64 505 BUG_ON(get_paca()->in_nmi == 0); 506 if (get_paca()->in_nmi > 1) 507 nmi_panic(regs, "Unrecoverable nested System Reset"); 508 #endif 509 /* Must die if the interrupt is not recoverable */ 510 if (!(regs->msr & MSR_RI)) 511 nmi_panic(regs, "Unrecoverable System Reset"); 512 513 if (saved_hsrrs) { 514 mtspr(SPRN_HSRR0, hsrr0); 515 mtspr(SPRN_HSRR1, hsrr1); 516 } 517 518 nmi_exit(); 519 520 /* What should we do here? We could issue a shutdown or hard reset. */ 521 } 522 523 /* 524 * I/O accesses can cause machine checks on powermacs. 525 * Check if the NIP corresponds to the address of a sync 526 * instruction for which there is an entry in the exception 527 * table. 528 * Note that the 601 only takes a machine check on TEA 529 * (transfer error ack) signal assertion, and does not 530 * set any of the top 16 bits of SRR1. 531 * -- paulus. 532 */ 533 static inline int check_io_access(struct pt_regs *regs) 534 { 535 #ifdef CONFIG_PPC32 536 unsigned long msr = regs->msr; 537 const struct exception_table_entry *entry; 538 unsigned int *nip = (unsigned int *)regs->nip; 539 540 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) 541 && (entry = search_exception_tables(regs->nip)) != NULL) { 542 /* 543 * Check that it's a sync instruction, or somewhere 544 * in the twi; isync; nop sequence that inb/inw/inl uses. 545 * As the address is in the exception table 546 * we should be able to read the instr there. 547 * For the debug message, we look at the preceding 548 * load or store. 549 */ 550 if (*nip == PPC_INST_NOP) 551 nip -= 2; 552 else if (*nip == PPC_INST_ISYNC) 553 --nip; 554 if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) { 555 unsigned int rb; 556 557 --nip; 558 rb = (*nip >> 11) & 0x1f; 559 printk(KERN_DEBUG "%s bad port %lx at %p\n", 560 (*nip & 0x100)? "OUT to": "IN from", 561 regs->gpr[rb] - _IO_BASE, nip); 562 regs->msr |= MSR_RI; 563 regs->nip = extable_fixup(entry); 564 return 1; 565 } 566 } 567 #endif /* CONFIG_PPC32 */ 568 return 0; 569 } 570 571 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 572 /* On 4xx, the reason for the machine check or program exception 573 is in the ESR. */ 574 #define get_reason(regs) ((regs)->dsisr) 575 #define REASON_FP ESR_FP 576 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) 577 #define REASON_PRIVILEGED ESR_PPR 578 #define REASON_TRAP ESR_PTR 579 580 /* single-step stuff */ 581 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC) 582 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC) 583 #define clear_br_trace(regs) do {} while(0) 584 #else 585 /* On non-4xx, the reason for the machine check or program 586 exception is in the MSR. */ 587 #define get_reason(regs) ((regs)->msr) 588 #define REASON_TM SRR1_PROGTM 589 #define REASON_FP SRR1_PROGFPE 590 #define REASON_ILLEGAL SRR1_PROGILL 591 #define REASON_PRIVILEGED SRR1_PROGPRIV 592 #define REASON_TRAP SRR1_PROGTRAP 593 594 #define single_stepping(regs) ((regs)->msr & MSR_SE) 595 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) 596 #define clear_br_trace(regs) ((regs)->msr &= ~MSR_BE) 597 #endif 598 599 #if defined(CONFIG_E500) 600 int machine_check_e500mc(struct pt_regs *regs) 601 { 602 unsigned long mcsr = mfspr(SPRN_MCSR); 603 unsigned long pvr = mfspr(SPRN_PVR); 604 unsigned long reason = mcsr; 605 int recoverable = 1; 606 607 if (reason & MCSR_LD) { 608 recoverable = fsl_rio_mcheck_exception(regs); 609 if (recoverable == 1) 610 goto silent_out; 611 } 612 613 printk("Machine check in kernel mode.\n"); 614 printk("Caused by (from MCSR=%lx): ", reason); 615 616 if (reason & MCSR_MCP) 617 pr_cont("Machine Check Signal\n"); 618 619 if (reason & MCSR_ICPERR) { 620 pr_cont("Instruction Cache Parity Error\n"); 621 622 /* 623 * This is recoverable by invalidating the i-cache. 624 */ 625 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); 626 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) 627 ; 628 629 /* 630 * This will generally be accompanied by an instruction 631 * fetch error report -- only treat MCSR_IF as fatal 632 * if it wasn't due to an L1 parity error. 633 */ 634 reason &= ~MCSR_IF; 635 } 636 637 if (reason & MCSR_DCPERR_MC) { 638 pr_cont("Data Cache Parity Error\n"); 639 640 /* 641 * In write shadow mode we auto-recover from the error, but it 642 * may still get logged and cause a machine check. We should 643 * only treat the non-write shadow case as non-recoverable. 644 */ 645 /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit 646 * is not implemented but L1 data cache always runs in write 647 * shadow mode. Hence on data cache parity errors HW will 648 * automatically invalidate the L1 Data Cache. 649 */ 650 if (PVR_VER(pvr) != PVR_VER_E6500) { 651 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) 652 recoverable = 0; 653 } 654 } 655 656 if (reason & MCSR_L2MMU_MHIT) { 657 pr_cont("Hit on multiple TLB entries\n"); 658 recoverable = 0; 659 } 660 661 if (reason & MCSR_NMI) 662 pr_cont("Non-maskable interrupt\n"); 663 664 if (reason & MCSR_IF) { 665 pr_cont("Instruction Fetch Error Report\n"); 666 recoverable = 0; 667 } 668 669 if (reason & MCSR_LD) { 670 pr_cont("Load Error Report\n"); 671 recoverable = 0; 672 } 673 674 if (reason & MCSR_ST) { 675 pr_cont("Store Error Report\n"); 676 recoverable = 0; 677 } 678 679 if (reason & MCSR_LDG) { 680 pr_cont("Guarded Load Error Report\n"); 681 recoverable = 0; 682 } 683 684 if (reason & MCSR_TLBSYNC) 685 pr_cont("Simultaneous tlbsync operations\n"); 686 687 if (reason & MCSR_BSL2_ERR) { 688 pr_cont("Level 2 Cache Error\n"); 689 recoverable = 0; 690 } 691 692 if (reason & MCSR_MAV) { 693 u64 addr; 694 695 addr = mfspr(SPRN_MCAR); 696 addr |= (u64)mfspr(SPRN_MCARU) << 32; 697 698 pr_cont("Machine Check %s Address: %#llx\n", 699 reason & MCSR_MEA ? "Effective" : "Physical", addr); 700 } 701 702 silent_out: 703 mtspr(SPRN_MCSR, mcsr); 704 return mfspr(SPRN_MCSR) == 0 && recoverable; 705 } 706 707 int machine_check_e500(struct pt_regs *regs) 708 { 709 unsigned long reason = mfspr(SPRN_MCSR); 710 711 if (reason & MCSR_BUS_RBERR) { 712 if (fsl_rio_mcheck_exception(regs)) 713 return 1; 714 if (fsl_pci_mcheck_exception(regs)) 715 return 1; 716 } 717 718 printk("Machine check in kernel mode.\n"); 719 printk("Caused by (from MCSR=%lx): ", reason); 720 721 if (reason & MCSR_MCP) 722 pr_cont("Machine Check Signal\n"); 723 if (reason & MCSR_ICPERR) 724 pr_cont("Instruction Cache Parity Error\n"); 725 if (reason & MCSR_DCP_PERR) 726 pr_cont("Data Cache Push Parity Error\n"); 727 if (reason & MCSR_DCPERR) 728 pr_cont("Data Cache Parity Error\n"); 729 if (reason & MCSR_BUS_IAERR) 730 pr_cont("Bus - Instruction Address Error\n"); 731 if (reason & MCSR_BUS_RAERR) 732 pr_cont("Bus - Read Address Error\n"); 733 if (reason & MCSR_BUS_WAERR) 734 pr_cont("Bus - Write Address Error\n"); 735 if (reason & MCSR_BUS_IBERR) 736 pr_cont("Bus - Instruction Data Error\n"); 737 if (reason & MCSR_BUS_RBERR) 738 pr_cont("Bus - Read Data Bus Error\n"); 739 if (reason & MCSR_BUS_WBERR) 740 pr_cont("Bus - Write Data Bus Error\n"); 741 if (reason & MCSR_BUS_IPERR) 742 pr_cont("Bus - Instruction Parity Error\n"); 743 if (reason & MCSR_BUS_RPERR) 744 pr_cont("Bus - Read Parity Error\n"); 745 746 return 0; 747 } 748 749 int machine_check_generic(struct pt_regs *regs) 750 { 751 return 0; 752 } 753 #elif defined(CONFIG_E200) 754 int machine_check_e200(struct pt_regs *regs) 755 { 756 unsigned long reason = mfspr(SPRN_MCSR); 757 758 printk("Machine check in kernel mode.\n"); 759 printk("Caused by (from MCSR=%lx): ", reason); 760 761 if (reason & MCSR_MCP) 762 pr_cont("Machine Check Signal\n"); 763 if (reason & MCSR_CP_PERR) 764 pr_cont("Cache Push Parity Error\n"); 765 if (reason & MCSR_CPERR) 766 pr_cont("Cache Parity Error\n"); 767 if (reason & MCSR_EXCP_ERR) 768 pr_cont("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); 769 if (reason & MCSR_BUS_IRERR) 770 pr_cont("Bus - Read Bus Error on instruction fetch\n"); 771 if (reason & MCSR_BUS_DRERR) 772 pr_cont("Bus - Read Bus Error on data load\n"); 773 if (reason & MCSR_BUS_WRERR) 774 pr_cont("Bus - Write Bus Error on buffered store or cache line push\n"); 775 776 return 0; 777 } 778 #elif defined(CONFIG_PPC32) 779 int machine_check_generic(struct pt_regs *regs) 780 { 781 unsigned long reason = regs->msr; 782 783 printk("Machine check in kernel mode.\n"); 784 printk("Caused by (from SRR1=%lx): ", reason); 785 switch (reason & 0x601F0000) { 786 case 0x80000: 787 pr_cont("Machine check signal\n"); 788 break; 789 case 0: /* for 601 */ 790 case 0x40000: 791 case 0x140000: /* 7450 MSS error and TEA */ 792 pr_cont("Transfer error ack signal\n"); 793 break; 794 case 0x20000: 795 pr_cont("Data parity error signal\n"); 796 break; 797 case 0x10000: 798 pr_cont("Address parity error signal\n"); 799 break; 800 case 0x20000000: 801 pr_cont("L1 Data Cache error\n"); 802 break; 803 case 0x40000000: 804 pr_cont("L1 Instruction Cache error\n"); 805 break; 806 case 0x00100000: 807 pr_cont("L2 data cache parity error\n"); 808 break; 809 default: 810 pr_cont("Unknown values in msr\n"); 811 } 812 return 0; 813 } 814 #endif /* everything else */ 815 816 void machine_check_exception(struct pt_regs *regs) 817 { 818 int recover = 0; 819 820 nmi_enter(); 821 822 __this_cpu_inc(irq_stat.mce_exceptions); 823 824 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 825 826 /* See if any machine dependent calls. In theory, we would want 827 * to call the CPU first, and call the ppc_md. one if the CPU 828 * one returns a positive number. However there is existing code 829 * that assumes the board gets a first chance, so let's keep it 830 * that way for now and fix things later. --BenH. 831 */ 832 if (ppc_md.machine_check_exception) 833 recover = ppc_md.machine_check_exception(regs); 834 else if (cur_cpu_spec->machine_check) 835 recover = cur_cpu_spec->machine_check(regs); 836 837 if (recover > 0) 838 goto bail; 839 840 if (debugger_fault_handler(regs)) 841 goto bail; 842 843 if (check_io_access(regs)) 844 goto bail; 845 846 nmi_exit(); 847 848 die("Machine check", regs, SIGBUS); 849 850 /* Must die if the interrupt is not recoverable */ 851 if (!(regs->msr & MSR_RI)) 852 nmi_panic(regs, "Unrecoverable Machine check"); 853 854 return; 855 856 bail: 857 nmi_exit(); 858 } 859 860 void SMIException(struct pt_regs *regs) 861 { 862 die("System Management Interrupt", regs, SIGABRT); 863 } 864 865 #ifdef CONFIG_VSX 866 static void p9_hmi_special_emu(struct pt_regs *regs) 867 { 868 unsigned int ra, rb, t, i, sel, instr, rc; 869 const void __user *addr; 870 u8 vbuf[16], *vdst; 871 unsigned long ea, msr, msr_mask; 872 bool swap; 873 874 if (__get_user_inatomic(instr, (unsigned int __user *)regs->nip)) 875 return; 876 877 /* 878 * lxvb16x opcode: 0x7c0006d8 879 * lxvd2x opcode: 0x7c000698 880 * lxvh8x opcode: 0x7c000658 881 * lxvw4x opcode: 0x7c000618 882 */ 883 if ((instr & 0xfc00073e) != 0x7c000618) { 884 pr_devel("HMI vec emu: not vector CI %i:%s[%d] nip=%016lx" 885 " instr=%08x\n", 886 smp_processor_id(), current->comm, current->pid, 887 regs->nip, instr); 888 return; 889 } 890 891 /* Grab vector registers into the task struct */ 892 msr = regs->msr; /* Grab msr before we flush the bits */ 893 flush_vsx_to_thread(current); 894 enable_kernel_altivec(); 895 896 /* 897 * Is userspace running with a different endian (this is rare but 898 * not impossible) 899 */ 900 swap = (msr & MSR_LE) != (MSR_KERNEL & MSR_LE); 901 902 /* Decode the instruction */ 903 ra = (instr >> 16) & 0x1f; 904 rb = (instr >> 11) & 0x1f; 905 t = (instr >> 21) & 0x1f; 906 if (instr & 1) 907 vdst = (u8 *)¤t->thread.vr_state.vr[t]; 908 else 909 vdst = (u8 *)¤t->thread.fp_state.fpr[t][0]; 910 911 /* Grab the vector address */ 912 ea = regs->gpr[rb] + (ra ? regs->gpr[ra] : 0); 913 if (is_32bit_task()) 914 ea &= 0xfffffffful; 915 addr = (__force const void __user *)ea; 916 917 /* Check it */ 918 if (!access_ok(addr, 16)) { 919 pr_devel("HMI vec emu: bad access %i:%s[%d] nip=%016lx" 920 " instr=%08x addr=%016lx\n", 921 smp_processor_id(), current->comm, current->pid, 922 regs->nip, instr, (unsigned long)addr); 923 return; 924 } 925 926 /* Read the vector */ 927 rc = 0; 928 if ((unsigned long)addr & 0xfUL) 929 /* unaligned case */ 930 rc = __copy_from_user_inatomic(vbuf, addr, 16); 931 else 932 __get_user_atomic_128_aligned(vbuf, addr, rc); 933 if (rc) { 934 pr_devel("HMI vec emu: page fault %i:%s[%d] nip=%016lx" 935 " instr=%08x addr=%016lx\n", 936 smp_processor_id(), current->comm, current->pid, 937 regs->nip, instr, (unsigned long)addr); 938 return; 939 } 940 941 pr_devel("HMI vec emu: emulated vector CI %i:%s[%d] nip=%016lx" 942 " instr=%08x addr=%016lx\n", 943 smp_processor_id(), current->comm, current->pid, regs->nip, 944 instr, (unsigned long) addr); 945 946 /* Grab instruction "selector" */ 947 sel = (instr >> 6) & 3; 948 949 /* 950 * Check to make sure the facility is actually enabled. This 951 * could happen if we get a false positive hit. 952 * 953 * lxvd2x/lxvw4x always check MSR VSX sel = 0,2 954 * lxvh8x/lxvb16x check MSR VSX or VEC depending on VSR used sel = 1,3 955 */ 956 msr_mask = MSR_VSX; 957 if ((sel & 1) && (instr & 1)) /* lxvh8x & lxvb16x + VSR >= 32 */ 958 msr_mask = MSR_VEC; 959 if (!(msr & msr_mask)) { 960 pr_devel("HMI vec emu: MSR fac clear %i:%s[%d] nip=%016lx" 961 " instr=%08x msr:%016lx\n", 962 smp_processor_id(), current->comm, current->pid, 963 regs->nip, instr, msr); 964 return; 965 } 966 967 /* Do logging here before we modify sel based on endian */ 968 switch (sel) { 969 case 0: /* lxvw4x */ 970 PPC_WARN_EMULATED(lxvw4x, regs); 971 break; 972 case 1: /* lxvh8x */ 973 PPC_WARN_EMULATED(lxvh8x, regs); 974 break; 975 case 2: /* lxvd2x */ 976 PPC_WARN_EMULATED(lxvd2x, regs); 977 break; 978 case 3: /* lxvb16x */ 979 PPC_WARN_EMULATED(lxvb16x, regs); 980 break; 981 } 982 983 #ifdef __LITTLE_ENDIAN__ 984 /* 985 * An LE kernel stores the vector in the task struct as an LE 986 * byte array (effectively swapping both the components and 987 * the content of the components). Those instructions expect 988 * the components to remain in ascending address order, so we 989 * swap them back. 990 * 991 * If we are running a BE user space, the expectation is that 992 * of a simple memcpy, so forcing the emulation to look like 993 * a lxvb16x should do the trick. 994 */ 995 if (swap) 996 sel = 3; 997 998 switch (sel) { 999 case 0: /* lxvw4x */ 1000 for (i = 0; i < 4; i++) 1001 ((u32 *)vdst)[i] = ((u32 *)vbuf)[3-i]; 1002 break; 1003 case 1: /* lxvh8x */ 1004 for (i = 0; i < 8; i++) 1005 ((u16 *)vdst)[i] = ((u16 *)vbuf)[7-i]; 1006 break; 1007 case 2: /* lxvd2x */ 1008 for (i = 0; i < 2; i++) 1009 ((u64 *)vdst)[i] = ((u64 *)vbuf)[1-i]; 1010 break; 1011 case 3: /* lxvb16x */ 1012 for (i = 0; i < 16; i++) 1013 vdst[i] = vbuf[15-i]; 1014 break; 1015 } 1016 #else /* __LITTLE_ENDIAN__ */ 1017 /* On a big endian kernel, a BE userspace only needs a memcpy */ 1018 if (!swap) 1019 sel = 3; 1020 1021 /* Otherwise, we need to swap the content of the components */ 1022 switch (sel) { 1023 case 0: /* lxvw4x */ 1024 for (i = 0; i < 4; i++) 1025 ((u32 *)vdst)[i] = cpu_to_le32(((u32 *)vbuf)[i]); 1026 break; 1027 case 1: /* lxvh8x */ 1028 for (i = 0; i < 8; i++) 1029 ((u16 *)vdst)[i] = cpu_to_le16(((u16 *)vbuf)[i]); 1030 break; 1031 case 2: /* lxvd2x */ 1032 for (i = 0; i < 2; i++) 1033 ((u64 *)vdst)[i] = cpu_to_le64(((u64 *)vbuf)[i]); 1034 break; 1035 case 3: /* lxvb16x */ 1036 memcpy(vdst, vbuf, 16); 1037 break; 1038 } 1039 #endif /* !__LITTLE_ENDIAN__ */ 1040 1041 /* Go to next instruction */ 1042 regs->nip += 4; 1043 } 1044 #endif /* CONFIG_VSX */ 1045 1046 void handle_hmi_exception(struct pt_regs *regs) 1047 { 1048 struct pt_regs *old_regs; 1049 1050 old_regs = set_irq_regs(regs); 1051 irq_enter(); 1052 1053 #ifdef CONFIG_VSX 1054 /* Real mode flagged P9 special emu is needed */ 1055 if (local_paca->hmi_p9_special_emu) { 1056 local_paca->hmi_p9_special_emu = 0; 1057 1058 /* 1059 * We don't want to take page faults while doing the 1060 * emulation, we just replay the instruction if necessary. 1061 */ 1062 pagefault_disable(); 1063 p9_hmi_special_emu(regs); 1064 pagefault_enable(); 1065 } 1066 #endif /* CONFIG_VSX */ 1067 1068 if (ppc_md.handle_hmi_exception) 1069 ppc_md.handle_hmi_exception(regs); 1070 1071 irq_exit(); 1072 set_irq_regs(old_regs); 1073 } 1074 1075 void unknown_exception(struct pt_regs *regs) 1076 { 1077 enum ctx_state prev_state = exception_enter(); 1078 1079 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 1080 regs->nip, regs->msr, regs->trap); 1081 1082 _exception(SIGTRAP, regs, TRAP_UNK, 0); 1083 1084 exception_exit(prev_state); 1085 } 1086 1087 void instruction_breakpoint_exception(struct pt_regs *regs) 1088 { 1089 enum ctx_state prev_state = exception_enter(); 1090 1091 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, 1092 5, SIGTRAP) == NOTIFY_STOP) 1093 goto bail; 1094 if (debugger_iabr_match(regs)) 1095 goto bail; 1096 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1097 1098 bail: 1099 exception_exit(prev_state); 1100 } 1101 1102 void RunModeException(struct pt_regs *regs) 1103 { 1104 _exception(SIGTRAP, regs, TRAP_UNK, 0); 1105 } 1106 1107 void single_step_exception(struct pt_regs *regs) 1108 { 1109 enum ctx_state prev_state = exception_enter(); 1110 1111 clear_single_step(regs); 1112 clear_br_trace(regs); 1113 1114 if (kprobe_post_handler(regs)) 1115 return; 1116 1117 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 1118 5, SIGTRAP) == NOTIFY_STOP) 1119 goto bail; 1120 if (debugger_sstep(regs)) 1121 goto bail; 1122 1123 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 1124 1125 bail: 1126 exception_exit(prev_state); 1127 } 1128 NOKPROBE_SYMBOL(single_step_exception); 1129 1130 /* 1131 * After we have successfully emulated an instruction, we have to 1132 * check if the instruction was being single-stepped, and if so, 1133 * pretend we got a single-step exception. This was pointed out 1134 * by Kumar Gala. -- paulus 1135 */ 1136 static void emulate_single_step(struct pt_regs *regs) 1137 { 1138 if (single_stepping(regs)) 1139 single_step_exception(regs); 1140 } 1141 1142 static inline int __parse_fpscr(unsigned long fpscr) 1143 { 1144 int ret = FPE_FLTUNK; 1145 1146 /* Invalid operation */ 1147 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) 1148 ret = FPE_FLTINV; 1149 1150 /* Overflow */ 1151 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) 1152 ret = FPE_FLTOVF; 1153 1154 /* Underflow */ 1155 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) 1156 ret = FPE_FLTUND; 1157 1158 /* Divide by zero */ 1159 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) 1160 ret = FPE_FLTDIV; 1161 1162 /* Inexact result */ 1163 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) 1164 ret = FPE_FLTRES; 1165 1166 return ret; 1167 } 1168 1169 static void parse_fpe(struct pt_regs *regs) 1170 { 1171 int code = 0; 1172 1173 flush_fp_to_thread(current); 1174 1175 code = __parse_fpscr(current->thread.fp_state.fpscr); 1176 1177 _exception(SIGFPE, regs, code, regs->nip); 1178 } 1179 1180 /* 1181 * Illegal instruction emulation support. Originally written to 1182 * provide the PVR to user applications using the mfspr rd, PVR. 1183 * Return non-zero if we can't emulate, or -EFAULT if the associated 1184 * memory access caused an access fault. Return zero on success. 1185 * 1186 * There are a couple of ways to do this, either "decode" the instruction 1187 * or directly match lots of bits. In this case, matching lots of 1188 * bits is faster and easier. 1189 * 1190 */ 1191 static int emulate_string_inst(struct pt_regs *regs, u32 instword) 1192 { 1193 u8 rT = (instword >> 21) & 0x1f; 1194 u8 rA = (instword >> 16) & 0x1f; 1195 u8 NB_RB = (instword >> 11) & 0x1f; 1196 u32 num_bytes; 1197 unsigned long EA; 1198 int pos = 0; 1199 1200 /* Early out if we are an invalid form of lswx */ 1201 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) 1202 if ((rT == rA) || (rT == NB_RB)) 1203 return -EINVAL; 1204 1205 EA = (rA == 0) ? 0 : regs->gpr[rA]; 1206 1207 switch (instword & PPC_INST_STRING_MASK) { 1208 case PPC_INST_LSWX: 1209 case PPC_INST_STSWX: 1210 EA += NB_RB; 1211 num_bytes = regs->xer & 0x7f; 1212 break; 1213 case PPC_INST_LSWI: 1214 case PPC_INST_STSWI: 1215 num_bytes = (NB_RB == 0) ? 32 : NB_RB; 1216 break; 1217 default: 1218 return -EINVAL; 1219 } 1220 1221 while (num_bytes != 0) 1222 { 1223 u8 val; 1224 u32 shift = 8 * (3 - (pos & 0x3)); 1225 1226 /* if process is 32-bit, clear upper 32 bits of EA */ 1227 if ((regs->msr & MSR_64BIT) == 0) 1228 EA &= 0xFFFFFFFF; 1229 1230 switch ((instword & PPC_INST_STRING_MASK)) { 1231 case PPC_INST_LSWX: 1232 case PPC_INST_LSWI: 1233 if (get_user(val, (u8 __user *)EA)) 1234 return -EFAULT; 1235 /* first time updating this reg, 1236 * zero it out */ 1237 if (pos == 0) 1238 regs->gpr[rT] = 0; 1239 regs->gpr[rT] |= val << shift; 1240 break; 1241 case PPC_INST_STSWI: 1242 case PPC_INST_STSWX: 1243 val = regs->gpr[rT] >> shift; 1244 if (put_user(val, (u8 __user *)EA)) 1245 return -EFAULT; 1246 break; 1247 } 1248 /* move EA to next address */ 1249 EA += 1; 1250 num_bytes--; 1251 1252 /* manage our position within the register */ 1253 if (++pos == 4) { 1254 pos = 0; 1255 if (++rT == 32) 1256 rT = 0; 1257 } 1258 } 1259 1260 return 0; 1261 } 1262 1263 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) 1264 { 1265 u32 ra,rs; 1266 unsigned long tmp; 1267 1268 ra = (instword >> 16) & 0x1f; 1269 rs = (instword >> 21) & 0x1f; 1270 1271 tmp = regs->gpr[rs]; 1272 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); 1273 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); 1274 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; 1275 regs->gpr[ra] = tmp; 1276 1277 return 0; 1278 } 1279 1280 static int emulate_isel(struct pt_regs *regs, u32 instword) 1281 { 1282 u8 rT = (instword >> 21) & 0x1f; 1283 u8 rA = (instword >> 16) & 0x1f; 1284 u8 rB = (instword >> 11) & 0x1f; 1285 u8 BC = (instword >> 6) & 0x1f; 1286 u8 bit; 1287 unsigned long tmp; 1288 1289 tmp = (rA == 0) ? 0 : regs->gpr[rA]; 1290 bit = (regs->ccr >> (31 - BC)) & 0x1; 1291 1292 regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; 1293 1294 return 0; 1295 } 1296 1297 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1298 static inline bool tm_abort_check(struct pt_regs *regs, int cause) 1299 { 1300 /* If we're emulating a load/store in an active transaction, we cannot 1301 * emulate it as the kernel operates in transaction suspended context. 1302 * We need to abort the transaction. This creates a persistent TM 1303 * abort so tell the user what caused it with a new code. 1304 */ 1305 if (MSR_TM_TRANSACTIONAL(regs->msr)) { 1306 tm_enable(); 1307 tm_abort(cause); 1308 return true; 1309 } 1310 return false; 1311 } 1312 #else 1313 static inline bool tm_abort_check(struct pt_regs *regs, int reason) 1314 { 1315 return false; 1316 } 1317 #endif 1318 1319 static int emulate_instruction(struct pt_regs *regs) 1320 { 1321 u32 instword; 1322 u32 rd; 1323 1324 if (!user_mode(regs)) 1325 return -EINVAL; 1326 CHECK_FULL_REGS(regs); 1327 1328 if (get_user(instword, (u32 __user *)(regs->nip))) 1329 return -EFAULT; 1330 1331 /* Emulate the mfspr rD, PVR. */ 1332 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { 1333 PPC_WARN_EMULATED(mfpvr, regs); 1334 rd = (instword >> 21) & 0x1f; 1335 regs->gpr[rd] = mfspr(SPRN_PVR); 1336 return 0; 1337 } 1338 1339 /* Emulating the dcba insn is just a no-op. */ 1340 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { 1341 PPC_WARN_EMULATED(dcba, regs); 1342 return 0; 1343 } 1344 1345 /* Emulate the mcrxr insn. */ 1346 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { 1347 int shift = (instword >> 21) & 0x1c; 1348 unsigned long msk = 0xf0000000UL >> shift; 1349 1350 PPC_WARN_EMULATED(mcrxr, regs); 1351 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); 1352 regs->xer &= ~0xf0000000UL; 1353 return 0; 1354 } 1355 1356 /* Emulate load/store string insn. */ 1357 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { 1358 if (tm_abort_check(regs, 1359 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) 1360 return -EINVAL; 1361 PPC_WARN_EMULATED(string, regs); 1362 return emulate_string_inst(regs, instword); 1363 } 1364 1365 /* Emulate the popcntb (Population Count Bytes) instruction. */ 1366 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { 1367 PPC_WARN_EMULATED(popcntb, regs); 1368 return emulate_popcntb_inst(regs, instword); 1369 } 1370 1371 /* Emulate isel (Integer Select) instruction */ 1372 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { 1373 PPC_WARN_EMULATED(isel, regs); 1374 return emulate_isel(regs, instword); 1375 } 1376 1377 /* Emulate sync instruction variants */ 1378 if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) { 1379 PPC_WARN_EMULATED(sync, regs); 1380 asm volatile("sync"); 1381 return 0; 1382 } 1383 1384 #ifdef CONFIG_PPC64 1385 /* Emulate the mfspr rD, DSCR. */ 1386 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) == 1387 PPC_INST_MFSPR_DSCR_USER) || 1388 ((instword & PPC_INST_MFSPR_DSCR_MASK) == 1389 PPC_INST_MFSPR_DSCR)) && 1390 cpu_has_feature(CPU_FTR_DSCR)) { 1391 PPC_WARN_EMULATED(mfdscr, regs); 1392 rd = (instword >> 21) & 0x1f; 1393 regs->gpr[rd] = mfspr(SPRN_DSCR); 1394 return 0; 1395 } 1396 /* Emulate the mtspr DSCR, rD. */ 1397 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) == 1398 PPC_INST_MTSPR_DSCR_USER) || 1399 ((instword & PPC_INST_MTSPR_DSCR_MASK) == 1400 PPC_INST_MTSPR_DSCR)) && 1401 cpu_has_feature(CPU_FTR_DSCR)) { 1402 PPC_WARN_EMULATED(mtdscr, regs); 1403 rd = (instword >> 21) & 0x1f; 1404 current->thread.dscr = regs->gpr[rd]; 1405 current->thread.dscr_inherit = 1; 1406 mtspr(SPRN_DSCR, current->thread.dscr); 1407 return 0; 1408 } 1409 #endif 1410 1411 return -EINVAL; 1412 } 1413 1414 int is_valid_bugaddr(unsigned long addr) 1415 { 1416 return is_kernel_addr(addr); 1417 } 1418 1419 #ifdef CONFIG_MATH_EMULATION 1420 static int emulate_math(struct pt_regs *regs) 1421 { 1422 int ret; 1423 extern int do_mathemu(struct pt_regs *regs); 1424 1425 ret = do_mathemu(regs); 1426 if (ret >= 0) 1427 PPC_WARN_EMULATED(math, regs); 1428 1429 switch (ret) { 1430 case 0: 1431 emulate_single_step(regs); 1432 return 0; 1433 case 1: { 1434 int code = 0; 1435 code = __parse_fpscr(current->thread.fp_state.fpscr); 1436 _exception(SIGFPE, regs, code, regs->nip); 1437 return 0; 1438 } 1439 case -EFAULT: 1440 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1441 return 0; 1442 } 1443 1444 return -1; 1445 } 1446 #else 1447 static inline int emulate_math(struct pt_regs *regs) { return -1; } 1448 #endif 1449 1450 void program_check_exception(struct pt_regs *regs) 1451 { 1452 enum ctx_state prev_state = exception_enter(); 1453 unsigned int reason = get_reason(regs); 1454 1455 /* We can now get here via a FP Unavailable exception if the core 1456 * has no FPU, in that case the reason flags will be 0 */ 1457 1458 if (reason & REASON_FP) { 1459 /* IEEE FP exception */ 1460 parse_fpe(regs); 1461 goto bail; 1462 } 1463 if (reason & REASON_TRAP) { 1464 unsigned long bugaddr; 1465 /* Debugger is first in line to stop recursive faults in 1466 * rcu_lock, notify_die, or atomic_notifier_call_chain */ 1467 if (debugger_bpt(regs)) 1468 goto bail; 1469 1470 if (kprobe_handler(regs)) 1471 goto bail; 1472 1473 /* trap exception */ 1474 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) 1475 == NOTIFY_STOP) 1476 goto bail; 1477 1478 bugaddr = regs->nip; 1479 /* 1480 * Fixup bugaddr for BUG_ON() in real mode 1481 */ 1482 if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR)) 1483 bugaddr += PAGE_OFFSET; 1484 1485 if (!(regs->msr & MSR_PR) && /* not user-mode */ 1486 report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) { 1487 regs->nip += 4; 1488 goto bail; 1489 } 1490 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1491 goto bail; 1492 } 1493 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1494 if (reason & REASON_TM) { 1495 /* This is a TM "Bad Thing Exception" program check. 1496 * This occurs when: 1497 * - An rfid/hrfid/mtmsrd attempts to cause an illegal 1498 * transition in TM states. 1499 * - A trechkpt is attempted when transactional. 1500 * - A treclaim is attempted when non transactional. 1501 * - A tend is illegally attempted. 1502 * - writing a TM SPR when transactional. 1503 * 1504 * If usermode caused this, it's done something illegal and 1505 * gets a SIGILL slap on the wrist. We call it an illegal 1506 * operand to distinguish from the instruction just being bad 1507 * (e.g. executing a 'tend' on a CPU without TM!); it's an 1508 * illegal /placement/ of a valid instruction. 1509 */ 1510 if (user_mode(regs)) { 1511 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip); 1512 goto bail; 1513 } else { 1514 printk(KERN_EMERG "Unexpected TM Bad Thing exception " 1515 "at %lx (msr 0x%lx) tm_scratch=%llx\n", 1516 regs->nip, regs->msr, get_paca()->tm_scratch); 1517 die("Unrecoverable exception", regs, SIGABRT); 1518 } 1519 } 1520 #endif 1521 1522 /* 1523 * If we took the program check in the kernel skip down to sending a 1524 * SIGILL. The subsequent cases all relate to emulating instructions 1525 * which we should only do for userspace. We also do not want to enable 1526 * interrupts for kernel faults because that might lead to further 1527 * faults, and loose the context of the original exception. 1528 */ 1529 if (!user_mode(regs)) 1530 goto sigill; 1531 1532 /* We restore the interrupt state now */ 1533 if (!arch_irq_disabled_regs(regs)) 1534 local_irq_enable(); 1535 1536 /* (reason & REASON_ILLEGAL) would be the obvious thing here, 1537 * but there seems to be a hardware bug on the 405GP (RevD) 1538 * that means ESR is sometimes set incorrectly - either to 1539 * ESR_DST (!?) or 0. In the process of chasing this with the 1540 * hardware people - not sure if it can happen on any illegal 1541 * instruction or only on FP instructions, whether there is a 1542 * pattern to occurrences etc. -dgibson 31/Mar/2003 1543 */ 1544 if (!emulate_math(regs)) 1545 goto bail; 1546 1547 /* Try to emulate it if we should. */ 1548 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { 1549 switch (emulate_instruction(regs)) { 1550 case 0: 1551 regs->nip += 4; 1552 emulate_single_step(regs); 1553 goto bail; 1554 case -EFAULT: 1555 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1556 goto bail; 1557 } 1558 } 1559 1560 sigill: 1561 if (reason & REASON_PRIVILEGED) 1562 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 1563 else 1564 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1565 1566 bail: 1567 exception_exit(prev_state); 1568 } 1569 NOKPROBE_SYMBOL(program_check_exception); 1570 1571 /* 1572 * This occurs when running in hypervisor mode on POWER6 or later 1573 * and an illegal instruction is encountered. 1574 */ 1575 void emulation_assist_interrupt(struct pt_regs *regs) 1576 { 1577 regs->msr |= REASON_ILLEGAL; 1578 program_check_exception(regs); 1579 } 1580 NOKPROBE_SYMBOL(emulation_assist_interrupt); 1581 1582 void alignment_exception(struct pt_regs *regs) 1583 { 1584 enum ctx_state prev_state = exception_enter(); 1585 int sig, code, fixed = 0; 1586 1587 /* We restore the interrupt state now */ 1588 if (!arch_irq_disabled_regs(regs)) 1589 local_irq_enable(); 1590 1591 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT)) 1592 goto bail; 1593 1594 /* we don't implement logging of alignment exceptions */ 1595 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) 1596 fixed = fix_alignment(regs); 1597 1598 if (fixed == 1) { 1599 regs->nip += 4; /* skip over emulated instruction */ 1600 emulate_single_step(regs); 1601 goto bail; 1602 } 1603 1604 /* Operand address was bad */ 1605 if (fixed == -EFAULT) { 1606 sig = SIGSEGV; 1607 code = SEGV_ACCERR; 1608 } else { 1609 sig = SIGBUS; 1610 code = BUS_ADRALN; 1611 } 1612 if (user_mode(regs)) 1613 _exception(sig, regs, code, regs->dar); 1614 else 1615 bad_page_fault(regs, regs->dar, sig); 1616 1617 bail: 1618 exception_exit(prev_state); 1619 } 1620 1621 void StackOverflow(struct pt_regs *regs) 1622 { 1623 pr_crit("Kernel stack overflow in process %s[%d], r1=%lx\n", 1624 current->comm, task_pid_nr(current), regs->gpr[1]); 1625 debugger(regs); 1626 show_regs(regs); 1627 panic("kernel stack overflow"); 1628 } 1629 1630 void stack_overflow_exception(struct pt_regs *regs) 1631 { 1632 enum ctx_state prev_state = exception_enter(); 1633 1634 die("Kernel stack overflow", regs, SIGSEGV); 1635 1636 exception_exit(prev_state); 1637 } 1638 1639 void kernel_fp_unavailable_exception(struct pt_regs *regs) 1640 { 1641 enum ctx_state prev_state = exception_enter(); 1642 1643 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " 1644 "%lx at %lx\n", regs->trap, regs->nip); 1645 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); 1646 1647 exception_exit(prev_state); 1648 } 1649 1650 void altivec_unavailable_exception(struct pt_regs *regs) 1651 { 1652 enum ctx_state prev_state = exception_enter(); 1653 1654 if (user_mode(regs)) { 1655 /* A user program has executed an altivec instruction, 1656 but this kernel doesn't support altivec. */ 1657 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1658 goto bail; 1659 } 1660 1661 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " 1662 "%lx at %lx\n", regs->trap, regs->nip); 1663 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); 1664 1665 bail: 1666 exception_exit(prev_state); 1667 } 1668 1669 void vsx_unavailable_exception(struct pt_regs *regs) 1670 { 1671 if (user_mode(regs)) { 1672 /* A user program has executed an vsx instruction, 1673 but this kernel doesn't support vsx. */ 1674 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1675 return; 1676 } 1677 1678 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " 1679 "%lx at %lx\n", regs->trap, regs->nip); 1680 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); 1681 } 1682 1683 #ifdef CONFIG_PPC64 1684 static void tm_unavailable(struct pt_regs *regs) 1685 { 1686 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1687 if (user_mode(regs)) { 1688 current->thread.load_tm++; 1689 regs->msr |= MSR_TM; 1690 tm_enable(); 1691 tm_restore_sprs(¤t->thread); 1692 return; 1693 } 1694 #endif 1695 pr_emerg("Unrecoverable TM Unavailable Exception " 1696 "%lx at %lx\n", regs->trap, regs->nip); 1697 die("Unrecoverable TM Unavailable Exception", regs, SIGABRT); 1698 } 1699 1700 void facility_unavailable_exception(struct pt_regs *regs) 1701 { 1702 static char *facility_strings[] = { 1703 [FSCR_FP_LG] = "FPU", 1704 [FSCR_VECVSX_LG] = "VMX/VSX", 1705 [FSCR_DSCR_LG] = "DSCR", 1706 [FSCR_PM_LG] = "PMU SPRs", 1707 [FSCR_BHRB_LG] = "BHRB", 1708 [FSCR_TM_LG] = "TM", 1709 [FSCR_EBB_LG] = "EBB", 1710 [FSCR_TAR_LG] = "TAR", 1711 [FSCR_MSGP_LG] = "MSGP", 1712 [FSCR_SCV_LG] = "SCV", 1713 }; 1714 char *facility = "unknown"; 1715 u64 value; 1716 u32 instword, rd; 1717 u8 status; 1718 bool hv; 1719 1720 hv = (TRAP(regs) == 0xf80); 1721 if (hv) 1722 value = mfspr(SPRN_HFSCR); 1723 else 1724 value = mfspr(SPRN_FSCR); 1725 1726 status = value >> 56; 1727 if ((hv || status >= 2) && 1728 (status < ARRAY_SIZE(facility_strings)) && 1729 facility_strings[status]) 1730 facility = facility_strings[status]; 1731 1732 /* We should not have taken this interrupt in kernel */ 1733 if (!user_mode(regs)) { 1734 pr_emerg("Facility '%s' unavailable (%d) exception in kernel mode at %lx\n", 1735 facility, status, regs->nip); 1736 die("Unexpected facility unavailable exception", regs, SIGABRT); 1737 } 1738 1739 /* We restore the interrupt state now */ 1740 if (!arch_irq_disabled_regs(regs)) 1741 local_irq_enable(); 1742 1743 if (status == FSCR_DSCR_LG) { 1744 /* 1745 * User is accessing the DSCR register using the problem 1746 * state only SPR number (0x03) either through a mfspr or 1747 * a mtspr instruction. If it is a write attempt through 1748 * a mtspr, then we set the inherit bit. This also allows 1749 * the user to write or read the register directly in the 1750 * future by setting via the FSCR DSCR bit. But in case it 1751 * is a read DSCR attempt through a mfspr instruction, we 1752 * just emulate the instruction instead. This code path will 1753 * always emulate all the mfspr instructions till the user 1754 * has attempted at least one mtspr instruction. This way it 1755 * preserves the same behaviour when the user is accessing 1756 * the DSCR through privilege level only SPR number (0x11) 1757 * which is emulated through illegal instruction exception. 1758 * We always leave HFSCR DSCR set. 1759 */ 1760 if (get_user(instword, (u32 __user *)(regs->nip))) { 1761 pr_err("Failed to fetch the user instruction\n"); 1762 return; 1763 } 1764 1765 /* Write into DSCR (mtspr 0x03, RS) */ 1766 if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK) 1767 == PPC_INST_MTSPR_DSCR_USER) { 1768 rd = (instword >> 21) & 0x1f; 1769 current->thread.dscr = regs->gpr[rd]; 1770 current->thread.dscr_inherit = 1; 1771 current->thread.fscr |= FSCR_DSCR; 1772 mtspr(SPRN_FSCR, current->thread.fscr); 1773 } 1774 1775 /* Read from DSCR (mfspr RT, 0x03) */ 1776 if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK) 1777 == PPC_INST_MFSPR_DSCR_USER) { 1778 if (emulate_instruction(regs)) { 1779 pr_err("DSCR based mfspr emulation failed\n"); 1780 return; 1781 } 1782 regs->nip += 4; 1783 emulate_single_step(regs); 1784 } 1785 return; 1786 } 1787 1788 if (status == FSCR_TM_LG) { 1789 /* 1790 * If we're here then the hardware is TM aware because it 1791 * generated an exception with FSRM_TM set. 1792 * 1793 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware 1794 * told us not to do TM, or the kernel is not built with TM 1795 * support. 1796 * 1797 * If both of those things are true, then userspace can spam the 1798 * console by triggering the printk() below just by continually 1799 * doing tbegin (or any TM instruction). So in that case just 1800 * send the process a SIGILL immediately. 1801 */ 1802 if (!cpu_has_feature(CPU_FTR_TM)) 1803 goto out; 1804 1805 tm_unavailable(regs); 1806 return; 1807 } 1808 1809 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n", 1810 hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr); 1811 1812 out: 1813 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1814 } 1815 #endif 1816 1817 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1818 1819 void fp_unavailable_tm(struct pt_regs *regs) 1820 { 1821 /* Note: This does not handle any kind of FP laziness. */ 1822 1823 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n", 1824 regs->nip, regs->msr); 1825 1826 /* We can only have got here if the task started using FP after 1827 * beginning the transaction. So, the transactional regs are just a 1828 * copy of the checkpointed ones. But, we still need to recheckpoint 1829 * as we're enabling FP for the process; it will return, abort the 1830 * transaction, and probably retry but now with FP enabled. So the 1831 * checkpointed FP registers need to be loaded. 1832 */ 1833 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1834 1835 /* 1836 * Reclaim initially saved out bogus (lazy) FPRs to ckfp_state, and 1837 * then it was overwrite by the thr->fp_state by tm_reclaim_thread(). 1838 * 1839 * At this point, ck{fp,vr}_state contains the exact values we want to 1840 * recheckpoint. 1841 */ 1842 1843 /* Enable FP for the task: */ 1844 current->thread.load_fp = 1; 1845 1846 /* 1847 * Recheckpoint all the checkpointed ckpt, ck{fp, vr}_state registers. 1848 */ 1849 tm_recheckpoint(¤t->thread); 1850 } 1851 1852 void altivec_unavailable_tm(struct pt_regs *regs) 1853 { 1854 /* See the comments in fp_unavailable_tm(). This function operates 1855 * the same way. 1856 */ 1857 1858 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx," 1859 "MSR=%lx\n", 1860 regs->nip, regs->msr); 1861 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1862 current->thread.load_vec = 1; 1863 tm_recheckpoint(¤t->thread); 1864 current->thread.used_vr = 1; 1865 } 1866 1867 void vsx_unavailable_tm(struct pt_regs *regs) 1868 { 1869 /* See the comments in fp_unavailable_tm(). This works similarly, 1870 * though we're loading both FP and VEC registers in here. 1871 * 1872 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC 1873 * regs. Either way, set MSR_VSX. 1874 */ 1875 1876 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx," 1877 "MSR=%lx\n", 1878 regs->nip, regs->msr); 1879 1880 current->thread.used_vsr = 1; 1881 1882 /* This reclaims FP and/or VR regs if they're already enabled */ 1883 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1884 1885 current->thread.load_vec = 1; 1886 current->thread.load_fp = 1; 1887 1888 tm_recheckpoint(¤t->thread); 1889 } 1890 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1891 1892 void performance_monitor_exception(struct pt_regs *regs) 1893 { 1894 __this_cpu_inc(irq_stat.pmu_irqs); 1895 1896 perf_irq(regs); 1897 } 1898 1899 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1900 static void handle_debug(struct pt_regs *regs, unsigned long debug_status) 1901 { 1902 int changed = 0; 1903 /* 1904 * Determine the cause of the debug event, clear the 1905 * event flags and send a trap to the handler. Torez 1906 */ 1907 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { 1908 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); 1909 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1910 current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; 1911 #endif 1912 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, 1913 5); 1914 changed |= 0x01; 1915 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { 1916 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); 1917 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, 1918 6); 1919 changed |= 0x01; 1920 } else if (debug_status & DBSR_IAC1) { 1921 current->thread.debug.dbcr0 &= ~DBCR0_IAC1; 1922 dbcr_iac_range(current) &= ~DBCR_IAC12MODE; 1923 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, 1924 1); 1925 changed |= 0x01; 1926 } else if (debug_status & DBSR_IAC2) { 1927 current->thread.debug.dbcr0 &= ~DBCR0_IAC2; 1928 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, 1929 2); 1930 changed |= 0x01; 1931 } else if (debug_status & DBSR_IAC3) { 1932 current->thread.debug.dbcr0 &= ~DBCR0_IAC3; 1933 dbcr_iac_range(current) &= ~DBCR_IAC34MODE; 1934 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, 1935 3); 1936 changed |= 0x01; 1937 } else if (debug_status & DBSR_IAC4) { 1938 current->thread.debug.dbcr0 &= ~DBCR0_IAC4; 1939 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, 1940 4); 1941 changed |= 0x01; 1942 } 1943 /* 1944 * At the point this routine was called, the MSR(DE) was turned off. 1945 * Check all other debug flags and see if that bit needs to be turned 1946 * back on or not. 1947 */ 1948 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 1949 current->thread.debug.dbcr1)) 1950 regs->msr |= MSR_DE; 1951 else 1952 /* Make sure the IDM flag is off */ 1953 current->thread.debug.dbcr0 &= ~DBCR0_IDM; 1954 1955 if (changed & 0x01) 1956 mtspr(SPRN_DBCR0, current->thread.debug.dbcr0); 1957 } 1958 1959 void DebugException(struct pt_regs *regs, unsigned long debug_status) 1960 { 1961 current->thread.debug.dbsr = debug_status; 1962 1963 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while 1964 * on server, it stops on the target of the branch. In order to simulate 1965 * the server behaviour, we thus restart right away with a single step 1966 * instead of stopping here when hitting a BT 1967 */ 1968 if (debug_status & DBSR_BT) { 1969 regs->msr &= ~MSR_DE; 1970 1971 /* Disable BT */ 1972 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); 1973 /* Clear the BT event */ 1974 mtspr(SPRN_DBSR, DBSR_BT); 1975 1976 /* Do the single step trick only when coming from userspace */ 1977 if (user_mode(regs)) { 1978 current->thread.debug.dbcr0 &= ~DBCR0_BT; 1979 current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; 1980 regs->msr |= MSR_DE; 1981 return; 1982 } 1983 1984 if (kprobe_post_handler(regs)) 1985 return; 1986 1987 if (notify_die(DIE_SSTEP, "block_step", regs, 5, 1988 5, SIGTRAP) == NOTIFY_STOP) { 1989 return; 1990 } 1991 if (debugger_sstep(regs)) 1992 return; 1993 } else if (debug_status & DBSR_IC) { /* Instruction complete */ 1994 regs->msr &= ~MSR_DE; 1995 1996 /* Disable instruction completion */ 1997 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); 1998 /* Clear the instruction completion event */ 1999 mtspr(SPRN_DBSR, DBSR_IC); 2000 2001 if (kprobe_post_handler(regs)) 2002 return; 2003 2004 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 2005 5, SIGTRAP) == NOTIFY_STOP) { 2006 return; 2007 } 2008 2009 if (debugger_sstep(regs)) 2010 return; 2011 2012 if (user_mode(regs)) { 2013 current->thread.debug.dbcr0 &= ~DBCR0_IC; 2014 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 2015 current->thread.debug.dbcr1)) 2016 regs->msr |= MSR_DE; 2017 else 2018 /* Make sure the IDM bit is off */ 2019 current->thread.debug.dbcr0 &= ~DBCR0_IDM; 2020 } 2021 2022 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 2023 } else 2024 handle_debug(regs, debug_status); 2025 } 2026 NOKPROBE_SYMBOL(DebugException); 2027 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 2028 2029 #if !defined(CONFIG_TAU_INT) 2030 void TAUException(struct pt_regs *regs) 2031 { 2032 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", 2033 regs->nip, regs->msr, regs->trap, print_tainted()); 2034 } 2035 #endif /* CONFIG_INT_TAU */ 2036 2037 #ifdef CONFIG_ALTIVEC 2038 void altivec_assist_exception(struct pt_regs *regs) 2039 { 2040 int err; 2041 2042 if (!user_mode(regs)) { 2043 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" 2044 " at %lx\n", regs->nip); 2045 die("Kernel VMX/Altivec assist exception", regs, SIGILL); 2046 } 2047 2048 flush_altivec_to_thread(current); 2049 2050 PPC_WARN_EMULATED(altivec, regs); 2051 err = emulate_altivec(regs); 2052 if (err == 0) { 2053 regs->nip += 4; /* skip emulated instruction */ 2054 emulate_single_step(regs); 2055 return; 2056 } 2057 2058 if (err == -EFAULT) { 2059 /* got an error reading the instruction */ 2060 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2061 } else { 2062 /* didn't recognize the instruction */ 2063 /* XXX quick hack for now: set the non-Java bit in the VSCR */ 2064 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " 2065 "in %s at %lx\n", current->comm, regs->nip); 2066 current->thread.vr_state.vscr.u[3] |= 0x10000; 2067 } 2068 } 2069 #endif /* CONFIG_ALTIVEC */ 2070 2071 #ifdef CONFIG_FSL_BOOKE 2072 void CacheLockingException(struct pt_regs *regs, unsigned long address, 2073 unsigned long error_code) 2074 { 2075 /* We treat cache locking instructions from the user 2076 * as priv ops, in the future we could try to do 2077 * something smarter 2078 */ 2079 if (error_code & (ESR_DLK|ESR_ILK)) 2080 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 2081 return; 2082 } 2083 #endif /* CONFIG_FSL_BOOKE */ 2084 2085 #ifdef CONFIG_SPE 2086 void SPEFloatingPointException(struct pt_regs *regs) 2087 { 2088 extern int do_spe_mathemu(struct pt_regs *regs); 2089 unsigned long spefscr; 2090 int fpexc_mode; 2091 int code = FPE_FLTUNK; 2092 int err; 2093 2094 /* We restore the interrupt state now */ 2095 if (!arch_irq_disabled_regs(regs)) 2096 local_irq_enable(); 2097 2098 flush_spe_to_thread(current); 2099 2100 spefscr = current->thread.spefscr; 2101 fpexc_mode = current->thread.fpexc_mode; 2102 2103 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { 2104 code = FPE_FLTOVF; 2105 } 2106 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { 2107 code = FPE_FLTUND; 2108 } 2109 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) 2110 code = FPE_FLTDIV; 2111 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { 2112 code = FPE_FLTINV; 2113 } 2114 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) 2115 code = FPE_FLTRES; 2116 2117 err = do_spe_mathemu(regs); 2118 if (err == 0) { 2119 regs->nip += 4; /* skip emulated instruction */ 2120 emulate_single_step(regs); 2121 return; 2122 } 2123 2124 if (err == -EFAULT) { 2125 /* got an error reading the instruction */ 2126 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2127 } else if (err == -EINVAL) { 2128 /* didn't recognize the instruction */ 2129 printk(KERN_ERR "unrecognized spe instruction " 2130 "in %s at %lx\n", current->comm, regs->nip); 2131 } else { 2132 _exception(SIGFPE, regs, code, regs->nip); 2133 } 2134 2135 return; 2136 } 2137 2138 void SPEFloatingPointRoundException(struct pt_regs *regs) 2139 { 2140 extern int speround_handler(struct pt_regs *regs); 2141 int err; 2142 2143 /* We restore the interrupt state now */ 2144 if (!arch_irq_disabled_regs(regs)) 2145 local_irq_enable(); 2146 2147 preempt_disable(); 2148 if (regs->msr & MSR_SPE) 2149 giveup_spe(current); 2150 preempt_enable(); 2151 2152 regs->nip -= 4; 2153 err = speround_handler(regs); 2154 if (err == 0) { 2155 regs->nip += 4; /* skip emulated instruction */ 2156 emulate_single_step(regs); 2157 return; 2158 } 2159 2160 if (err == -EFAULT) { 2161 /* got an error reading the instruction */ 2162 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2163 } else if (err == -EINVAL) { 2164 /* didn't recognize the instruction */ 2165 printk(KERN_ERR "unrecognized spe instruction " 2166 "in %s at %lx\n", current->comm, regs->nip); 2167 } else { 2168 _exception(SIGFPE, regs, FPE_FLTUNK, regs->nip); 2169 return; 2170 } 2171 } 2172 #endif 2173 2174 /* 2175 * We enter here if we get an unrecoverable exception, that is, one 2176 * that happened at a point where the RI (recoverable interrupt) bit 2177 * in the MSR is 0. This indicates that SRR0/1 are live, and that 2178 * we therefore lost state by taking this exception. 2179 */ 2180 void unrecoverable_exception(struct pt_regs *regs) 2181 { 2182 pr_emerg("Unrecoverable exception %lx at %lx (msr=%lx)\n", 2183 regs->trap, regs->nip, regs->msr); 2184 die("Unrecoverable exception", regs, SIGABRT); 2185 } 2186 NOKPROBE_SYMBOL(unrecoverable_exception); 2187 2188 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x) 2189 /* 2190 * Default handler for a Watchdog exception, 2191 * spins until a reboot occurs 2192 */ 2193 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) 2194 { 2195 /* Generic WatchdogHandler, implement your own */ 2196 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); 2197 return; 2198 } 2199 2200 void WatchdogException(struct pt_regs *regs) 2201 { 2202 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); 2203 WatchdogHandler(regs); 2204 } 2205 #endif 2206 2207 /* 2208 * We enter here if we discover during exception entry that we are 2209 * running in supervisor mode with a userspace value in the stack pointer. 2210 */ 2211 void kernel_bad_stack(struct pt_regs *regs) 2212 { 2213 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", 2214 regs->gpr[1], regs->nip); 2215 die("Bad kernel stack pointer", regs, SIGABRT); 2216 } 2217 NOKPROBE_SYMBOL(kernel_bad_stack); 2218 2219 void __init trap_init(void) 2220 { 2221 } 2222 2223 2224 #ifdef CONFIG_PPC_EMULATED_STATS 2225 2226 #define WARN_EMULATED_SETUP(type) .type = { .name = #type } 2227 2228 struct ppc_emulated ppc_emulated = { 2229 #ifdef CONFIG_ALTIVEC 2230 WARN_EMULATED_SETUP(altivec), 2231 #endif 2232 WARN_EMULATED_SETUP(dcba), 2233 WARN_EMULATED_SETUP(dcbz), 2234 WARN_EMULATED_SETUP(fp_pair), 2235 WARN_EMULATED_SETUP(isel), 2236 WARN_EMULATED_SETUP(mcrxr), 2237 WARN_EMULATED_SETUP(mfpvr), 2238 WARN_EMULATED_SETUP(multiple), 2239 WARN_EMULATED_SETUP(popcntb), 2240 WARN_EMULATED_SETUP(spe), 2241 WARN_EMULATED_SETUP(string), 2242 WARN_EMULATED_SETUP(sync), 2243 WARN_EMULATED_SETUP(unaligned), 2244 #ifdef CONFIG_MATH_EMULATION 2245 WARN_EMULATED_SETUP(math), 2246 #endif 2247 #ifdef CONFIG_VSX 2248 WARN_EMULATED_SETUP(vsx), 2249 #endif 2250 #ifdef CONFIG_PPC64 2251 WARN_EMULATED_SETUP(mfdscr), 2252 WARN_EMULATED_SETUP(mtdscr), 2253 WARN_EMULATED_SETUP(lq_stq), 2254 WARN_EMULATED_SETUP(lxvw4x), 2255 WARN_EMULATED_SETUP(lxvh8x), 2256 WARN_EMULATED_SETUP(lxvd2x), 2257 WARN_EMULATED_SETUP(lxvb16x), 2258 #endif 2259 }; 2260 2261 u32 ppc_warn_emulated; 2262 2263 void ppc_warn_emulated_print(const char *type) 2264 { 2265 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, 2266 type); 2267 } 2268 2269 static int __init ppc_warn_emulated_init(void) 2270 { 2271 struct dentry *dir; 2272 unsigned int i; 2273 struct ppc_emulated_entry *entries = (void *)&ppc_emulated; 2274 2275 dir = debugfs_create_dir("emulated_instructions", 2276 powerpc_debugfs_root); 2277 2278 debugfs_create_u32("do_warn", 0644, dir, &ppc_warn_emulated); 2279 2280 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) 2281 debugfs_create_u32(entries[i].name, 0644, dir, 2282 (u32 *)&entries[i].val.counter); 2283 2284 return 0; 2285 } 2286 2287 device_initcall(ppc_warn_emulated_init); 2288 2289 #endif /* CONFIG_PPC_EMULATED_STATS */ 2290