1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * Copyright 2007-2010 Freescale Semiconductor, Inc. 5 * 6 * Modified by Cort Dougan (cort@cs.nmt.edu) 7 * and Paul Mackerras (paulus@samba.org) 8 */ 9 10 /* 11 * This file handles the architecture-dependent parts of hardware exceptions 12 */ 13 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/sched/debug.h> 17 #include <linux/kernel.h> 18 #include <linux/mm.h> 19 #include <linux/pkeys.h> 20 #include <linux/stddef.h> 21 #include <linux/unistd.h> 22 #include <linux/ptrace.h> 23 #include <linux/user.h> 24 #include <linux/interrupt.h> 25 #include <linux/init.h> 26 #include <linux/extable.h> 27 #include <linux/module.h> /* print_modules */ 28 #include <linux/prctl.h> 29 #include <linux/delay.h> 30 #include <linux/kprobes.h> 31 #include <linux/kexec.h> 32 #include <linux/backlight.h> 33 #include <linux/bug.h> 34 #include <linux/kdebug.h> 35 #include <linux/ratelimit.h> 36 #include <linux/context_tracking.h> 37 #include <linux/smp.h> 38 #include <linux/console.h> 39 #include <linux/kmsg_dump.h> 40 41 #include <asm/emulated_ops.h> 42 #include <linux/uaccess.h> 43 #include <asm/debugfs.h> 44 #include <asm/interrupt.h> 45 #include <asm/io.h> 46 #include <asm/machdep.h> 47 #include <asm/rtas.h> 48 #include <asm/pmc.h> 49 #include <asm/reg.h> 50 #ifdef CONFIG_PMAC_BACKLIGHT 51 #include <asm/backlight.h> 52 #endif 53 #ifdef CONFIG_PPC64 54 #include <asm/firmware.h> 55 #include <asm/processor.h> 56 #endif 57 #include <asm/kexec.h> 58 #include <asm/ppc-opcode.h> 59 #include <asm/rio.h> 60 #include <asm/fadump.h> 61 #include <asm/switch_to.h> 62 #include <asm/tm.h> 63 #include <asm/debug.h> 64 #include <asm/asm-prototypes.h> 65 #include <asm/hmi.h> 66 #include <sysdev/fsl_pci.h> 67 #include <asm/kprobes.h> 68 #include <asm/stacktrace.h> 69 #include <asm/nmi.h> 70 #include <asm/disassemble.h> 71 72 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE) 73 int (*__debugger)(struct pt_regs *regs) __read_mostly; 74 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; 75 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; 76 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; 77 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; 78 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly; 79 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; 80 81 EXPORT_SYMBOL(__debugger); 82 EXPORT_SYMBOL(__debugger_ipi); 83 EXPORT_SYMBOL(__debugger_bpt); 84 EXPORT_SYMBOL(__debugger_sstep); 85 EXPORT_SYMBOL(__debugger_iabr_match); 86 EXPORT_SYMBOL(__debugger_break_match); 87 EXPORT_SYMBOL(__debugger_fault_handler); 88 #endif 89 90 /* Transactional Memory trap debug */ 91 #ifdef TM_DEBUG_SW 92 #define TM_DEBUG(x...) printk(KERN_INFO x) 93 #else 94 #define TM_DEBUG(x...) do { } while(0) 95 #endif 96 97 static const char *signame(int signr) 98 { 99 switch (signr) { 100 case SIGBUS: return "bus error"; 101 case SIGFPE: return "floating point exception"; 102 case SIGILL: return "illegal instruction"; 103 case SIGSEGV: return "segfault"; 104 case SIGTRAP: return "unhandled trap"; 105 } 106 107 return "unknown signal"; 108 } 109 110 /* 111 * Trap & Exception support 112 */ 113 114 #ifdef CONFIG_PMAC_BACKLIGHT 115 static void pmac_backlight_unblank(void) 116 { 117 mutex_lock(&pmac_backlight_mutex); 118 if (pmac_backlight) { 119 struct backlight_properties *props; 120 121 props = &pmac_backlight->props; 122 props->brightness = props->max_brightness; 123 props->power = FB_BLANK_UNBLANK; 124 backlight_update_status(pmac_backlight); 125 } 126 mutex_unlock(&pmac_backlight_mutex); 127 } 128 #else 129 static inline void pmac_backlight_unblank(void) { } 130 #endif 131 132 /* 133 * If oops/die is expected to crash the machine, return true here. 134 * 135 * This should not be expected to be 100% accurate, there may be 136 * notifiers registered or other unexpected conditions that may bring 137 * down the kernel. Or if the current process in the kernel is holding 138 * locks or has other critical state, the kernel may become effectively 139 * unusable anyway. 140 */ 141 bool die_will_crash(void) 142 { 143 if (should_fadump_crash()) 144 return true; 145 if (kexec_should_crash(current)) 146 return true; 147 if (in_interrupt() || panic_on_oops || 148 !current->pid || is_global_init(current)) 149 return true; 150 151 return false; 152 } 153 154 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; 155 static int die_owner = -1; 156 static unsigned int die_nest_count; 157 static int die_counter; 158 159 extern void panic_flush_kmsg_start(void) 160 { 161 /* 162 * These are mostly taken from kernel/panic.c, but tries to do 163 * relatively minimal work. Don't use delay functions (TB may 164 * be broken), don't crash dump (need to set a firmware log), 165 * don't run notifiers. We do want to get some information to 166 * Linux console. 167 */ 168 console_verbose(); 169 bust_spinlocks(1); 170 } 171 172 extern void panic_flush_kmsg_end(void) 173 { 174 printk_safe_flush_on_panic(); 175 kmsg_dump(KMSG_DUMP_PANIC); 176 bust_spinlocks(0); 177 debug_locks_off(); 178 console_flush_on_panic(CONSOLE_FLUSH_PENDING); 179 } 180 181 static unsigned long oops_begin(struct pt_regs *regs) 182 { 183 int cpu; 184 unsigned long flags; 185 186 oops_enter(); 187 188 /* racy, but better than risking deadlock. */ 189 raw_local_irq_save(flags); 190 cpu = smp_processor_id(); 191 if (!arch_spin_trylock(&die_lock)) { 192 if (cpu == die_owner) 193 /* nested oops. should stop eventually */; 194 else 195 arch_spin_lock(&die_lock); 196 } 197 die_nest_count++; 198 die_owner = cpu; 199 console_verbose(); 200 bust_spinlocks(1); 201 if (machine_is(powermac)) 202 pmac_backlight_unblank(); 203 return flags; 204 } 205 NOKPROBE_SYMBOL(oops_begin); 206 207 static void oops_end(unsigned long flags, struct pt_regs *regs, 208 int signr) 209 { 210 bust_spinlocks(0); 211 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 212 die_nest_count--; 213 oops_exit(); 214 printk("\n"); 215 if (!die_nest_count) { 216 /* Nest count reaches zero, release the lock. */ 217 die_owner = -1; 218 arch_spin_unlock(&die_lock); 219 } 220 raw_local_irq_restore(flags); 221 222 /* 223 * system_reset_excption handles debugger, crash dump, panic, for 0x100 224 */ 225 if (TRAP(regs) == INTERRUPT_SYSTEM_RESET) 226 return; 227 228 crash_fadump(regs, "die oops"); 229 230 if (kexec_should_crash(current)) 231 crash_kexec(regs); 232 233 if (!signr) 234 return; 235 236 /* 237 * While our oops output is serialised by a spinlock, output 238 * from panic() called below can race and corrupt it. If we 239 * know we are going to panic, delay for 1 second so we have a 240 * chance to get clean backtraces from all CPUs that are oopsing. 241 */ 242 if (in_interrupt() || panic_on_oops || !current->pid || 243 is_global_init(current)) { 244 mdelay(MSEC_PER_SEC); 245 } 246 247 if (panic_on_oops) 248 panic("Fatal exception"); 249 do_exit(signr); 250 } 251 NOKPROBE_SYMBOL(oops_end); 252 253 static char *get_mmu_str(void) 254 { 255 if (early_radix_enabled()) 256 return " MMU=Radix"; 257 if (early_mmu_has_feature(MMU_FTR_HPTE_TABLE)) 258 return " MMU=Hash"; 259 return ""; 260 } 261 262 static int __die(const char *str, struct pt_regs *regs, long err) 263 { 264 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); 265 266 printk("%s PAGE_SIZE=%luK%s%s%s%s%s%s %s\n", 267 IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN) ? "LE" : "BE", 268 PAGE_SIZE / 1024, get_mmu_str(), 269 IS_ENABLED(CONFIG_PREEMPT) ? " PREEMPT" : "", 270 IS_ENABLED(CONFIG_SMP) ? " SMP" : "", 271 IS_ENABLED(CONFIG_SMP) ? (" NR_CPUS=" __stringify(NR_CPUS)) : "", 272 debug_pagealloc_enabled() ? " DEBUG_PAGEALLOC" : "", 273 IS_ENABLED(CONFIG_NUMA) ? " NUMA" : "", 274 ppc_md.name ? ppc_md.name : ""); 275 276 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP) 277 return 1; 278 279 print_modules(); 280 show_regs(regs); 281 282 return 0; 283 } 284 NOKPROBE_SYMBOL(__die); 285 286 void die(const char *str, struct pt_regs *regs, long err) 287 { 288 unsigned long flags; 289 290 /* 291 * system_reset_excption handles debugger, crash dump, panic, for 0x100 292 */ 293 if (TRAP(regs) != INTERRUPT_SYSTEM_RESET) { 294 if (debugger(regs)) 295 return; 296 } 297 298 flags = oops_begin(regs); 299 if (__die(str, regs, err)) 300 err = 0; 301 oops_end(flags, regs, err); 302 } 303 NOKPROBE_SYMBOL(die); 304 305 void user_single_step_report(struct pt_regs *regs) 306 { 307 force_sig_fault(SIGTRAP, TRAP_TRACE, (void __user *)regs->nip); 308 } 309 310 static void show_signal_msg(int signr, struct pt_regs *regs, int code, 311 unsigned long addr) 312 { 313 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, 314 DEFAULT_RATELIMIT_BURST); 315 316 if (!show_unhandled_signals) 317 return; 318 319 if (!unhandled_signal(current, signr)) 320 return; 321 322 if (!__ratelimit(&rs)) 323 return; 324 325 pr_info("%s[%d]: %s (%d) at %lx nip %lx lr %lx code %x", 326 current->comm, current->pid, signame(signr), signr, 327 addr, regs->nip, regs->link, code); 328 329 print_vma_addr(KERN_CONT " in ", regs->nip); 330 331 pr_cont("\n"); 332 333 show_user_instructions(regs); 334 } 335 336 static bool exception_common(int signr, struct pt_regs *regs, int code, 337 unsigned long addr) 338 { 339 if (!user_mode(regs)) { 340 die("Exception in kernel mode", regs, signr); 341 return false; 342 } 343 344 show_signal_msg(signr, regs, code, addr); 345 346 if (arch_irqs_disabled()) 347 interrupt_cond_local_irq_enable(regs); 348 349 current->thread.trap_nr = code; 350 351 return true; 352 } 353 354 void _exception_pkey(struct pt_regs *regs, unsigned long addr, int key) 355 { 356 if (!exception_common(SIGSEGV, regs, SEGV_PKUERR, addr)) 357 return; 358 359 force_sig_pkuerr((void __user *) addr, key); 360 } 361 362 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) 363 { 364 if (!exception_common(signr, regs, code, addr)) 365 return; 366 367 force_sig_fault(signr, code, (void __user *)addr); 368 } 369 370 /* 371 * The interrupt architecture has a quirk in that the HV interrupts excluding 372 * the NMIs (0x100 and 0x200) do not clear MSR[RI] at entry. The first thing 373 * that an interrupt handler must do is save off a GPR into a scratch register, 374 * and all interrupts on POWERNV (HV=1) use the HSPRG1 register as scratch. 375 * Therefore an NMI can clobber an HV interrupt's live HSPRG1 without noticing 376 * that it is non-reentrant, which leads to random data corruption. 377 * 378 * The solution is for NMI interrupts in HV mode to check if they originated 379 * from these critical HV interrupt regions. If so, then mark them not 380 * recoverable. 381 * 382 * An alternative would be for HV NMIs to use SPRG for scratch to avoid the 383 * HSPRG1 clobber, however this would cause guest SPRG to be clobbered. Linux 384 * guests should always have MSR[RI]=0 when its scratch SPRG is in use, so 385 * that would work. However any other guest OS that may have the SPRG live 386 * and MSR[RI]=1 could encounter silent corruption. 387 * 388 * Builds that do not support KVM could take this second option to increase 389 * the recoverability of NMIs. 390 */ 391 void hv_nmi_check_nonrecoverable(struct pt_regs *regs) 392 { 393 #ifdef CONFIG_PPC_POWERNV 394 unsigned long kbase = (unsigned long)_stext; 395 unsigned long nip = regs->nip; 396 397 if (!(regs->msr & MSR_RI)) 398 return; 399 if (!(regs->msr & MSR_HV)) 400 return; 401 if (regs->msr & MSR_PR) 402 return; 403 404 /* 405 * Now test if the interrupt has hit a range that may be using 406 * HSPRG1 without having RI=0 (i.e., an HSRR interrupt). The 407 * problem ranges all run un-relocated. Test real and virt modes 408 * at the same time by dropping the high bit of the nip (virt mode 409 * entry points still have the +0x4000 offset). 410 */ 411 nip &= ~0xc000000000000000ULL; 412 if ((nip >= 0x500 && nip < 0x600) || (nip >= 0x4500 && nip < 0x4600)) 413 goto nonrecoverable; 414 if ((nip >= 0x980 && nip < 0xa00) || (nip >= 0x4980 && nip < 0x4a00)) 415 goto nonrecoverable; 416 if ((nip >= 0xe00 && nip < 0xec0) || (nip >= 0x4e00 && nip < 0x4ec0)) 417 goto nonrecoverable; 418 if ((nip >= 0xf80 && nip < 0xfa0) || (nip >= 0x4f80 && nip < 0x4fa0)) 419 goto nonrecoverable; 420 421 /* Trampoline code runs un-relocated so subtract kbase. */ 422 if (nip >= (unsigned long)(start_real_trampolines - kbase) && 423 nip < (unsigned long)(end_real_trampolines - kbase)) 424 goto nonrecoverable; 425 if (nip >= (unsigned long)(start_virt_trampolines - kbase) && 426 nip < (unsigned long)(end_virt_trampolines - kbase)) 427 goto nonrecoverable; 428 return; 429 430 nonrecoverable: 431 regs_set_return_msr(regs, regs->msr & ~MSR_RI); 432 #endif 433 } 434 DEFINE_INTERRUPT_HANDLER_NMI(system_reset_exception) 435 { 436 unsigned long hsrr0, hsrr1; 437 bool saved_hsrrs = false; 438 439 /* 440 * System reset can interrupt code where HSRRs are live and MSR[RI]=1. 441 * The system reset interrupt itself may clobber HSRRs (e.g., to call 442 * OPAL), so save them here and restore them before returning. 443 * 444 * Machine checks don't need to save HSRRs, as the real mode handler 445 * is careful to avoid them, and the regular handler is not delivered 446 * as an NMI. 447 */ 448 if (cpu_has_feature(CPU_FTR_HVMODE)) { 449 hsrr0 = mfspr(SPRN_HSRR0); 450 hsrr1 = mfspr(SPRN_HSRR1); 451 saved_hsrrs = true; 452 } 453 454 hv_nmi_check_nonrecoverable(regs); 455 456 __this_cpu_inc(irq_stat.sreset_irqs); 457 458 /* See if any machine dependent calls */ 459 if (ppc_md.system_reset_exception) { 460 if (ppc_md.system_reset_exception(regs)) 461 goto out; 462 } 463 464 if (debugger(regs)) 465 goto out; 466 467 kmsg_dump(KMSG_DUMP_OOPS); 468 /* 469 * A system reset is a request to dump, so we always send 470 * it through the crashdump code (if fadump or kdump are 471 * registered). 472 */ 473 crash_fadump(regs, "System Reset"); 474 475 crash_kexec(regs); 476 477 /* 478 * We aren't the primary crash CPU. We need to send it 479 * to a holding pattern to avoid it ending up in the panic 480 * code. 481 */ 482 crash_kexec_secondary(regs); 483 484 /* 485 * No debugger or crash dump registered, print logs then 486 * panic. 487 */ 488 die("System Reset", regs, SIGABRT); 489 490 mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */ 491 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 492 nmi_panic(regs, "System Reset"); 493 494 out: 495 #ifdef CONFIG_PPC_BOOK3S_64 496 BUG_ON(get_paca()->in_nmi == 0); 497 if (get_paca()->in_nmi > 1) 498 die("Unrecoverable nested System Reset", regs, SIGABRT); 499 #endif 500 /* Must die if the interrupt is not recoverable */ 501 if (!(regs->msr & MSR_RI)) { 502 /* For the reason explained in die_mce, nmi_exit before die */ 503 nmi_exit(); 504 die("Unrecoverable System Reset", regs, SIGABRT); 505 } 506 507 if (saved_hsrrs) { 508 mtspr(SPRN_HSRR0, hsrr0); 509 mtspr(SPRN_HSRR1, hsrr1); 510 } 511 512 /* What should we do here? We could issue a shutdown or hard reset. */ 513 514 return 0; 515 } 516 517 /* 518 * I/O accesses can cause machine checks on powermacs. 519 * Check if the NIP corresponds to the address of a sync 520 * instruction for which there is an entry in the exception 521 * table. 522 * -- paulus. 523 */ 524 static inline int check_io_access(struct pt_regs *regs) 525 { 526 #ifdef CONFIG_PPC32 527 unsigned long msr = regs->msr; 528 const struct exception_table_entry *entry; 529 unsigned int *nip = (unsigned int *)regs->nip; 530 531 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) 532 && (entry = search_exception_tables(regs->nip)) != NULL) { 533 /* 534 * Check that it's a sync instruction, or somewhere 535 * in the twi; isync; nop sequence that inb/inw/inl uses. 536 * As the address is in the exception table 537 * we should be able to read the instr there. 538 * For the debug message, we look at the preceding 539 * load or store. 540 */ 541 if (*nip == PPC_RAW_NOP()) 542 nip -= 2; 543 else if (*nip == PPC_RAW_ISYNC()) 544 --nip; 545 if (*nip == PPC_RAW_SYNC() || get_op(*nip) == OP_TRAP) { 546 unsigned int rb; 547 548 --nip; 549 rb = (*nip >> 11) & 0x1f; 550 printk(KERN_DEBUG "%s bad port %lx at %p\n", 551 (*nip & 0x100)? "OUT to": "IN from", 552 regs->gpr[rb] - _IO_BASE, nip); 553 regs_set_return_msr(regs, regs->msr | MSR_RI); 554 regs_set_return_ip(regs, extable_fixup(entry)); 555 return 1; 556 } 557 } 558 #endif /* CONFIG_PPC32 */ 559 return 0; 560 } 561 562 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 563 /* On 4xx, the reason for the machine check or program exception 564 is in the ESR. */ 565 #define get_reason(regs) ((regs)->dsisr) 566 #define REASON_FP ESR_FP 567 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) 568 #define REASON_PRIVILEGED ESR_PPR 569 #define REASON_TRAP ESR_PTR 570 #define REASON_PREFIXED 0 571 #define REASON_BOUNDARY 0 572 573 /* single-step stuff */ 574 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC) 575 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC) 576 #define clear_br_trace(regs) do {} while(0) 577 #else 578 /* On non-4xx, the reason for the machine check or program 579 exception is in the MSR. */ 580 #define get_reason(regs) ((regs)->msr) 581 #define REASON_TM SRR1_PROGTM 582 #define REASON_FP SRR1_PROGFPE 583 #define REASON_ILLEGAL SRR1_PROGILL 584 #define REASON_PRIVILEGED SRR1_PROGPRIV 585 #define REASON_TRAP SRR1_PROGTRAP 586 #define REASON_PREFIXED SRR1_PREFIXED 587 #define REASON_BOUNDARY SRR1_BOUNDARY 588 589 #define single_stepping(regs) ((regs)->msr & MSR_SE) 590 #define clear_single_step(regs) (regs_set_return_msr((regs), (regs)->msr & ~MSR_SE)) 591 #define clear_br_trace(regs) (regs_set_return_msr((regs), (regs)->msr & ~MSR_BE)) 592 #endif 593 594 #define inst_length(reason) (((reason) & REASON_PREFIXED) ? 8 : 4) 595 596 #if defined(CONFIG_E500) 597 int machine_check_e500mc(struct pt_regs *regs) 598 { 599 unsigned long mcsr = mfspr(SPRN_MCSR); 600 unsigned long pvr = mfspr(SPRN_PVR); 601 unsigned long reason = mcsr; 602 int recoverable = 1; 603 604 if (reason & MCSR_LD) { 605 recoverable = fsl_rio_mcheck_exception(regs); 606 if (recoverable == 1) 607 goto silent_out; 608 } 609 610 printk("Machine check in kernel mode.\n"); 611 printk("Caused by (from MCSR=%lx): ", reason); 612 613 if (reason & MCSR_MCP) 614 pr_cont("Machine Check Signal\n"); 615 616 if (reason & MCSR_ICPERR) { 617 pr_cont("Instruction Cache Parity Error\n"); 618 619 /* 620 * This is recoverable by invalidating the i-cache. 621 */ 622 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); 623 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) 624 ; 625 626 /* 627 * This will generally be accompanied by an instruction 628 * fetch error report -- only treat MCSR_IF as fatal 629 * if it wasn't due to an L1 parity error. 630 */ 631 reason &= ~MCSR_IF; 632 } 633 634 if (reason & MCSR_DCPERR_MC) { 635 pr_cont("Data Cache Parity Error\n"); 636 637 /* 638 * In write shadow mode we auto-recover from the error, but it 639 * may still get logged and cause a machine check. We should 640 * only treat the non-write shadow case as non-recoverable. 641 */ 642 /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit 643 * is not implemented but L1 data cache always runs in write 644 * shadow mode. Hence on data cache parity errors HW will 645 * automatically invalidate the L1 Data Cache. 646 */ 647 if (PVR_VER(pvr) != PVR_VER_E6500) { 648 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) 649 recoverable = 0; 650 } 651 } 652 653 if (reason & MCSR_L2MMU_MHIT) { 654 pr_cont("Hit on multiple TLB entries\n"); 655 recoverable = 0; 656 } 657 658 if (reason & MCSR_NMI) 659 pr_cont("Non-maskable interrupt\n"); 660 661 if (reason & MCSR_IF) { 662 pr_cont("Instruction Fetch Error Report\n"); 663 recoverable = 0; 664 } 665 666 if (reason & MCSR_LD) { 667 pr_cont("Load Error Report\n"); 668 recoverable = 0; 669 } 670 671 if (reason & MCSR_ST) { 672 pr_cont("Store Error Report\n"); 673 recoverable = 0; 674 } 675 676 if (reason & MCSR_LDG) { 677 pr_cont("Guarded Load Error Report\n"); 678 recoverable = 0; 679 } 680 681 if (reason & MCSR_TLBSYNC) 682 pr_cont("Simultaneous tlbsync operations\n"); 683 684 if (reason & MCSR_BSL2_ERR) { 685 pr_cont("Level 2 Cache Error\n"); 686 recoverable = 0; 687 } 688 689 if (reason & MCSR_MAV) { 690 u64 addr; 691 692 addr = mfspr(SPRN_MCAR); 693 addr |= (u64)mfspr(SPRN_MCARU) << 32; 694 695 pr_cont("Machine Check %s Address: %#llx\n", 696 reason & MCSR_MEA ? "Effective" : "Physical", addr); 697 } 698 699 silent_out: 700 mtspr(SPRN_MCSR, mcsr); 701 return mfspr(SPRN_MCSR) == 0 && recoverable; 702 } 703 704 int machine_check_e500(struct pt_regs *regs) 705 { 706 unsigned long reason = mfspr(SPRN_MCSR); 707 708 if (reason & MCSR_BUS_RBERR) { 709 if (fsl_rio_mcheck_exception(regs)) 710 return 1; 711 if (fsl_pci_mcheck_exception(regs)) 712 return 1; 713 } 714 715 printk("Machine check in kernel mode.\n"); 716 printk("Caused by (from MCSR=%lx): ", reason); 717 718 if (reason & MCSR_MCP) 719 pr_cont("Machine Check Signal\n"); 720 if (reason & MCSR_ICPERR) 721 pr_cont("Instruction Cache Parity Error\n"); 722 if (reason & MCSR_DCP_PERR) 723 pr_cont("Data Cache Push Parity Error\n"); 724 if (reason & MCSR_DCPERR) 725 pr_cont("Data Cache Parity Error\n"); 726 if (reason & MCSR_BUS_IAERR) 727 pr_cont("Bus - Instruction Address Error\n"); 728 if (reason & MCSR_BUS_RAERR) 729 pr_cont("Bus - Read Address Error\n"); 730 if (reason & MCSR_BUS_WAERR) 731 pr_cont("Bus - Write Address Error\n"); 732 if (reason & MCSR_BUS_IBERR) 733 pr_cont("Bus - Instruction Data Error\n"); 734 if (reason & MCSR_BUS_RBERR) 735 pr_cont("Bus - Read Data Bus Error\n"); 736 if (reason & MCSR_BUS_WBERR) 737 pr_cont("Bus - Write Data Bus Error\n"); 738 if (reason & MCSR_BUS_IPERR) 739 pr_cont("Bus - Instruction Parity Error\n"); 740 if (reason & MCSR_BUS_RPERR) 741 pr_cont("Bus - Read Parity Error\n"); 742 743 return 0; 744 } 745 746 int machine_check_generic(struct pt_regs *regs) 747 { 748 return 0; 749 } 750 #elif defined(CONFIG_PPC32) 751 int machine_check_generic(struct pt_regs *regs) 752 { 753 unsigned long reason = regs->msr; 754 755 printk("Machine check in kernel mode.\n"); 756 printk("Caused by (from SRR1=%lx): ", reason); 757 switch (reason & 0x601F0000) { 758 case 0x80000: 759 pr_cont("Machine check signal\n"); 760 break; 761 case 0x40000: 762 case 0x140000: /* 7450 MSS error and TEA */ 763 pr_cont("Transfer error ack signal\n"); 764 break; 765 case 0x20000: 766 pr_cont("Data parity error signal\n"); 767 break; 768 case 0x10000: 769 pr_cont("Address parity error signal\n"); 770 break; 771 case 0x20000000: 772 pr_cont("L1 Data Cache error\n"); 773 break; 774 case 0x40000000: 775 pr_cont("L1 Instruction Cache error\n"); 776 break; 777 case 0x00100000: 778 pr_cont("L2 data cache parity error\n"); 779 break; 780 default: 781 pr_cont("Unknown values in msr\n"); 782 } 783 return 0; 784 } 785 #endif /* everything else */ 786 787 void die_mce(const char *str, struct pt_regs *regs, long err) 788 { 789 /* 790 * The machine check wants to kill the interrupted context, but 791 * do_exit() checks for in_interrupt() and panics in that case, so 792 * exit the irq/nmi before calling die. 793 */ 794 if (IS_ENABLED(CONFIG_PPC_BOOK3S_64)) 795 irq_exit(); 796 else 797 nmi_exit(); 798 die(str, regs, err); 799 } 800 801 /* 802 * BOOK3S_64 does not call this handler as a non-maskable interrupt 803 * (it uses its own early real-mode handler to handle the MCE proper 804 * and then raises irq_work to call this handler when interrupts are 805 * enabled). 806 */ 807 #ifdef CONFIG_PPC_BOOK3S_64 808 DEFINE_INTERRUPT_HANDLER_ASYNC(machine_check_exception) 809 #else 810 DEFINE_INTERRUPT_HANDLER_NMI(machine_check_exception) 811 #endif 812 { 813 int recover = 0; 814 815 __this_cpu_inc(irq_stat.mce_exceptions); 816 817 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 818 819 /* See if any machine dependent calls. In theory, we would want 820 * to call the CPU first, and call the ppc_md. one if the CPU 821 * one returns a positive number. However there is existing code 822 * that assumes the board gets a first chance, so let's keep it 823 * that way for now and fix things later. --BenH. 824 */ 825 if (ppc_md.machine_check_exception) 826 recover = ppc_md.machine_check_exception(regs); 827 else if (cur_cpu_spec->machine_check) 828 recover = cur_cpu_spec->machine_check(regs); 829 830 if (recover > 0) 831 goto bail; 832 833 if (debugger_fault_handler(regs)) 834 goto bail; 835 836 if (check_io_access(regs)) 837 goto bail; 838 839 die_mce("Machine check", regs, SIGBUS); 840 841 bail: 842 /* Must die if the interrupt is not recoverable */ 843 if (!(regs->msr & MSR_RI)) 844 die_mce("Unrecoverable Machine check", regs, SIGBUS); 845 846 #ifdef CONFIG_PPC_BOOK3S_64 847 return; 848 #else 849 return 0; 850 #endif 851 } 852 853 DEFINE_INTERRUPT_HANDLER(SMIException) /* async? */ 854 { 855 die("System Management Interrupt", regs, SIGABRT); 856 } 857 858 #ifdef CONFIG_VSX 859 static void p9_hmi_special_emu(struct pt_regs *regs) 860 { 861 unsigned int ra, rb, t, i, sel, instr, rc; 862 const void __user *addr; 863 u8 vbuf[16] __aligned(16), *vdst; 864 unsigned long ea, msr, msr_mask; 865 bool swap; 866 867 if (__get_user(instr, (unsigned int __user *)regs->nip)) 868 return; 869 870 /* 871 * lxvb16x opcode: 0x7c0006d8 872 * lxvd2x opcode: 0x7c000698 873 * lxvh8x opcode: 0x7c000658 874 * lxvw4x opcode: 0x7c000618 875 */ 876 if ((instr & 0xfc00073e) != 0x7c000618) { 877 pr_devel("HMI vec emu: not vector CI %i:%s[%d] nip=%016lx" 878 " instr=%08x\n", 879 smp_processor_id(), current->comm, current->pid, 880 regs->nip, instr); 881 return; 882 } 883 884 /* Grab vector registers into the task struct */ 885 msr = regs->msr; /* Grab msr before we flush the bits */ 886 flush_vsx_to_thread(current); 887 enable_kernel_altivec(); 888 889 /* 890 * Is userspace running with a different endian (this is rare but 891 * not impossible) 892 */ 893 swap = (msr & MSR_LE) != (MSR_KERNEL & MSR_LE); 894 895 /* Decode the instruction */ 896 ra = (instr >> 16) & 0x1f; 897 rb = (instr >> 11) & 0x1f; 898 t = (instr >> 21) & 0x1f; 899 if (instr & 1) 900 vdst = (u8 *)¤t->thread.vr_state.vr[t]; 901 else 902 vdst = (u8 *)¤t->thread.fp_state.fpr[t][0]; 903 904 /* Grab the vector address */ 905 ea = regs->gpr[rb] + (ra ? regs->gpr[ra] : 0); 906 if (is_32bit_task()) 907 ea &= 0xfffffffful; 908 addr = (__force const void __user *)ea; 909 910 /* Check it */ 911 if (!access_ok(addr, 16)) { 912 pr_devel("HMI vec emu: bad access %i:%s[%d] nip=%016lx" 913 " instr=%08x addr=%016lx\n", 914 smp_processor_id(), current->comm, current->pid, 915 regs->nip, instr, (unsigned long)addr); 916 return; 917 } 918 919 /* Read the vector */ 920 rc = 0; 921 if ((unsigned long)addr & 0xfUL) 922 /* unaligned case */ 923 rc = __copy_from_user_inatomic(vbuf, addr, 16); 924 else 925 __get_user_atomic_128_aligned(vbuf, addr, rc); 926 if (rc) { 927 pr_devel("HMI vec emu: page fault %i:%s[%d] nip=%016lx" 928 " instr=%08x addr=%016lx\n", 929 smp_processor_id(), current->comm, current->pid, 930 regs->nip, instr, (unsigned long)addr); 931 return; 932 } 933 934 pr_devel("HMI vec emu: emulated vector CI %i:%s[%d] nip=%016lx" 935 " instr=%08x addr=%016lx\n", 936 smp_processor_id(), current->comm, current->pid, regs->nip, 937 instr, (unsigned long) addr); 938 939 /* Grab instruction "selector" */ 940 sel = (instr >> 6) & 3; 941 942 /* 943 * Check to make sure the facility is actually enabled. This 944 * could happen if we get a false positive hit. 945 * 946 * lxvd2x/lxvw4x always check MSR VSX sel = 0,2 947 * lxvh8x/lxvb16x check MSR VSX or VEC depending on VSR used sel = 1,3 948 */ 949 msr_mask = MSR_VSX; 950 if ((sel & 1) && (instr & 1)) /* lxvh8x & lxvb16x + VSR >= 32 */ 951 msr_mask = MSR_VEC; 952 if (!(msr & msr_mask)) { 953 pr_devel("HMI vec emu: MSR fac clear %i:%s[%d] nip=%016lx" 954 " instr=%08x msr:%016lx\n", 955 smp_processor_id(), current->comm, current->pid, 956 regs->nip, instr, msr); 957 return; 958 } 959 960 /* Do logging here before we modify sel based on endian */ 961 switch (sel) { 962 case 0: /* lxvw4x */ 963 PPC_WARN_EMULATED(lxvw4x, regs); 964 break; 965 case 1: /* lxvh8x */ 966 PPC_WARN_EMULATED(lxvh8x, regs); 967 break; 968 case 2: /* lxvd2x */ 969 PPC_WARN_EMULATED(lxvd2x, regs); 970 break; 971 case 3: /* lxvb16x */ 972 PPC_WARN_EMULATED(lxvb16x, regs); 973 break; 974 } 975 976 #ifdef __LITTLE_ENDIAN__ 977 /* 978 * An LE kernel stores the vector in the task struct as an LE 979 * byte array (effectively swapping both the components and 980 * the content of the components). Those instructions expect 981 * the components to remain in ascending address order, so we 982 * swap them back. 983 * 984 * If we are running a BE user space, the expectation is that 985 * of a simple memcpy, so forcing the emulation to look like 986 * a lxvb16x should do the trick. 987 */ 988 if (swap) 989 sel = 3; 990 991 switch (sel) { 992 case 0: /* lxvw4x */ 993 for (i = 0; i < 4; i++) 994 ((u32 *)vdst)[i] = ((u32 *)vbuf)[3-i]; 995 break; 996 case 1: /* lxvh8x */ 997 for (i = 0; i < 8; i++) 998 ((u16 *)vdst)[i] = ((u16 *)vbuf)[7-i]; 999 break; 1000 case 2: /* lxvd2x */ 1001 for (i = 0; i < 2; i++) 1002 ((u64 *)vdst)[i] = ((u64 *)vbuf)[1-i]; 1003 break; 1004 case 3: /* lxvb16x */ 1005 for (i = 0; i < 16; i++) 1006 vdst[i] = vbuf[15-i]; 1007 break; 1008 } 1009 #else /* __LITTLE_ENDIAN__ */ 1010 /* On a big endian kernel, a BE userspace only needs a memcpy */ 1011 if (!swap) 1012 sel = 3; 1013 1014 /* Otherwise, we need to swap the content of the components */ 1015 switch (sel) { 1016 case 0: /* lxvw4x */ 1017 for (i = 0; i < 4; i++) 1018 ((u32 *)vdst)[i] = cpu_to_le32(((u32 *)vbuf)[i]); 1019 break; 1020 case 1: /* lxvh8x */ 1021 for (i = 0; i < 8; i++) 1022 ((u16 *)vdst)[i] = cpu_to_le16(((u16 *)vbuf)[i]); 1023 break; 1024 case 2: /* lxvd2x */ 1025 for (i = 0; i < 2; i++) 1026 ((u64 *)vdst)[i] = cpu_to_le64(((u64 *)vbuf)[i]); 1027 break; 1028 case 3: /* lxvb16x */ 1029 memcpy(vdst, vbuf, 16); 1030 break; 1031 } 1032 #endif /* !__LITTLE_ENDIAN__ */ 1033 1034 /* Go to next instruction */ 1035 regs_add_return_ip(regs, 4); 1036 } 1037 #endif /* CONFIG_VSX */ 1038 1039 DEFINE_INTERRUPT_HANDLER_ASYNC(handle_hmi_exception) 1040 { 1041 struct pt_regs *old_regs; 1042 1043 old_regs = set_irq_regs(regs); 1044 1045 #ifdef CONFIG_VSX 1046 /* Real mode flagged P9 special emu is needed */ 1047 if (local_paca->hmi_p9_special_emu) { 1048 local_paca->hmi_p9_special_emu = 0; 1049 1050 /* 1051 * We don't want to take page faults while doing the 1052 * emulation, we just replay the instruction if necessary. 1053 */ 1054 pagefault_disable(); 1055 p9_hmi_special_emu(regs); 1056 pagefault_enable(); 1057 } 1058 #endif /* CONFIG_VSX */ 1059 1060 if (ppc_md.handle_hmi_exception) 1061 ppc_md.handle_hmi_exception(regs); 1062 1063 set_irq_regs(old_regs); 1064 } 1065 1066 DEFINE_INTERRUPT_HANDLER(unknown_exception) 1067 { 1068 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 1069 regs->nip, regs->msr, regs->trap); 1070 1071 _exception(SIGTRAP, regs, TRAP_UNK, 0); 1072 } 1073 1074 DEFINE_INTERRUPT_HANDLER_ASYNC(unknown_async_exception) 1075 { 1076 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 1077 regs->nip, regs->msr, regs->trap); 1078 1079 _exception(SIGTRAP, regs, TRAP_UNK, 0); 1080 } 1081 1082 DEFINE_INTERRUPT_HANDLER_NMI(unknown_nmi_exception) 1083 { 1084 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 1085 regs->nip, regs->msr, regs->trap); 1086 1087 _exception(SIGTRAP, regs, TRAP_UNK, 0); 1088 1089 return 0; 1090 } 1091 1092 DEFINE_INTERRUPT_HANDLER(instruction_breakpoint_exception) 1093 { 1094 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, 1095 5, SIGTRAP) == NOTIFY_STOP) 1096 return; 1097 if (debugger_iabr_match(regs)) 1098 return; 1099 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1100 } 1101 1102 DEFINE_INTERRUPT_HANDLER(RunModeException) 1103 { 1104 _exception(SIGTRAP, regs, TRAP_UNK, 0); 1105 } 1106 1107 DEFINE_INTERRUPT_HANDLER(single_step_exception) 1108 { 1109 clear_single_step(regs); 1110 clear_br_trace(regs); 1111 1112 if (kprobe_post_handler(regs)) 1113 return; 1114 1115 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 1116 5, SIGTRAP) == NOTIFY_STOP) 1117 return; 1118 if (debugger_sstep(regs)) 1119 return; 1120 1121 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 1122 } 1123 1124 /* 1125 * After we have successfully emulated an instruction, we have to 1126 * check if the instruction was being single-stepped, and if so, 1127 * pretend we got a single-step exception. This was pointed out 1128 * by Kumar Gala. -- paulus 1129 */ 1130 static void emulate_single_step(struct pt_regs *regs) 1131 { 1132 if (single_stepping(regs)) 1133 single_step_exception(regs); 1134 } 1135 1136 static inline int __parse_fpscr(unsigned long fpscr) 1137 { 1138 int ret = FPE_FLTUNK; 1139 1140 /* Invalid operation */ 1141 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) 1142 ret = FPE_FLTINV; 1143 1144 /* Overflow */ 1145 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) 1146 ret = FPE_FLTOVF; 1147 1148 /* Underflow */ 1149 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) 1150 ret = FPE_FLTUND; 1151 1152 /* Divide by zero */ 1153 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) 1154 ret = FPE_FLTDIV; 1155 1156 /* Inexact result */ 1157 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) 1158 ret = FPE_FLTRES; 1159 1160 return ret; 1161 } 1162 1163 static void parse_fpe(struct pt_regs *regs) 1164 { 1165 int code = 0; 1166 1167 flush_fp_to_thread(current); 1168 1169 #ifdef CONFIG_PPC_FPU_REGS 1170 code = __parse_fpscr(current->thread.fp_state.fpscr); 1171 #endif 1172 1173 _exception(SIGFPE, regs, code, regs->nip); 1174 } 1175 1176 /* 1177 * Illegal instruction emulation support. Originally written to 1178 * provide the PVR to user applications using the mfspr rd, PVR. 1179 * Return non-zero if we can't emulate, or -EFAULT if the associated 1180 * memory access caused an access fault. Return zero on success. 1181 * 1182 * There are a couple of ways to do this, either "decode" the instruction 1183 * or directly match lots of bits. In this case, matching lots of 1184 * bits is faster and easier. 1185 * 1186 */ 1187 static int emulate_string_inst(struct pt_regs *regs, u32 instword) 1188 { 1189 u8 rT = (instword >> 21) & 0x1f; 1190 u8 rA = (instword >> 16) & 0x1f; 1191 u8 NB_RB = (instword >> 11) & 0x1f; 1192 u32 num_bytes; 1193 unsigned long EA; 1194 int pos = 0; 1195 1196 /* Early out if we are an invalid form of lswx */ 1197 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) 1198 if ((rT == rA) || (rT == NB_RB)) 1199 return -EINVAL; 1200 1201 EA = (rA == 0) ? 0 : regs->gpr[rA]; 1202 1203 switch (instword & PPC_INST_STRING_MASK) { 1204 case PPC_INST_LSWX: 1205 case PPC_INST_STSWX: 1206 EA += NB_RB; 1207 num_bytes = regs->xer & 0x7f; 1208 break; 1209 case PPC_INST_LSWI: 1210 case PPC_INST_STSWI: 1211 num_bytes = (NB_RB == 0) ? 32 : NB_RB; 1212 break; 1213 default: 1214 return -EINVAL; 1215 } 1216 1217 while (num_bytes != 0) 1218 { 1219 u8 val; 1220 u32 shift = 8 * (3 - (pos & 0x3)); 1221 1222 /* if process is 32-bit, clear upper 32 bits of EA */ 1223 if ((regs->msr & MSR_64BIT) == 0) 1224 EA &= 0xFFFFFFFF; 1225 1226 switch ((instword & PPC_INST_STRING_MASK)) { 1227 case PPC_INST_LSWX: 1228 case PPC_INST_LSWI: 1229 if (get_user(val, (u8 __user *)EA)) 1230 return -EFAULT; 1231 /* first time updating this reg, 1232 * zero it out */ 1233 if (pos == 0) 1234 regs->gpr[rT] = 0; 1235 regs->gpr[rT] |= val << shift; 1236 break; 1237 case PPC_INST_STSWI: 1238 case PPC_INST_STSWX: 1239 val = regs->gpr[rT] >> shift; 1240 if (put_user(val, (u8 __user *)EA)) 1241 return -EFAULT; 1242 break; 1243 } 1244 /* move EA to next address */ 1245 EA += 1; 1246 num_bytes--; 1247 1248 /* manage our position within the register */ 1249 if (++pos == 4) { 1250 pos = 0; 1251 if (++rT == 32) 1252 rT = 0; 1253 } 1254 } 1255 1256 return 0; 1257 } 1258 1259 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) 1260 { 1261 u32 ra,rs; 1262 unsigned long tmp; 1263 1264 ra = (instword >> 16) & 0x1f; 1265 rs = (instword >> 21) & 0x1f; 1266 1267 tmp = regs->gpr[rs]; 1268 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); 1269 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); 1270 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; 1271 regs->gpr[ra] = tmp; 1272 1273 return 0; 1274 } 1275 1276 static int emulate_isel(struct pt_regs *regs, u32 instword) 1277 { 1278 u8 rT = (instword >> 21) & 0x1f; 1279 u8 rA = (instword >> 16) & 0x1f; 1280 u8 rB = (instword >> 11) & 0x1f; 1281 u8 BC = (instword >> 6) & 0x1f; 1282 u8 bit; 1283 unsigned long tmp; 1284 1285 tmp = (rA == 0) ? 0 : regs->gpr[rA]; 1286 bit = (regs->ccr >> (31 - BC)) & 0x1; 1287 1288 regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; 1289 1290 return 0; 1291 } 1292 1293 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1294 static inline bool tm_abort_check(struct pt_regs *regs, int cause) 1295 { 1296 /* If we're emulating a load/store in an active transaction, we cannot 1297 * emulate it as the kernel operates in transaction suspended context. 1298 * We need to abort the transaction. This creates a persistent TM 1299 * abort so tell the user what caused it with a new code. 1300 */ 1301 if (MSR_TM_TRANSACTIONAL(regs->msr)) { 1302 tm_enable(); 1303 tm_abort(cause); 1304 return true; 1305 } 1306 return false; 1307 } 1308 #else 1309 static inline bool tm_abort_check(struct pt_regs *regs, int reason) 1310 { 1311 return false; 1312 } 1313 #endif 1314 1315 static int emulate_instruction(struct pt_regs *regs) 1316 { 1317 u32 instword; 1318 u32 rd; 1319 1320 if (!user_mode(regs)) 1321 return -EINVAL; 1322 1323 if (get_user(instword, (u32 __user *)(regs->nip))) 1324 return -EFAULT; 1325 1326 /* Emulate the mfspr rD, PVR. */ 1327 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { 1328 PPC_WARN_EMULATED(mfpvr, regs); 1329 rd = (instword >> 21) & 0x1f; 1330 regs->gpr[rd] = mfspr(SPRN_PVR); 1331 return 0; 1332 } 1333 1334 /* Emulating the dcba insn is just a no-op. */ 1335 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { 1336 PPC_WARN_EMULATED(dcba, regs); 1337 return 0; 1338 } 1339 1340 /* Emulate the mcrxr insn. */ 1341 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { 1342 int shift = (instword >> 21) & 0x1c; 1343 unsigned long msk = 0xf0000000UL >> shift; 1344 1345 PPC_WARN_EMULATED(mcrxr, regs); 1346 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); 1347 regs->xer &= ~0xf0000000UL; 1348 return 0; 1349 } 1350 1351 /* Emulate load/store string insn. */ 1352 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { 1353 if (tm_abort_check(regs, 1354 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) 1355 return -EINVAL; 1356 PPC_WARN_EMULATED(string, regs); 1357 return emulate_string_inst(regs, instword); 1358 } 1359 1360 /* Emulate the popcntb (Population Count Bytes) instruction. */ 1361 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { 1362 PPC_WARN_EMULATED(popcntb, regs); 1363 return emulate_popcntb_inst(regs, instword); 1364 } 1365 1366 /* Emulate isel (Integer Select) instruction */ 1367 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { 1368 PPC_WARN_EMULATED(isel, regs); 1369 return emulate_isel(regs, instword); 1370 } 1371 1372 /* Emulate sync instruction variants */ 1373 if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) { 1374 PPC_WARN_EMULATED(sync, regs); 1375 asm volatile("sync"); 1376 return 0; 1377 } 1378 1379 #ifdef CONFIG_PPC64 1380 /* Emulate the mfspr rD, DSCR. */ 1381 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) == 1382 PPC_INST_MFSPR_DSCR_USER) || 1383 ((instword & PPC_INST_MFSPR_DSCR_MASK) == 1384 PPC_INST_MFSPR_DSCR)) && 1385 cpu_has_feature(CPU_FTR_DSCR)) { 1386 PPC_WARN_EMULATED(mfdscr, regs); 1387 rd = (instword >> 21) & 0x1f; 1388 regs->gpr[rd] = mfspr(SPRN_DSCR); 1389 return 0; 1390 } 1391 /* Emulate the mtspr DSCR, rD. */ 1392 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) == 1393 PPC_INST_MTSPR_DSCR_USER) || 1394 ((instword & PPC_INST_MTSPR_DSCR_MASK) == 1395 PPC_INST_MTSPR_DSCR)) && 1396 cpu_has_feature(CPU_FTR_DSCR)) { 1397 PPC_WARN_EMULATED(mtdscr, regs); 1398 rd = (instword >> 21) & 0x1f; 1399 current->thread.dscr = regs->gpr[rd]; 1400 current->thread.dscr_inherit = 1; 1401 mtspr(SPRN_DSCR, current->thread.dscr); 1402 return 0; 1403 } 1404 #endif 1405 1406 return -EINVAL; 1407 } 1408 1409 int is_valid_bugaddr(unsigned long addr) 1410 { 1411 return is_kernel_addr(addr); 1412 } 1413 1414 #ifdef CONFIG_MATH_EMULATION 1415 static int emulate_math(struct pt_regs *regs) 1416 { 1417 int ret; 1418 1419 ret = do_mathemu(regs); 1420 if (ret >= 0) 1421 PPC_WARN_EMULATED(math, regs); 1422 1423 switch (ret) { 1424 case 0: 1425 emulate_single_step(regs); 1426 return 0; 1427 case 1: { 1428 int code = 0; 1429 code = __parse_fpscr(current->thread.fp_state.fpscr); 1430 _exception(SIGFPE, regs, code, regs->nip); 1431 return 0; 1432 } 1433 case -EFAULT: 1434 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1435 return 0; 1436 } 1437 1438 return -1; 1439 } 1440 #else 1441 static inline int emulate_math(struct pt_regs *regs) { return -1; } 1442 #endif 1443 1444 static void do_program_check(struct pt_regs *regs) 1445 { 1446 unsigned int reason = get_reason(regs); 1447 1448 /* We can now get here via a FP Unavailable exception if the core 1449 * has no FPU, in that case the reason flags will be 0 */ 1450 1451 if (reason & REASON_FP) { 1452 /* IEEE FP exception */ 1453 parse_fpe(regs); 1454 return; 1455 } 1456 if (reason & REASON_TRAP) { 1457 unsigned long bugaddr; 1458 /* Debugger is first in line to stop recursive faults in 1459 * rcu_lock, notify_die, or atomic_notifier_call_chain */ 1460 if (debugger_bpt(regs)) 1461 return; 1462 1463 if (kprobe_handler(regs)) 1464 return; 1465 1466 /* trap exception */ 1467 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) 1468 == NOTIFY_STOP) 1469 return; 1470 1471 bugaddr = regs->nip; 1472 /* 1473 * Fixup bugaddr for BUG_ON() in real mode 1474 */ 1475 if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR)) 1476 bugaddr += PAGE_OFFSET; 1477 1478 if (!(regs->msr & MSR_PR) && /* not user-mode */ 1479 report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) { 1480 regs_add_return_ip(regs, 4); 1481 return; 1482 } 1483 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1484 return; 1485 } 1486 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1487 if (reason & REASON_TM) { 1488 /* This is a TM "Bad Thing Exception" program check. 1489 * This occurs when: 1490 * - An rfid/hrfid/mtmsrd attempts to cause an illegal 1491 * transition in TM states. 1492 * - A trechkpt is attempted when transactional. 1493 * - A treclaim is attempted when non transactional. 1494 * - A tend is illegally attempted. 1495 * - writing a TM SPR when transactional. 1496 * 1497 * If usermode caused this, it's done something illegal and 1498 * gets a SIGILL slap on the wrist. We call it an illegal 1499 * operand to distinguish from the instruction just being bad 1500 * (e.g. executing a 'tend' on a CPU without TM!); it's an 1501 * illegal /placement/ of a valid instruction. 1502 */ 1503 if (user_mode(regs)) { 1504 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip); 1505 return; 1506 } else { 1507 printk(KERN_EMERG "Unexpected TM Bad Thing exception " 1508 "at %lx (msr 0x%lx) tm_scratch=%llx\n", 1509 regs->nip, regs->msr, get_paca()->tm_scratch); 1510 die("Unrecoverable exception", regs, SIGABRT); 1511 } 1512 } 1513 #endif 1514 1515 /* 1516 * If we took the program check in the kernel skip down to sending a 1517 * SIGILL. The subsequent cases all relate to emulating instructions 1518 * which we should only do for userspace. We also do not want to enable 1519 * interrupts for kernel faults because that might lead to further 1520 * faults, and loose the context of the original exception. 1521 */ 1522 if (!user_mode(regs)) 1523 goto sigill; 1524 1525 interrupt_cond_local_irq_enable(regs); 1526 1527 /* (reason & REASON_ILLEGAL) would be the obvious thing here, 1528 * but there seems to be a hardware bug on the 405GP (RevD) 1529 * that means ESR is sometimes set incorrectly - either to 1530 * ESR_DST (!?) or 0. In the process of chasing this with the 1531 * hardware people - not sure if it can happen on any illegal 1532 * instruction or only on FP instructions, whether there is a 1533 * pattern to occurrences etc. -dgibson 31/Mar/2003 1534 */ 1535 if (!emulate_math(regs)) 1536 return; 1537 1538 /* Try to emulate it if we should. */ 1539 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { 1540 switch (emulate_instruction(regs)) { 1541 case 0: 1542 regs_add_return_ip(regs, 4); 1543 emulate_single_step(regs); 1544 return; 1545 case -EFAULT: 1546 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1547 return; 1548 } 1549 } 1550 1551 sigill: 1552 if (reason & REASON_PRIVILEGED) 1553 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 1554 else 1555 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1556 1557 } 1558 1559 DEFINE_INTERRUPT_HANDLER(program_check_exception) 1560 { 1561 do_program_check(regs); 1562 } 1563 1564 /* 1565 * This occurs when running in hypervisor mode on POWER6 or later 1566 * and an illegal instruction is encountered. 1567 */ 1568 DEFINE_INTERRUPT_HANDLER(emulation_assist_interrupt) 1569 { 1570 regs_set_return_msr(regs, regs->msr | REASON_ILLEGAL); 1571 do_program_check(regs); 1572 } 1573 1574 DEFINE_INTERRUPT_HANDLER(alignment_exception) 1575 { 1576 int sig, code, fixed = 0; 1577 unsigned long reason; 1578 1579 interrupt_cond_local_irq_enable(regs); 1580 1581 reason = get_reason(regs); 1582 if (reason & REASON_BOUNDARY) { 1583 sig = SIGBUS; 1584 code = BUS_ADRALN; 1585 goto bad; 1586 } 1587 1588 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT)) 1589 return; 1590 1591 /* we don't implement logging of alignment exceptions */ 1592 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) 1593 fixed = fix_alignment(regs); 1594 1595 if (fixed == 1) { 1596 /* skip over emulated instruction */ 1597 regs_add_return_ip(regs, inst_length(reason)); 1598 emulate_single_step(regs); 1599 return; 1600 } 1601 1602 /* Operand address was bad */ 1603 if (fixed == -EFAULT) { 1604 sig = SIGSEGV; 1605 code = SEGV_ACCERR; 1606 } else { 1607 sig = SIGBUS; 1608 code = BUS_ADRALN; 1609 } 1610 bad: 1611 if (user_mode(regs)) 1612 _exception(sig, regs, code, regs->dar); 1613 else 1614 bad_page_fault(regs, sig); 1615 } 1616 1617 DEFINE_INTERRUPT_HANDLER(stack_overflow_exception) 1618 { 1619 die("Kernel stack overflow", regs, SIGSEGV); 1620 } 1621 1622 DEFINE_INTERRUPT_HANDLER(kernel_fp_unavailable_exception) 1623 { 1624 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " 1625 "%lx at %lx\n", regs->trap, regs->nip); 1626 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); 1627 } 1628 1629 DEFINE_INTERRUPT_HANDLER(altivec_unavailable_exception) 1630 { 1631 if (user_mode(regs)) { 1632 /* A user program has executed an altivec instruction, 1633 but this kernel doesn't support altivec. */ 1634 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1635 return; 1636 } 1637 1638 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " 1639 "%lx at %lx\n", regs->trap, regs->nip); 1640 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); 1641 } 1642 1643 DEFINE_INTERRUPT_HANDLER(vsx_unavailable_exception) 1644 { 1645 if (user_mode(regs)) { 1646 /* A user program has executed an vsx instruction, 1647 but this kernel doesn't support vsx. */ 1648 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1649 return; 1650 } 1651 1652 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " 1653 "%lx at %lx\n", regs->trap, regs->nip); 1654 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); 1655 } 1656 1657 #ifdef CONFIG_PPC64 1658 static void tm_unavailable(struct pt_regs *regs) 1659 { 1660 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1661 if (user_mode(regs)) { 1662 current->thread.load_tm++; 1663 regs_set_return_msr(regs, regs->msr | MSR_TM); 1664 tm_enable(); 1665 tm_restore_sprs(¤t->thread); 1666 return; 1667 } 1668 #endif 1669 pr_emerg("Unrecoverable TM Unavailable Exception " 1670 "%lx at %lx\n", regs->trap, regs->nip); 1671 die("Unrecoverable TM Unavailable Exception", regs, SIGABRT); 1672 } 1673 1674 DEFINE_INTERRUPT_HANDLER(facility_unavailable_exception) 1675 { 1676 static char *facility_strings[] = { 1677 [FSCR_FP_LG] = "FPU", 1678 [FSCR_VECVSX_LG] = "VMX/VSX", 1679 [FSCR_DSCR_LG] = "DSCR", 1680 [FSCR_PM_LG] = "PMU SPRs", 1681 [FSCR_BHRB_LG] = "BHRB", 1682 [FSCR_TM_LG] = "TM", 1683 [FSCR_EBB_LG] = "EBB", 1684 [FSCR_TAR_LG] = "TAR", 1685 [FSCR_MSGP_LG] = "MSGP", 1686 [FSCR_SCV_LG] = "SCV", 1687 [FSCR_PREFIX_LG] = "PREFIX", 1688 }; 1689 char *facility = "unknown"; 1690 u64 value; 1691 u32 instword, rd; 1692 u8 status; 1693 bool hv; 1694 1695 hv = (TRAP(regs) == INTERRUPT_H_FAC_UNAVAIL); 1696 if (hv) 1697 value = mfspr(SPRN_HFSCR); 1698 else 1699 value = mfspr(SPRN_FSCR); 1700 1701 status = value >> 56; 1702 if ((hv || status >= 2) && 1703 (status < ARRAY_SIZE(facility_strings)) && 1704 facility_strings[status]) 1705 facility = facility_strings[status]; 1706 1707 /* We should not have taken this interrupt in kernel */ 1708 if (!user_mode(regs)) { 1709 pr_emerg("Facility '%s' unavailable (%d) exception in kernel mode at %lx\n", 1710 facility, status, regs->nip); 1711 die("Unexpected facility unavailable exception", regs, SIGABRT); 1712 } 1713 1714 interrupt_cond_local_irq_enable(regs); 1715 1716 if (status == FSCR_DSCR_LG) { 1717 /* 1718 * User is accessing the DSCR register using the problem 1719 * state only SPR number (0x03) either through a mfspr or 1720 * a mtspr instruction. If it is a write attempt through 1721 * a mtspr, then we set the inherit bit. This also allows 1722 * the user to write or read the register directly in the 1723 * future by setting via the FSCR DSCR bit. But in case it 1724 * is a read DSCR attempt through a mfspr instruction, we 1725 * just emulate the instruction instead. This code path will 1726 * always emulate all the mfspr instructions till the user 1727 * has attempted at least one mtspr instruction. This way it 1728 * preserves the same behaviour when the user is accessing 1729 * the DSCR through privilege level only SPR number (0x11) 1730 * which is emulated through illegal instruction exception. 1731 * We always leave HFSCR DSCR set. 1732 */ 1733 if (get_user(instword, (u32 __user *)(regs->nip))) { 1734 pr_err("Failed to fetch the user instruction\n"); 1735 return; 1736 } 1737 1738 /* Write into DSCR (mtspr 0x03, RS) */ 1739 if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK) 1740 == PPC_INST_MTSPR_DSCR_USER) { 1741 rd = (instword >> 21) & 0x1f; 1742 current->thread.dscr = regs->gpr[rd]; 1743 current->thread.dscr_inherit = 1; 1744 current->thread.fscr |= FSCR_DSCR; 1745 mtspr(SPRN_FSCR, current->thread.fscr); 1746 } 1747 1748 /* Read from DSCR (mfspr RT, 0x03) */ 1749 if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK) 1750 == PPC_INST_MFSPR_DSCR_USER) { 1751 if (emulate_instruction(regs)) { 1752 pr_err("DSCR based mfspr emulation failed\n"); 1753 return; 1754 } 1755 regs_add_return_ip(regs, 4); 1756 emulate_single_step(regs); 1757 } 1758 return; 1759 } 1760 1761 if (status == FSCR_TM_LG) { 1762 /* 1763 * If we're here then the hardware is TM aware because it 1764 * generated an exception with FSRM_TM set. 1765 * 1766 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware 1767 * told us not to do TM, or the kernel is not built with TM 1768 * support. 1769 * 1770 * If both of those things are true, then userspace can spam the 1771 * console by triggering the printk() below just by continually 1772 * doing tbegin (or any TM instruction). So in that case just 1773 * send the process a SIGILL immediately. 1774 */ 1775 if (!cpu_has_feature(CPU_FTR_TM)) 1776 goto out; 1777 1778 tm_unavailable(regs); 1779 return; 1780 } 1781 1782 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n", 1783 hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr); 1784 1785 out: 1786 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1787 } 1788 #endif 1789 1790 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1791 1792 DEFINE_INTERRUPT_HANDLER(fp_unavailable_tm) 1793 { 1794 /* Note: This does not handle any kind of FP laziness. */ 1795 1796 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n", 1797 regs->nip, regs->msr); 1798 1799 /* We can only have got here if the task started using FP after 1800 * beginning the transaction. So, the transactional regs are just a 1801 * copy of the checkpointed ones. But, we still need to recheckpoint 1802 * as we're enabling FP for the process; it will return, abort the 1803 * transaction, and probably retry but now with FP enabled. So the 1804 * checkpointed FP registers need to be loaded. 1805 */ 1806 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1807 1808 /* 1809 * Reclaim initially saved out bogus (lazy) FPRs to ckfp_state, and 1810 * then it was overwrite by the thr->fp_state by tm_reclaim_thread(). 1811 * 1812 * At this point, ck{fp,vr}_state contains the exact values we want to 1813 * recheckpoint. 1814 */ 1815 1816 /* Enable FP for the task: */ 1817 current->thread.load_fp = 1; 1818 1819 /* 1820 * Recheckpoint all the checkpointed ckpt, ck{fp, vr}_state registers. 1821 */ 1822 tm_recheckpoint(¤t->thread); 1823 } 1824 1825 DEFINE_INTERRUPT_HANDLER(altivec_unavailable_tm) 1826 { 1827 /* See the comments in fp_unavailable_tm(). This function operates 1828 * the same way. 1829 */ 1830 1831 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx," 1832 "MSR=%lx\n", 1833 regs->nip, regs->msr); 1834 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1835 current->thread.load_vec = 1; 1836 tm_recheckpoint(¤t->thread); 1837 current->thread.used_vr = 1; 1838 } 1839 1840 DEFINE_INTERRUPT_HANDLER(vsx_unavailable_tm) 1841 { 1842 /* See the comments in fp_unavailable_tm(). This works similarly, 1843 * though we're loading both FP and VEC registers in here. 1844 * 1845 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC 1846 * regs. Either way, set MSR_VSX. 1847 */ 1848 1849 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx," 1850 "MSR=%lx\n", 1851 regs->nip, regs->msr); 1852 1853 current->thread.used_vsr = 1; 1854 1855 /* This reclaims FP and/or VR regs if they're already enabled */ 1856 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1857 1858 current->thread.load_vec = 1; 1859 current->thread.load_fp = 1; 1860 1861 tm_recheckpoint(¤t->thread); 1862 } 1863 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1864 1865 #ifdef CONFIG_PPC64 1866 DECLARE_INTERRUPT_HANDLER_NMI(performance_monitor_exception_nmi); 1867 DEFINE_INTERRUPT_HANDLER_NMI(performance_monitor_exception_nmi) 1868 { 1869 __this_cpu_inc(irq_stat.pmu_irqs); 1870 1871 perf_irq(regs); 1872 1873 return 0; 1874 } 1875 #endif 1876 1877 DECLARE_INTERRUPT_HANDLER_ASYNC(performance_monitor_exception_async); 1878 DEFINE_INTERRUPT_HANDLER_ASYNC(performance_monitor_exception_async) 1879 { 1880 __this_cpu_inc(irq_stat.pmu_irqs); 1881 1882 perf_irq(regs); 1883 } 1884 1885 DEFINE_INTERRUPT_HANDLER_RAW(performance_monitor_exception) 1886 { 1887 /* 1888 * On 64-bit, if perf interrupts hit in a local_irq_disable 1889 * (soft-masked) region, we consider them as NMIs. This is required to 1890 * prevent hash faults on user addresses when reading callchains (and 1891 * looks better from an irq tracing perspective). 1892 */ 1893 if (IS_ENABLED(CONFIG_PPC64) && unlikely(arch_irq_disabled_regs(regs))) 1894 performance_monitor_exception_nmi(regs); 1895 else 1896 performance_monitor_exception_async(regs); 1897 1898 return 0; 1899 } 1900 1901 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1902 static void handle_debug(struct pt_regs *regs, unsigned long debug_status) 1903 { 1904 int changed = 0; 1905 /* 1906 * Determine the cause of the debug event, clear the 1907 * event flags and send a trap to the handler. Torez 1908 */ 1909 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { 1910 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); 1911 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1912 current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; 1913 #endif 1914 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, 1915 5); 1916 changed |= 0x01; 1917 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { 1918 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); 1919 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, 1920 6); 1921 changed |= 0x01; 1922 } else if (debug_status & DBSR_IAC1) { 1923 current->thread.debug.dbcr0 &= ~DBCR0_IAC1; 1924 dbcr_iac_range(current) &= ~DBCR_IAC12MODE; 1925 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, 1926 1); 1927 changed |= 0x01; 1928 } else if (debug_status & DBSR_IAC2) { 1929 current->thread.debug.dbcr0 &= ~DBCR0_IAC2; 1930 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, 1931 2); 1932 changed |= 0x01; 1933 } else if (debug_status & DBSR_IAC3) { 1934 current->thread.debug.dbcr0 &= ~DBCR0_IAC3; 1935 dbcr_iac_range(current) &= ~DBCR_IAC34MODE; 1936 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, 1937 3); 1938 changed |= 0x01; 1939 } else if (debug_status & DBSR_IAC4) { 1940 current->thread.debug.dbcr0 &= ~DBCR0_IAC4; 1941 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, 1942 4); 1943 changed |= 0x01; 1944 } 1945 /* 1946 * At the point this routine was called, the MSR(DE) was turned off. 1947 * Check all other debug flags and see if that bit needs to be turned 1948 * back on or not. 1949 */ 1950 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 1951 current->thread.debug.dbcr1)) 1952 regs_set_return_msr(regs, regs->msr | MSR_DE); 1953 else 1954 /* Make sure the IDM flag is off */ 1955 current->thread.debug.dbcr0 &= ~DBCR0_IDM; 1956 1957 if (changed & 0x01) 1958 mtspr(SPRN_DBCR0, current->thread.debug.dbcr0); 1959 } 1960 1961 DEFINE_INTERRUPT_HANDLER(DebugException) 1962 { 1963 unsigned long debug_status = regs->dsisr; 1964 1965 current->thread.debug.dbsr = debug_status; 1966 1967 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while 1968 * on server, it stops on the target of the branch. In order to simulate 1969 * the server behaviour, we thus restart right away with a single step 1970 * instead of stopping here when hitting a BT 1971 */ 1972 if (debug_status & DBSR_BT) { 1973 regs_set_return_msr(regs, regs->msr & ~MSR_DE); 1974 1975 /* Disable BT */ 1976 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); 1977 /* Clear the BT event */ 1978 mtspr(SPRN_DBSR, DBSR_BT); 1979 1980 /* Do the single step trick only when coming from userspace */ 1981 if (user_mode(regs)) { 1982 current->thread.debug.dbcr0 &= ~DBCR0_BT; 1983 current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; 1984 regs_set_return_msr(regs, regs->msr | MSR_DE); 1985 return; 1986 } 1987 1988 if (kprobe_post_handler(regs)) 1989 return; 1990 1991 if (notify_die(DIE_SSTEP, "block_step", regs, 5, 1992 5, SIGTRAP) == NOTIFY_STOP) { 1993 return; 1994 } 1995 if (debugger_sstep(regs)) 1996 return; 1997 } else if (debug_status & DBSR_IC) { /* Instruction complete */ 1998 regs_set_return_msr(regs, regs->msr & ~MSR_DE); 1999 2000 /* Disable instruction completion */ 2001 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); 2002 /* Clear the instruction completion event */ 2003 mtspr(SPRN_DBSR, DBSR_IC); 2004 2005 if (kprobe_post_handler(regs)) 2006 return; 2007 2008 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 2009 5, SIGTRAP) == NOTIFY_STOP) { 2010 return; 2011 } 2012 2013 if (debugger_sstep(regs)) 2014 return; 2015 2016 if (user_mode(regs)) { 2017 current->thread.debug.dbcr0 &= ~DBCR0_IC; 2018 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 2019 current->thread.debug.dbcr1)) 2020 regs_set_return_msr(regs, regs->msr | MSR_DE); 2021 else 2022 /* Make sure the IDM bit is off */ 2023 current->thread.debug.dbcr0 &= ~DBCR0_IDM; 2024 } 2025 2026 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 2027 } else 2028 handle_debug(regs, debug_status); 2029 } 2030 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 2031 2032 #ifdef CONFIG_ALTIVEC 2033 DEFINE_INTERRUPT_HANDLER(altivec_assist_exception) 2034 { 2035 int err; 2036 2037 if (!user_mode(regs)) { 2038 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" 2039 " at %lx\n", regs->nip); 2040 die("Kernel VMX/Altivec assist exception", regs, SIGILL); 2041 } 2042 2043 flush_altivec_to_thread(current); 2044 2045 PPC_WARN_EMULATED(altivec, regs); 2046 err = emulate_altivec(regs); 2047 if (err == 0) { 2048 regs_add_return_ip(regs, 4); /* skip emulated instruction */ 2049 emulate_single_step(regs); 2050 return; 2051 } 2052 2053 if (err == -EFAULT) { 2054 /* got an error reading the instruction */ 2055 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2056 } else { 2057 /* didn't recognize the instruction */ 2058 /* XXX quick hack for now: set the non-Java bit in the VSCR */ 2059 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " 2060 "in %s at %lx\n", current->comm, regs->nip); 2061 current->thread.vr_state.vscr.u[3] |= 0x10000; 2062 } 2063 } 2064 #endif /* CONFIG_ALTIVEC */ 2065 2066 #ifdef CONFIG_FSL_BOOKE 2067 DEFINE_INTERRUPT_HANDLER(CacheLockingException) 2068 { 2069 unsigned long error_code = regs->dsisr; 2070 2071 /* We treat cache locking instructions from the user 2072 * as priv ops, in the future we could try to do 2073 * something smarter 2074 */ 2075 if (error_code & (ESR_DLK|ESR_ILK)) 2076 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 2077 return; 2078 } 2079 #endif /* CONFIG_FSL_BOOKE */ 2080 2081 #ifdef CONFIG_SPE 2082 DEFINE_INTERRUPT_HANDLER(SPEFloatingPointException) 2083 { 2084 extern int do_spe_mathemu(struct pt_regs *regs); 2085 unsigned long spefscr; 2086 int fpexc_mode; 2087 int code = FPE_FLTUNK; 2088 int err; 2089 2090 interrupt_cond_local_irq_enable(regs); 2091 2092 flush_spe_to_thread(current); 2093 2094 spefscr = current->thread.spefscr; 2095 fpexc_mode = current->thread.fpexc_mode; 2096 2097 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { 2098 code = FPE_FLTOVF; 2099 } 2100 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { 2101 code = FPE_FLTUND; 2102 } 2103 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) 2104 code = FPE_FLTDIV; 2105 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { 2106 code = FPE_FLTINV; 2107 } 2108 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) 2109 code = FPE_FLTRES; 2110 2111 err = do_spe_mathemu(regs); 2112 if (err == 0) { 2113 regs_add_return_ip(regs, 4); /* skip emulated instruction */ 2114 emulate_single_step(regs); 2115 return; 2116 } 2117 2118 if (err == -EFAULT) { 2119 /* got an error reading the instruction */ 2120 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2121 } else if (err == -EINVAL) { 2122 /* didn't recognize the instruction */ 2123 printk(KERN_ERR "unrecognized spe instruction " 2124 "in %s at %lx\n", current->comm, regs->nip); 2125 } else { 2126 _exception(SIGFPE, regs, code, regs->nip); 2127 } 2128 2129 return; 2130 } 2131 2132 DEFINE_INTERRUPT_HANDLER(SPEFloatingPointRoundException) 2133 { 2134 extern int speround_handler(struct pt_regs *regs); 2135 int err; 2136 2137 interrupt_cond_local_irq_enable(regs); 2138 2139 preempt_disable(); 2140 if (regs->msr & MSR_SPE) 2141 giveup_spe(current); 2142 preempt_enable(); 2143 2144 regs_add_return_ip(regs, -4); 2145 err = speround_handler(regs); 2146 if (err == 0) { 2147 regs_add_return_ip(regs, 4); /* skip emulated instruction */ 2148 emulate_single_step(regs); 2149 return; 2150 } 2151 2152 if (err == -EFAULT) { 2153 /* got an error reading the instruction */ 2154 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2155 } else if (err == -EINVAL) { 2156 /* didn't recognize the instruction */ 2157 printk(KERN_ERR "unrecognized spe instruction " 2158 "in %s at %lx\n", current->comm, regs->nip); 2159 } else { 2160 _exception(SIGFPE, regs, FPE_FLTUNK, regs->nip); 2161 return; 2162 } 2163 } 2164 #endif 2165 2166 /* 2167 * We enter here if we get an unrecoverable exception, that is, one 2168 * that happened at a point where the RI (recoverable interrupt) bit 2169 * in the MSR is 0. This indicates that SRR0/1 are live, and that 2170 * we therefore lost state by taking this exception. 2171 */ 2172 void __noreturn unrecoverable_exception(struct pt_regs *regs) 2173 { 2174 pr_emerg("Unrecoverable exception %lx at %lx (msr=%lx)\n", 2175 regs->trap, regs->nip, regs->msr); 2176 die("Unrecoverable exception", regs, SIGABRT); 2177 /* die() should not return */ 2178 for (;;) 2179 ; 2180 } 2181 2182 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x) 2183 /* 2184 * Default handler for a Watchdog exception, 2185 * spins until a reboot occurs 2186 */ 2187 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) 2188 { 2189 /* Generic WatchdogHandler, implement your own */ 2190 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); 2191 return; 2192 } 2193 2194 DEFINE_INTERRUPT_HANDLER_NMI(WatchdogException) 2195 { 2196 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); 2197 WatchdogHandler(regs); 2198 return 0; 2199 } 2200 #endif 2201 2202 /* 2203 * We enter here if we discover during exception entry that we are 2204 * running in supervisor mode with a userspace value in the stack pointer. 2205 */ 2206 DEFINE_INTERRUPT_HANDLER(kernel_bad_stack) 2207 { 2208 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", 2209 regs->gpr[1], regs->nip); 2210 die("Bad kernel stack pointer", regs, SIGABRT); 2211 } 2212 2213 void __init trap_init(void) 2214 { 2215 } 2216 2217 2218 #ifdef CONFIG_PPC_EMULATED_STATS 2219 2220 #define WARN_EMULATED_SETUP(type) .type = { .name = #type } 2221 2222 struct ppc_emulated ppc_emulated = { 2223 #ifdef CONFIG_ALTIVEC 2224 WARN_EMULATED_SETUP(altivec), 2225 #endif 2226 WARN_EMULATED_SETUP(dcba), 2227 WARN_EMULATED_SETUP(dcbz), 2228 WARN_EMULATED_SETUP(fp_pair), 2229 WARN_EMULATED_SETUP(isel), 2230 WARN_EMULATED_SETUP(mcrxr), 2231 WARN_EMULATED_SETUP(mfpvr), 2232 WARN_EMULATED_SETUP(multiple), 2233 WARN_EMULATED_SETUP(popcntb), 2234 WARN_EMULATED_SETUP(spe), 2235 WARN_EMULATED_SETUP(string), 2236 WARN_EMULATED_SETUP(sync), 2237 WARN_EMULATED_SETUP(unaligned), 2238 #ifdef CONFIG_MATH_EMULATION 2239 WARN_EMULATED_SETUP(math), 2240 #endif 2241 #ifdef CONFIG_VSX 2242 WARN_EMULATED_SETUP(vsx), 2243 #endif 2244 #ifdef CONFIG_PPC64 2245 WARN_EMULATED_SETUP(mfdscr), 2246 WARN_EMULATED_SETUP(mtdscr), 2247 WARN_EMULATED_SETUP(lq_stq), 2248 WARN_EMULATED_SETUP(lxvw4x), 2249 WARN_EMULATED_SETUP(lxvh8x), 2250 WARN_EMULATED_SETUP(lxvd2x), 2251 WARN_EMULATED_SETUP(lxvb16x), 2252 #endif 2253 }; 2254 2255 u32 ppc_warn_emulated; 2256 2257 void ppc_warn_emulated_print(const char *type) 2258 { 2259 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, 2260 type); 2261 } 2262 2263 static int __init ppc_warn_emulated_init(void) 2264 { 2265 struct dentry *dir; 2266 unsigned int i; 2267 struct ppc_emulated_entry *entries = (void *)&ppc_emulated; 2268 2269 dir = debugfs_create_dir("emulated_instructions", 2270 powerpc_debugfs_root); 2271 2272 debugfs_create_u32("do_warn", 0644, dir, &ppc_warn_emulated); 2273 2274 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) 2275 debugfs_create_u32(entries[i].name, 0644, dir, 2276 (u32 *)&entries[i].val.counter); 2277 2278 return 0; 2279 } 2280 2281 device_initcall(ppc_warn_emulated_init); 2282 2283 #endif /* CONFIG_PPC_EMULATED_STATS */ 2284