1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * Copyright 2007-2010 Freescale Semiconductor, Inc. 5 * 6 * Modified by Cort Dougan (cort@cs.nmt.edu) 7 * and Paul Mackerras (paulus@samba.org) 8 */ 9 10 /* 11 * This file handles the architecture-dependent parts of hardware exceptions 12 */ 13 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/sched/debug.h> 17 #include <linux/kernel.h> 18 #include <linux/mm.h> 19 #include <linux/pkeys.h> 20 #include <linux/stddef.h> 21 #include <linux/unistd.h> 22 #include <linux/ptrace.h> 23 #include <linux/user.h> 24 #include <linux/interrupt.h> 25 #include <linux/init.h> 26 #include <linux/extable.h> 27 #include <linux/module.h> /* print_modules */ 28 #include <linux/prctl.h> 29 #include <linux/delay.h> 30 #include <linux/kprobes.h> 31 #include <linux/kexec.h> 32 #include <linux/backlight.h> 33 #include <linux/bug.h> 34 #include <linux/kdebug.h> 35 #include <linux/ratelimit.h> 36 #include <linux/context_tracking.h> 37 #include <linux/smp.h> 38 #include <linux/console.h> 39 #include <linux/kmsg_dump.h> 40 41 #include <asm/emulated_ops.h> 42 #include <linux/uaccess.h> 43 #include <asm/debugfs.h> 44 #include <asm/interrupt.h> 45 #include <asm/io.h> 46 #include <asm/machdep.h> 47 #include <asm/rtas.h> 48 #include <asm/pmc.h> 49 #include <asm/reg.h> 50 #ifdef CONFIG_PMAC_BACKLIGHT 51 #include <asm/backlight.h> 52 #endif 53 #ifdef CONFIG_PPC64 54 #include <asm/firmware.h> 55 #include <asm/processor.h> 56 #include <asm/tm.h> 57 #endif 58 #include <asm/kexec.h> 59 #include <asm/ppc-opcode.h> 60 #include <asm/rio.h> 61 #include <asm/fadump.h> 62 #include <asm/switch_to.h> 63 #include <asm/tm.h> 64 #include <asm/debug.h> 65 #include <asm/asm-prototypes.h> 66 #include <asm/hmi.h> 67 #include <sysdev/fsl_pci.h> 68 #include <asm/kprobes.h> 69 #include <asm/stacktrace.h> 70 #include <asm/nmi.h> 71 72 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE) 73 int (*__debugger)(struct pt_regs *regs) __read_mostly; 74 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; 75 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; 76 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; 77 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; 78 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly; 79 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; 80 81 EXPORT_SYMBOL(__debugger); 82 EXPORT_SYMBOL(__debugger_ipi); 83 EXPORT_SYMBOL(__debugger_bpt); 84 EXPORT_SYMBOL(__debugger_sstep); 85 EXPORT_SYMBOL(__debugger_iabr_match); 86 EXPORT_SYMBOL(__debugger_break_match); 87 EXPORT_SYMBOL(__debugger_fault_handler); 88 #endif 89 90 /* Transactional Memory trap debug */ 91 #ifdef TM_DEBUG_SW 92 #define TM_DEBUG(x...) printk(KERN_INFO x) 93 #else 94 #define TM_DEBUG(x...) do { } while(0) 95 #endif 96 97 static const char *signame(int signr) 98 { 99 switch (signr) { 100 case SIGBUS: return "bus error"; 101 case SIGFPE: return "floating point exception"; 102 case SIGILL: return "illegal instruction"; 103 case SIGSEGV: return "segfault"; 104 case SIGTRAP: return "unhandled trap"; 105 } 106 107 return "unknown signal"; 108 } 109 110 /* 111 * Trap & Exception support 112 */ 113 114 #ifdef CONFIG_PMAC_BACKLIGHT 115 static void pmac_backlight_unblank(void) 116 { 117 mutex_lock(&pmac_backlight_mutex); 118 if (pmac_backlight) { 119 struct backlight_properties *props; 120 121 props = &pmac_backlight->props; 122 props->brightness = props->max_brightness; 123 props->power = FB_BLANK_UNBLANK; 124 backlight_update_status(pmac_backlight); 125 } 126 mutex_unlock(&pmac_backlight_mutex); 127 } 128 #else 129 static inline void pmac_backlight_unblank(void) { } 130 #endif 131 132 /* 133 * If oops/die is expected to crash the machine, return true here. 134 * 135 * This should not be expected to be 100% accurate, there may be 136 * notifiers registered or other unexpected conditions that may bring 137 * down the kernel. Or if the current process in the kernel is holding 138 * locks or has other critical state, the kernel may become effectively 139 * unusable anyway. 140 */ 141 bool die_will_crash(void) 142 { 143 if (should_fadump_crash()) 144 return true; 145 if (kexec_should_crash(current)) 146 return true; 147 if (in_interrupt() || panic_on_oops || 148 !current->pid || is_global_init(current)) 149 return true; 150 151 return false; 152 } 153 154 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; 155 static int die_owner = -1; 156 static unsigned int die_nest_count; 157 static int die_counter; 158 159 extern void panic_flush_kmsg_start(void) 160 { 161 /* 162 * These are mostly taken from kernel/panic.c, but tries to do 163 * relatively minimal work. Don't use delay functions (TB may 164 * be broken), don't crash dump (need to set a firmware log), 165 * don't run notifiers. We do want to get some information to 166 * Linux console. 167 */ 168 console_verbose(); 169 bust_spinlocks(1); 170 } 171 172 extern void panic_flush_kmsg_end(void) 173 { 174 printk_safe_flush_on_panic(); 175 kmsg_dump(KMSG_DUMP_PANIC); 176 bust_spinlocks(0); 177 debug_locks_off(); 178 console_flush_on_panic(CONSOLE_FLUSH_PENDING); 179 } 180 181 static unsigned long oops_begin(struct pt_regs *regs) 182 { 183 int cpu; 184 unsigned long flags; 185 186 oops_enter(); 187 188 /* racy, but better than risking deadlock. */ 189 raw_local_irq_save(flags); 190 cpu = smp_processor_id(); 191 if (!arch_spin_trylock(&die_lock)) { 192 if (cpu == die_owner) 193 /* nested oops. should stop eventually */; 194 else 195 arch_spin_lock(&die_lock); 196 } 197 die_nest_count++; 198 die_owner = cpu; 199 console_verbose(); 200 bust_spinlocks(1); 201 if (machine_is(powermac)) 202 pmac_backlight_unblank(); 203 return flags; 204 } 205 NOKPROBE_SYMBOL(oops_begin); 206 207 static void oops_end(unsigned long flags, struct pt_regs *regs, 208 int signr) 209 { 210 bust_spinlocks(0); 211 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 212 die_nest_count--; 213 oops_exit(); 214 printk("\n"); 215 if (!die_nest_count) { 216 /* Nest count reaches zero, release the lock. */ 217 die_owner = -1; 218 arch_spin_unlock(&die_lock); 219 } 220 raw_local_irq_restore(flags); 221 222 /* 223 * system_reset_excption handles debugger, crash dump, panic, for 0x100 224 */ 225 if (TRAP(regs) == 0x100) 226 return; 227 228 crash_fadump(regs, "die oops"); 229 230 if (kexec_should_crash(current)) 231 crash_kexec(regs); 232 233 if (!signr) 234 return; 235 236 /* 237 * While our oops output is serialised by a spinlock, output 238 * from panic() called below can race and corrupt it. If we 239 * know we are going to panic, delay for 1 second so we have a 240 * chance to get clean backtraces from all CPUs that are oopsing. 241 */ 242 if (in_interrupt() || panic_on_oops || !current->pid || 243 is_global_init(current)) { 244 mdelay(MSEC_PER_SEC); 245 } 246 247 if (panic_on_oops) 248 panic("Fatal exception"); 249 do_exit(signr); 250 } 251 NOKPROBE_SYMBOL(oops_end); 252 253 static char *get_mmu_str(void) 254 { 255 if (early_radix_enabled()) 256 return " MMU=Radix"; 257 if (early_mmu_has_feature(MMU_FTR_HPTE_TABLE)) 258 return " MMU=Hash"; 259 return ""; 260 } 261 262 static int __die(const char *str, struct pt_regs *regs, long err) 263 { 264 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); 265 266 printk("%s PAGE_SIZE=%luK%s%s%s%s%s%s %s\n", 267 IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN) ? "LE" : "BE", 268 PAGE_SIZE / 1024, get_mmu_str(), 269 IS_ENABLED(CONFIG_PREEMPT) ? " PREEMPT" : "", 270 IS_ENABLED(CONFIG_SMP) ? " SMP" : "", 271 IS_ENABLED(CONFIG_SMP) ? (" NR_CPUS=" __stringify(NR_CPUS)) : "", 272 debug_pagealloc_enabled() ? " DEBUG_PAGEALLOC" : "", 273 IS_ENABLED(CONFIG_NUMA) ? " NUMA" : "", 274 ppc_md.name ? ppc_md.name : ""); 275 276 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP) 277 return 1; 278 279 print_modules(); 280 show_regs(regs); 281 282 return 0; 283 } 284 NOKPROBE_SYMBOL(__die); 285 286 void die(const char *str, struct pt_regs *regs, long err) 287 { 288 unsigned long flags; 289 290 /* 291 * system_reset_excption handles debugger, crash dump, panic, for 0x100 292 */ 293 if (TRAP(regs) != 0x100) { 294 if (debugger(regs)) 295 return; 296 } 297 298 flags = oops_begin(regs); 299 if (__die(str, regs, err)) 300 err = 0; 301 oops_end(flags, regs, err); 302 } 303 NOKPROBE_SYMBOL(die); 304 305 void user_single_step_report(struct pt_regs *regs) 306 { 307 force_sig_fault(SIGTRAP, TRAP_TRACE, (void __user *)regs->nip); 308 } 309 310 static void show_signal_msg(int signr, struct pt_regs *regs, int code, 311 unsigned long addr) 312 { 313 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, 314 DEFAULT_RATELIMIT_BURST); 315 316 if (!show_unhandled_signals) 317 return; 318 319 if (!unhandled_signal(current, signr)) 320 return; 321 322 if (!__ratelimit(&rs)) 323 return; 324 325 pr_info("%s[%d]: %s (%d) at %lx nip %lx lr %lx code %x", 326 current->comm, current->pid, signame(signr), signr, 327 addr, regs->nip, regs->link, code); 328 329 print_vma_addr(KERN_CONT " in ", regs->nip); 330 331 pr_cont("\n"); 332 333 show_user_instructions(regs); 334 } 335 336 static bool exception_common(int signr, struct pt_regs *regs, int code, 337 unsigned long addr) 338 { 339 if (!user_mode(regs)) { 340 die("Exception in kernel mode", regs, signr); 341 return false; 342 } 343 344 show_signal_msg(signr, regs, code, addr); 345 346 if (arch_irqs_disabled()) 347 interrupt_cond_local_irq_enable(regs); 348 349 current->thread.trap_nr = code; 350 351 return true; 352 } 353 354 void _exception_pkey(struct pt_regs *regs, unsigned long addr, int key) 355 { 356 if (!exception_common(SIGSEGV, regs, SEGV_PKUERR, addr)) 357 return; 358 359 force_sig_pkuerr((void __user *) addr, key); 360 } 361 362 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) 363 { 364 if (!exception_common(signr, regs, code, addr)) 365 return; 366 367 force_sig_fault(signr, code, (void __user *)addr); 368 } 369 370 /* 371 * The interrupt architecture has a quirk in that the HV interrupts excluding 372 * the NMIs (0x100 and 0x200) do not clear MSR[RI] at entry. The first thing 373 * that an interrupt handler must do is save off a GPR into a scratch register, 374 * and all interrupts on POWERNV (HV=1) use the HSPRG1 register as scratch. 375 * Therefore an NMI can clobber an HV interrupt's live HSPRG1 without noticing 376 * that it is non-reentrant, which leads to random data corruption. 377 * 378 * The solution is for NMI interrupts in HV mode to check if they originated 379 * from these critical HV interrupt regions. If so, then mark them not 380 * recoverable. 381 * 382 * An alternative would be for HV NMIs to use SPRG for scratch to avoid the 383 * HSPRG1 clobber, however this would cause guest SPRG to be clobbered. Linux 384 * guests should always have MSR[RI]=0 when its scratch SPRG is in use, so 385 * that would work. However any other guest OS that may have the SPRG live 386 * and MSR[RI]=1 could encounter silent corruption. 387 * 388 * Builds that do not support KVM could take this second option to increase 389 * the recoverability of NMIs. 390 */ 391 void hv_nmi_check_nonrecoverable(struct pt_regs *regs) 392 { 393 #ifdef CONFIG_PPC_POWERNV 394 unsigned long kbase = (unsigned long)_stext; 395 unsigned long nip = regs->nip; 396 397 if (!(regs->msr & MSR_RI)) 398 return; 399 if (!(regs->msr & MSR_HV)) 400 return; 401 if (regs->msr & MSR_PR) 402 return; 403 404 /* 405 * Now test if the interrupt has hit a range that may be using 406 * HSPRG1 without having RI=0 (i.e., an HSRR interrupt). The 407 * problem ranges all run un-relocated. Test real and virt modes 408 * at the same time by droping the high bit of the nip (virt mode 409 * entry points still have the +0x4000 offset). 410 */ 411 nip &= ~0xc000000000000000ULL; 412 if ((nip >= 0x500 && nip < 0x600) || (nip >= 0x4500 && nip < 0x4600)) 413 goto nonrecoverable; 414 if ((nip >= 0x980 && nip < 0xa00) || (nip >= 0x4980 && nip < 0x4a00)) 415 goto nonrecoverable; 416 if ((nip >= 0xe00 && nip < 0xec0) || (nip >= 0x4e00 && nip < 0x4ec0)) 417 goto nonrecoverable; 418 if ((nip >= 0xf80 && nip < 0xfa0) || (nip >= 0x4f80 && nip < 0x4fa0)) 419 goto nonrecoverable; 420 421 /* Trampoline code runs un-relocated so subtract kbase. */ 422 if (nip >= (unsigned long)(start_real_trampolines - kbase) && 423 nip < (unsigned long)(end_real_trampolines - kbase)) 424 goto nonrecoverable; 425 if (nip >= (unsigned long)(start_virt_trampolines - kbase) && 426 nip < (unsigned long)(end_virt_trampolines - kbase)) 427 goto nonrecoverable; 428 return; 429 430 nonrecoverable: 431 regs->msr &= ~MSR_RI; 432 #endif 433 } 434 DEFINE_INTERRUPT_HANDLER_NMI(system_reset_exception) 435 { 436 unsigned long hsrr0, hsrr1; 437 bool saved_hsrrs = false; 438 439 /* 440 * System reset can interrupt code where HSRRs are live and MSR[RI]=1. 441 * The system reset interrupt itself may clobber HSRRs (e.g., to call 442 * OPAL), so save them here and restore them before returning. 443 * 444 * Machine checks don't need to save HSRRs, as the real mode handler 445 * is careful to avoid them, and the regular handler is not delivered 446 * as an NMI. 447 */ 448 if (cpu_has_feature(CPU_FTR_HVMODE)) { 449 hsrr0 = mfspr(SPRN_HSRR0); 450 hsrr1 = mfspr(SPRN_HSRR1); 451 saved_hsrrs = true; 452 } 453 454 hv_nmi_check_nonrecoverable(regs); 455 456 __this_cpu_inc(irq_stat.sreset_irqs); 457 458 /* See if any machine dependent calls */ 459 if (ppc_md.system_reset_exception) { 460 if (ppc_md.system_reset_exception(regs)) 461 goto out; 462 } 463 464 if (debugger(regs)) 465 goto out; 466 467 kmsg_dump(KMSG_DUMP_OOPS); 468 /* 469 * A system reset is a request to dump, so we always send 470 * it through the crashdump code (if fadump or kdump are 471 * registered). 472 */ 473 crash_fadump(regs, "System Reset"); 474 475 crash_kexec(regs); 476 477 /* 478 * We aren't the primary crash CPU. We need to send it 479 * to a holding pattern to avoid it ending up in the panic 480 * code. 481 */ 482 crash_kexec_secondary(regs); 483 484 /* 485 * No debugger or crash dump registered, print logs then 486 * panic. 487 */ 488 die("System Reset", regs, SIGABRT); 489 490 mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */ 491 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 492 nmi_panic(regs, "System Reset"); 493 494 out: 495 #ifdef CONFIG_PPC_BOOK3S_64 496 BUG_ON(get_paca()->in_nmi == 0); 497 if (get_paca()->in_nmi > 1) 498 die("Unrecoverable nested System Reset", regs, SIGABRT); 499 #endif 500 /* Must die if the interrupt is not recoverable */ 501 if (!(regs->msr & MSR_RI)) { 502 /* For the reason explained in die_mce, nmi_exit before die */ 503 nmi_exit(); 504 die("Unrecoverable System Reset", regs, SIGABRT); 505 } 506 507 if (saved_hsrrs) { 508 mtspr(SPRN_HSRR0, hsrr0); 509 mtspr(SPRN_HSRR1, hsrr1); 510 } 511 512 /* What should we do here? We could issue a shutdown or hard reset. */ 513 514 return 0; 515 } 516 517 /* 518 * I/O accesses can cause machine checks on powermacs. 519 * Check if the NIP corresponds to the address of a sync 520 * instruction for which there is an entry in the exception 521 * table. 522 * -- paulus. 523 */ 524 static inline int check_io_access(struct pt_regs *regs) 525 { 526 #ifdef CONFIG_PPC32 527 unsigned long msr = regs->msr; 528 const struct exception_table_entry *entry; 529 unsigned int *nip = (unsigned int *)regs->nip; 530 531 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) 532 && (entry = search_exception_tables(regs->nip)) != NULL) { 533 /* 534 * Check that it's a sync instruction, or somewhere 535 * in the twi; isync; nop sequence that inb/inw/inl uses. 536 * As the address is in the exception table 537 * we should be able to read the instr there. 538 * For the debug message, we look at the preceding 539 * load or store. 540 */ 541 if (*nip == PPC_INST_NOP) 542 nip -= 2; 543 else if (*nip == PPC_INST_ISYNC) 544 --nip; 545 if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) { 546 unsigned int rb; 547 548 --nip; 549 rb = (*nip >> 11) & 0x1f; 550 printk(KERN_DEBUG "%s bad port %lx at %p\n", 551 (*nip & 0x100)? "OUT to": "IN from", 552 regs->gpr[rb] - _IO_BASE, nip); 553 regs->msr |= MSR_RI; 554 regs->nip = extable_fixup(entry); 555 return 1; 556 } 557 } 558 #endif /* CONFIG_PPC32 */ 559 return 0; 560 } 561 562 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 563 /* On 4xx, the reason for the machine check or program exception 564 is in the ESR. */ 565 #define get_reason(regs) ((regs)->dsisr) 566 #define REASON_FP ESR_FP 567 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) 568 #define REASON_PRIVILEGED ESR_PPR 569 #define REASON_TRAP ESR_PTR 570 #define REASON_PREFIXED 0 571 #define REASON_BOUNDARY 0 572 573 /* single-step stuff */ 574 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC) 575 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC) 576 #define clear_br_trace(regs) do {} while(0) 577 #else 578 /* On non-4xx, the reason for the machine check or program 579 exception is in the MSR. */ 580 #define get_reason(regs) ((regs)->msr) 581 #define REASON_TM SRR1_PROGTM 582 #define REASON_FP SRR1_PROGFPE 583 #define REASON_ILLEGAL SRR1_PROGILL 584 #define REASON_PRIVILEGED SRR1_PROGPRIV 585 #define REASON_TRAP SRR1_PROGTRAP 586 #define REASON_PREFIXED SRR1_PREFIXED 587 #define REASON_BOUNDARY SRR1_BOUNDARY 588 589 #define single_stepping(regs) ((regs)->msr & MSR_SE) 590 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) 591 #define clear_br_trace(regs) ((regs)->msr &= ~MSR_BE) 592 #endif 593 594 #define inst_length(reason) (((reason) & REASON_PREFIXED) ? 8 : 4) 595 596 #if defined(CONFIG_E500) 597 int machine_check_e500mc(struct pt_regs *regs) 598 { 599 unsigned long mcsr = mfspr(SPRN_MCSR); 600 unsigned long pvr = mfspr(SPRN_PVR); 601 unsigned long reason = mcsr; 602 int recoverable = 1; 603 604 if (reason & MCSR_LD) { 605 recoverable = fsl_rio_mcheck_exception(regs); 606 if (recoverable == 1) 607 goto silent_out; 608 } 609 610 printk("Machine check in kernel mode.\n"); 611 printk("Caused by (from MCSR=%lx): ", reason); 612 613 if (reason & MCSR_MCP) 614 pr_cont("Machine Check Signal\n"); 615 616 if (reason & MCSR_ICPERR) { 617 pr_cont("Instruction Cache Parity Error\n"); 618 619 /* 620 * This is recoverable by invalidating the i-cache. 621 */ 622 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); 623 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) 624 ; 625 626 /* 627 * This will generally be accompanied by an instruction 628 * fetch error report -- only treat MCSR_IF as fatal 629 * if it wasn't due to an L1 parity error. 630 */ 631 reason &= ~MCSR_IF; 632 } 633 634 if (reason & MCSR_DCPERR_MC) { 635 pr_cont("Data Cache Parity Error\n"); 636 637 /* 638 * In write shadow mode we auto-recover from the error, but it 639 * may still get logged and cause a machine check. We should 640 * only treat the non-write shadow case as non-recoverable. 641 */ 642 /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit 643 * is not implemented but L1 data cache always runs in write 644 * shadow mode. Hence on data cache parity errors HW will 645 * automatically invalidate the L1 Data Cache. 646 */ 647 if (PVR_VER(pvr) != PVR_VER_E6500) { 648 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) 649 recoverable = 0; 650 } 651 } 652 653 if (reason & MCSR_L2MMU_MHIT) { 654 pr_cont("Hit on multiple TLB entries\n"); 655 recoverable = 0; 656 } 657 658 if (reason & MCSR_NMI) 659 pr_cont("Non-maskable interrupt\n"); 660 661 if (reason & MCSR_IF) { 662 pr_cont("Instruction Fetch Error Report\n"); 663 recoverable = 0; 664 } 665 666 if (reason & MCSR_LD) { 667 pr_cont("Load Error Report\n"); 668 recoverable = 0; 669 } 670 671 if (reason & MCSR_ST) { 672 pr_cont("Store Error Report\n"); 673 recoverable = 0; 674 } 675 676 if (reason & MCSR_LDG) { 677 pr_cont("Guarded Load Error Report\n"); 678 recoverable = 0; 679 } 680 681 if (reason & MCSR_TLBSYNC) 682 pr_cont("Simultaneous tlbsync operations\n"); 683 684 if (reason & MCSR_BSL2_ERR) { 685 pr_cont("Level 2 Cache Error\n"); 686 recoverable = 0; 687 } 688 689 if (reason & MCSR_MAV) { 690 u64 addr; 691 692 addr = mfspr(SPRN_MCAR); 693 addr |= (u64)mfspr(SPRN_MCARU) << 32; 694 695 pr_cont("Machine Check %s Address: %#llx\n", 696 reason & MCSR_MEA ? "Effective" : "Physical", addr); 697 } 698 699 silent_out: 700 mtspr(SPRN_MCSR, mcsr); 701 return mfspr(SPRN_MCSR) == 0 && recoverable; 702 } 703 704 int machine_check_e500(struct pt_regs *regs) 705 { 706 unsigned long reason = mfspr(SPRN_MCSR); 707 708 if (reason & MCSR_BUS_RBERR) { 709 if (fsl_rio_mcheck_exception(regs)) 710 return 1; 711 if (fsl_pci_mcheck_exception(regs)) 712 return 1; 713 } 714 715 printk("Machine check in kernel mode.\n"); 716 printk("Caused by (from MCSR=%lx): ", reason); 717 718 if (reason & MCSR_MCP) 719 pr_cont("Machine Check Signal\n"); 720 if (reason & MCSR_ICPERR) 721 pr_cont("Instruction Cache Parity Error\n"); 722 if (reason & MCSR_DCP_PERR) 723 pr_cont("Data Cache Push Parity Error\n"); 724 if (reason & MCSR_DCPERR) 725 pr_cont("Data Cache Parity Error\n"); 726 if (reason & MCSR_BUS_IAERR) 727 pr_cont("Bus - Instruction Address Error\n"); 728 if (reason & MCSR_BUS_RAERR) 729 pr_cont("Bus - Read Address Error\n"); 730 if (reason & MCSR_BUS_WAERR) 731 pr_cont("Bus - Write Address Error\n"); 732 if (reason & MCSR_BUS_IBERR) 733 pr_cont("Bus - Instruction Data Error\n"); 734 if (reason & MCSR_BUS_RBERR) 735 pr_cont("Bus - Read Data Bus Error\n"); 736 if (reason & MCSR_BUS_WBERR) 737 pr_cont("Bus - Write Data Bus Error\n"); 738 if (reason & MCSR_BUS_IPERR) 739 pr_cont("Bus - Instruction Parity Error\n"); 740 if (reason & MCSR_BUS_RPERR) 741 pr_cont("Bus - Read Parity Error\n"); 742 743 return 0; 744 } 745 746 int machine_check_generic(struct pt_regs *regs) 747 { 748 return 0; 749 } 750 #elif defined(CONFIG_PPC32) 751 int machine_check_generic(struct pt_regs *regs) 752 { 753 unsigned long reason = regs->msr; 754 755 printk("Machine check in kernel mode.\n"); 756 printk("Caused by (from SRR1=%lx): ", reason); 757 switch (reason & 0x601F0000) { 758 case 0x80000: 759 pr_cont("Machine check signal\n"); 760 break; 761 case 0x40000: 762 case 0x140000: /* 7450 MSS error and TEA */ 763 pr_cont("Transfer error ack signal\n"); 764 break; 765 case 0x20000: 766 pr_cont("Data parity error signal\n"); 767 break; 768 case 0x10000: 769 pr_cont("Address parity error signal\n"); 770 break; 771 case 0x20000000: 772 pr_cont("L1 Data Cache error\n"); 773 break; 774 case 0x40000000: 775 pr_cont("L1 Instruction Cache error\n"); 776 break; 777 case 0x00100000: 778 pr_cont("L2 data cache parity error\n"); 779 break; 780 default: 781 pr_cont("Unknown values in msr\n"); 782 } 783 return 0; 784 } 785 #endif /* everything else */ 786 787 void die_mce(const char *str, struct pt_regs *regs, long err) 788 { 789 /* 790 * The machine check wants to kill the interrupted context, but 791 * do_exit() checks for in_interrupt() and panics in that case, so 792 * exit the irq/nmi before calling die. 793 */ 794 if (IS_ENABLED(CONFIG_PPC_BOOK3S_64)) 795 irq_exit(); 796 else 797 nmi_exit(); 798 die(str, regs, err); 799 } 800 801 /* 802 * BOOK3S_64 does not call this handler as a non-maskable interrupt 803 * (it uses its own early real-mode handler to handle the MCE proper 804 * and then raises irq_work to call this handler when interrupts are 805 * enabled). 806 */ 807 #ifdef CONFIG_PPC_BOOK3S_64 808 DEFINE_INTERRUPT_HANDLER_ASYNC(machine_check_exception) 809 #else 810 DEFINE_INTERRUPT_HANDLER_NMI(machine_check_exception) 811 #endif 812 { 813 int recover = 0; 814 815 __this_cpu_inc(irq_stat.mce_exceptions); 816 817 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 818 819 /* See if any machine dependent calls. In theory, we would want 820 * to call the CPU first, and call the ppc_md. one if the CPU 821 * one returns a positive number. However there is existing code 822 * that assumes the board gets a first chance, so let's keep it 823 * that way for now and fix things later. --BenH. 824 */ 825 if (ppc_md.machine_check_exception) 826 recover = ppc_md.machine_check_exception(regs); 827 else if (cur_cpu_spec->machine_check) 828 recover = cur_cpu_spec->machine_check(regs); 829 830 if (recover > 0) 831 goto bail; 832 833 if (debugger_fault_handler(regs)) 834 goto bail; 835 836 if (check_io_access(regs)) 837 goto bail; 838 839 die_mce("Machine check", regs, SIGBUS); 840 841 bail: 842 /* Must die if the interrupt is not recoverable */ 843 if (!(regs->msr & MSR_RI)) 844 die_mce("Unrecoverable Machine check", regs, SIGBUS); 845 846 #ifdef CONFIG_PPC_BOOK3S_64 847 return; 848 #else 849 return 0; 850 #endif 851 } 852 853 DEFINE_INTERRUPT_HANDLER(SMIException) /* async? */ 854 { 855 die("System Management Interrupt", regs, SIGABRT); 856 } 857 858 #ifdef CONFIG_VSX 859 static void p9_hmi_special_emu(struct pt_regs *regs) 860 { 861 unsigned int ra, rb, t, i, sel, instr, rc; 862 const void __user *addr; 863 u8 vbuf[16] __aligned(16), *vdst; 864 unsigned long ea, msr, msr_mask; 865 bool swap; 866 867 if (__get_user_inatomic(instr, (unsigned int __user *)regs->nip)) 868 return; 869 870 /* 871 * lxvb16x opcode: 0x7c0006d8 872 * lxvd2x opcode: 0x7c000698 873 * lxvh8x opcode: 0x7c000658 874 * lxvw4x opcode: 0x7c000618 875 */ 876 if ((instr & 0xfc00073e) != 0x7c000618) { 877 pr_devel("HMI vec emu: not vector CI %i:%s[%d] nip=%016lx" 878 " instr=%08x\n", 879 smp_processor_id(), current->comm, current->pid, 880 regs->nip, instr); 881 return; 882 } 883 884 /* Grab vector registers into the task struct */ 885 msr = regs->msr; /* Grab msr before we flush the bits */ 886 flush_vsx_to_thread(current); 887 enable_kernel_altivec(); 888 889 /* 890 * Is userspace running with a different endian (this is rare but 891 * not impossible) 892 */ 893 swap = (msr & MSR_LE) != (MSR_KERNEL & MSR_LE); 894 895 /* Decode the instruction */ 896 ra = (instr >> 16) & 0x1f; 897 rb = (instr >> 11) & 0x1f; 898 t = (instr >> 21) & 0x1f; 899 if (instr & 1) 900 vdst = (u8 *)¤t->thread.vr_state.vr[t]; 901 else 902 vdst = (u8 *)¤t->thread.fp_state.fpr[t][0]; 903 904 /* Grab the vector address */ 905 ea = regs->gpr[rb] + (ra ? regs->gpr[ra] : 0); 906 if (is_32bit_task()) 907 ea &= 0xfffffffful; 908 addr = (__force const void __user *)ea; 909 910 /* Check it */ 911 if (!access_ok(addr, 16)) { 912 pr_devel("HMI vec emu: bad access %i:%s[%d] nip=%016lx" 913 " instr=%08x addr=%016lx\n", 914 smp_processor_id(), current->comm, current->pid, 915 regs->nip, instr, (unsigned long)addr); 916 return; 917 } 918 919 /* Read the vector */ 920 rc = 0; 921 if ((unsigned long)addr & 0xfUL) 922 /* unaligned case */ 923 rc = __copy_from_user_inatomic(vbuf, addr, 16); 924 else 925 __get_user_atomic_128_aligned(vbuf, addr, rc); 926 if (rc) { 927 pr_devel("HMI vec emu: page fault %i:%s[%d] nip=%016lx" 928 " instr=%08x addr=%016lx\n", 929 smp_processor_id(), current->comm, current->pid, 930 regs->nip, instr, (unsigned long)addr); 931 return; 932 } 933 934 pr_devel("HMI vec emu: emulated vector CI %i:%s[%d] nip=%016lx" 935 " instr=%08x addr=%016lx\n", 936 smp_processor_id(), current->comm, current->pid, regs->nip, 937 instr, (unsigned long) addr); 938 939 /* Grab instruction "selector" */ 940 sel = (instr >> 6) & 3; 941 942 /* 943 * Check to make sure the facility is actually enabled. This 944 * could happen if we get a false positive hit. 945 * 946 * lxvd2x/lxvw4x always check MSR VSX sel = 0,2 947 * lxvh8x/lxvb16x check MSR VSX or VEC depending on VSR used sel = 1,3 948 */ 949 msr_mask = MSR_VSX; 950 if ((sel & 1) && (instr & 1)) /* lxvh8x & lxvb16x + VSR >= 32 */ 951 msr_mask = MSR_VEC; 952 if (!(msr & msr_mask)) { 953 pr_devel("HMI vec emu: MSR fac clear %i:%s[%d] nip=%016lx" 954 " instr=%08x msr:%016lx\n", 955 smp_processor_id(), current->comm, current->pid, 956 regs->nip, instr, msr); 957 return; 958 } 959 960 /* Do logging here before we modify sel based on endian */ 961 switch (sel) { 962 case 0: /* lxvw4x */ 963 PPC_WARN_EMULATED(lxvw4x, regs); 964 break; 965 case 1: /* lxvh8x */ 966 PPC_WARN_EMULATED(lxvh8x, regs); 967 break; 968 case 2: /* lxvd2x */ 969 PPC_WARN_EMULATED(lxvd2x, regs); 970 break; 971 case 3: /* lxvb16x */ 972 PPC_WARN_EMULATED(lxvb16x, regs); 973 break; 974 } 975 976 #ifdef __LITTLE_ENDIAN__ 977 /* 978 * An LE kernel stores the vector in the task struct as an LE 979 * byte array (effectively swapping both the components and 980 * the content of the components). Those instructions expect 981 * the components to remain in ascending address order, so we 982 * swap them back. 983 * 984 * If we are running a BE user space, the expectation is that 985 * of a simple memcpy, so forcing the emulation to look like 986 * a lxvb16x should do the trick. 987 */ 988 if (swap) 989 sel = 3; 990 991 switch (sel) { 992 case 0: /* lxvw4x */ 993 for (i = 0; i < 4; i++) 994 ((u32 *)vdst)[i] = ((u32 *)vbuf)[3-i]; 995 break; 996 case 1: /* lxvh8x */ 997 for (i = 0; i < 8; i++) 998 ((u16 *)vdst)[i] = ((u16 *)vbuf)[7-i]; 999 break; 1000 case 2: /* lxvd2x */ 1001 for (i = 0; i < 2; i++) 1002 ((u64 *)vdst)[i] = ((u64 *)vbuf)[1-i]; 1003 break; 1004 case 3: /* lxvb16x */ 1005 for (i = 0; i < 16; i++) 1006 vdst[i] = vbuf[15-i]; 1007 break; 1008 } 1009 #else /* __LITTLE_ENDIAN__ */ 1010 /* On a big endian kernel, a BE userspace only needs a memcpy */ 1011 if (!swap) 1012 sel = 3; 1013 1014 /* Otherwise, we need to swap the content of the components */ 1015 switch (sel) { 1016 case 0: /* lxvw4x */ 1017 for (i = 0; i < 4; i++) 1018 ((u32 *)vdst)[i] = cpu_to_le32(((u32 *)vbuf)[i]); 1019 break; 1020 case 1: /* lxvh8x */ 1021 for (i = 0; i < 8; i++) 1022 ((u16 *)vdst)[i] = cpu_to_le16(((u16 *)vbuf)[i]); 1023 break; 1024 case 2: /* lxvd2x */ 1025 for (i = 0; i < 2; i++) 1026 ((u64 *)vdst)[i] = cpu_to_le64(((u64 *)vbuf)[i]); 1027 break; 1028 case 3: /* lxvb16x */ 1029 memcpy(vdst, vbuf, 16); 1030 break; 1031 } 1032 #endif /* !__LITTLE_ENDIAN__ */ 1033 1034 /* Go to next instruction */ 1035 regs->nip += 4; 1036 } 1037 #endif /* CONFIG_VSX */ 1038 1039 DEFINE_INTERRUPT_HANDLER_ASYNC(handle_hmi_exception) 1040 { 1041 struct pt_regs *old_regs; 1042 1043 old_regs = set_irq_regs(regs); 1044 1045 #ifdef CONFIG_VSX 1046 /* Real mode flagged P9 special emu is needed */ 1047 if (local_paca->hmi_p9_special_emu) { 1048 local_paca->hmi_p9_special_emu = 0; 1049 1050 /* 1051 * We don't want to take page faults while doing the 1052 * emulation, we just replay the instruction if necessary. 1053 */ 1054 pagefault_disable(); 1055 p9_hmi_special_emu(regs); 1056 pagefault_enable(); 1057 } 1058 #endif /* CONFIG_VSX */ 1059 1060 if (ppc_md.handle_hmi_exception) 1061 ppc_md.handle_hmi_exception(regs); 1062 1063 set_irq_regs(old_regs); 1064 } 1065 1066 DEFINE_INTERRUPT_HANDLER(unknown_exception) 1067 { 1068 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 1069 regs->nip, regs->msr, regs->trap); 1070 1071 _exception(SIGTRAP, regs, TRAP_UNK, 0); 1072 } 1073 1074 DEFINE_INTERRUPT_HANDLER_ASYNC(unknown_async_exception) 1075 { 1076 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 1077 regs->nip, regs->msr, regs->trap); 1078 1079 _exception(SIGTRAP, regs, TRAP_UNK, 0); 1080 } 1081 1082 DEFINE_INTERRUPT_HANDLER(instruction_breakpoint_exception) 1083 { 1084 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, 1085 5, SIGTRAP) == NOTIFY_STOP) 1086 return; 1087 if (debugger_iabr_match(regs)) 1088 return; 1089 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1090 } 1091 1092 DEFINE_INTERRUPT_HANDLER(RunModeException) 1093 { 1094 _exception(SIGTRAP, regs, TRAP_UNK, 0); 1095 } 1096 1097 DEFINE_INTERRUPT_HANDLER(single_step_exception) 1098 { 1099 clear_single_step(regs); 1100 clear_br_trace(regs); 1101 1102 if (kprobe_post_handler(regs)) 1103 return; 1104 1105 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 1106 5, SIGTRAP) == NOTIFY_STOP) 1107 return; 1108 if (debugger_sstep(regs)) 1109 return; 1110 1111 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 1112 } 1113 1114 /* 1115 * After we have successfully emulated an instruction, we have to 1116 * check if the instruction was being single-stepped, and if so, 1117 * pretend we got a single-step exception. This was pointed out 1118 * by Kumar Gala. -- paulus 1119 */ 1120 static void emulate_single_step(struct pt_regs *regs) 1121 { 1122 if (single_stepping(regs)) 1123 single_step_exception(regs); 1124 } 1125 1126 static inline int __parse_fpscr(unsigned long fpscr) 1127 { 1128 int ret = FPE_FLTUNK; 1129 1130 /* Invalid operation */ 1131 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) 1132 ret = FPE_FLTINV; 1133 1134 /* Overflow */ 1135 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) 1136 ret = FPE_FLTOVF; 1137 1138 /* Underflow */ 1139 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) 1140 ret = FPE_FLTUND; 1141 1142 /* Divide by zero */ 1143 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) 1144 ret = FPE_FLTDIV; 1145 1146 /* Inexact result */ 1147 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) 1148 ret = FPE_FLTRES; 1149 1150 return ret; 1151 } 1152 1153 static void parse_fpe(struct pt_regs *regs) 1154 { 1155 int code = 0; 1156 1157 flush_fp_to_thread(current); 1158 1159 #ifdef CONFIG_PPC_FPU_REGS 1160 code = __parse_fpscr(current->thread.fp_state.fpscr); 1161 #endif 1162 1163 _exception(SIGFPE, regs, code, regs->nip); 1164 } 1165 1166 /* 1167 * Illegal instruction emulation support. Originally written to 1168 * provide the PVR to user applications using the mfspr rd, PVR. 1169 * Return non-zero if we can't emulate, or -EFAULT if the associated 1170 * memory access caused an access fault. Return zero on success. 1171 * 1172 * There are a couple of ways to do this, either "decode" the instruction 1173 * or directly match lots of bits. In this case, matching lots of 1174 * bits is faster and easier. 1175 * 1176 */ 1177 static int emulate_string_inst(struct pt_regs *regs, u32 instword) 1178 { 1179 u8 rT = (instword >> 21) & 0x1f; 1180 u8 rA = (instword >> 16) & 0x1f; 1181 u8 NB_RB = (instword >> 11) & 0x1f; 1182 u32 num_bytes; 1183 unsigned long EA; 1184 int pos = 0; 1185 1186 /* Early out if we are an invalid form of lswx */ 1187 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) 1188 if ((rT == rA) || (rT == NB_RB)) 1189 return -EINVAL; 1190 1191 EA = (rA == 0) ? 0 : regs->gpr[rA]; 1192 1193 switch (instword & PPC_INST_STRING_MASK) { 1194 case PPC_INST_LSWX: 1195 case PPC_INST_STSWX: 1196 EA += NB_RB; 1197 num_bytes = regs->xer & 0x7f; 1198 break; 1199 case PPC_INST_LSWI: 1200 case PPC_INST_STSWI: 1201 num_bytes = (NB_RB == 0) ? 32 : NB_RB; 1202 break; 1203 default: 1204 return -EINVAL; 1205 } 1206 1207 while (num_bytes != 0) 1208 { 1209 u8 val; 1210 u32 shift = 8 * (3 - (pos & 0x3)); 1211 1212 /* if process is 32-bit, clear upper 32 bits of EA */ 1213 if ((regs->msr & MSR_64BIT) == 0) 1214 EA &= 0xFFFFFFFF; 1215 1216 switch ((instword & PPC_INST_STRING_MASK)) { 1217 case PPC_INST_LSWX: 1218 case PPC_INST_LSWI: 1219 if (get_user(val, (u8 __user *)EA)) 1220 return -EFAULT; 1221 /* first time updating this reg, 1222 * zero it out */ 1223 if (pos == 0) 1224 regs->gpr[rT] = 0; 1225 regs->gpr[rT] |= val << shift; 1226 break; 1227 case PPC_INST_STSWI: 1228 case PPC_INST_STSWX: 1229 val = regs->gpr[rT] >> shift; 1230 if (put_user(val, (u8 __user *)EA)) 1231 return -EFAULT; 1232 break; 1233 } 1234 /* move EA to next address */ 1235 EA += 1; 1236 num_bytes--; 1237 1238 /* manage our position within the register */ 1239 if (++pos == 4) { 1240 pos = 0; 1241 if (++rT == 32) 1242 rT = 0; 1243 } 1244 } 1245 1246 return 0; 1247 } 1248 1249 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) 1250 { 1251 u32 ra,rs; 1252 unsigned long tmp; 1253 1254 ra = (instword >> 16) & 0x1f; 1255 rs = (instword >> 21) & 0x1f; 1256 1257 tmp = regs->gpr[rs]; 1258 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); 1259 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); 1260 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; 1261 regs->gpr[ra] = tmp; 1262 1263 return 0; 1264 } 1265 1266 static int emulate_isel(struct pt_regs *regs, u32 instword) 1267 { 1268 u8 rT = (instword >> 21) & 0x1f; 1269 u8 rA = (instword >> 16) & 0x1f; 1270 u8 rB = (instword >> 11) & 0x1f; 1271 u8 BC = (instword >> 6) & 0x1f; 1272 u8 bit; 1273 unsigned long tmp; 1274 1275 tmp = (rA == 0) ? 0 : regs->gpr[rA]; 1276 bit = (regs->ccr >> (31 - BC)) & 0x1; 1277 1278 regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; 1279 1280 return 0; 1281 } 1282 1283 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1284 static inline bool tm_abort_check(struct pt_regs *regs, int cause) 1285 { 1286 /* If we're emulating a load/store in an active transaction, we cannot 1287 * emulate it as the kernel operates in transaction suspended context. 1288 * We need to abort the transaction. This creates a persistent TM 1289 * abort so tell the user what caused it with a new code. 1290 */ 1291 if (MSR_TM_TRANSACTIONAL(regs->msr)) { 1292 tm_enable(); 1293 tm_abort(cause); 1294 return true; 1295 } 1296 return false; 1297 } 1298 #else 1299 static inline bool tm_abort_check(struct pt_regs *regs, int reason) 1300 { 1301 return false; 1302 } 1303 #endif 1304 1305 static int emulate_instruction(struct pt_regs *regs) 1306 { 1307 u32 instword; 1308 u32 rd; 1309 1310 if (!user_mode(regs)) 1311 return -EINVAL; 1312 CHECK_FULL_REGS(regs); 1313 1314 if (get_user(instword, (u32 __user *)(regs->nip))) 1315 return -EFAULT; 1316 1317 /* Emulate the mfspr rD, PVR. */ 1318 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { 1319 PPC_WARN_EMULATED(mfpvr, regs); 1320 rd = (instword >> 21) & 0x1f; 1321 regs->gpr[rd] = mfspr(SPRN_PVR); 1322 return 0; 1323 } 1324 1325 /* Emulating the dcba insn is just a no-op. */ 1326 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { 1327 PPC_WARN_EMULATED(dcba, regs); 1328 return 0; 1329 } 1330 1331 /* Emulate the mcrxr insn. */ 1332 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { 1333 int shift = (instword >> 21) & 0x1c; 1334 unsigned long msk = 0xf0000000UL >> shift; 1335 1336 PPC_WARN_EMULATED(mcrxr, regs); 1337 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); 1338 regs->xer &= ~0xf0000000UL; 1339 return 0; 1340 } 1341 1342 /* Emulate load/store string insn. */ 1343 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { 1344 if (tm_abort_check(regs, 1345 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) 1346 return -EINVAL; 1347 PPC_WARN_EMULATED(string, regs); 1348 return emulate_string_inst(regs, instword); 1349 } 1350 1351 /* Emulate the popcntb (Population Count Bytes) instruction. */ 1352 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { 1353 PPC_WARN_EMULATED(popcntb, regs); 1354 return emulate_popcntb_inst(regs, instword); 1355 } 1356 1357 /* Emulate isel (Integer Select) instruction */ 1358 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { 1359 PPC_WARN_EMULATED(isel, regs); 1360 return emulate_isel(regs, instword); 1361 } 1362 1363 /* Emulate sync instruction variants */ 1364 if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) { 1365 PPC_WARN_EMULATED(sync, regs); 1366 asm volatile("sync"); 1367 return 0; 1368 } 1369 1370 #ifdef CONFIG_PPC64 1371 /* Emulate the mfspr rD, DSCR. */ 1372 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) == 1373 PPC_INST_MFSPR_DSCR_USER) || 1374 ((instword & PPC_INST_MFSPR_DSCR_MASK) == 1375 PPC_INST_MFSPR_DSCR)) && 1376 cpu_has_feature(CPU_FTR_DSCR)) { 1377 PPC_WARN_EMULATED(mfdscr, regs); 1378 rd = (instword >> 21) & 0x1f; 1379 regs->gpr[rd] = mfspr(SPRN_DSCR); 1380 return 0; 1381 } 1382 /* Emulate the mtspr DSCR, rD. */ 1383 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) == 1384 PPC_INST_MTSPR_DSCR_USER) || 1385 ((instword & PPC_INST_MTSPR_DSCR_MASK) == 1386 PPC_INST_MTSPR_DSCR)) && 1387 cpu_has_feature(CPU_FTR_DSCR)) { 1388 PPC_WARN_EMULATED(mtdscr, regs); 1389 rd = (instword >> 21) & 0x1f; 1390 current->thread.dscr = regs->gpr[rd]; 1391 current->thread.dscr_inherit = 1; 1392 mtspr(SPRN_DSCR, current->thread.dscr); 1393 return 0; 1394 } 1395 #endif 1396 1397 return -EINVAL; 1398 } 1399 1400 int is_valid_bugaddr(unsigned long addr) 1401 { 1402 return is_kernel_addr(addr); 1403 } 1404 1405 #ifdef CONFIG_MATH_EMULATION 1406 static int emulate_math(struct pt_regs *regs) 1407 { 1408 int ret; 1409 extern int do_mathemu(struct pt_regs *regs); 1410 1411 ret = do_mathemu(regs); 1412 if (ret >= 0) 1413 PPC_WARN_EMULATED(math, regs); 1414 1415 switch (ret) { 1416 case 0: 1417 emulate_single_step(regs); 1418 return 0; 1419 case 1: { 1420 int code = 0; 1421 code = __parse_fpscr(current->thread.fp_state.fpscr); 1422 _exception(SIGFPE, regs, code, regs->nip); 1423 return 0; 1424 } 1425 case -EFAULT: 1426 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1427 return 0; 1428 } 1429 1430 return -1; 1431 } 1432 #else 1433 static inline int emulate_math(struct pt_regs *regs) { return -1; } 1434 #endif 1435 1436 static void do_program_check(struct pt_regs *regs) 1437 { 1438 unsigned int reason = get_reason(regs); 1439 1440 /* We can now get here via a FP Unavailable exception if the core 1441 * has no FPU, in that case the reason flags will be 0 */ 1442 1443 if (reason & REASON_FP) { 1444 /* IEEE FP exception */ 1445 parse_fpe(regs); 1446 return; 1447 } 1448 if (reason & REASON_TRAP) { 1449 unsigned long bugaddr; 1450 /* Debugger is first in line to stop recursive faults in 1451 * rcu_lock, notify_die, or atomic_notifier_call_chain */ 1452 if (debugger_bpt(regs)) 1453 return; 1454 1455 if (kprobe_handler(regs)) 1456 return; 1457 1458 /* trap exception */ 1459 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) 1460 == NOTIFY_STOP) 1461 return; 1462 1463 bugaddr = regs->nip; 1464 /* 1465 * Fixup bugaddr for BUG_ON() in real mode 1466 */ 1467 if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR)) 1468 bugaddr += PAGE_OFFSET; 1469 1470 if (!(regs->msr & MSR_PR) && /* not user-mode */ 1471 report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) { 1472 regs->nip += 4; 1473 return; 1474 } 1475 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 1476 return; 1477 } 1478 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1479 if (reason & REASON_TM) { 1480 /* This is a TM "Bad Thing Exception" program check. 1481 * This occurs when: 1482 * - An rfid/hrfid/mtmsrd attempts to cause an illegal 1483 * transition in TM states. 1484 * - A trechkpt is attempted when transactional. 1485 * - A treclaim is attempted when non transactional. 1486 * - A tend is illegally attempted. 1487 * - writing a TM SPR when transactional. 1488 * 1489 * If usermode caused this, it's done something illegal and 1490 * gets a SIGILL slap on the wrist. We call it an illegal 1491 * operand to distinguish from the instruction just being bad 1492 * (e.g. executing a 'tend' on a CPU without TM!); it's an 1493 * illegal /placement/ of a valid instruction. 1494 */ 1495 if (user_mode(regs)) { 1496 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip); 1497 return; 1498 } else { 1499 printk(KERN_EMERG "Unexpected TM Bad Thing exception " 1500 "at %lx (msr 0x%lx) tm_scratch=%llx\n", 1501 regs->nip, regs->msr, get_paca()->tm_scratch); 1502 die("Unrecoverable exception", regs, SIGABRT); 1503 } 1504 } 1505 #endif 1506 1507 /* 1508 * If we took the program check in the kernel skip down to sending a 1509 * SIGILL. The subsequent cases all relate to emulating instructions 1510 * which we should only do for userspace. We also do not want to enable 1511 * interrupts for kernel faults because that might lead to further 1512 * faults, and loose the context of the original exception. 1513 */ 1514 if (!user_mode(regs)) 1515 goto sigill; 1516 1517 interrupt_cond_local_irq_enable(regs); 1518 1519 /* (reason & REASON_ILLEGAL) would be the obvious thing here, 1520 * but there seems to be a hardware bug on the 405GP (RevD) 1521 * that means ESR is sometimes set incorrectly - either to 1522 * ESR_DST (!?) or 0. In the process of chasing this with the 1523 * hardware people - not sure if it can happen on any illegal 1524 * instruction or only on FP instructions, whether there is a 1525 * pattern to occurrences etc. -dgibson 31/Mar/2003 1526 */ 1527 if (!emulate_math(regs)) 1528 return; 1529 1530 /* Try to emulate it if we should. */ 1531 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { 1532 switch (emulate_instruction(regs)) { 1533 case 0: 1534 regs->nip += 4; 1535 emulate_single_step(regs); 1536 return; 1537 case -EFAULT: 1538 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 1539 return; 1540 } 1541 } 1542 1543 sigill: 1544 if (reason & REASON_PRIVILEGED) 1545 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 1546 else 1547 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1548 1549 } 1550 1551 DEFINE_INTERRUPT_HANDLER(program_check_exception) 1552 { 1553 do_program_check(regs); 1554 } 1555 1556 /* 1557 * This occurs when running in hypervisor mode on POWER6 or later 1558 * and an illegal instruction is encountered. 1559 */ 1560 DEFINE_INTERRUPT_HANDLER(emulation_assist_interrupt) 1561 { 1562 regs->msr |= REASON_ILLEGAL; 1563 do_program_check(regs); 1564 } 1565 1566 DEFINE_INTERRUPT_HANDLER(alignment_exception) 1567 { 1568 int sig, code, fixed = 0; 1569 unsigned long reason; 1570 1571 interrupt_cond_local_irq_enable(regs); 1572 1573 reason = get_reason(regs); 1574 if (reason & REASON_BOUNDARY) { 1575 sig = SIGBUS; 1576 code = BUS_ADRALN; 1577 goto bad; 1578 } 1579 1580 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT)) 1581 return; 1582 1583 /* we don't implement logging of alignment exceptions */ 1584 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) 1585 fixed = fix_alignment(regs); 1586 1587 if (fixed == 1) { 1588 /* skip over emulated instruction */ 1589 regs->nip += inst_length(reason); 1590 emulate_single_step(regs); 1591 return; 1592 } 1593 1594 /* Operand address was bad */ 1595 if (fixed == -EFAULT) { 1596 sig = SIGSEGV; 1597 code = SEGV_ACCERR; 1598 } else { 1599 sig = SIGBUS; 1600 code = BUS_ADRALN; 1601 } 1602 bad: 1603 if (user_mode(regs)) 1604 _exception(sig, regs, code, regs->dar); 1605 else 1606 bad_page_fault(regs, sig); 1607 } 1608 1609 DEFINE_INTERRUPT_HANDLER(StackOverflow) 1610 { 1611 pr_crit("Kernel stack overflow in process %s[%d], r1=%lx\n", 1612 current->comm, task_pid_nr(current), regs->gpr[1]); 1613 debugger(regs); 1614 show_regs(regs); 1615 panic("kernel stack overflow"); 1616 } 1617 1618 DEFINE_INTERRUPT_HANDLER(stack_overflow_exception) 1619 { 1620 die("Kernel stack overflow", regs, SIGSEGV); 1621 } 1622 1623 DEFINE_INTERRUPT_HANDLER(kernel_fp_unavailable_exception) 1624 { 1625 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " 1626 "%lx at %lx\n", regs->trap, regs->nip); 1627 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); 1628 } 1629 1630 DEFINE_INTERRUPT_HANDLER(altivec_unavailable_exception) 1631 { 1632 if (user_mode(regs)) { 1633 /* A user program has executed an altivec instruction, 1634 but this kernel doesn't support altivec. */ 1635 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1636 return; 1637 } 1638 1639 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " 1640 "%lx at %lx\n", regs->trap, regs->nip); 1641 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); 1642 } 1643 1644 DEFINE_INTERRUPT_HANDLER(vsx_unavailable_exception) 1645 { 1646 if (user_mode(regs)) { 1647 /* A user program has executed an vsx instruction, 1648 but this kernel doesn't support vsx. */ 1649 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1650 return; 1651 } 1652 1653 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " 1654 "%lx at %lx\n", regs->trap, regs->nip); 1655 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); 1656 } 1657 1658 #ifdef CONFIG_PPC64 1659 static void tm_unavailable(struct pt_regs *regs) 1660 { 1661 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1662 if (user_mode(regs)) { 1663 current->thread.load_tm++; 1664 regs->msr |= MSR_TM; 1665 tm_enable(); 1666 tm_restore_sprs(¤t->thread); 1667 return; 1668 } 1669 #endif 1670 pr_emerg("Unrecoverable TM Unavailable Exception " 1671 "%lx at %lx\n", regs->trap, regs->nip); 1672 die("Unrecoverable TM Unavailable Exception", regs, SIGABRT); 1673 } 1674 1675 DEFINE_INTERRUPT_HANDLER(facility_unavailable_exception) 1676 { 1677 static char *facility_strings[] = { 1678 [FSCR_FP_LG] = "FPU", 1679 [FSCR_VECVSX_LG] = "VMX/VSX", 1680 [FSCR_DSCR_LG] = "DSCR", 1681 [FSCR_PM_LG] = "PMU SPRs", 1682 [FSCR_BHRB_LG] = "BHRB", 1683 [FSCR_TM_LG] = "TM", 1684 [FSCR_EBB_LG] = "EBB", 1685 [FSCR_TAR_LG] = "TAR", 1686 [FSCR_MSGP_LG] = "MSGP", 1687 [FSCR_SCV_LG] = "SCV", 1688 [FSCR_PREFIX_LG] = "PREFIX", 1689 }; 1690 char *facility = "unknown"; 1691 u64 value; 1692 u32 instword, rd; 1693 u8 status; 1694 bool hv; 1695 1696 hv = (TRAP(regs) == 0xf80); 1697 if (hv) 1698 value = mfspr(SPRN_HFSCR); 1699 else 1700 value = mfspr(SPRN_FSCR); 1701 1702 status = value >> 56; 1703 if ((hv || status >= 2) && 1704 (status < ARRAY_SIZE(facility_strings)) && 1705 facility_strings[status]) 1706 facility = facility_strings[status]; 1707 1708 /* We should not have taken this interrupt in kernel */ 1709 if (!user_mode(regs)) { 1710 pr_emerg("Facility '%s' unavailable (%d) exception in kernel mode at %lx\n", 1711 facility, status, regs->nip); 1712 die("Unexpected facility unavailable exception", regs, SIGABRT); 1713 } 1714 1715 interrupt_cond_local_irq_enable(regs); 1716 1717 if (status == FSCR_DSCR_LG) { 1718 /* 1719 * User is accessing the DSCR register using the problem 1720 * state only SPR number (0x03) either through a mfspr or 1721 * a mtspr instruction. If it is a write attempt through 1722 * a mtspr, then we set the inherit bit. This also allows 1723 * the user to write or read the register directly in the 1724 * future by setting via the FSCR DSCR bit. But in case it 1725 * is a read DSCR attempt through a mfspr instruction, we 1726 * just emulate the instruction instead. This code path will 1727 * always emulate all the mfspr instructions till the user 1728 * has attempted at least one mtspr instruction. This way it 1729 * preserves the same behaviour when the user is accessing 1730 * the DSCR through privilege level only SPR number (0x11) 1731 * which is emulated through illegal instruction exception. 1732 * We always leave HFSCR DSCR set. 1733 */ 1734 if (get_user(instword, (u32 __user *)(regs->nip))) { 1735 pr_err("Failed to fetch the user instruction\n"); 1736 return; 1737 } 1738 1739 /* Write into DSCR (mtspr 0x03, RS) */ 1740 if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK) 1741 == PPC_INST_MTSPR_DSCR_USER) { 1742 rd = (instword >> 21) & 0x1f; 1743 current->thread.dscr = regs->gpr[rd]; 1744 current->thread.dscr_inherit = 1; 1745 current->thread.fscr |= FSCR_DSCR; 1746 mtspr(SPRN_FSCR, current->thread.fscr); 1747 } 1748 1749 /* Read from DSCR (mfspr RT, 0x03) */ 1750 if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK) 1751 == PPC_INST_MFSPR_DSCR_USER) { 1752 if (emulate_instruction(regs)) { 1753 pr_err("DSCR based mfspr emulation failed\n"); 1754 return; 1755 } 1756 regs->nip += 4; 1757 emulate_single_step(regs); 1758 } 1759 return; 1760 } 1761 1762 if (status == FSCR_TM_LG) { 1763 /* 1764 * If we're here then the hardware is TM aware because it 1765 * generated an exception with FSRM_TM set. 1766 * 1767 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware 1768 * told us not to do TM, or the kernel is not built with TM 1769 * support. 1770 * 1771 * If both of those things are true, then userspace can spam the 1772 * console by triggering the printk() below just by continually 1773 * doing tbegin (or any TM instruction). So in that case just 1774 * send the process a SIGILL immediately. 1775 */ 1776 if (!cpu_has_feature(CPU_FTR_TM)) 1777 goto out; 1778 1779 tm_unavailable(regs); 1780 return; 1781 } 1782 1783 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n", 1784 hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr); 1785 1786 out: 1787 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 1788 } 1789 #endif 1790 1791 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1792 1793 DEFINE_INTERRUPT_HANDLER(fp_unavailable_tm) 1794 { 1795 /* Note: This does not handle any kind of FP laziness. */ 1796 1797 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n", 1798 regs->nip, regs->msr); 1799 1800 /* We can only have got here if the task started using FP after 1801 * beginning the transaction. So, the transactional regs are just a 1802 * copy of the checkpointed ones. But, we still need to recheckpoint 1803 * as we're enabling FP for the process; it will return, abort the 1804 * transaction, and probably retry but now with FP enabled. So the 1805 * checkpointed FP registers need to be loaded. 1806 */ 1807 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1808 1809 /* 1810 * Reclaim initially saved out bogus (lazy) FPRs to ckfp_state, and 1811 * then it was overwrite by the thr->fp_state by tm_reclaim_thread(). 1812 * 1813 * At this point, ck{fp,vr}_state contains the exact values we want to 1814 * recheckpoint. 1815 */ 1816 1817 /* Enable FP for the task: */ 1818 current->thread.load_fp = 1; 1819 1820 /* 1821 * Recheckpoint all the checkpointed ckpt, ck{fp, vr}_state registers. 1822 */ 1823 tm_recheckpoint(¤t->thread); 1824 } 1825 1826 DEFINE_INTERRUPT_HANDLER(altivec_unavailable_tm) 1827 { 1828 /* See the comments in fp_unavailable_tm(). This function operates 1829 * the same way. 1830 */ 1831 1832 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx," 1833 "MSR=%lx\n", 1834 regs->nip, regs->msr); 1835 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1836 current->thread.load_vec = 1; 1837 tm_recheckpoint(¤t->thread); 1838 current->thread.used_vr = 1; 1839 } 1840 1841 DEFINE_INTERRUPT_HANDLER(vsx_unavailable_tm) 1842 { 1843 /* See the comments in fp_unavailable_tm(). This works similarly, 1844 * though we're loading both FP and VEC registers in here. 1845 * 1846 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC 1847 * regs. Either way, set MSR_VSX. 1848 */ 1849 1850 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx," 1851 "MSR=%lx\n", 1852 regs->nip, regs->msr); 1853 1854 current->thread.used_vsr = 1; 1855 1856 /* This reclaims FP and/or VR regs if they're already enabled */ 1857 tm_reclaim_current(TM_CAUSE_FAC_UNAV); 1858 1859 current->thread.load_vec = 1; 1860 current->thread.load_fp = 1; 1861 1862 tm_recheckpoint(¤t->thread); 1863 } 1864 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 1865 1866 #ifdef CONFIG_PPC64 1867 DECLARE_INTERRUPT_HANDLER_NMI(performance_monitor_exception_nmi); 1868 DEFINE_INTERRUPT_HANDLER_NMI(performance_monitor_exception_nmi) 1869 { 1870 __this_cpu_inc(irq_stat.pmu_irqs); 1871 1872 perf_irq(regs); 1873 1874 return 0; 1875 } 1876 #endif 1877 1878 DECLARE_INTERRUPT_HANDLER_ASYNC(performance_monitor_exception_async); 1879 DEFINE_INTERRUPT_HANDLER_ASYNC(performance_monitor_exception_async) 1880 { 1881 __this_cpu_inc(irq_stat.pmu_irqs); 1882 1883 perf_irq(regs); 1884 } 1885 1886 DEFINE_INTERRUPT_HANDLER_RAW(performance_monitor_exception) 1887 { 1888 /* 1889 * On 64-bit, if perf interrupts hit in a local_irq_disable 1890 * (soft-masked) region, we consider them as NMIs. This is required to 1891 * prevent hash faults on user addresses when reading callchains (and 1892 * looks better from an irq tracing perspective). 1893 */ 1894 if (IS_ENABLED(CONFIG_PPC64) && unlikely(arch_irq_disabled_regs(regs))) 1895 performance_monitor_exception_nmi(regs); 1896 else 1897 performance_monitor_exception_async(regs); 1898 1899 return 0; 1900 } 1901 1902 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 1903 static void handle_debug(struct pt_regs *regs, unsigned long debug_status) 1904 { 1905 int changed = 0; 1906 /* 1907 * Determine the cause of the debug event, clear the 1908 * event flags and send a trap to the handler. Torez 1909 */ 1910 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { 1911 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); 1912 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1913 current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; 1914 #endif 1915 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, 1916 5); 1917 changed |= 0x01; 1918 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { 1919 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); 1920 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, 1921 6); 1922 changed |= 0x01; 1923 } else if (debug_status & DBSR_IAC1) { 1924 current->thread.debug.dbcr0 &= ~DBCR0_IAC1; 1925 dbcr_iac_range(current) &= ~DBCR_IAC12MODE; 1926 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, 1927 1); 1928 changed |= 0x01; 1929 } else if (debug_status & DBSR_IAC2) { 1930 current->thread.debug.dbcr0 &= ~DBCR0_IAC2; 1931 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, 1932 2); 1933 changed |= 0x01; 1934 } else if (debug_status & DBSR_IAC3) { 1935 current->thread.debug.dbcr0 &= ~DBCR0_IAC3; 1936 dbcr_iac_range(current) &= ~DBCR_IAC34MODE; 1937 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, 1938 3); 1939 changed |= 0x01; 1940 } else if (debug_status & DBSR_IAC4) { 1941 current->thread.debug.dbcr0 &= ~DBCR0_IAC4; 1942 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, 1943 4); 1944 changed |= 0x01; 1945 } 1946 /* 1947 * At the point this routine was called, the MSR(DE) was turned off. 1948 * Check all other debug flags and see if that bit needs to be turned 1949 * back on or not. 1950 */ 1951 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 1952 current->thread.debug.dbcr1)) 1953 regs->msr |= MSR_DE; 1954 else 1955 /* Make sure the IDM flag is off */ 1956 current->thread.debug.dbcr0 &= ~DBCR0_IDM; 1957 1958 if (changed & 0x01) 1959 mtspr(SPRN_DBCR0, current->thread.debug.dbcr0); 1960 } 1961 1962 DEFINE_INTERRUPT_HANDLER(DebugException) 1963 { 1964 unsigned long debug_status = regs->dsisr; 1965 1966 current->thread.debug.dbsr = debug_status; 1967 1968 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while 1969 * on server, it stops on the target of the branch. In order to simulate 1970 * the server behaviour, we thus restart right away with a single step 1971 * instead of stopping here when hitting a BT 1972 */ 1973 if (debug_status & DBSR_BT) { 1974 regs->msr &= ~MSR_DE; 1975 1976 /* Disable BT */ 1977 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); 1978 /* Clear the BT event */ 1979 mtspr(SPRN_DBSR, DBSR_BT); 1980 1981 /* Do the single step trick only when coming from userspace */ 1982 if (user_mode(regs)) { 1983 current->thread.debug.dbcr0 &= ~DBCR0_BT; 1984 current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; 1985 regs->msr |= MSR_DE; 1986 return; 1987 } 1988 1989 if (kprobe_post_handler(regs)) 1990 return; 1991 1992 if (notify_die(DIE_SSTEP, "block_step", regs, 5, 1993 5, SIGTRAP) == NOTIFY_STOP) { 1994 return; 1995 } 1996 if (debugger_sstep(regs)) 1997 return; 1998 } else if (debug_status & DBSR_IC) { /* Instruction complete */ 1999 regs->msr &= ~MSR_DE; 2000 2001 /* Disable instruction completion */ 2002 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); 2003 /* Clear the instruction completion event */ 2004 mtspr(SPRN_DBSR, DBSR_IC); 2005 2006 if (kprobe_post_handler(regs)) 2007 return; 2008 2009 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 2010 5, SIGTRAP) == NOTIFY_STOP) { 2011 return; 2012 } 2013 2014 if (debugger_sstep(regs)) 2015 return; 2016 2017 if (user_mode(regs)) { 2018 current->thread.debug.dbcr0 &= ~DBCR0_IC; 2019 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, 2020 current->thread.debug.dbcr1)) 2021 regs->msr |= MSR_DE; 2022 else 2023 /* Make sure the IDM bit is off */ 2024 current->thread.debug.dbcr0 &= ~DBCR0_IDM; 2025 } 2026 2027 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 2028 } else 2029 handle_debug(regs, debug_status); 2030 } 2031 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 2032 2033 #ifdef CONFIG_ALTIVEC 2034 DEFINE_INTERRUPT_HANDLER(altivec_assist_exception) 2035 { 2036 int err; 2037 2038 if (!user_mode(regs)) { 2039 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" 2040 " at %lx\n", regs->nip); 2041 die("Kernel VMX/Altivec assist exception", regs, SIGILL); 2042 } 2043 2044 flush_altivec_to_thread(current); 2045 2046 PPC_WARN_EMULATED(altivec, regs); 2047 err = emulate_altivec(regs); 2048 if (err == 0) { 2049 regs->nip += 4; /* skip emulated instruction */ 2050 emulate_single_step(regs); 2051 return; 2052 } 2053 2054 if (err == -EFAULT) { 2055 /* got an error reading the instruction */ 2056 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2057 } else { 2058 /* didn't recognize the instruction */ 2059 /* XXX quick hack for now: set the non-Java bit in the VSCR */ 2060 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " 2061 "in %s at %lx\n", current->comm, regs->nip); 2062 current->thread.vr_state.vscr.u[3] |= 0x10000; 2063 } 2064 } 2065 #endif /* CONFIG_ALTIVEC */ 2066 2067 #ifdef CONFIG_FSL_BOOKE 2068 DEFINE_INTERRUPT_HANDLER(CacheLockingException) 2069 { 2070 unsigned long error_code = regs->dsisr; 2071 2072 /* We treat cache locking instructions from the user 2073 * as priv ops, in the future we could try to do 2074 * something smarter 2075 */ 2076 if (error_code & (ESR_DLK|ESR_ILK)) 2077 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 2078 return; 2079 } 2080 #endif /* CONFIG_FSL_BOOKE */ 2081 2082 #ifdef CONFIG_SPE 2083 DEFINE_INTERRUPT_HANDLER(SPEFloatingPointException) 2084 { 2085 extern int do_spe_mathemu(struct pt_regs *regs); 2086 unsigned long spefscr; 2087 int fpexc_mode; 2088 int code = FPE_FLTUNK; 2089 int err; 2090 2091 interrupt_cond_local_irq_enable(regs); 2092 2093 flush_spe_to_thread(current); 2094 2095 spefscr = current->thread.spefscr; 2096 fpexc_mode = current->thread.fpexc_mode; 2097 2098 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { 2099 code = FPE_FLTOVF; 2100 } 2101 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { 2102 code = FPE_FLTUND; 2103 } 2104 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) 2105 code = FPE_FLTDIV; 2106 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { 2107 code = FPE_FLTINV; 2108 } 2109 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) 2110 code = FPE_FLTRES; 2111 2112 err = do_spe_mathemu(regs); 2113 if (err == 0) { 2114 regs->nip += 4; /* skip emulated instruction */ 2115 emulate_single_step(regs); 2116 return; 2117 } 2118 2119 if (err == -EFAULT) { 2120 /* got an error reading the instruction */ 2121 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2122 } else if (err == -EINVAL) { 2123 /* didn't recognize the instruction */ 2124 printk(KERN_ERR "unrecognized spe instruction " 2125 "in %s at %lx\n", current->comm, regs->nip); 2126 } else { 2127 _exception(SIGFPE, regs, code, regs->nip); 2128 } 2129 2130 return; 2131 } 2132 2133 DEFINE_INTERRUPT_HANDLER(SPEFloatingPointRoundException) 2134 { 2135 extern int speround_handler(struct pt_regs *regs); 2136 int err; 2137 2138 interrupt_cond_local_irq_enable(regs); 2139 2140 preempt_disable(); 2141 if (regs->msr & MSR_SPE) 2142 giveup_spe(current); 2143 preempt_enable(); 2144 2145 regs->nip -= 4; 2146 err = speround_handler(regs); 2147 if (err == 0) { 2148 regs->nip += 4; /* skip emulated instruction */ 2149 emulate_single_step(regs); 2150 return; 2151 } 2152 2153 if (err == -EFAULT) { 2154 /* got an error reading the instruction */ 2155 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 2156 } else if (err == -EINVAL) { 2157 /* didn't recognize the instruction */ 2158 printk(KERN_ERR "unrecognized spe instruction " 2159 "in %s at %lx\n", current->comm, regs->nip); 2160 } else { 2161 _exception(SIGFPE, regs, FPE_FLTUNK, regs->nip); 2162 return; 2163 } 2164 } 2165 #endif 2166 2167 /* 2168 * We enter here if we get an unrecoverable exception, that is, one 2169 * that happened at a point where the RI (recoverable interrupt) bit 2170 * in the MSR is 0. This indicates that SRR0/1 are live, and that 2171 * we therefore lost state by taking this exception. 2172 */ 2173 DEFINE_INTERRUPT_HANDLER(unrecoverable_exception) 2174 { 2175 pr_emerg("Unrecoverable exception %lx at %lx (msr=%lx)\n", 2176 regs->trap, regs->nip, regs->msr); 2177 die("Unrecoverable exception", regs, SIGABRT); 2178 } 2179 2180 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x) 2181 /* 2182 * Default handler for a Watchdog exception, 2183 * spins until a reboot occurs 2184 */ 2185 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) 2186 { 2187 /* Generic WatchdogHandler, implement your own */ 2188 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); 2189 return; 2190 } 2191 2192 DEFINE_INTERRUPT_HANDLER(WatchdogException) /* XXX NMI? async? */ 2193 { 2194 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); 2195 WatchdogHandler(regs); 2196 } 2197 #endif 2198 2199 /* 2200 * We enter here if we discover during exception entry that we are 2201 * running in supervisor mode with a userspace value in the stack pointer. 2202 */ 2203 DEFINE_INTERRUPT_HANDLER(kernel_bad_stack) 2204 { 2205 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", 2206 regs->gpr[1], regs->nip); 2207 die("Bad kernel stack pointer", regs, SIGABRT); 2208 } 2209 2210 void __init trap_init(void) 2211 { 2212 } 2213 2214 2215 #ifdef CONFIG_PPC_EMULATED_STATS 2216 2217 #define WARN_EMULATED_SETUP(type) .type = { .name = #type } 2218 2219 struct ppc_emulated ppc_emulated = { 2220 #ifdef CONFIG_ALTIVEC 2221 WARN_EMULATED_SETUP(altivec), 2222 #endif 2223 WARN_EMULATED_SETUP(dcba), 2224 WARN_EMULATED_SETUP(dcbz), 2225 WARN_EMULATED_SETUP(fp_pair), 2226 WARN_EMULATED_SETUP(isel), 2227 WARN_EMULATED_SETUP(mcrxr), 2228 WARN_EMULATED_SETUP(mfpvr), 2229 WARN_EMULATED_SETUP(multiple), 2230 WARN_EMULATED_SETUP(popcntb), 2231 WARN_EMULATED_SETUP(spe), 2232 WARN_EMULATED_SETUP(string), 2233 WARN_EMULATED_SETUP(sync), 2234 WARN_EMULATED_SETUP(unaligned), 2235 #ifdef CONFIG_MATH_EMULATION 2236 WARN_EMULATED_SETUP(math), 2237 #endif 2238 #ifdef CONFIG_VSX 2239 WARN_EMULATED_SETUP(vsx), 2240 #endif 2241 #ifdef CONFIG_PPC64 2242 WARN_EMULATED_SETUP(mfdscr), 2243 WARN_EMULATED_SETUP(mtdscr), 2244 WARN_EMULATED_SETUP(lq_stq), 2245 WARN_EMULATED_SETUP(lxvw4x), 2246 WARN_EMULATED_SETUP(lxvh8x), 2247 WARN_EMULATED_SETUP(lxvd2x), 2248 WARN_EMULATED_SETUP(lxvb16x), 2249 #endif 2250 }; 2251 2252 u32 ppc_warn_emulated; 2253 2254 void ppc_warn_emulated_print(const char *type) 2255 { 2256 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, 2257 type); 2258 } 2259 2260 static int __init ppc_warn_emulated_init(void) 2261 { 2262 struct dentry *dir; 2263 unsigned int i; 2264 struct ppc_emulated_entry *entries = (void *)&ppc_emulated; 2265 2266 dir = debugfs_create_dir("emulated_instructions", 2267 powerpc_debugfs_root); 2268 2269 debugfs_create_u32("do_warn", 0644, dir, &ppc_warn_emulated); 2270 2271 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) 2272 debugfs_create_u32(entries[i].name, 0644, dir, 2273 (u32 *)&entries[i].val.counter); 2274 2275 return 0; 2276 } 2277 2278 device_initcall(ppc_warn_emulated_init); 2279 2280 #endif /* CONFIG_PPC_EMULATED_STATS */ 2281