1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Transactional memory support routines to reclaim and recheckpoint 4 * transactional process state. 5 * 6 * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation. 7 */ 8 9#include <asm/asm-offsets.h> 10#include <asm/ppc_asm.h> 11#include <asm/ppc-opcode.h> 12#include <asm/ptrace.h> 13#include <asm/reg.h> 14#include <asm/bug.h> 15#include <asm/export.h> 16#include <asm/feature-fixups.h> 17 18#ifdef CONFIG_VSX 19/* See fpu.S, this is borrowed from there */ 20#define __SAVE_32FPRS_VSRS(n,c,base) \ 21BEGIN_FTR_SECTION \ 22 b 2f; \ 23END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 24 SAVE_32FPRS(n,base); \ 25 b 3f; \ 262: SAVE_32VSRS(n,c,base); \ 273: 28#define __REST_32FPRS_VSRS(n,c,base) \ 29BEGIN_FTR_SECTION \ 30 b 2f; \ 31END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 32 REST_32FPRS(n,base); \ 33 b 3f; \ 342: REST_32VSRS(n,c,base); \ 353: 36#else 37#define __SAVE_32FPRS_VSRS(n,c,base) SAVE_32FPRS(n, base) 38#define __REST_32FPRS_VSRS(n,c,base) REST_32FPRS(n, base) 39#endif 40#define SAVE_32FPRS_VSRS(n,c,base) \ 41 __SAVE_32FPRS_VSRS(n,__REG_##c,__REG_##base) 42#define REST_32FPRS_VSRS(n,c,base) \ 43 __REST_32FPRS_VSRS(n,__REG_##c,__REG_##base) 44 45/* Stack frame offsets for local variables. */ 46#define TM_FRAME_L0 TM_FRAME_SIZE-16 47#define TM_FRAME_L1 TM_FRAME_SIZE-8 48 49 50/* In order to access the TM SPRs, TM must be enabled. So, do so: */ 51_GLOBAL(tm_enable) 52 mfmsr r4 53 li r3, MSR_TM >> 32 54 sldi r3, r3, 32 55 and. r0, r4, r3 56 bne 1f 57 or r4, r4, r3 58 mtmsrd r4 591: blr 60EXPORT_SYMBOL_GPL(tm_enable); 61 62_GLOBAL(tm_disable) 63 mfmsr r4 64 li r3, MSR_TM >> 32 65 sldi r3, r3, 32 66 andc r4, r4, r3 67 mtmsrd r4 68 blr 69EXPORT_SYMBOL_GPL(tm_disable); 70 71_GLOBAL(tm_save_sprs) 72 mfspr r0, SPRN_TFHAR 73 std r0, THREAD_TM_TFHAR(r3) 74 mfspr r0, SPRN_TEXASR 75 std r0, THREAD_TM_TEXASR(r3) 76 mfspr r0, SPRN_TFIAR 77 std r0, THREAD_TM_TFIAR(r3) 78 blr 79 80_GLOBAL(tm_restore_sprs) 81 ld r0, THREAD_TM_TFHAR(r3) 82 mtspr SPRN_TFHAR, r0 83 ld r0, THREAD_TM_TEXASR(r3) 84 mtspr SPRN_TEXASR, r0 85 ld r0, THREAD_TM_TFIAR(r3) 86 mtspr SPRN_TFIAR, r0 87 blr 88 89 /* Passed an 8-bit failure cause as first argument. */ 90_GLOBAL(tm_abort) 91 TABORT(R3) 92 blr 93EXPORT_SYMBOL_GPL(tm_abort); 94 95/* void tm_reclaim(struct thread_struct *thread, 96 * uint8_t cause) 97 * 98 * - Performs a full reclaim. This destroys outstanding 99 * transactions and updates thread->regs.tm_ckpt_* with the 100 * original checkpointed state. Note that thread->regs is 101 * unchanged. 102 * 103 * Purpose is to both abort transactions of, and preserve the state of, 104 * a transactions at a context switch. We preserve/restore both sets of process 105 * state to restore them when the thread's scheduled again. We continue in 106 * userland as though nothing happened, but when the transaction is resumed 107 * they will abort back to the checkpointed state we save out here. 108 * 109 * Call with IRQs off, stacks get all out of sync for some periods in here! 110 */ 111_GLOBAL(tm_reclaim) 112 mfcr r5 113 mflr r0 114 stw r5, 8(r1) 115 std r0, 16(r1) 116 std r2, STK_GOT(r1) 117 stdu r1, -TM_FRAME_SIZE(r1) 118 119 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */ 120 121 std r3, STK_PARAM(R3)(r1) 122 SAVE_NVGPRS(r1) 123 124 /* We need to setup MSR for VSX register save instructions. */ 125 mfmsr r14 126 mr r15, r14 127 ori r15, r15, MSR_FP 128 li r16, 0 129 ori r16, r16, MSR_EE /* IRQs hard off */ 130 andc r15, r15, r16 131 oris r15, r15, MSR_VEC@h 132#ifdef CONFIG_VSX 133 BEGIN_FTR_SECTION 134 oris r15,r15, MSR_VSX@h 135 END_FTR_SECTION_IFSET(CPU_FTR_VSX) 136#endif 137 mtmsrd r15 138 std r14, TM_FRAME_L0(r1) 139 140 /* Do sanity check on MSR to make sure we are suspended */ 141 li r7, (MSR_TS_S)@higher 142 srdi r6, r14, 32 143 and r6, r6, r7 1441: tdeqi r6, 0 145 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0 146 147 /* Stash the stack pointer away for use after reclaim */ 148 std r1, PACAR1(r13) 149 150 /* Clear MSR RI since we are about to change r1, EE is already off. */ 151 li r5, 0 152 mtmsrd r5, 1 153 154 /* 155 * BE CAREFUL HERE: 156 * At this point we can't take an SLB miss since we have MSR_RI 157 * off. Load only to/from the stack/paca which are in SLB bolted regions 158 * until we turn MSR RI back on. 159 * 160 * The moment we treclaim, ALL of our GPRs will switch 161 * to user register state. (FPRs, CCR etc. also!) 162 * Use an sprg and a tm_scratch in the PACA to shuffle. 163 */ 164 TRECLAIM(R4) /* Cause in r4 */ 165 166 /* ******************** GPRs ******************** */ 167 /* Stash the checkpointed r13 away in the scratch SPR and get the real 168 * paca 169 */ 170 SET_SCRATCH0(r13) 171 GET_PACA(r13) 172 173 /* Stash the checkpointed r1 away in paca tm_scratch and get the real 174 * stack pointer back 175 */ 176 std r1, PACATMSCRATCH(r13) 177 ld r1, PACAR1(r13) 178 179 std r11, GPR11(r1) /* Temporary stash */ 180 181 /* 182 * Move the saved user r1 to the kernel stack in case PACATMSCRATCH is 183 * clobbered by an exception once we turn on MSR_RI below. 184 */ 185 ld r11, PACATMSCRATCH(r13) 186 std r11, GPR1(r1) 187 188 /* 189 * Store r13 away so we can free up the scratch SPR for the SLB fault 190 * handler (needed once we start accessing the thread_struct). 191 */ 192 GET_SCRATCH0(r11) 193 std r11, GPR13(r1) 194 195 /* Reset MSR RI so we can take SLB faults again */ 196 li r11, MSR_RI 197 mtmsrd r11, 1 198 199 /* Store the PPR in r11 and reset to decent value */ 200 mfspr r11, SPRN_PPR 201 HMT_MEDIUM 202 203 /* Now get some more GPRS free */ 204 std r7, GPR7(r1) /* Temporary stash */ 205 std r12, GPR12(r1) /* '' '' '' */ 206 ld r12, STK_PARAM(R3)(r1) /* Param 0, thread_struct * */ 207 208 std r11, THREAD_TM_PPR(r12) /* Store PPR and free r11 */ 209 210 addi r7, r12, PT_CKPT_REGS /* Thread's ckpt_regs */ 211 212 /* Make r7 look like an exception frame so that we 213 * can use the neat GPRx(n) macros. r7 is NOT a pt_regs ptr! 214 */ 215 subi r7, r7, STACK_FRAME_OVERHEAD 216 217 /* Sync the userland GPRs 2-12, 14-31 to thread->regs: */ 218 SAVE_GPR(0, r7) /* user r0 */ 219 SAVE_GPR(2, r7) /* user r2 */ 220 SAVE_4GPRS(3, r7) /* user r3-r6 */ 221 SAVE_GPR(8, r7) /* user r8 */ 222 SAVE_GPR(9, r7) /* user r9 */ 223 SAVE_GPR(10, r7) /* user r10 */ 224 ld r3, GPR1(r1) /* user r1 */ 225 ld r4, GPR7(r1) /* user r7 */ 226 ld r5, GPR11(r1) /* user r11 */ 227 ld r6, GPR12(r1) /* user r12 */ 228 ld r8, GPR13(r1) /* user r13 */ 229 std r3, GPR1(r7) 230 std r4, GPR7(r7) 231 std r5, GPR11(r7) 232 std r6, GPR12(r7) 233 std r8, GPR13(r7) 234 235 SAVE_NVGPRS(r7) /* user r14-r31 */ 236 237 /* ******************** NIP ******************** */ 238 mfspr r3, SPRN_TFHAR 239 std r3, _NIP(r7) /* Returns to failhandler */ 240 /* The checkpointed NIP is ignored when rescheduling/rechkpting, 241 * but is used in signal return to 'wind back' to the abort handler. 242 */ 243 244 /* ******************** CR,LR,CCR,MSR ********** */ 245 mfctr r3 246 mflr r4 247 mfcr r5 248 mfxer r6 249 250 std r3, _CTR(r7) 251 std r4, _LINK(r7) 252 std r5, _CCR(r7) 253 std r6, _XER(r7) 254 255 256 /* ******************** TAR, DSCR ********** */ 257 mfspr r3, SPRN_TAR 258 mfspr r4, SPRN_DSCR 259 260 std r3, THREAD_TM_TAR(r12) 261 std r4, THREAD_TM_DSCR(r12) 262 263 /* MSR and flags: We don't change CRs, and we don't need to alter 264 * MSR. 265 */ 266 267 268 /* ******************** FPR/VR/VSRs ************ 269 * After reclaiming, capture the checkpointed FPRs/VRs. 270 * 271 * We enabled VEC/FP/VSX in the msr above, so we can execute these 272 * instructions! 273 */ 274 mr r3, r12 275 276 /* Altivec (VEC/VMX/VR)*/ 277 addi r7, r3, THREAD_CKVRSTATE 278 SAVE_32VRS(0, r6, r7) /* r6 scratch, r7 transact vr state */ 279 mfvscr v0 280 li r6, VRSTATE_VSCR 281 stvx v0, r7, r6 282 283 /* VRSAVE */ 284 mfspr r0, SPRN_VRSAVE 285 std r0, THREAD_CKVRSAVE(r3) 286 287 /* Floating Point (FP) */ 288 addi r7, r3, THREAD_CKFPSTATE 289 SAVE_32FPRS_VSRS(0, R6, R7) /* r6 scratch, r7 transact fp state */ 290 mffs fr0 291 stfd fr0,FPSTATE_FPSCR(r7) 292 293 294 /* TM regs, incl TEXASR -- these live in thread_struct. Note they've 295 * been updated by the treclaim, to explain to userland the failure 296 * cause (aborted). 297 */ 298 mfspr r0, SPRN_TEXASR 299 mfspr r3, SPRN_TFHAR 300 mfspr r4, SPRN_TFIAR 301 std r0, THREAD_TM_TEXASR(r12) 302 std r3, THREAD_TM_TFHAR(r12) 303 std r4, THREAD_TM_TFIAR(r12) 304 305 /* AMR is checkpointed too, but is unsupported by Linux. */ 306 307 /* Restore original MSR/IRQ state & clear TM mode */ 308 ld r14, TM_FRAME_L0(r1) /* Orig MSR */ 309 310 li r15, 0 311 rldimi r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1 312 mtmsrd r14 313 314 REST_NVGPRS(r1) 315 316 addi r1, r1, TM_FRAME_SIZE 317 lwz r4, 8(r1) 318 ld r0, 16(r1) 319 mtcr r4 320 mtlr r0 321 ld r2, STK_GOT(r1) 322 323 /* Load CPU's default DSCR */ 324 ld r0, PACA_DSCR_DEFAULT(r13) 325 mtspr SPRN_DSCR, r0 326 327 blr 328 329 330 /* 331 * void __tm_recheckpoint(struct thread_struct *thread) 332 * - Restore the checkpointed register state saved by tm_reclaim 333 * when we switch_to a process. 334 * 335 * Call with IRQs off, stacks get all out of sync for 336 * some periods in here! 337 */ 338_GLOBAL(__tm_recheckpoint) 339 mfcr r5 340 mflr r0 341 stw r5, 8(r1) 342 std r0, 16(r1) 343 std r2, STK_GOT(r1) 344 stdu r1, -TM_FRAME_SIZE(r1) 345 346 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. 347 * This is used for backing up the NVGPRs: 348 */ 349 SAVE_NVGPRS(r1) 350 351 /* Load complete register state from ts_ckpt* registers */ 352 353 addi r7, r3, PT_CKPT_REGS /* Thread's ckpt_regs */ 354 355 /* Make r7 look like an exception frame so that we 356 * can use the neat GPRx(n) macros. r7 is now NOT a pt_regs ptr! 357 */ 358 subi r7, r7, STACK_FRAME_OVERHEAD 359 360 /* We need to setup MSR for FP/VMX/VSX register save instructions. */ 361 mfmsr r6 362 mr r5, r6 363 ori r5, r5, MSR_FP 364#ifdef CONFIG_ALTIVEC 365 oris r5, r5, MSR_VEC@h 366#endif 367#ifdef CONFIG_VSX 368 BEGIN_FTR_SECTION 369 oris r5,r5, MSR_VSX@h 370 END_FTR_SECTION_IFSET(CPU_FTR_VSX) 371#endif 372 mtmsrd r5 373 374#ifdef CONFIG_ALTIVEC 375 /* 376 * FP and VEC registers: These are recheckpointed from 377 * thread.ckfp_state and thread.ckvr_state respectively. The 378 * thread.fp_state[] version holds the 'live' (transactional) 379 * and will be loaded subsequently by any FPUnavailable trap. 380 */ 381 addi r8, r3, THREAD_CKVRSTATE 382 li r5, VRSTATE_VSCR 383 lvx v0, r8, r5 384 mtvscr v0 385 REST_32VRS(0, r5, r8) /* r5 scratch, r8 ptr */ 386 ld r5, THREAD_CKVRSAVE(r3) 387 mtspr SPRN_VRSAVE, r5 388#endif 389 390 addi r8, r3, THREAD_CKFPSTATE 391 lfd fr0, FPSTATE_FPSCR(r8) 392 MTFSF_L(fr0) 393 REST_32FPRS_VSRS(0, R4, R8) 394 395 mtmsr r6 /* FP/Vec off again! */ 396 397restore_gprs: 398 399 /* ******************** CR,LR,CCR,MSR ********** */ 400 ld r4, _CTR(r7) 401 ld r5, _LINK(r7) 402 ld r8, _XER(r7) 403 404 mtctr r4 405 mtlr r5 406 mtxer r8 407 408 /* ******************** TAR ******************** */ 409 ld r4, THREAD_TM_TAR(r3) 410 mtspr SPRN_TAR, r4 411 412 /* Load up the PPR and DSCR in GPRs only at this stage */ 413 ld r5, THREAD_TM_DSCR(r3) 414 ld r6, THREAD_TM_PPR(r3) 415 416 REST_GPR(0, r7) /* GPR0 */ 417 REST_2GPRS(2, r7) /* GPR2-3 */ 418 REST_GPR(4, r7) /* GPR4 */ 419 REST_4GPRS(8, r7) /* GPR8-11 */ 420 REST_2GPRS(12, r7) /* GPR12-13 */ 421 422 REST_NVGPRS(r7) /* GPR14-31 */ 423 424 /* Load up PPR and DSCR here so we don't run with user values for long 425 */ 426 mtspr SPRN_DSCR, r5 427 mtspr SPRN_PPR, r6 428 429 /* Do final sanity check on TEXASR to make sure FS is set. Do this 430 * here before we load up the userspace r1 so any bugs we hit will get 431 * a call chain */ 432 mfspr r5, SPRN_TEXASR 433 srdi r5, r5, 16 434 li r6, (TEXASR_FS)@h 435 and r6, r6, r5 4361: tdeqi r6, 0 437 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0 438 439 /* Do final sanity check on MSR to make sure we are not transactional 440 * or suspended 441 */ 442 mfmsr r6 443 li r5, (MSR_TS_MASK)@higher 444 srdi r6, r6, 32 445 and r6, r6, r5 4461: tdnei r6, 0 447 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0 448 449 /* Restore CR */ 450 ld r6, _CCR(r7) 451 mtcr r6 452 453 REST_GPR(6, r7) 454 455 /* 456 * Store r1 and r5 on the stack so that we can access them 457 * after we clear MSR RI. 458 */ 459 460 REST_GPR(5, r7) 461 std r5, -8(r1) 462 ld r5, GPR1(r7) 463 std r5, -16(r1) 464 465 REST_GPR(7, r7) 466 467 /* Clear MSR RI since we are about to change r1. EE is already off */ 468 li r5, 0 469 mtmsrd r5, 1 470 471 /* 472 * BE CAREFUL HERE: 473 * At this point we can't take an SLB miss since we have MSR_RI 474 * off. Load only to/from the stack/paca which are in SLB bolted regions 475 * until we turn MSR RI back on. 476 */ 477 478 SET_SCRATCH0(r1) 479 ld r5, -8(r1) 480 ld r1, -16(r1) 481 482 /* Commit register state as checkpointed state: */ 483 TRECHKPT 484 485 HMT_MEDIUM 486 487 /* Our transactional state has now changed. 488 * 489 * Now just get out of here. Transactional (current) state will be 490 * updated once restore is called on the return path in the _switch-ed 491 * -to process. 492 */ 493 494 GET_PACA(r13) 495 GET_SCRATCH0(r1) 496 497 /* R1 is restored, so we are recoverable again. EE is still off */ 498 li r4, MSR_RI 499 mtmsrd r4, 1 500 501 REST_NVGPRS(r1) 502 503 addi r1, r1, TM_FRAME_SIZE 504 lwz r4, 8(r1) 505 ld r0, 16(r1) 506 mtcr r4 507 mtlr r0 508 ld r2, STK_GOT(r1) 509 510 /* Load CPU's default DSCR */ 511 ld r0, PACA_DSCR_DEFAULT(r13) 512 mtspr SPRN_DSCR, r0 513 514 blr 515 516 /* ****************************************************************** */ 517