1/* 2 * Transactional memory support routines to reclaim and recheckpoint 3 * transactional process state. 4 * 5 * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation. 6 */ 7 8#include <asm/asm-offsets.h> 9#include <asm/ppc_asm.h> 10#include <asm/ppc-opcode.h> 11#include <asm/ptrace.h> 12#include <asm/reg.h> 13#include <asm/bug.h> 14 15#ifdef CONFIG_VSX 16/* See fpu.S, this is borrowed from there */ 17#define __SAVE_32FPRS_VSRS(n,c,base) \ 18BEGIN_FTR_SECTION \ 19 b 2f; \ 20END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 21 SAVE_32FPRS(n,base); \ 22 b 3f; \ 232: SAVE_32VSRS(n,c,base); \ 243: 25#define __REST_32FPRS_VSRS(n,c,base) \ 26BEGIN_FTR_SECTION \ 27 b 2f; \ 28END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 29 REST_32FPRS(n,base); \ 30 b 3f; \ 312: REST_32VSRS(n,c,base); \ 323: 33#else 34#define __SAVE_32FPRS_VSRS(n,c,base) SAVE_32FPRS(n, base) 35#define __REST_32FPRS_VSRS(n,c,base) REST_32FPRS(n, base) 36#endif 37#define SAVE_32FPRS_VSRS(n,c,base) \ 38 __SAVE_32FPRS_VSRS(n,__REG_##c,__REG_##base) 39#define REST_32FPRS_VSRS(n,c,base) \ 40 __REST_32FPRS_VSRS(n,__REG_##c,__REG_##base) 41 42/* Stack frame offsets for local variables. */ 43#define TM_FRAME_L0 TM_FRAME_SIZE-16 44#define TM_FRAME_L1 TM_FRAME_SIZE-8 45 46 47/* In order to access the TM SPRs, TM must be enabled. So, do so: */ 48_GLOBAL(tm_enable) 49 mfmsr r4 50 li r3, MSR_TM >> 32 51 sldi r3, r3, 32 52 and. r0, r4, r3 53 bne 1f 54 or r4, r4, r3 55 mtmsrd r4 561: blr 57 58_GLOBAL(tm_save_sprs) 59 mfspr r0, SPRN_TFHAR 60 std r0, THREAD_TM_TFHAR(r3) 61 mfspr r0, SPRN_TEXASR 62 std r0, THREAD_TM_TEXASR(r3) 63 mfspr r0, SPRN_TFIAR 64 std r0, THREAD_TM_TFIAR(r3) 65 blr 66 67_GLOBAL(tm_restore_sprs) 68 ld r0, THREAD_TM_TFHAR(r3) 69 mtspr SPRN_TFHAR, r0 70 ld r0, THREAD_TM_TEXASR(r3) 71 mtspr SPRN_TEXASR, r0 72 ld r0, THREAD_TM_TFIAR(r3) 73 mtspr SPRN_TFIAR, r0 74 blr 75 76 /* Passed an 8-bit failure cause as first argument. */ 77_GLOBAL(tm_abort) 78 TABORT(R3) 79 blr 80 81/* void tm_reclaim(struct thread_struct *thread, 82 * unsigned long orig_msr, 83 * uint8_t cause) 84 * 85 * - Performs a full reclaim. This destroys outstanding 86 * transactions and updates thread->regs.tm_ckpt_* with the 87 * original checkpointed state. Note that thread->regs is 88 * unchanged. 89 * - FP regs are written back to thread->transact_fpr before 90 * reclaiming. These are the transactional (current) versions. 91 * 92 * Purpose is to both abort transactions of, and preserve the state of, 93 * a transactions at a context switch. We preserve/restore both sets of process 94 * state to restore them when the thread's scheduled again. We continue in 95 * userland as though nothing happened, but when the transaction is resumed 96 * they will abort back to the checkpointed state we save out here. 97 * 98 * Call with IRQs off, stacks get all out of sync for some periods in here! 99 */ 100_GLOBAL(tm_reclaim) 101 mfcr r6 102 mflr r0 103 stw r6, 8(r1) 104 std r0, 16(r1) 105 std r2, STK_GOT(r1) 106 stdu r1, -TM_FRAME_SIZE(r1) 107 108 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */ 109 110 std r3, STK_PARAM(R3)(r1) 111 SAVE_NVGPRS(r1) 112 113 /* We need to setup MSR for VSX register save instructions. */ 114 mfmsr r14 115 mr r15, r14 116 ori r15, r15, MSR_FP 117 li r16, 0 118 ori r16, r16, MSR_EE /* IRQs hard off */ 119 andc r15, r15, r16 120 oris r15, r15, MSR_VEC@h 121#ifdef CONFIG_VSX 122 BEGIN_FTR_SECTION 123 oris r15,r15, MSR_VSX@h 124 END_FTR_SECTION_IFSET(CPU_FTR_VSX) 125#endif 126 mtmsrd r15 127 std r14, TM_FRAME_L0(r1) 128 129 /* Stash the stack pointer away for use after reclaim */ 130 std r1, PACAR1(r13) 131 132 /* ******************** FPR/VR/VSRs ************ 133 * Before reclaiming, capture the current/transactional FPR/VR 134 * versions /if used/. 135 * 136 * (If VSX used, FP and VMX are implied. Or, we don't need to look 137 * at MSR.VSX as copying FP regs if .FP, vector regs if .VMX covers it.) 138 * 139 * We're passed the thread's MSR as parameter 2. 140 * 141 * We enabled VEC/FP/VSX in the msr above, so we can execute these 142 * instructions! 143 */ 144 andis. r0, r4, MSR_VEC@h 145 beq dont_backup_vec 146 147 addi r7, r3, THREAD_TRANSACT_VRSTATE 148 SAVE_32VRS(0, r6, r7) /* r6 scratch, r7 transact vr state */ 149 mfvscr v0 150 li r6, VRSTATE_VSCR 151 stvx v0, r7, r6 152dont_backup_vec: 153 mfspr r0, SPRN_VRSAVE 154 std r0, THREAD_TRANSACT_VRSAVE(r3) 155 156 andi. r0, r4, MSR_FP 157 beq dont_backup_fp 158 159 addi r7, r3, THREAD_TRANSACT_FPSTATE 160 SAVE_32FPRS_VSRS(0, R6, R7) /* r6 scratch, r7 transact fp state */ 161 162 mffs fr0 163 stfd fr0,FPSTATE_FPSCR(r7) 164 165dont_backup_fp: 166 /* Do sanity check on MSR to make sure we are suspended */ 167 li r7, (MSR_TS_S)@higher 168 srdi r6, r14, 32 169 and r6, r6, r7 1701: tdeqi r6, 0 171 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0 172 173 /* Clear MSR RI since we are about to change r1, EE is already off. */ 174 li r4, 0 175 mtmsrd r4, 1 176 177 /* 178 * BE CAREFUL HERE: 179 * At this point we can't take an SLB miss since we have MSR_RI 180 * off. Load only to/from the stack/paca which are in SLB bolted regions 181 * until we turn MSR RI back on. 182 * 183 * The moment we treclaim, ALL of our GPRs will switch 184 * to user register state. (FPRs, CCR etc. also!) 185 * Use an sprg and a tm_scratch in the PACA to shuffle. 186 */ 187 TRECLAIM(R5) /* Cause in r5 */ 188 189 /* ******************** GPRs ******************** */ 190 /* Stash the checkpointed r13 away in the scratch SPR and get the real 191 * paca 192 */ 193 SET_SCRATCH0(r13) 194 GET_PACA(r13) 195 196 /* Stash the checkpointed r1 away in paca tm_scratch and get the real 197 * stack pointer back 198 */ 199 std r1, PACATMSCRATCH(r13) 200 ld r1, PACAR1(r13) 201 202 /* Store the PPR in r11 and reset to decent value */ 203 std r11, GPR11(r1) /* Temporary stash */ 204 205 /* Reset MSR RI so we can take SLB faults again */ 206 li r11, MSR_RI 207 mtmsrd r11, 1 208 209 mfspr r11, SPRN_PPR 210 HMT_MEDIUM 211 212 /* Now get some more GPRS free */ 213 std r7, GPR7(r1) /* Temporary stash */ 214 std r12, GPR12(r1) /* '' '' '' */ 215 ld r12, STK_PARAM(R3)(r1) /* Param 0, thread_struct * */ 216 217 std r11, THREAD_TM_PPR(r12) /* Store PPR and free r11 */ 218 219 addi r7, r12, PT_CKPT_REGS /* Thread's ckpt_regs */ 220 221 /* Make r7 look like an exception frame so that we 222 * can use the neat GPRx(n) macros. r7 is NOT a pt_regs ptr! 223 */ 224 subi r7, r7, STACK_FRAME_OVERHEAD 225 226 /* Sync the userland GPRs 2-12, 14-31 to thread->regs: */ 227 SAVE_GPR(0, r7) /* user r0 */ 228 SAVE_GPR(2, r7) /* user r2 */ 229 SAVE_4GPRS(3, r7) /* user r3-r6 */ 230 SAVE_GPR(8, r7) /* user r8 */ 231 SAVE_GPR(9, r7) /* user r9 */ 232 SAVE_GPR(10, r7) /* user r10 */ 233 ld r3, PACATMSCRATCH(r13) /* user r1 */ 234 ld r4, GPR7(r1) /* user r7 */ 235 ld r5, GPR11(r1) /* user r11 */ 236 ld r6, GPR12(r1) /* user r12 */ 237 GET_SCRATCH0(8) /* user r13 */ 238 std r3, GPR1(r7) 239 std r4, GPR7(r7) 240 std r5, GPR11(r7) 241 std r6, GPR12(r7) 242 std r8, GPR13(r7) 243 244 SAVE_NVGPRS(r7) /* user r14-r31 */ 245 246 /* ******************** NIP ******************** */ 247 mfspr r3, SPRN_TFHAR 248 std r3, _NIP(r7) /* Returns to failhandler */ 249 /* The checkpointed NIP is ignored when rescheduling/rechkpting, 250 * but is used in signal return to 'wind back' to the abort handler. 251 */ 252 253 /* ******************** CR,LR,CCR,MSR ********** */ 254 mfctr r3 255 mflr r4 256 mfcr r5 257 mfxer r6 258 259 std r3, _CTR(r7) 260 std r4, _LINK(r7) 261 std r5, _CCR(r7) 262 std r6, _XER(r7) 263 264 265 /* ******************** TAR, DSCR ********** */ 266 mfspr r3, SPRN_TAR 267 mfspr r4, SPRN_DSCR 268 269 std r3, THREAD_TM_TAR(r12) 270 std r4, THREAD_TM_DSCR(r12) 271 272 /* MSR and flags: We don't change CRs, and we don't need to alter 273 * MSR. 274 */ 275 276 /* TM regs, incl TEXASR -- these live in thread_struct. Note they've 277 * been updated by the treclaim, to explain to userland the failure 278 * cause (aborted). 279 */ 280 mfspr r0, SPRN_TEXASR 281 mfspr r3, SPRN_TFHAR 282 mfspr r4, SPRN_TFIAR 283 std r0, THREAD_TM_TEXASR(r12) 284 std r3, THREAD_TM_TFHAR(r12) 285 std r4, THREAD_TM_TFIAR(r12) 286 287 /* AMR is checkpointed too, but is unsupported by Linux. */ 288 289 /* Restore original MSR/IRQ state & clear TM mode */ 290 ld r14, TM_FRAME_L0(r1) /* Orig MSR */ 291 li r15, 0 292 rldimi r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1 293 mtmsrd r14 294 295 REST_NVGPRS(r1) 296 297 addi r1, r1, TM_FRAME_SIZE 298 lwz r4, 8(r1) 299 ld r0, 16(r1) 300 mtcr r4 301 mtlr r0 302 ld r2, STK_GOT(r1) 303 304 /* Load CPU's default DSCR */ 305 ld r0, PACA_DSCR_DEFAULT(r13) 306 mtspr SPRN_DSCR, r0 307 308 blr 309 310 311 /* void tm_recheckpoint(struct thread_struct *thread, 312 * unsigned long orig_msr) 313 * - Restore the checkpointed register state saved by tm_reclaim 314 * when we switch_to a process. 315 * 316 * Call with IRQs off, stacks get all out of sync for 317 * some periods in here! 318 */ 319_GLOBAL(__tm_recheckpoint) 320 mfcr r5 321 mflr r0 322 stw r5, 8(r1) 323 std r0, 16(r1) 324 std r2, STK_GOT(r1) 325 stdu r1, -TM_FRAME_SIZE(r1) 326 327 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. 328 * This is used for backing up the NVGPRs: 329 */ 330 SAVE_NVGPRS(r1) 331 332 /* Load complete register state from ts_ckpt* registers */ 333 334 addi r7, r3, PT_CKPT_REGS /* Thread's ckpt_regs */ 335 336 /* Make r7 look like an exception frame so that we 337 * can use the neat GPRx(n) macros. r7 is now NOT a pt_regs ptr! 338 */ 339 subi r7, r7, STACK_FRAME_OVERHEAD 340 341 mfmsr r6 342 /* R4 = original MSR to indicate whether thread used FP/Vector etc. */ 343 344 /* Enable FP/vec in MSR if necessary! */ 345 lis r5, MSR_VEC@h 346 ori r5, r5, MSR_FP 347 and. r5, r4, r5 348 beq restore_gprs /* if neither, skip both */ 349 350#ifdef CONFIG_VSX 351 BEGIN_FTR_SECTION 352 oris r5, r5, MSR_VSX@h 353 END_FTR_SECTION_IFSET(CPU_FTR_VSX) 354#endif 355 or r5, r6, r5 /* Set MSR.FP+.VSX/.VEC */ 356 mtmsr r5 357 358#ifdef CONFIG_ALTIVEC 359 /* FP and VEC registers: These are recheckpointed from thread.fpr[] 360 * and thread.vr[] respectively. The thread.transact_fpr[] version 361 * is more modern, and will be loaded subsequently by any FPUnavailable 362 * trap. 363 */ 364 andis. r0, r4, MSR_VEC@h 365 beq dont_restore_vec 366 367 addi r8, r3, THREAD_VRSTATE 368 li r5, VRSTATE_VSCR 369 lvx v0, r8, r5 370 mtvscr v0 371 REST_32VRS(0, r5, r8) /* r5 scratch, r8 ptr */ 372dont_restore_vec: 373 ld r5, THREAD_VRSAVE(r3) 374 mtspr SPRN_VRSAVE, r5 375#endif 376 377 andi. r0, r4, MSR_FP 378 beq dont_restore_fp 379 380 addi r8, r3, THREAD_FPSTATE 381 lfd fr0, FPSTATE_FPSCR(r8) 382 MTFSF_L(fr0) 383 REST_32FPRS_VSRS(0, R4, R8) 384 385dont_restore_fp: 386 mtmsr r6 /* FP/Vec off again! */ 387 388restore_gprs: 389 390 /* ******************** CR,LR,CCR,MSR ********** */ 391 ld r4, _CTR(r7) 392 ld r5, _LINK(r7) 393 ld r8, _XER(r7) 394 395 mtctr r4 396 mtlr r5 397 mtxer r8 398 399 /* ******************** TAR ******************** */ 400 ld r4, THREAD_TM_TAR(r3) 401 mtspr SPRN_TAR, r4 402 403 /* Load up the PPR and DSCR in GPRs only at this stage */ 404 ld r5, THREAD_TM_DSCR(r3) 405 ld r6, THREAD_TM_PPR(r3) 406 407 REST_GPR(0, r7) /* GPR0 */ 408 REST_2GPRS(2, r7) /* GPR2-3 */ 409 REST_GPR(4, r7) /* GPR4 */ 410 REST_4GPRS(8, r7) /* GPR8-11 */ 411 REST_2GPRS(12, r7) /* GPR12-13 */ 412 413 REST_NVGPRS(r7) /* GPR14-31 */ 414 415 /* Load up PPR and DSCR here so we don't run with user values for long 416 */ 417 mtspr SPRN_DSCR, r5 418 mtspr SPRN_PPR, r6 419 420 /* Do final sanity check on TEXASR to make sure FS is set. Do this 421 * here before we load up the userspace r1 so any bugs we hit will get 422 * a call chain */ 423 mfspr r5, SPRN_TEXASR 424 srdi r5, r5, 16 425 li r6, (TEXASR_FS)@h 426 and r6, r6, r5 4271: tdeqi r6, 0 428 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0 429 430 /* Do final sanity check on MSR to make sure we are not transactional 431 * or suspended 432 */ 433 mfmsr r6 434 li r5, (MSR_TS_MASK)@higher 435 srdi r6, r6, 32 436 and r6, r6, r5 4371: tdnei r6, 0 438 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0 439 440 /* Restore CR */ 441 ld r6, _CCR(r7) 442 mtcr r6 443 444 REST_GPR(6, r7) 445 446 /* 447 * Store r1 and r5 on the stack so that we can access them 448 * after we clear MSR RI. 449 */ 450 451 REST_GPR(5, r7) 452 std r5, -8(r1) 453 ld r5, GPR1(r7) 454 std r5, -16(r1) 455 456 REST_GPR(7, r7) 457 458 /* Clear MSR RI since we are about to change r1. EE is already off */ 459 li r5, 0 460 mtmsrd r5, 1 461 462 /* 463 * BE CAREFUL HERE: 464 * At this point we can't take an SLB miss since we have MSR_RI 465 * off. Load only to/from the stack/paca which are in SLB bolted regions 466 * until we turn MSR RI back on. 467 */ 468 469 SET_SCRATCH0(r1) 470 ld r5, -8(r1) 471 ld r1, -16(r1) 472 473 /* Commit register state as checkpointed state: */ 474 TRECHKPT 475 476 HMT_MEDIUM 477 478 /* Our transactional state has now changed. 479 * 480 * Now just get out of here. Transactional (current) state will be 481 * updated once restore is called on the return path in the _switch-ed 482 * -to process. 483 */ 484 485 GET_PACA(r13) 486 GET_SCRATCH0(r1) 487 488 /* R1 is restored, so we are recoverable again. EE is still off */ 489 li r4, MSR_RI 490 mtmsrd r4, 1 491 492 REST_NVGPRS(r1) 493 494 addi r1, r1, TM_FRAME_SIZE 495 lwz r4, 8(r1) 496 ld r0, 16(r1) 497 mtcr r4 498 mtlr r0 499 ld r2, STK_GOT(r1) 500 501 /* Load CPU's default DSCR */ 502 ld r0, PACA_DSCR_DEFAULT(r13) 503 mtspr SPRN_DSCR, r0 504 505 blr 506 507 /* ****************************************************************** */ 508